drivers/net/phy/broadcom.c

   1 /*
   2  *      drivers/net/phy/broadcom.c
   3  *
   4  *      Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
   5  *      transceivers.
   6  *
   7  *      Copyright (c) 2006  Maciej W. Rozycki
   8  *
   9  *      Inspired by code written by Amy Fong.
  10  *
  11  *      This program is free software; you can redistribute it and/or
  12  *      modify it under the terms of the GNU General Public License
  13  *      as published by the Free Software Foundation; either version
  14  *      2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include "bcm-phy-lib.h"
  18 #include <linux/delay.h>
  19 #include <linux/module.h>
  20 #include <linux/phy.h>
  21 #include <linux/brcmphy.h>
  22
  23
  24 #define BRCM_PHY_MODEL(phydev) \
  25         ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
  26
  27 #define BRCM_PHY_REV(phydev) \
  28         ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
  29
  30 MODULE_DESCRIPTION("Broadcom PHY driver");
  31 MODULE_AUTHOR("Maciej W. Rozycki");
  32 MODULE_LICENSE("GPL");
  33
  34 static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
  35 {
  36         return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
  37 }
  38
  39 /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
  40 static int bcm50610_a0_workaround(struct phy_device *phydev)
  41 {
  42         int err;
  43
  44         err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0,
  45                                 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
  46                                 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
  47         if (err < 0)
  48                 return err;
  49
  50         err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3,
  51                                 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
  52         if (err < 0)
  53                 return err;
  54
  55         err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75,
  56                                 MII_BCM54XX_EXP_EXP75_VDACCTRL);
  57         if (err < 0)
  58                 return err;
  59
  60         err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96,
  61                                 MII_BCM54XX_EXP_EXP96_MYST);
  62         if (err < 0)
  63                 return err;
  64
  65         err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97,
  66                                 MII_BCM54XX_EXP_EXP97_MYST);
  67
  68         return err;
  69 }
  70
  71 static int bcm54xx_phydsp_config(struct phy_device *phydev)
  72 {
  73         int err, err2;
  74
  75         /* Enable the SMDSP clock */
  76         err = bcm54xx_auxctl_write(phydev,
  77                                    MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
  78                                    MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
  79                                    MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
  80         if (err < 0)
  81                 return err;
  82
  83         if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
  84             BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
  85                 /* Clear bit 9 to fix a phy interop issue. */
  86                 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08,
  87                                         MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
  88                 if (err < 0)
  89                         goto error;
  90
  91                 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
  92                         err = bcm50610_a0_workaround(phydev);
  93                         if (err < 0)
  94                                 goto error;
  95                 }
  96         }
  97
  98         if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
  99                 int val;
 100
 101                 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75);
 102                 if (val < 0)
 103                         goto error;
 104
 105                 val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
 106                 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val);
 107         }
 108
 109 error:
 110         /* Disable the SMDSP clock */
 111         err2 = bcm54xx_auxctl_write(phydev,
 112                                     MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
 113                                     MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
 114
 115         /* Return the first error reported. */
 116         return err ? err : err2;
 117 }
 118
 119 static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
 120 {
 121         u32 orig;
 122         int val;
 123         bool clk125en = true;
 124
 125         /* Abort if we are using an untested phy. */
 126         if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
 127             BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
 128             BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M)
 129                 return;
 130
 131         val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
 132         if (val < 0)
 133                 return;
 134
 135         orig = val;
 136
 137         if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
 138              BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
 139             BRCM_PHY_REV(phydev) >= 0x3) {
 140                 /*
 141                  * Here, bit 0 _disables_ CLK125 when set.
 142                  * This bit is set by default.
 143                  */
 144                 clk125en = false;
 145         } else {
 146                 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
 147                         /* Here, bit 0 _enables_ CLK125 when set */
 148                         val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
 149                         clk125en = false;
 150                 }
 151         }
 152
 153         if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
 154                 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
 155         else
 156                 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
 157
 158         if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY)
 159                 val |= BCM54XX_SHD_SCR3_TRDDAPD;
 160
 161         if (orig != val)
 162                 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
 163
 164         val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
 165         if (val < 0)
 166                 return;
 167
 168         orig = val;
 169
 170         if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
 171                 val |= BCM54XX_SHD_APD_EN;
 172         else
 173                 val &= ~BCM54XX_SHD_APD_EN;
 174
 175         if (orig != val)
 176                 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
 177 }
 178
 179 static int bcm54xx_config_init(struct phy_device *phydev)
 180 {
 181         int reg, err;
 182
 183         reg = phy_read(phydev, MII_BCM54XX_ECR);
 184         if (reg < 0)
 185                 return reg;
 186
 187         /* Mask interrupts globally.  */
 188         reg |= MII_BCM54XX_ECR_IM;
 189         err = phy_write(phydev, MII_BCM54XX_ECR, reg);
 190         if (err < 0)
 191                 return err;
 192
 193         /* Unmask events we are interested in.  */
 194         reg = ~(MII_BCM54XX_INT_DUPLEX |
 195                 MII_BCM54XX_INT_SPEED |
 196                 MII_BCM54XX_INT_LINK);
 197         err = phy_write(phydev, MII_BCM54XX_IMR, reg);
 198         if (err < 0)
 199                 return err;
 200
 201         if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
 202              BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
 203             (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
 204                 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0);
 205
 206         if ((phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) ||
 207             (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) ||
 208             (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
 209                 bcm54xx_adjust_rxrefclk(phydev);
 210
 211         bcm54xx_phydsp_config(phydev);
 212
 213         return 0;
 214 }
 215
 216 static int bcm5482_config_init(struct phy_device *phydev)
 217 {
 218         int err, reg;
 219
 220         err = bcm54xx_config_init(phydev);
 221
 222         if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
 223                 /*
 224                  * Enable secondary SerDes and its use as an LED source
 225                  */
 226                 reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_SSD);
 227                 bcm_phy_write_shadow(phydev, BCM5482_SHD_SSD,
 228                                      reg |
 229                                      BCM5482_SHD_SSD_LEDM |
 230                                      BCM5482_SHD_SSD_EN);
 231
 232                 /*
 233                  * Enable SGMII slave mode and auto-detection
 234                  */
 235                 reg = BCM5482_SSD_SGMII_SLAVE | MII_BCM54XX_EXP_SEL_SSD;
 236                 err = bcm_phy_read_exp(phydev, reg);
 237                 if (err < 0)
 238                         return err;
 239                 err = bcm_phy_write_exp(phydev, reg, err |
 240                                         BCM5482_SSD_SGMII_SLAVE_EN |
 241                                         BCM5482_SSD_SGMII_SLAVE_AD);
 242                 if (err < 0)
 243                         return err;
 244
 245                 /*
 246                  * Disable secondary SerDes powerdown
 247                  */
 248                 reg = BCM5482_SSD_1000BX_CTL | MII_BCM54XX_EXP_SEL_SSD;
 249                 err = bcm_phy_read_exp(phydev, reg);
 250                 if (err < 0)
 251                         return err;
 252                 err = bcm_phy_write_exp(phydev, reg,
 253                                         err & ~BCM5482_SSD_1000BX_CTL_PWRDOWN);
 254                 if (err < 0)
 255                         return err;
 256
 257                 /*
 258                  * Select 1000BASE-X register set (primary SerDes)
 259                  */
 260                 reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_MODE);
 261                 bcm_phy_write_shadow(phydev, BCM5482_SHD_MODE,
 262                                      reg | BCM5482_SHD_MODE_1000BX);
 263
 264                 /*
 265                  * LED1=ACTIVITYLED, LED3=LINKSPD[2]
 266                  * (Use LED1 as secondary SerDes ACTIVITY LED)
 267                  */
 268                 bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1,
 269                         BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_ACTIVITYLED) |
 270                         BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_LINKSPD2));
 271
 272                 /*
 273                  * Auto-negotiation doesn't seem to work quite right
 274                  * in this mode, so we disable it and force it to the
 275                  * right speed/duplex setting.  Only 'link status'
 276                  * is important.
 277                  */
 278                 phydev->autoneg = AUTONEG_DISABLE;
 279                 phydev->speed = SPEED_1000;
 280                 phydev->duplex = DUPLEX_FULL;
 281         }
 282
 283         return err;
 284 }
 285
 286 static int bcm5482_read_status(struct phy_device *phydev)
 287 {
 288         int err;
 289
 290         err = genphy_read_status(phydev);
 291
 292         if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
 293                 /*
 294                  * Only link status matters for 1000Base-X mode, so force
 295                  * 1000 Mbit/s full-duplex status
 296                  */
 297                 if (phydev->link) {
 298                         phydev->speed = SPEED_1000;
 299                         phydev->duplex = DUPLEX_FULL;
 300                 }
 301         }
 302
 303         return err;
 304 }
 305
 306 static int bcm5481_config_aneg(struct phy_device *phydev)
 307 {
 308         int ret;
 309
 310         /* Aneg firsly. */
 311         ret = genphy_config_aneg(phydev);
 312
 313         /* Then we can set up the delay. */
 314         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
 315                 u16 reg;
 316
 317                 /*
 318                  * There is no BCM5481 specification available, so down
 319                  * here is everything we know about "register 0x18". This
 320                  * at least helps BCM5481 to successfully receive packets
 321                  * on MPC8360E-RDK board. Peter Barada <peterb@logicpd.com>
 322                  * says: "This sets delay between the RXD and RXC signals
 323                  * instead of using trace lengths to achieve timing".
 324                  */
 325
 326                 /* Set RDX clk delay. */
 327                 reg = 0x7 | (0x7 << 12);
 328                 phy_write(phydev, 0x18, reg);
 329
 330                 reg = phy_read(phydev, 0x18);
 331                 /* Set RDX-RXC skew. */
 332                 reg |= (1 << 8);
 333                 /* Write bits 14:0. */
 334                 reg |= (1 << 15);
 335                 phy_write(phydev, 0x18, reg);
 336         }
 337
 338         return ret;
 339 }
 340
 341 static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
 342 {
 343         int val;
 344
 345         val = phy_read(phydev, reg);
 346         if (val < 0)
 347                 return val;
 348
 349         return phy_write(phydev, reg, val | set);
 350 }
 351
 352 static int brcm_fet_config_init(struct phy_device *phydev)
 353 {
 354         int reg, err, err2, brcmtest;
 355
 356         /* Reset the PHY to bring it to a known state. */
 357         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 358         if (err < 0)
 359                 return err;
 360
 361         /* The datasheet indicates the PHY needs up to 1us to complete a reset,
 362          * build some slack here.
 363          */
 364         usleep_range(1000, 2000);
 365
 366         /* The PHY requires 65 MDC clock cycles to complete a write operation
 367          * and turnaround the line properly.
 368          *
 369          * We ignore -EIO here as the MDIO controller (e.g.: mdio-bcm-unimac)
 370          * may flag the lack of turn-around as a read failure. This is
 371          * particularly true with this combination since the MDIO controller
 372          * only used 64 MDC cycles. This is not a critical failure in this
 373          * specific case and it has no functional impact otherwise, so we let
 374          * that one go through. If there is a genuine bus error, the next read
 375          * of MII_BRCM_FET_INTREG will error out.
 376          */
 377         err = phy_read(phydev, MII_BMCR);
 378         if (err < 0 && err != -EIO)
 379                 return err;
 380
 381         reg = phy_read(phydev, MII_BRCM_FET_INTREG);
 382         if (reg < 0)
 383                 return reg;
 384
 385         /* Unmask events we are interested in and mask interrupts globally. */
 386         reg = MII_BRCM_FET_IR_DUPLEX_EN |
 387               MII_BRCM_FET_IR_SPEED_EN |
 388               MII_BRCM_FET_IR_LINK_EN |
 389               MII_BRCM_FET_IR_ENABLE |
 390               MII_BRCM_FET_IR_MASK;
 391
 392         err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
 393         if (err < 0)
 394                 return err;
 395
 396         /* Enable shadow register access */
 397         brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
 398         if (brcmtest < 0)
 399                 return brcmtest;
 400
 401         reg = brcmtest | MII_BRCM_FET_BT_SRE;
 402
 403         err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
 404         if (err < 0)
 405                 return err;
 406
 407         /* Set the LED mode */
 408         reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
 409         if (reg < 0) {
 410                 err = reg;
 411                 goto done;
 412         }
 413
 414         reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
 415         reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
 416
 417         err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
 418         if (err < 0)
 419                 goto done;
 420
 421         /* Enable auto MDIX */
 422         err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
 423                                        MII_BRCM_FET_SHDW_MC_FAME);
 424         if (err < 0)
 425                 goto done;
 426
 427         if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
 428                 /* Enable auto power down */
 429                 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
 430                                                MII_BRCM_FET_SHDW_AS2_APDE);
 431         }
 432
 433 done:
 434         /* Disable shadow register access */
 435         err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
 436         if (!err)
 437                 err = err2;
 438
 439         return err;
 440 }
 441
 442 static int brcm_fet_ack_interrupt(struct phy_device *phydev)
 443 {
 444         int reg;
 445
 446         /* Clear pending interrupts.  */
 447         reg = phy_read(phydev, MII_BRCM_FET_INTREG);
 448         if (reg < 0)
 449                 return reg;
 450
 451         return 0;
 452 }
 453
 454 static int brcm_fet_config_intr(struct phy_device *phydev)
 455 {
 456         int reg, err;
 457
 458         reg = phy_read(phydev, MII_BRCM_FET_INTREG);
 459         if (reg < 0)
 460                 return reg;
 461
 462         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 463                 reg &= ~MII_BRCM_FET_IR_MASK;
 464         else
 465                 reg |= MII_BRCM_FET_IR_MASK;
 466
 467         err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
 468         return err;
 469 }
 470
 471 static struct phy_driver broadcom_drivers[] = {
 472 {
 473         .phy_id         = PHY_ID_BCM5411,
 474         .phy_id_mask    = 0xfffffff0,
 475         .name           = "Broadcom BCM5411",
 476         .features       = PHY_GBIT_FEATURES |
 477                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 478         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 479         .config_init    = bcm54xx_config_init,
 480         .config_aneg    = genphy_config_aneg,
 481         .read_status    = genphy_read_status,
 482         .ack_interrupt  = bcm_phy_ack_intr,
 483         .config_intr    = bcm_phy_config_intr,
 484 }, {
 485         .phy_id         = PHY_ID_BCM5421,
 486         .phy_id_mask    = 0xfffffff0,
 487         .name           = "Broadcom BCM5421",
 488         .features       = PHY_GBIT_FEATURES |
 489                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 490         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 491         .config_init    = bcm54xx_config_init,
 492         .config_aneg    = genphy_config_aneg,
 493         .read_status    = genphy_read_status,
 494         .ack_interrupt  = bcm_phy_ack_intr,
 495         .config_intr    = bcm_phy_config_intr,
 496 }, {
 497         .phy_id         = PHY_ID_BCM5461,
 498         .phy_id_mask    = 0xfffffff0,
 499         .name           = "Broadcom BCM5461",
 500         .features       = PHY_GBIT_FEATURES |
 501                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 502         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 503         .config_init    = bcm54xx_config_init,
 504         .config_aneg    = genphy_config_aneg,
 505         .read_status    = genphy_read_status,
 506         .ack_interrupt  = bcm_phy_ack_intr,
 507         .config_intr    = bcm_phy_config_intr,
 508 }, {
 509         .phy_id         = PHY_ID_BCM54616S,
 510         .phy_id_mask    = 0xfffffff0,
 511         .name           = "Broadcom BCM54616S",
 512         .features       = PHY_GBIT_FEATURES |
 513                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 514         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 515         .config_init    = bcm54xx_config_init,
 516         .config_aneg    = genphy_config_aneg,
 517         .read_status    = genphy_read_status,
 518         .ack_interrupt  = bcm_phy_ack_intr,
 519         .config_intr    = bcm_phy_config_intr,
 520 }, {
 521         .phy_id         = PHY_ID_BCM5464,
 522         .phy_id_mask    = 0xfffffff0,
 523         .name           = "Broadcom BCM5464",
 524         .features       = PHY_GBIT_FEATURES |
 525                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 526         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 527         .config_init    = bcm54xx_config_init,
 528         .config_aneg    = genphy_config_aneg,
 529         .read_status    = genphy_read_status,
 530         .ack_interrupt  = bcm_phy_ack_intr,
 531         .config_intr    = bcm_phy_config_intr,
 532 }, {
 533         .phy_id         = PHY_ID_BCM5481,
 534         .phy_id_mask    = 0xfffffff0,
 535         .name           = "Broadcom BCM5481",
 536         .features       = PHY_GBIT_FEATURES |
 537                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 538         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 539         .config_init    = bcm54xx_config_init,
 540         .config_aneg    = bcm5481_config_aneg,
 541         .read_status    = genphy_read_status,
 542         .ack_interrupt  = bcm_phy_ack_intr,
 543         .config_intr    = bcm_phy_config_intr,
 544 }, {
 545         .phy_id         = PHY_ID_BCM5482,
 546         .phy_id_mask    = 0xfffffff0,
 547         .name           = "Broadcom BCM5482",
 548         .features       = PHY_GBIT_FEATURES |
 549                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 550         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 551         .config_init    = bcm5482_config_init,
 552         .config_aneg    = genphy_config_aneg,
 553         .read_status    = bcm5482_read_status,
 554         .ack_interrupt  = bcm_phy_ack_intr,
 555         .config_intr    = bcm_phy_config_intr,
 556 }, {
 557         .phy_id         = PHY_ID_BCM50610,
 558         .phy_id_mask    = 0xfffffff0,
 559         .name           = "Broadcom BCM50610",
 560         .features       = PHY_GBIT_FEATURES |
 561                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 562         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 563         .config_init    = bcm54xx_config_init,
 564         .config_aneg    = genphy_config_aneg,
 565         .read_status    = genphy_read_status,
 566         .ack_interrupt  = bcm_phy_ack_intr,
 567         .config_intr    = bcm_phy_config_intr,
 568 }, {
 569         .phy_id         = PHY_ID_BCM50610M,
 570         .phy_id_mask    = 0xfffffff0,
 571         .name           = "Broadcom BCM50610M",
 572         .features       = PHY_GBIT_FEATURES |
 573                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 574         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 575         .config_init    = bcm54xx_config_init,
 576         .config_aneg    = genphy_config_aneg,
 577         .read_status    = genphy_read_status,
 578         .ack_interrupt  = bcm_phy_ack_intr,
 579         .config_intr    = bcm_phy_config_intr,
 580 }, {
 581         .phy_id         = PHY_ID_BCM57780,
 582         .phy_id_mask    = 0xfffffff0,
 583         .name           = "Broadcom BCM57780",
 584         .features       = PHY_GBIT_FEATURES |
 585                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 586         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 587         .config_init    = bcm54xx_config_init,
 588         .config_aneg    = genphy_config_aneg,
 589         .read_status    = genphy_read_status,
 590         .ack_interrupt  = bcm_phy_ack_intr,
 591         .config_intr    = bcm_phy_config_intr,
 592 }, {
 593         .phy_id         = PHY_ID_BCMAC131,
 594         .phy_id_mask    = 0xfffffff0,
 595         .name           = "Broadcom BCMAC131",
 596         .features       = PHY_BASIC_FEATURES |
 597                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 598         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 599         .config_init    = brcm_fet_config_init,
 600         .config_aneg    = genphy_config_aneg,
 601         .read_status    = genphy_read_status,
 602         .ack_interrupt  = brcm_fet_ack_interrupt,
 603         .config_intr    = brcm_fet_config_intr,
 604 }, {
 605         .phy_id         = PHY_ID_BCM5241,
 606         .phy_id_mask    = 0xfffffff0,
 607         .name           = "Broadcom BCM5241",
 608         .features       = PHY_BASIC_FEATURES |
 609                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 610         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 611         .config_init    = brcm_fet_config_init,
 612         .config_aneg    = genphy_config_aneg,
 613         .read_status    = genphy_read_status,
 614         .ack_interrupt  = brcm_fet_ack_interrupt,
 615         .config_intr    = brcm_fet_config_intr,
 616 } };
 617
 618 module_phy_driver(broadcom_drivers);
 619
 620 static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
 621         { PHY_ID_BCM5411, 0xfffffff0 },
 622         { PHY_ID_BCM5421, 0xfffffff0 },
 623         { PHY_ID_BCM5461, 0xfffffff0 },
 624         { PHY_ID_BCM54616S, 0xfffffff0 },
 625         { PHY_ID_BCM5464, 0xfffffff0 },
 626         { PHY_ID_BCM5481, 0xfffffff0 },
 627         { PHY_ID_BCM5482, 0xfffffff0 },
 628         { PHY_ID_BCM50610, 0xfffffff0 },
 629         { PHY_ID_BCM50610M, 0xfffffff0 },
 630         { PHY_ID_BCM57780, 0xfffffff0 },
 631         { PHY_ID_BCMAC131, 0xfffffff0 },
 632         { PHY_ID_BCM5241, 0xfffffff0 },
 633         { }
 634 };
 635
 636 MODULE_DEVICE_TABLE(mdio, broadcom_tbl);