1 // SPDX-License-Identifier: GPL-2.0
2 // Broadcom BCM84881 NBASE-T PHY driver, as found on a SFP+ module.
3 // Copyright (C) 2019 Russell King, Deep Blue Solutions Ltd.
5 // Like the Marvell 88x3310, the Broadcom 84881 changes its host-side
6 // interface according to the operating speed between 10GBASE-R,
7 // 2500BASE-X and SGMII (but unlike the 88x3310, without the control
10 // This driver only supports those aspects of the PHY that I'm able to
11 // observe and test with the SFP+ module, which is an incomplete subset
12 // of what this PHY is able to support. For example, I only assume it
13 // supports a single lane Serdes connection, but it may be that the PHY
14 // is able to support more than that.
15 #include <linux/delay.h>
16 #include <linux/module.h>
17 #include <linux/phy.h>
23 static int bcm84881_wait_init(struct phy_device *phydev)
27 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
28 val, !(val & MDIO_CTRL1_RESET),
29 100000, 2000000, false);
32 static void bcm84881_fill_possible_interfaces(struct phy_device *phydev)
34 unsigned long *possible = phydev->possible_interfaces;
36 __set_bit(PHY_INTERFACE_MODE_SGMII, possible);
37 __set_bit(PHY_INTERFACE_MODE_2500BASEX, possible);
38 __set_bit(PHY_INTERFACE_MODE_10GBASER, possible);
41 static int bcm84881_config_init(struct phy_device *phydev)
43 bcm84881_fill_possible_interfaces(phydev);
45 switch (phydev->interface) {
46 case PHY_INTERFACE_MODE_SGMII:
47 case PHY_INTERFACE_MODE_2500BASEX:
48 case PHY_INTERFACE_MODE_10GBASER:
57 static int bcm84881_probe(struct phy_device *phydev)
59 /* This driver requires PMAPMD and AN blocks */
60 const u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
62 if (!phydev->is_c45 ||
63 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
69 static int bcm84881_get_features(struct phy_device *phydev)
73 ret = genphy_c45_pma_read_abilities(phydev);
77 /* Although the PHY sets bit 1.11.8, it does not support 10M modes */
78 linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
80 linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
86 static int bcm84881_config_aneg(struct phy_device *phydev)
92 /* Wait for the PHY to finish initialising, otherwise our
93 * advertisement may be overwritten.
95 ret = bcm84881_wait_init(phydev);
99 /* We don't support manual MDI control */
100 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
102 /* disabled autoneg doesn't seem to work with this PHY */
103 if (phydev->autoneg == AUTONEG_DISABLE)
106 ret = genphy_c45_an_config_aneg(phydev);
112 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
113 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
114 MDIO_AN_C22 + MII_CTRL1000,
115 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
122 return genphy_c45_check_and_restart_aneg(phydev, changed);
125 static int bcm84881_aneg_done(struct phy_device *phydev)
129 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
133 bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR);
137 return !!(val & MDIO_AN_STAT1_COMPLETE) &&
138 !!(bmsr & BMSR_ANEGCOMPLETE);
141 static int bcm84881_read_status(struct phy_device *phydev)
146 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
150 if (val & MDIO_AN_CTRL1_RESTART) {
155 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
159 bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR);
163 phydev->autoneg_complete = !!(val & MDIO_AN_STAT1_COMPLETE) &&
164 !!(bmsr & BMSR_ANEGCOMPLETE);
165 phydev->link = !!(val & MDIO_STAT1_LSTATUS) &&
166 !!(bmsr & BMSR_LSTATUS);
167 if (phydev->autoneg == AUTONEG_ENABLE && !phydev->autoneg_complete)
168 phydev->link = false;
170 linkmode_zero(phydev->lp_advertising);
171 phydev->speed = SPEED_UNKNOWN;
172 phydev->duplex = DUPLEX_UNKNOWN;
174 phydev->asym_pause = 0;
180 if (phydev->autoneg_complete) {
181 val = genphy_c45_read_lpa(phydev);
185 val = phy_read_mmd(phydev, MDIO_MMD_AN,
186 MDIO_AN_C22 + MII_STAT1000);
190 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
192 if (phydev->autoneg == AUTONEG_ENABLE)
193 phy_resolve_aneg_linkmode(phydev);
196 if (phydev->autoneg == AUTONEG_DISABLE) {
197 /* disabled autoneg doesn't seem to work, so force the link
204 /* Set the host link mode - we set the phy interface mode and
205 * the speed according to this register so that downshift works.
206 * We leave the duplex setting as per the resolution from the
209 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x4011);
210 mode = (val & 0x1e) >> 1;
211 if (mode == 1 || mode == 2)
212 phydev->interface = PHY_INTERFACE_MODE_SGMII;
214 phydev->interface = PHY_INTERFACE_MODE_10GBASER;
216 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
219 phydev->speed = SPEED_100;
222 phydev->speed = SPEED_1000;
225 phydev->speed = SPEED_10000;
228 phydev->speed = SPEED_2500;
231 phydev->speed = SPEED_5000;
235 return genphy_c45_read_mdix(phydev);
238 static struct phy_driver bcm84881_drivers[] = {
240 .phy_id = 0xae025150,
241 .phy_id_mask = 0xfffffff0,
242 .name = "Broadcom BCM84881",
243 .config_init = bcm84881_config_init,
244 .probe = bcm84881_probe,
245 .get_features = bcm84881_get_features,
246 .config_aneg = bcm84881_config_aneg,
247 .aneg_done = bcm84881_aneg_done,
248 .read_status = bcm84881_read_status,
252 module_phy_driver(bcm84881_drivers);
254 /* FIXME: module auto-loading for Clause 45 PHYs seems non-functional */
255 static struct mdio_device_id __maybe_unused bcm84881_tbl[] = {
256 { 0xae025150, 0xfffffff0 },
259 MODULE_AUTHOR("Russell King");
260 MODULE_DESCRIPTION("Broadcom BCM84881 PHY driver");
261 MODULE_DEVICE_TABLE(mdio, bcm84881_tbl);
262 MODULE_LICENSE("GPL");