1 // SPDX-License-Identifier: GPL-2.0+
2 /* Broadcom BCM54140 Quad SGMII/QSGMII Copper/Fiber Gigabit PHY
4 * Copyright (c) 2020 Michael Walle <michael@walle.cc>
7 #include <linux/bitfield.h>
8 #include <linux/brcmphy.h>
9 #include <linux/hwmon.h>
10 #include <linux/module.h>
11 #include <linux/phy.h>
13 #include "bcm-phy-lib.h"
15 /* RDB per-port registers
17 #define BCM54140_RDB_ISR 0x00a /* interrupt status */
18 #define BCM54140_RDB_IMR 0x00b /* interrupt mask */
19 #define BCM54140_RDB_INT_LINK BIT(1) /* link status changed */
20 #define BCM54140_RDB_INT_SPEED BIT(2) /* link speed change */
21 #define BCM54140_RDB_INT_DUPLEX BIT(3) /* duplex mode changed */
22 #define BCM54140_RDB_SPARE1 0x012 /* spare control 1 */
23 #define BCM54140_RDB_SPARE1_LSLM BIT(2) /* link speed LED mode */
24 #define BCM54140_RDB_SPARE2 0x014 /* spare control 2 */
25 #define BCM54140_RDB_SPARE2_WS_RTRY_DIS BIT(8) /* wirespeed retry disable */
26 #define BCM54140_RDB_SPARE2_WS_RTRY_LIMIT GENMASK(4, 2) /* retry limit */
27 #define BCM54140_RDB_SPARE3 0x015 /* spare control 3 */
28 #define BCM54140_RDB_SPARE3_BIT0 BIT(0)
29 #define BCM54140_RDB_LED_CTRL 0x019 /* LED control */
30 #define BCM54140_RDB_LED_CTRL_ACTLINK0 BIT(4)
31 #define BCM54140_RDB_LED_CTRL_ACTLINK1 BIT(8)
32 #define BCM54140_RDB_C_APWR 0x01a /* auto power down control */
33 #define BCM54140_RDB_C_APWR_SINGLE_PULSE BIT(8) /* single pulse */
34 #define BCM54140_RDB_C_APWR_APD_MODE_DIS 0 /* ADP disable */
35 #define BCM54140_RDB_C_APWR_APD_MODE_EN 1 /* ADP enable */
36 #define BCM54140_RDB_C_APWR_APD_MODE_DIS2 2 /* ADP disable */
37 #define BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG 3 /* ADP enable w/ aneg */
38 #define BCM54140_RDB_C_APWR_APD_MODE_MASK GENMASK(6, 5)
39 #define BCM54140_RDB_C_APWR_SLP_TIM_MASK BIT(4)/* sleep timer */
40 #define BCM54140_RDB_C_APWR_SLP_TIM_2_7 0 /* 2.7s */
41 #define BCM54140_RDB_C_APWR_SLP_TIM_5_4 1 /* 5.4s */
42 #define BCM54140_RDB_C_PWR 0x02a /* copper power control */
43 #define BCM54140_RDB_C_PWR_ISOLATE BIT(5) /* super isolate mode */
44 #define BCM54140_RDB_C_MISC_CTRL 0x02f /* misc copper control */
45 #define BCM54140_RDB_C_MISC_CTRL_WS_EN BIT(4) /* wirespeed enable */
47 /* RDB global registers
49 #define BCM54140_RDB_TOP_IMR 0x82d /* interrupt mask */
50 #define BCM54140_RDB_TOP_IMR_PORT0 BIT(4)
51 #define BCM54140_RDB_TOP_IMR_PORT1 BIT(5)
52 #define BCM54140_RDB_TOP_IMR_PORT2 BIT(6)
53 #define BCM54140_RDB_TOP_IMR_PORT3 BIT(7)
54 #define BCM54140_RDB_MON_CTRL 0x831 /* monitor control */
55 #define BCM54140_RDB_MON_CTRL_V_MODE BIT(3) /* voltage mode */
56 #define BCM54140_RDB_MON_CTRL_SEL_MASK GENMASK(2, 1)
57 #define BCM54140_RDB_MON_CTRL_SEL_TEMP 0 /* meassure temperature */
58 #define BCM54140_RDB_MON_CTRL_SEL_1V0 1 /* meassure AVDDL 1.0V */
59 #define BCM54140_RDB_MON_CTRL_SEL_3V3 2 /* meassure AVDDH 3.3V */
60 #define BCM54140_RDB_MON_CTRL_SEL_RR 3 /* meassure all round-robin */
61 #define BCM54140_RDB_MON_CTRL_PWR_DOWN BIT(0) /* power-down monitor */
62 #define BCM54140_RDB_MON_TEMP_VAL 0x832 /* temperature value */
63 #define BCM54140_RDB_MON_TEMP_MAX 0x833 /* temperature high thresh */
64 #define BCM54140_RDB_MON_TEMP_MIN 0x834 /* temperature low thresh */
65 #define BCM54140_RDB_MON_TEMP_DATA_MASK GENMASK(9, 0)
66 #define BCM54140_RDB_MON_1V0_VAL 0x835 /* AVDDL 1.0V value */
67 #define BCM54140_RDB_MON_1V0_MAX 0x836 /* AVDDL 1.0V high thresh */
68 #define BCM54140_RDB_MON_1V0_MIN 0x837 /* AVDDL 1.0V low thresh */
69 #define BCM54140_RDB_MON_1V0_DATA_MASK GENMASK(10, 0)
70 #define BCM54140_RDB_MON_3V3_VAL 0x838 /* AVDDH 3.3V value */
71 #define BCM54140_RDB_MON_3V3_MAX 0x839 /* AVDDH 3.3V high thresh */
72 #define BCM54140_RDB_MON_3V3_MIN 0x83a /* AVDDH 3.3V low thresh */
73 #define BCM54140_RDB_MON_3V3_DATA_MASK GENMASK(11, 0)
74 #define BCM54140_RDB_MON_ISR 0x83b /* interrupt status */
75 #define BCM54140_RDB_MON_ISR_3V3 BIT(2) /* AVDDH 3.3V alarm */
76 #define BCM54140_RDB_MON_ISR_1V0 BIT(1) /* AVDDL 1.0V alarm */
77 #define BCM54140_RDB_MON_ISR_TEMP BIT(0) /* temperature alarm */
79 /* According to the datasheet the formula is:
80 * T = 413.35 - (0.49055 * bits[9:0])
82 #define BCM54140_HWMON_TO_TEMP(v) (413350L - (v) * 491)
83 #define BCM54140_HWMON_FROM_TEMP(v) DIV_ROUND_CLOSEST_ULL(413350L - (v), 491)
85 /* According to the datasheet the formula is:
86 * U = bits[11:0] / 1024 * 220 / 0.2
89 * U = bits[11:0] / 4096 * 2514
91 #define BCM54140_HWMON_TO_IN_1V0(v) ((v) * 2514 >> 11)
92 #define BCM54140_HWMON_FROM_IN_1V0(v) DIV_ROUND_CLOSEST_ULL(((v) << 11), 2514)
94 /* According to the datasheet the formula is:
95 * U = bits[10:0] / 1024 * 880 / 0.7
98 * U = bits[10:0] / 2048 * 4400
100 #define BCM54140_HWMON_TO_IN_3V3(v) ((v) * 4400 >> 12)
101 #define BCM54140_HWMON_FROM_IN_3V3(v) DIV_ROUND_CLOSEST_ULL(((v) << 12), 4400)
103 #define BCM54140_HWMON_TO_IN(ch, v) ((ch) ? BCM54140_HWMON_TO_IN_3V3(v) \
104 : BCM54140_HWMON_TO_IN_1V0(v))
105 #define BCM54140_HWMON_FROM_IN(ch, v) ((ch) ? BCM54140_HWMON_FROM_IN_3V3(v) \
106 : BCM54140_HWMON_FROM_IN_1V0(v))
107 #define BCM54140_HWMON_IN_MASK(ch) ((ch) ? BCM54140_RDB_MON_3V3_DATA_MASK \
108 : BCM54140_RDB_MON_1V0_DATA_MASK)
109 #define BCM54140_HWMON_IN_VAL_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_VAL \
110 : BCM54140_RDB_MON_1V0_VAL)
111 #define BCM54140_HWMON_IN_MIN_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_MIN \
112 : BCM54140_RDB_MON_1V0_MIN)
113 #define BCM54140_HWMON_IN_MAX_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_MAX \
114 : BCM54140_RDB_MON_1V0_MAX)
115 #define BCM54140_HWMON_IN_ALARM_BIT(ch) ((ch) ? BCM54140_RDB_MON_ISR_3V3 \
116 : BCM54140_RDB_MON_ISR_1V0)
118 /* This PHY has two different PHY IDs depening on its MODE_SEL pin. This
119 * pin choses between 4x SGMII and QSGMII mode:
123 #define BCM54140_PHY_ID_MASK 0xffffffe8
125 #define BCM54140_PHY_ID_REV(phy_id) ((phy_id) & 0x7)
126 #define BCM54140_REV_B0 1
128 #define BCM54140_DEFAULT_DOWNSHIFT 5
129 #define BCM54140_MAX_DOWNSHIFT 9
131 enum bcm54140_global_phy {
132 BCM54140_BASE_ADDR = 0,
135 struct bcm54140_priv {
138 #if IS_ENABLED(CONFIG_HWMON)
139 /* protect the alarm bits */
140 struct mutex alarm_lock;
145 #if IS_ENABLED(CONFIG_HWMON)
146 static umode_t bcm54140_hwmon_is_visible(const void *data,
147 enum hwmon_sensor_types type,
148 u32 attr, int channel)
168 case hwmon_temp_input:
169 case hwmon_temp_alarm:
179 static int bcm54140_hwmon_read_alarm(struct device *dev, unsigned int bit,
182 struct phy_device *phydev = dev_get_drvdata(dev);
183 struct bcm54140_priv *priv = phydev->priv;
186 mutex_lock(&priv->alarm_lock);
188 /* latch any alarm bits */
189 tmp = bcm_phy_read_rdb(phydev, BCM54140_RDB_MON_ISR);
196 *val = !!(priv->alarm & bit);
200 mutex_unlock(&priv->alarm_lock);
204 static int bcm54140_hwmon_read_temp(struct device *dev, u32 attr, long *val)
206 struct phy_device *phydev = dev_get_drvdata(dev);
211 case hwmon_temp_input:
212 reg = BCM54140_RDB_MON_TEMP_VAL;
215 reg = BCM54140_RDB_MON_TEMP_MIN;
218 reg = BCM54140_RDB_MON_TEMP_MAX;
220 case hwmon_temp_alarm:
221 return bcm54140_hwmon_read_alarm(dev,
222 BCM54140_RDB_MON_ISR_TEMP,
228 tmp = bcm_phy_read_rdb(phydev, reg);
232 *val = BCM54140_HWMON_TO_TEMP(tmp & BCM54140_RDB_MON_TEMP_DATA_MASK);
237 static int bcm54140_hwmon_read_in(struct device *dev, u32 attr,
238 int channel, long *val)
240 struct phy_device *phydev = dev_get_drvdata(dev);
246 reg = BCM54140_HWMON_IN_VAL_REG(channel);
249 reg = BCM54140_HWMON_IN_MIN_REG(channel);
252 reg = BCM54140_HWMON_IN_MAX_REG(channel);
255 bit = BCM54140_HWMON_IN_ALARM_BIT(channel);
256 return bcm54140_hwmon_read_alarm(dev, bit, val);
261 tmp = bcm_phy_read_rdb(phydev, reg);
265 tmp &= BCM54140_HWMON_IN_MASK(channel);
266 *val = BCM54140_HWMON_TO_IN(channel, tmp);
271 static int bcm54140_hwmon_read(struct device *dev,
272 enum hwmon_sensor_types type, u32 attr,
273 int channel, long *val)
277 return bcm54140_hwmon_read_temp(dev, attr, val);
279 return bcm54140_hwmon_read_in(dev, attr, channel, val);
285 static const char *const bcm54140_hwmon_in_labels[] = {
290 static int bcm54140_hwmon_read_string(struct device *dev,
291 enum hwmon_sensor_types type, u32 attr,
292 int channel, const char **str)
298 *str = bcm54140_hwmon_in_labels[channel];
308 static int bcm54140_hwmon_write_temp(struct device *dev, u32 attr,
309 int channel, long val)
311 struct phy_device *phydev = dev_get_drvdata(dev);
312 u16 mask = BCM54140_RDB_MON_TEMP_DATA_MASK;
315 val = clamp_val(val, BCM54140_HWMON_TO_TEMP(mask),
316 BCM54140_HWMON_TO_TEMP(0));
320 reg = BCM54140_RDB_MON_TEMP_MIN;
323 reg = BCM54140_RDB_MON_TEMP_MAX;
329 return bcm_phy_modify_rdb(phydev, reg, mask,
330 BCM54140_HWMON_FROM_TEMP(val));
333 static int bcm54140_hwmon_write_in(struct device *dev, u32 attr,
334 int channel, long val)
336 struct phy_device *phydev = dev_get_drvdata(dev);
337 u16 mask = BCM54140_HWMON_IN_MASK(channel);
340 val = clamp_val(val, 0, BCM54140_HWMON_TO_IN(channel, mask));
344 reg = BCM54140_HWMON_IN_MIN_REG(channel);
347 reg = BCM54140_HWMON_IN_MAX_REG(channel);
353 return bcm_phy_modify_rdb(phydev, reg, mask,
354 BCM54140_HWMON_FROM_IN(channel, val));
357 static int bcm54140_hwmon_write(struct device *dev,
358 enum hwmon_sensor_types type, u32 attr,
359 int channel, long val)
363 return bcm54140_hwmon_write_temp(dev, attr, channel, val);
365 return bcm54140_hwmon_write_in(dev, attr, channel, val);
371 static const struct hwmon_channel_info * const bcm54140_hwmon_info[] = {
372 HWMON_CHANNEL_INFO(temp,
373 HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
375 HWMON_CHANNEL_INFO(in,
376 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
377 HWMON_I_ALARM | HWMON_I_LABEL,
378 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
379 HWMON_I_ALARM | HWMON_I_LABEL),
383 static const struct hwmon_ops bcm54140_hwmon_ops = {
384 .is_visible = bcm54140_hwmon_is_visible,
385 .read = bcm54140_hwmon_read,
386 .read_string = bcm54140_hwmon_read_string,
387 .write = bcm54140_hwmon_write,
390 static const struct hwmon_chip_info bcm54140_chip_info = {
391 .ops = &bcm54140_hwmon_ops,
392 .info = bcm54140_hwmon_info,
395 static int bcm54140_enable_monitoring(struct phy_device *phydev)
399 /* 3.3V voltage mode */
400 set = BCM54140_RDB_MON_CTRL_V_MODE;
402 /* select round-robin */
403 mask = BCM54140_RDB_MON_CTRL_SEL_MASK;
404 set |= FIELD_PREP(BCM54140_RDB_MON_CTRL_SEL_MASK,
405 BCM54140_RDB_MON_CTRL_SEL_RR);
407 /* remove power-down bit */
408 mask |= BCM54140_RDB_MON_CTRL_PWR_DOWN;
410 return bcm_phy_modify_rdb(phydev, BCM54140_RDB_MON_CTRL, mask, set);
413 static int bcm54140_probe_once(struct phy_device *phydev)
415 struct device *hwmon;
418 /* enable hardware monitoring */
419 ret = bcm54140_enable_monitoring(phydev);
423 hwmon = devm_hwmon_device_register_with_info(&phydev->mdio.dev,
427 return PTR_ERR_OR_ZERO(hwmon);
431 static int bcm54140_base_read_rdb(struct phy_device *phydev, u16 rdb)
435 phy_lock_mdio_bus(phydev);
436 ret = __phy_package_write(phydev, BCM54140_BASE_ADDR,
437 MII_BCM54XX_RDB_ADDR, rdb);
441 ret = __phy_package_read(phydev, BCM54140_BASE_ADDR,
442 MII_BCM54XX_RDB_DATA);
445 phy_unlock_mdio_bus(phydev);
449 static int bcm54140_base_write_rdb(struct phy_device *phydev,
454 phy_lock_mdio_bus(phydev);
455 ret = __phy_package_write(phydev, BCM54140_BASE_ADDR,
456 MII_BCM54XX_RDB_ADDR, rdb);
460 ret = __phy_package_write(phydev, BCM54140_BASE_ADDR,
461 MII_BCM54XX_RDB_DATA, val);
464 phy_unlock_mdio_bus(phydev);
468 /* Under some circumstances a core PLL may not lock, this will then prevent
469 * a successful link establishment. Restart the PLL after the voltages are
470 * stable to workaround this issue.
472 static int bcm54140_b0_workaround(struct phy_device *phydev)
477 spare3 = bcm_phy_read_rdb(phydev, BCM54140_RDB_SPARE3);
481 spare3 &= ~BCM54140_RDB_SPARE3_BIT0;
483 ret = bcm_phy_write_rdb(phydev, BCM54140_RDB_SPARE3, spare3);
487 ret = phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN);
491 ret = phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0);
495 spare3 |= BCM54140_RDB_SPARE3_BIT0;
497 return bcm_phy_write_rdb(phydev, BCM54140_RDB_SPARE3, spare3);
500 /* The BCM54140 is a quad PHY where only the first port has access to the
501 * global register. Thus we need to find out its PHY address.
504 static int bcm54140_get_base_addr_and_port(struct phy_device *phydev)
506 struct bcm54140_priv *priv = phydev->priv;
507 struct mii_bus *bus = phydev->mdio.bus;
508 int addr, min_addr, max_addr;
513 min_addr = phydev->mdio.addr;
514 max_addr = phydev->mdio.addr;
515 addr = phydev->mdio.addr;
517 /* We scan forward and backwards and look for PHYs which have the
518 * same phy_id like we do. Step 1 will scan forward, step 2
519 * backwards. Once we are finished, we have a min_addr and
520 * max_addr which resembles the range of PHY addresses of the same
521 * type of PHY. There is one caveat; there may be many PHYs of
522 * the same type, but we know that each PHY takes exactly 4
523 * consecutive addresses. Therefore we can deduce our offset
524 * to the base address of this quad PHY.
530 } else if (step == 1) {
538 if (addr < 0 || addr >= PHY_MAX_ADDR) {
539 addr = phydev->mdio.addr;
544 /* read the PHY id */
545 tmp = mdiobus_read(bus, addr, MII_PHYSID1);
549 tmp = mdiobus_read(bus, addr, MII_PHYSID2);
554 /* see if it is still the same PHY */
555 if ((phy_id & phydev->drv->phy_id_mask) !=
556 (phydev->drv->phy_id & phydev->drv->phy_id_mask)) {
557 addr = phydev->mdio.addr;
562 /* The range we get should be a multiple of four. Please note that both
563 * the min_addr and max_addr are inclusive. So we have to add one if we
566 if ((max_addr - min_addr + 1) % 4) {
567 dev_err(&phydev->mdio.dev,
568 "Detected Quad PHY IDs %d..%d doesn't make sense.\n",
573 priv->port = (phydev->mdio.addr - min_addr) % 4;
574 priv->base_addr = phydev->mdio.addr - priv->port;
579 static int bcm54140_probe(struct phy_device *phydev)
581 struct bcm54140_priv *priv;
584 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
590 ret = bcm54140_get_base_addr_and_port(phydev);
594 devm_phy_package_join(&phydev->mdio.dev, phydev, priv->base_addr, 0);
596 #if IS_ENABLED(CONFIG_HWMON)
597 mutex_init(&priv->alarm_lock);
599 if (phy_package_init_once(phydev)) {
600 ret = bcm54140_probe_once(phydev);
606 phydev_dbg(phydev, "probed (port %d, base PHY address %d)\n",
607 priv->port, priv->base_addr);
612 static int bcm54140_config_init(struct phy_device *phydev)
617 /* Apply hardware errata */
618 if (BCM54140_PHY_ID_REV(phydev->phy_id) == BCM54140_REV_B0) {
619 ret = bcm54140_b0_workaround(phydev);
624 /* Unmask events we are interested in. */
625 reg &= ~(BCM54140_RDB_INT_DUPLEX |
626 BCM54140_RDB_INT_SPEED |
627 BCM54140_RDB_INT_LINK);
628 ret = bcm_phy_write_rdb(phydev, BCM54140_RDB_IMR, reg);
632 /* LED1=LINKSPD[1], LED2=LINKSPD[2], LED3=LINK/ACTIVITY */
633 ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_SPARE1,
634 0, BCM54140_RDB_SPARE1_LSLM);
638 ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_LED_CTRL,
639 0, BCM54140_RDB_LED_CTRL_ACTLINK0);
643 /* disable super isolate mode */
644 return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_PWR,
645 BCM54140_RDB_C_PWR_ISOLATE, 0);
648 static irqreturn_t bcm54140_handle_interrupt(struct phy_device *phydev)
650 int irq_status, irq_mask;
652 irq_status = bcm_phy_read_rdb(phydev, BCM54140_RDB_ISR);
653 if (irq_status < 0) {
658 irq_mask = bcm_phy_read_rdb(phydev, BCM54140_RDB_IMR);
663 irq_mask = ~irq_mask;
665 if (!(irq_status & irq_mask))
668 phy_trigger_machine(phydev);
673 static int bcm54140_ack_intr(struct phy_device *phydev)
677 /* clear pending interrupts */
678 reg = bcm_phy_read_rdb(phydev, BCM54140_RDB_ISR);
685 static int bcm54140_config_intr(struct phy_device *phydev)
687 struct bcm54140_priv *priv = phydev->priv;
688 static const u16 port_to_imr_bit[] = {
689 BCM54140_RDB_TOP_IMR_PORT0, BCM54140_RDB_TOP_IMR_PORT1,
690 BCM54140_RDB_TOP_IMR_PORT2, BCM54140_RDB_TOP_IMR_PORT3,
694 if (priv->port >= ARRAY_SIZE(port_to_imr_bit))
697 reg = bcm54140_base_read_rdb(phydev, BCM54140_RDB_TOP_IMR);
701 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
702 err = bcm54140_ack_intr(phydev);
706 reg &= ~port_to_imr_bit[priv->port];
707 err = bcm54140_base_write_rdb(phydev, BCM54140_RDB_TOP_IMR, reg);
709 reg |= port_to_imr_bit[priv->port];
710 err = bcm54140_base_write_rdb(phydev, BCM54140_RDB_TOP_IMR, reg);
714 err = bcm54140_ack_intr(phydev);
720 static int bcm54140_get_downshift(struct phy_device *phydev, u8 *data)
724 val = bcm_phy_read_rdb(phydev, BCM54140_RDB_C_MISC_CTRL);
728 if (!(val & BCM54140_RDB_C_MISC_CTRL_WS_EN)) {
729 *data = DOWNSHIFT_DEV_DISABLE;
733 val = bcm_phy_read_rdb(phydev, BCM54140_RDB_SPARE2);
737 if (val & BCM54140_RDB_SPARE2_WS_RTRY_DIS)
740 *data = FIELD_GET(BCM54140_RDB_SPARE2_WS_RTRY_LIMIT, val) + 2;
745 static int bcm54140_set_downshift(struct phy_device *phydev, u8 cnt)
750 if (cnt > BCM54140_MAX_DOWNSHIFT && cnt != DOWNSHIFT_DEV_DEFAULT_COUNT)
754 return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_MISC_CTRL,
755 BCM54140_RDB_C_MISC_CTRL_WS_EN, 0);
757 if (cnt == DOWNSHIFT_DEV_DEFAULT_COUNT)
758 cnt = BCM54140_DEFAULT_DOWNSHIFT;
762 set = BCM54140_RDB_SPARE2_WS_RTRY_DIS;
764 mask = BCM54140_RDB_SPARE2_WS_RTRY_DIS;
765 mask |= BCM54140_RDB_SPARE2_WS_RTRY_LIMIT;
766 set = FIELD_PREP(BCM54140_RDB_SPARE2_WS_RTRY_LIMIT, cnt - 2);
768 ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_SPARE2,
773 return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_MISC_CTRL,
774 0, BCM54140_RDB_C_MISC_CTRL_WS_EN);
777 static int bcm54140_get_edpd(struct phy_device *phydev, u16 *tx_interval)
781 val = bcm_phy_read_rdb(phydev, BCM54140_RDB_C_APWR);
785 switch (FIELD_GET(BCM54140_RDB_C_APWR_APD_MODE_MASK, val)) {
786 case BCM54140_RDB_C_APWR_APD_MODE_DIS:
787 case BCM54140_RDB_C_APWR_APD_MODE_DIS2:
788 *tx_interval = ETHTOOL_PHY_EDPD_DISABLE;
790 case BCM54140_RDB_C_APWR_APD_MODE_EN:
791 case BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG:
792 switch (FIELD_GET(BCM54140_RDB_C_APWR_SLP_TIM_MASK, val)) {
793 case BCM54140_RDB_C_APWR_SLP_TIM_2_7:
796 case BCM54140_RDB_C_APWR_SLP_TIM_5_4:
805 static int bcm54140_set_edpd(struct phy_device *phydev, u16 tx_interval)
809 mask = BCM54140_RDB_C_APWR_APD_MODE_MASK;
810 if (tx_interval == ETHTOOL_PHY_EDPD_DISABLE)
811 set = FIELD_PREP(BCM54140_RDB_C_APWR_APD_MODE_MASK,
812 BCM54140_RDB_C_APWR_APD_MODE_DIS);
814 set = FIELD_PREP(BCM54140_RDB_C_APWR_APD_MODE_MASK,
815 BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG);
817 /* enable single pulse mode */
818 set |= BCM54140_RDB_C_APWR_SINGLE_PULSE;
820 /* set sleep timer */
821 mask |= BCM54140_RDB_C_APWR_SLP_TIM_MASK;
822 switch (tx_interval) {
823 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
824 case ETHTOOL_PHY_EDPD_DISABLE:
826 set |= BCM54140_RDB_C_APWR_SLP_TIM_2_7;
829 set |= BCM54140_RDB_C_APWR_SLP_TIM_5_4;
835 return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_APWR, mask, set);
838 static int bcm54140_get_tunable(struct phy_device *phydev,
839 struct ethtool_tunable *tuna, void *data)
842 case ETHTOOL_PHY_DOWNSHIFT:
843 return bcm54140_get_downshift(phydev, data);
844 case ETHTOOL_PHY_EDPD:
845 return bcm54140_get_edpd(phydev, data);
851 static int bcm54140_set_tunable(struct phy_device *phydev,
852 struct ethtool_tunable *tuna, const void *data)
855 case ETHTOOL_PHY_DOWNSHIFT:
856 return bcm54140_set_downshift(phydev, *(const u8 *)data);
857 case ETHTOOL_PHY_EDPD:
858 return bcm54140_set_edpd(phydev, *(const u16 *)data);
864 static struct phy_driver bcm54140_drivers[] = {
866 .phy_id = PHY_ID_BCM54140,
867 .phy_id_mask = BCM54140_PHY_ID_MASK,
868 .name = "Broadcom BCM54140",
869 .flags = PHY_POLL_CABLE_TEST,
870 .features = PHY_GBIT_FEATURES,
871 .config_init = bcm54140_config_init,
872 .handle_interrupt = bcm54140_handle_interrupt,
873 .config_intr = bcm54140_config_intr,
874 .probe = bcm54140_probe,
875 .suspend = genphy_suspend,
876 .resume = genphy_resume,
877 .soft_reset = genphy_soft_reset,
878 .get_tunable = bcm54140_get_tunable,
879 .set_tunable = bcm54140_set_tunable,
880 .cable_test_start = bcm_phy_cable_test_start_rdb,
881 .cable_test_get_status = bcm_phy_cable_test_get_status_rdb,
884 module_phy_driver(bcm54140_drivers);
886 static struct mdio_device_id __maybe_unused bcm54140_tbl[] = {
887 { PHY_ID_BCM54140, BCM54140_PHY_ID_MASK },
891 MODULE_AUTHOR("Michael Walle");
892 MODULE_DESCRIPTION("Broadcom BCM54140 PHY driver");
893 MODULE_DEVICE_TABLE(mdio, bcm54140_tbl);
894 MODULE_LICENSE("GPL");