1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015-2017 Broadcom
6 #include "bcm-phy-lib.h"
7 #include <linux/bitfield.h>
8 #include <linux/brcmphy.h>
9 #include <linux/export.h>
10 #include <linux/mdio.h>
11 #include <linux/module.h>
12 #include <linux/phy.h>
13 #include <linux/ethtool.h>
14 #include <linux/ethtool_netlink.h>
16 #define MII_BCM_CHANNEL_WIDTH 0x2000
17 #define BCM_CL45VEN_EEE_ADV 0x3c
19 int __bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val)
23 rc = __phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);
27 return __phy_write(phydev, MII_BCM54XX_EXP_DATA, val);
29 EXPORT_SYMBOL_GPL(__bcm_phy_write_exp);
31 int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val)
35 phy_lock_mdio_bus(phydev);
36 rc = __bcm_phy_write_exp(phydev, reg, val);
37 phy_unlock_mdio_bus(phydev);
41 EXPORT_SYMBOL_GPL(bcm_phy_write_exp);
43 int __bcm_phy_read_exp(struct phy_device *phydev, u16 reg)
47 val = __phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);
51 val = __phy_read(phydev, MII_BCM54XX_EXP_DATA);
53 /* Restore default value. It's O.K. if this write fails. */
54 __phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);
58 EXPORT_SYMBOL_GPL(__bcm_phy_read_exp);
60 int bcm_phy_read_exp(struct phy_device *phydev, u16 reg)
64 phy_lock_mdio_bus(phydev);
65 rc = __bcm_phy_read_exp(phydev, reg);
66 phy_unlock_mdio_bus(phydev);
70 EXPORT_SYMBOL_GPL(bcm_phy_read_exp);
72 int __bcm_phy_modify_exp(struct phy_device *phydev, u16 reg, u16 mask, u16 set)
76 ret = __phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);
80 ret = __phy_read(phydev, MII_BCM54XX_EXP_DATA);
84 new = (ret & ~mask) | set;
88 return __phy_write(phydev, MII_BCM54XX_EXP_DATA, new);
90 EXPORT_SYMBOL_GPL(__bcm_phy_modify_exp);
92 int bcm_phy_modify_exp(struct phy_device *phydev, u16 reg, u16 mask, u16 set)
96 phy_lock_mdio_bus(phydev);
97 ret = __bcm_phy_modify_exp(phydev, reg, mask, set);
98 phy_unlock_mdio_bus(phydev);
102 EXPORT_SYMBOL_GPL(bcm_phy_modify_exp);
104 int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
106 /* The register must be written to both the Shadow Register Select and
107 * the Shadow Read Register Selector
109 phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MASK |
110 regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT);
111 return phy_read(phydev, MII_BCM54XX_AUX_CTL);
113 EXPORT_SYMBOL_GPL(bcm54xx_auxctl_read);
115 int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
117 return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
119 EXPORT_SYMBOL(bcm54xx_auxctl_write);
121 int bcm_phy_write_misc(struct phy_device *phydev,
122 u16 reg, u16 chl, u16 val)
127 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL,
128 MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
132 tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
133 tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
134 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
138 tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg;
139 rc = bcm_phy_write_exp(phydev, tmp, val);
143 EXPORT_SYMBOL_GPL(bcm_phy_write_misc);
145 int bcm_phy_read_misc(struct phy_device *phydev,
151 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL,
152 MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
156 tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
157 tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
158 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
162 tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg;
163 rc = bcm_phy_read_exp(phydev, tmp);
167 EXPORT_SYMBOL_GPL(bcm_phy_read_misc);
169 int bcm_phy_ack_intr(struct phy_device *phydev)
173 /* Clear pending interrupts. */
174 reg = phy_read(phydev, MII_BCM54XX_ISR);
180 EXPORT_SYMBOL_GPL(bcm_phy_ack_intr);
182 int bcm_phy_config_intr(struct phy_device *phydev)
186 reg = phy_read(phydev, MII_BCM54XX_ECR);
190 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
191 reg &= ~MII_BCM54XX_ECR_IM;
193 reg |= MII_BCM54XX_ECR_IM;
195 return phy_write(phydev, MII_BCM54XX_ECR, reg);
197 EXPORT_SYMBOL_GPL(bcm_phy_config_intr);
199 int bcm_phy_read_shadow(struct phy_device *phydev, u16 shadow)
201 phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
202 return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));
204 EXPORT_SYMBOL_GPL(bcm_phy_read_shadow);
206 int bcm_phy_write_shadow(struct phy_device *phydev, u16 shadow,
209 return phy_write(phydev, MII_BCM54XX_SHD,
210 MII_BCM54XX_SHD_WRITE |
211 MII_BCM54XX_SHD_VAL(shadow) |
212 MII_BCM54XX_SHD_DATA(val));
214 EXPORT_SYMBOL_GPL(bcm_phy_write_shadow);
216 int __bcm_phy_read_rdb(struct phy_device *phydev, u16 rdb)
220 val = __phy_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
224 return __phy_read(phydev, MII_BCM54XX_RDB_DATA);
226 EXPORT_SYMBOL_GPL(__bcm_phy_read_rdb);
228 int bcm_phy_read_rdb(struct phy_device *phydev, u16 rdb)
232 phy_lock_mdio_bus(phydev);
233 ret = __bcm_phy_read_rdb(phydev, rdb);
234 phy_unlock_mdio_bus(phydev);
238 EXPORT_SYMBOL_GPL(bcm_phy_read_rdb);
240 int __bcm_phy_write_rdb(struct phy_device *phydev, u16 rdb, u16 val)
244 ret = __phy_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
248 return __phy_write(phydev, MII_BCM54XX_RDB_DATA, val);
250 EXPORT_SYMBOL_GPL(__bcm_phy_write_rdb);
252 int bcm_phy_write_rdb(struct phy_device *phydev, u16 rdb, u16 val)
256 phy_lock_mdio_bus(phydev);
257 ret = __bcm_phy_write_rdb(phydev, rdb, val);
258 phy_unlock_mdio_bus(phydev);
262 EXPORT_SYMBOL_GPL(bcm_phy_write_rdb);
264 int __bcm_phy_modify_rdb(struct phy_device *phydev, u16 rdb, u16 mask, u16 set)
268 ret = __phy_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
272 ret = __phy_read(phydev, MII_BCM54XX_RDB_DATA);
276 new = (ret & ~mask) | set;
280 return __phy_write(phydev, MII_BCM54XX_RDB_DATA, new);
282 EXPORT_SYMBOL_GPL(__bcm_phy_modify_rdb);
284 int bcm_phy_modify_rdb(struct phy_device *phydev, u16 rdb, u16 mask, u16 set)
288 phy_lock_mdio_bus(phydev);
289 ret = __bcm_phy_modify_rdb(phydev, rdb, mask, set);
290 phy_unlock_mdio_bus(phydev);
294 EXPORT_SYMBOL_GPL(bcm_phy_modify_rdb);
296 int bcm_phy_enable_apd(struct phy_device *phydev, bool dll_pwr_down)
301 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
305 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
306 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
309 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
314 val &= BCM_APD_CLR_MASK;
316 if (phydev->autoneg == AUTONEG_ENABLE)
317 val |= BCM54XX_SHD_APD_EN;
319 val |= BCM_NO_ANEG_APD_EN;
321 /* Enable energy detect single link pulse for easy wakeup */
322 val |= BCM_APD_SINGLELP_EN;
324 /* Enable Auto Power-Down (APD) for the PHY */
325 return bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
327 EXPORT_SYMBOL_GPL(bcm_phy_enable_apd);
329 int bcm_phy_set_eee(struct phy_device *phydev, bool enable)
333 /* Enable EEE at PHY level */
334 val = phy_read_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL);
339 val |= LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X;
341 val &= ~(LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X);
343 phy_write_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL, (u32)val);
346 val = phy_read_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV);
350 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
352 mask |= MDIO_EEE_1000T;
353 if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
355 mask |= MDIO_EEE_100TX;
362 phy_write_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV, (u32)val);
366 EXPORT_SYMBOL_GPL(bcm_phy_set_eee);
368 int bcm_phy_downshift_get(struct phy_device *phydev, u8 *count)
372 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
376 /* Check if wirespeed is enabled or not */
377 if (!(val & MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN)) {
378 *count = DOWNSHIFT_DEV_DISABLE;
382 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2);
386 /* Downgrade after one link attempt */
387 if (val & BCM54XX_SHD_SCR2_WSPD_RTRY_DIS) {
390 /* Downgrade after configured retry count */
391 val >>= BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
392 val &= BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK;
393 *count = val + BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET;
398 EXPORT_SYMBOL_GPL(bcm_phy_downshift_get);
400 int bcm_phy_downshift_set(struct phy_device *phydev, u8 count)
402 int val = 0, ret = 0;
404 /* Range check the number given */
405 if (count - BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET >
406 BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK &&
407 count != DOWNSHIFT_DEV_DEFAULT_COUNT) {
411 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
415 /* Se the write enable bit */
416 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
418 if (count == DOWNSHIFT_DEV_DISABLE) {
419 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN;
420 return bcm54xx_auxctl_write(phydev,
421 MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
424 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN;
425 ret = bcm54xx_auxctl_write(phydev,
426 MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
432 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2);
433 val &= ~(BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK <<
434 BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT |
435 BCM54XX_SHD_SCR2_WSPD_RTRY_DIS);
439 val |= BCM54XX_SHD_SCR2_WSPD_RTRY_DIS;
441 case DOWNSHIFT_DEV_DEFAULT_COUNT:
442 val |= 1 << BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
445 val |= (count - BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET) <<
446 BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
450 return bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR2, val);
452 EXPORT_SYMBOL_GPL(bcm_phy_downshift_set);
454 struct bcm_phy_hw_stat {
461 /* Counters freeze at either 0xffff or 0xff, better than nothing */
462 static const struct bcm_phy_hw_stat bcm_phy_hw_stats[] = {
463 { "phy_receive_errors", MII_BRCM_CORE_BASE12, 0, 16 },
464 { "phy_serdes_ber_errors", MII_BRCM_CORE_BASE13, 8, 8 },
465 { "phy_false_carrier_sense_errors", MII_BRCM_CORE_BASE13, 0, 8 },
466 { "phy_local_rcvr_nok", MII_BRCM_CORE_BASE14, 8, 8 },
467 { "phy_remote_rcv_nok", MII_BRCM_CORE_BASE14, 0, 8 },
470 int bcm_phy_get_sset_count(struct phy_device *phydev)
472 return ARRAY_SIZE(bcm_phy_hw_stats);
474 EXPORT_SYMBOL_GPL(bcm_phy_get_sset_count);
476 void bcm_phy_get_strings(struct phy_device *phydev, u8 *data)
480 for (i = 0; i < ARRAY_SIZE(bcm_phy_hw_stats); i++)
481 strlcpy(data + i * ETH_GSTRING_LEN,
482 bcm_phy_hw_stats[i].string, ETH_GSTRING_LEN);
484 EXPORT_SYMBOL_GPL(bcm_phy_get_strings);
486 /* Caller is supposed to provide appropriate storage for the library code to
487 * access the shadow copy
489 static u64 bcm_phy_get_stat(struct phy_device *phydev, u64 *shadow,
492 struct bcm_phy_hw_stat stat = bcm_phy_hw_stats[i];
496 val = phy_read(phydev, stat.reg);
501 val = val & ((1 << stat.bits) - 1);
509 void bcm_phy_get_stats(struct phy_device *phydev, u64 *shadow,
510 struct ethtool_stats *stats, u64 *data)
514 for (i = 0; i < ARRAY_SIZE(bcm_phy_hw_stats); i++)
515 data[i] = bcm_phy_get_stat(phydev, shadow, i);
517 EXPORT_SYMBOL_GPL(bcm_phy_get_stats);
519 void bcm_phy_r_rc_cal_reset(struct phy_device *phydev)
521 /* Reset R_CAL/RC_CAL Engine */
522 bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0010);
524 /* Disable Reset R_AL/RC_CAL Engine */
525 bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0000);
527 EXPORT_SYMBOL_GPL(bcm_phy_r_rc_cal_reset);
529 int bcm_phy_28nm_a0b0_afe_config_init(struct phy_device *phydev)
531 /* Increase VCO range to prevent unlocking problem of PLL at low
534 bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);
536 /* Change Ki to 011 */
537 bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);
539 /* Disable loading of TVCO buffer to bandgap, set bandgap trim
542 bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);
544 /* Adjust bias current trim by -3 */
545 bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b);
547 /* Switch to CORE_BASE1E */
548 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd);
550 bcm_phy_r_rc_cal_reset(phydev);
552 /* write AFE_RXCONFIG_0 */
553 bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
555 /* write AFE_RXCONFIG_1 */
556 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);
558 /* write AFE_RX_LP_COUNTER */
559 bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
561 /* write AFE_HPF_TRIM_OTHERS */
562 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);
564 /* write AFTE_TX_CONFIG */
565 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);
569 EXPORT_SYMBOL_GPL(bcm_phy_28nm_a0b0_afe_config_init);
571 int bcm_phy_enable_jumbo(struct phy_device *phydev)
575 ret = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL);
579 /* Enable extended length packet reception */
580 ret = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
581 ret | MII_BCM54XX_AUXCTL_ACTL_EXT_PKT_LEN);
585 /* Enable the elastic FIFO for raising the transmission limit from
586 * 4.5KB to 10KB, at the expense of an additional 16 ns in propagation
589 return phy_set_bits(phydev, MII_BCM54XX_ECR, MII_BCM54XX_ECR_FIFOE);
591 EXPORT_SYMBOL_GPL(bcm_phy_enable_jumbo);
593 static int __bcm_phy_enable_rdb_access(struct phy_device *phydev)
595 return __bcm_phy_write_exp(phydev, BCM54XX_EXP_REG7E, 0);
598 static int __bcm_phy_enable_legacy_access(struct phy_device *phydev)
600 return __bcm_phy_write_rdb(phydev, BCM54XX_RDB_REG0087,
601 BCM54XX_ACCESS_MODE_LEGACY_EN);
604 static int _bcm_phy_cable_test_start(struct phy_device *phydev, bool is_rdb)
609 /* Auto-negotiation must be enabled for cable diagnostics to work, but
610 * don't advertise any capabilities.
612 phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
613 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
614 phy_write(phydev, MII_CTRL1000, 0);
616 phy_lock_mdio_bus(phydev);
618 ret = __bcm_phy_enable_legacy_access(phydev);
623 mask = BCM54XX_ECD_CTRL_CROSS_SHORT_DIS | BCM54XX_ECD_CTRL_UNIT_MASK;
624 set = BCM54XX_ECD_CTRL_RUN | BCM54XX_ECD_CTRL_BREAK_LINK |
625 FIELD_PREP(BCM54XX_ECD_CTRL_UNIT_MASK,
626 BCM54XX_ECD_CTRL_UNIT_CM);
628 ret = __bcm_phy_modify_exp(phydev, BCM54XX_EXP_ECD_CTRL, mask, set);
631 /* re-enable the RDB access even if there was an error */
633 ret = __bcm_phy_enable_rdb_access(phydev) ? : ret;
635 phy_unlock_mdio_bus(phydev);
640 static int bcm_phy_cable_test_report_trans(int result)
643 case BCM54XX_ECD_FAULT_TYPE_OK:
644 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
645 case BCM54XX_ECD_FAULT_TYPE_OPEN:
646 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
647 case BCM54XX_ECD_FAULT_TYPE_SAME_SHORT:
648 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
649 case BCM54XX_ECD_FAULT_TYPE_CROSS_SHORT:
650 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
651 case BCM54XX_ECD_FAULT_TYPE_INVALID:
652 case BCM54XX_ECD_FAULT_TYPE_BUSY:
654 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
658 static bool bcm_phy_distance_valid(int result)
661 case BCM54XX_ECD_FAULT_TYPE_OPEN:
662 case BCM54XX_ECD_FAULT_TYPE_SAME_SHORT:
663 case BCM54XX_ECD_FAULT_TYPE_CROSS_SHORT:
669 static int bcm_phy_report_length(struct phy_device *phydev, int pair)
673 val = __bcm_phy_read_exp(phydev,
674 BCM54XX_EXP_ECD_PAIR_A_LENGTH_RESULTS + pair);
678 if (val == BCM54XX_ECD_LENGTH_RESULTS_INVALID)
681 ethnl_cable_test_fault_length(phydev, pair, val);
686 static int _bcm_phy_cable_test_get_status(struct phy_device *phydev,
687 bool *finished, bool is_rdb)
689 int pair_a, pair_b, pair_c, pair_d, ret;
693 phy_lock_mdio_bus(phydev);
696 ret = __bcm_phy_enable_legacy_access(phydev);
701 ret = __bcm_phy_read_exp(phydev, BCM54XX_EXP_ECD_CTRL);
705 if (ret & BCM54XX_ECD_CTRL_IN_PROGRESS) {
710 ret = __bcm_phy_read_exp(phydev, BCM54XX_EXP_ECD_FAULT_TYPE);
714 pair_a = FIELD_GET(BCM54XX_ECD_FAULT_TYPE_PAIR_A_MASK, ret);
715 pair_b = FIELD_GET(BCM54XX_ECD_FAULT_TYPE_PAIR_B_MASK, ret);
716 pair_c = FIELD_GET(BCM54XX_ECD_FAULT_TYPE_PAIR_C_MASK, ret);
717 pair_d = FIELD_GET(BCM54XX_ECD_FAULT_TYPE_PAIR_D_MASK, ret);
719 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
720 bcm_phy_cable_test_report_trans(pair_a));
721 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
722 bcm_phy_cable_test_report_trans(pair_b));
723 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
724 bcm_phy_cable_test_report_trans(pair_c));
725 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
726 bcm_phy_cable_test_report_trans(pair_d));
728 if (bcm_phy_distance_valid(pair_a))
729 bcm_phy_report_length(phydev, 0);
730 if (bcm_phy_distance_valid(pair_b))
731 bcm_phy_report_length(phydev, 1);
732 if (bcm_phy_distance_valid(pair_c))
733 bcm_phy_report_length(phydev, 2);
734 if (bcm_phy_distance_valid(pair_d))
735 bcm_phy_report_length(phydev, 3);
740 /* re-enable the RDB access even if there was an error */
742 ret = __bcm_phy_enable_rdb_access(phydev) ? : ret;
744 phy_unlock_mdio_bus(phydev);
749 int bcm_phy_cable_test_start(struct phy_device *phydev)
751 return _bcm_phy_cable_test_start(phydev, false);
753 EXPORT_SYMBOL_GPL(bcm_phy_cable_test_start);
755 int bcm_phy_cable_test_get_status(struct phy_device *phydev, bool *finished)
757 return _bcm_phy_cable_test_get_status(phydev, finished, false);
759 EXPORT_SYMBOL_GPL(bcm_phy_cable_test_get_status);
761 /* We assume that all PHYs which support RDB access can be switched to legacy
762 * mode. If, in the future, this is not true anymore, we have to re-implement
763 * this with RDB access.
765 int bcm_phy_cable_test_start_rdb(struct phy_device *phydev)
767 return _bcm_phy_cable_test_start(phydev, true);
769 EXPORT_SYMBOL_GPL(bcm_phy_cable_test_start_rdb);
771 int bcm_phy_cable_test_get_status_rdb(struct phy_device *phydev,
774 return _bcm_phy_cable_test_get_status(phydev, finished, true);
776 EXPORT_SYMBOL_GPL(bcm_phy_cable_test_get_status_rdb);
778 MODULE_DESCRIPTION("Broadcom PHY Library");
779 MODULE_LICENSE("GPL v2");
780 MODULE_AUTHOR("Broadcom Corporation");