GNU Linux-libre 4.19.314-gnu1
[releases.git] / drivers / net / phy / bcm-phy-lib.c
1 /*
2  * Copyright (C) 2015-2017 Broadcom
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation version 2.
7  *
8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9  * kind, whether express or implied; without even the implied warranty
10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11  * GNU General Public License for more details.
12  */
13
14 #include "bcm-phy-lib.h"
15 #include <linux/brcmphy.h>
16 #include <linux/export.h>
17 #include <linux/mdio.h>
18 #include <linux/module.h>
19 #include <linux/phy.h>
20 #include <linux/ethtool.h>
21
22 #define MII_BCM_CHANNEL_WIDTH     0x2000
23 #define BCM_CL45VEN_EEE_ADV       0x3c
24
25 int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val)
26 {
27         int rc;
28
29         rc = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);
30         if (rc < 0)
31                 return rc;
32
33         return phy_write(phydev, MII_BCM54XX_EXP_DATA, val);
34 }
35 EXPORT_SYMBOL_GPL(bcm_phy_write_exp);
36
37 int bcm_phy_read_exp(struct phy_device *phydev, u16 reg)
38 {
39         int val;
40
41         val = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);
42         if (val < 0)
43                 return val;
44
45         val = phy_read(phydev, MII_BCM54XX_EXP_DATA);
46
47         /* Restore default value.  It's O.K. if this write fails. */
48         phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);
49
50         return val;
51 }
52 EXPORT_SYMBOL_GPL(bcm_phy_read_exp);
53
54 int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
55 {
56         /* The register must be written to both the Shadow Register Select and
57          * the Shadow Read Register Selector
58          */
59         phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MASK |
60                   regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT);
61         return phy_read(phydev, MII_BCM54XX_AUX_CTL);
62 }
63 EXPORT_SYMBOL_GPL(bcm54xx_auxctl_read);
64
65 int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
66 {
67         return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
68 }
69 EXPORT_SYMBOL(bcm54xx_auxctl_write);
70
71 int bcm_phy_write_misc(struct phy_device *phydev,
72                        u16 reg, u16 chl, u16 val)
73 {
74         int rc;
75         int tmp;
76
77         rc = phy_write(phydev, MII_BCM54XX_AUX_CTL,
78                        MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
79         if (rc < 0)
80                 return rc;
81
82         tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
83         tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
84         rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
85         if (rc < 0)
86                 return rc;
87
88         tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg;
89         rc = bcm_phy_write_exp(phydev, tmp, val);
90
91         return rc;
92 }
93 EXPORT_SYMBOL_GPL(bcm_phy_write_misc);
94
95 int bcm_phy_read_misc(struct phy_device *phydev,
96                       u16 reg, u16 chl)
97 {
98         int rc;
99         int tmp;
100
101         rc = phy_write(phydev, MII_BCM54XX_AUX_CTL,
102                        MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
103         if (rc < 0)
104                 return rc;
105
106         tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
107         tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
108         rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
109         if (rc < 0)
110                 return rc;
111
112         tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg;
113         rc = bcm_phy_read_exp(phydev, tmp);
114
115         return rc;
116 }
117 EXPORT_SYMBOL_GPL(bcm_phy_read_misc);
118
119 int bcm_phy_ack_intr(struct phy_device *phydev)
120 {
121         int reg;
122
123         /* Clear pending interrupts.  */
124         reg = phy_read(phydev, MII_BCM54XX_ISR);
125         if (reg < 0)
126                 return reg;
127
128         return 0;
129 }
130 EXPORT_SYMBOL_GPL(bcm_phy_ack_intr);
131
132 int bcm_phy_config_intr(struct phy_device *phydev)
133 {
134         int reg;
135
136         reg = phy_read(phydev, MII_BCM54XX_ECR);
137         if (reg < 0)
138                 return reg;
139
140         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
141                 reg &= ~MII_BCM54XX_ECR_IM;
142         else
143                 reg |= MII_BCM54XX_ECR_IM;
144
145         return phy_write(phydev, MII_BCM54XX_ECR, reg);
146 }
147 EXPORT_SYMBOL_GPL(bcm_phy_config_intr);
148
149 int bcm_phy_read_shadow(struct phy_device *phydev, u16 shadow)
150 {
151         phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
152         return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));
153 }
154 EXPORT_SYMBOL_GPL(bcm_phy_read_shadow);
155
156 int bcm_phy_write_shadow(struct phy_device *phydev, u16 shadow,
157                          u16 val)
158 {
159         return phy_write(phydev, MII_BCM54XX_SHD,
160                          MII_BCM54XX_SHD_WRITE |
161                          MII_BCM54XX_SHD_VAL(shadow) |
162                          MII_BCM54XX_SHD_DATA(val));
163 }
164 EXPORT_SYMBOL_GPL(bcm_phy_write_shadow);
165
166 int bcm_phy_enable_apd(struct phy_device *phydev, bool dll_pwr_down)
167 {
168         int val;
169
170         if (dll_pwr_down) {
171                 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
172                 if (val < 0)
173                         return val;
174
175                 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
176                 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
177         }
178
179         val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
180         if (val < 0)
181                 return val;
182
183         /* Clear APD bits */
184         val &= BCM_APD_CLR_MASK;
185
186         if (phydev->autoneg == AUTONEG_ENABLE)
187                 val |= BCM54XX_SHD_APD_EN;
188         else
189                 val |= BCM_NO_ANEG_APD_EN;
190
191         /* Enable energy detect single link pulse for easy wakeup */
192         val |= BCM_APD_SINGLELP_EN;
193
194         /* Enable Auto Power-Down (APD) for the PHY */
195         return bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
196 }
197 EXPORT_SYMBOL_GPL(bcm_phy_enable_apd);
198
199 int bcm_phy_set_eee(struct phy_device *phydev, bool enable)
200 {
201         int val, mask = 0;
202
203         /* Enable EEE at PHY level */
204         val = phy_read_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL);
205         if (val < 0)
206                 return val;
207
208         if (enable)
209                 val |= LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X;
210         else
211                 val &= ~(LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X);
212
213         phy_write_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL, (u32)val);
214
215         /* Advertise EEE */
216         val = phy_read_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV);
217         if (val < 0)
218                 return val;
219
220         if (phydev->supported & SUPPORTED_1000baseT_Full)
221                 mask |= MDIO_EEE_1000T;
222         if (phydev->supported & SUPPORTED_100baseT_Full)
223                 mask |= MDIO_EEE_100TX;
224
225         if (enable)
226                 val |= mask;
227         else
228                 val &= ~mask;
229
230         phy_write_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV, (u32)val);
231
232         return 0;
233 }
234 EXPORT_SYMBOL_GPL(bcm_phy_set_eee);
235
236 int bcm_phy_downshift_get(struct phy_device *phydev, u8 *count)
237 {
238         int val;
239
240         val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
241         if (val < 0)
242                 return val;
243
244         /* Check if wirespeed is enabled or not */
245         if (!(val & MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN)) {
246                 *count = DOWNSHIFT_DEV_DISABLE;
247                 return 0;
248         }
249
250         val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2);
251         if (val < 0)
252                 return val;
253
254         /* Downgrade after one link attempt */
255         if (val & BCM54XX_SHD_SCR2_WSPD_RTRY_DIS) {
256                 *count = 1;
257         } else {
258                 /* Downgrade after configured retry count */
259                 val >>= BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
260                 val &= BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK;
261                 *count = val + BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET;
262         }
263
264         return 0;
265 }
266 EXPORT_SYMBOL_GPL(bcm_phy_downshift_get);
267
268 int bcm_phy_downshift_set(struct phy_device *phydev, u8 count)
269 {
270         int val = 0, ret = 0;
271
272         /* Range check the number given */
273         if (count - BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET >
274             BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK &&
275             count != DOWNSHIFT_DEV_DEFAULT_COUNT) {
276                 return -ERANGE;
277         }
278
279         val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
280         if (val < 0)
281                 return val;
282
283         /* Se the write enable bit */
284         val |= MII_BCM54XX_AUXCTL_MISC_WREN;
285
286         if (count == DOWNSHIFT_DEV_DISABLE) {
287                 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN;
288                 return bcm54xx_auxctl_write(phydev,
289                                             MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
290                                             val);
291         } else {
292                 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN;
293                 ret = bcm54xx_auxctl_write(phydev,
294                                            MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
295                                            val);
296                 if (ret < 0)
297                         return ret;
298         }
299
300         val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2);
301         val &= ~(BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK <<
302                  BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT |
303                  BCM54XX_SHD_SCR2_WSPD_RTRY_DIS);
304
305         switch (count) {
306         case 1:
307                 val |= BCM54XX_SHD_SCR2_WSPD_RTRY_DIS;
308                 break;
309         case DOWNSHIFT_DEV_DEFAULT_COUNT:
310                 val |= 1 << BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
311                 break;
312         default:
313                 val |= (count - BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET) <<
314                         BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
315                 break;
316         }
317
318         return bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR2, val);
319 }
320 EXPORT_SYMBOL_GPL(bcm_phy_downshift_set);
321
322 struct bcm_phy_hw_stat {
323         const char *string;
324         u8 reg;
325         u8 shift;
326         u8 bits;
327 };
328
329 /* Counters freeze at either 0xffff or 0xff, better than nothing */
330 static const struct bcm_phy_hw_stat bcm_phy_hw_stats[] = {
331         { "phy_receive_errors", MII_BRCM_CORE_BASE12, 0, 16 },
332         { "phy_serdes_ber_errors", MII_BRCM_CORE_BASE13, 8, 8 },
333         { "phy_false_carrier_sense_errors", MII_BRCM_CORE_BASE13, 0, 8 },
334         { "phy_local_rcvr_nok", MII_BRCM_CORE_BASE14, 8, 8 },
335         { "phy_remote_rcv_nok", MII_BRCM_CORE_BASE14, 0, 8 },
336 };
337
338 int bcm_phy_get_sset_count(struct phy_device *phydev)
339 {
340         return ARRAY_SIZE(bcm_phy_hw_stats);
341 }
342 EXPORT_SYMBOL_GPL(bcm_phy_get_sset_count);
343
344 void bcm_phy_get_strings(struct phy_device *phydev, u8 *data)
345 {
346         unsigned int i;
347
348         for (i = 0; i < ARRAY_SIZE(bcm_phy_hw_stats); i++)
349                 strlcpy(data + i * ETH_GSTRING_LEN,
350                         bcm_phy_hw_stats[i].string, ETH_GSTRING_LEN);
351 }
352 EXPORT_SYMBOL_GPL(bcm_phy_get_strings);
353
354 /* Caller is supposed to provide appropriate storage for the library code to
355  * access the shadow copy
356  */
357 static u64 bcm_phy_get_stat(struct phy_device *phydev, u64 *shadow,
358                             unsigned int i)
359 {
360         struct bcm_phy_hw_stat stat = bcm_phy_hw_stats[i];
361         int val;
362         u64 ret;
363
364         val = phy_read(phydev, stat.reg);
365         if (val < 0) {
366                 ret = U64_MAX;
367         } else {
368                 val >>= stat.shift;
369                 val = val & ((1 << stat.bits) - 1);
370                 shadow[i] += val;
371                 ret = shadow[i];
372         }
373
374         return ret;
375 }
376
377 void bcm_phy_get_stats(struct phy_device *phydev, u64 *shadow,
378                        struct ethtool_stats *stats, u64 *data)
379 {
380         unsigned int i;
381
382         for (i = 0; i < ARRAY_SIZE(bcm_phy_hw_stats); i++)
383                 data[i] = bcm_phy_get_stat(phydev, shadow, i);
384 }
385 EXPORT_SYMBOL_GPL(bcm_phy_get_stats);
386
387 MODULE_DESCRIPTION("Broadcom PHY Library");
388 MODULE_LICENSE("GPL v2");
389 MODULE_AUTHOR("Broadcom Corporation");