drivers/net/phy/at803x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/net/phy/at803x.c
   4  *
   5  * Driver for Qualcomm Atheros AR803x PHY
   6  *
   7  * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
   8  */
   9
  10 #include <linux/phy.h>
  11 #include <linux/module.h>
  12 #include <linux/string.h>
  13 #include <linux/netdevice.h>
  14 #include <linux/etherdevice.h>
  15 #include <linux/ethtool_netlink.h>
  16 #include <linux/bitfield.h>
  17 #include <linux/regulator/of_regulator.h>
  18 #include <linux/regulator/driver.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/of.h>
  21 #include <linux/phylink.h>
  22 #include <linux/sfp.h>
  23 #include <dt-bindings/net/qca-ar803x.h>
  24
  25 #define AT803X_SPECIFIC_FUNCTION_CONTROL        0x10
  26 #define AT803X_SFC_ASSERT_CRS                   BIT(11)
  27 #define AT803X_SFC_FORCE_LINK                   BIT(10)
  28 #define AT803X_SFC_MDI_CROSSOVER_MODE_M         GENMASK(6, 5)
  29 #define AT803X_SFC_AUTOMATIC_CROSSOVER          0x3
  30 #define AT803X_SFC_MANUAL_MDIX                  0x1
  31 #define AT803X_SFC_MANUAL_MDI                   0x0
  32 #define AT803X_SFC_SQE_TEST                     BIT(2)
  33 #define AT803X_SFC_POLARITY_REVERSAL            BIT(1)
  34 #define AT803X_SFC_DISABLE_JABBER               BIT(0)
  35
  36 #define AT803X_SPECIFIC_STATUS                  0x11
  37 #define AT803X_SS_SPEED_MASK                    GENMASK(15, 14)
  38 #define AT803X_SS_SPEED_1000                    2
  39 #define AT803X_SS_SPEED_100                     1
  40 #define AT803X_SS_SPEED_10                      0
  41 #define AT803X_SS_DUPLEX                        BIT(13)
  42 #define AT803X_SS_SPEED_DUPLEX_RESOLVED         BIT(11)
  43 #define AT803X_SS_MDIX                          BIT(6)
  44
  45 #define QCA808X_SS_SPEED_MASK                   GENMASK(9, 7)
  46 #define QCA808X_SS_SPEED_2500                   4
  47
  48 #define AT803X_INTR_ENABLE                      0x12
  49 #define AT803X_INTR_ENABLE_AUTONEG_ERR          BIT(15)
  50 #define AT803X_INTR_ENABLE_SPEED_CHANGED        BIT(14)
  51 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED       BIT(13)
  52 #define AT803X_INTR_ENABLE_PAGE_RECEIVED        BIT(12)
  53 #define AT803X_INTR_ENABLE_LINK_FAIL            BIT(11)
  54 #define AT803X_INTR_ENABLE_LINK_SUCCESS         BIT(10)
  55 #define AT803X_INTR_ENABLE_LINK_FAIL_BX         BIT(8)
  56 #define AT803X_INTR_ENABLE_LINK_SUCCESS_BX      BIT(7)
  57 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE  BIT(5)
  58 #define AT803X_INTR_ENABLE_POLARITY_CHANGED     BIT(1)
  59 #define AT803X_INTR_ENABLE_WOL                  BIT(0)
  60
  61 #define AT803X_INTR_STATUS                      0x13
  62
  63 #define AT803X_SMART_SPEED                      0x14
  64 #define AT803X_SMART_SPEED_ENABLE               BIT(5)
  65 #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK     GENMASK(4, 2)
  66 #define AT803X_SMART_SPEED_BYPASS_TIMER         BIT(1)
  67 #define AT803X_CDT                              0x16
  68 #define AT803X_CDT_MDI_PAIR_MASK                GENMASK(9, 8)
  69 #define AT803X_CDT_ENABLE_TEST                  BIT(0)
  70 #define AT803X_CDT_STATUS                       0x1c
  71 #define AT803X_CDT_STATUS_STAT_NORMAL           0
  72 #define AT803X_CDT_STATUS_STAT_SHORT            1
  73 #define AT803X_CDT_STATUS_STAT_OPEN             2
  74 #define AT803X_CDT_STATUS_STAT_FAIL             3
  75 #define AT803X_CDT_STATUS_STAT_MASK             GENMASK(9, 8)
  76 #define AT803X_CDT_STATUS_DELTA_TIME_MASK       GENMASK(7, 0)
  77 #define AT803X_LED_CONTROL                      0x18
  78
  79 #define AT803X_PHY_MMD3_WOL_CTRL                0x8012
  80 #define AT803X_WOL_EN                           BIT(5)
  81 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET         0x804C
  82 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET        0x804B
  83 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET        0x804A
  84 #define AT803X_REG_CHIP_CONFIG                  0x1f
  85 #define AT803X_BT_BX_REG_SEL                    0x8000
  86
  87 #define AT803X_DEBUG_ADDR                       0x1D
  88 #define AT803X_DEBUG_DATA                       0x1E
  89
  90 #define AT803X_MODE_CFG_MASK                    0x0F
  91 #define AT803X_MODE_CFG_BASET_RGMII             0x00
  92 #define AT803X_MODE_CFG_BASET_SGMII             0x01
  93 #define AT803X_MODE_CFG_BX1000_RGMII_50OHM      0x02
  94 #define AT803X_MODE_CFG_BX1000_RGMII_75OHM      0x03
  95 #define AT803X_MODE_CFG_BX1000_CONV_50OHM       0x04
  96 #define AT803X_MODE_CFG_BX1000_CONV_75OHM       0x05
  97 #define AT803X_MODE_CFG_FX100_RGMII_50OHM       0x06
  98 #define AT803X_MODE_CFG_FX100_CONV_50OHM        0x07
  99 #define AT803X_MODE_CFG_RGMII_AUTO_MDET         0x0B
 100 #define AT803X_MODE_CFG_FX100_RGMII_75OHM       0x0E
 101 #define AT803X_MODE_CFG_FX100_CONV_75OHM        0x0F
 102
 103 #define AT803X_PSSR                             0x11    /*PHY-Specific Status Register*/
 104 #define AT803X_PSSR_MR_AN_COMPLETE              0x0200
 105
 106 #define AT803X_DEBUG_ANALOG_TEST_CTRL           0x00
 107 #define QCA8327_DEBUG_MANU_CTRL_EN              BIT(2)
 108 #define QCA8337_DEBUG_MANU_CTRL_EN              GENMASK(3, 2)
 109 #define AT803X_DEBUG_RX_CLK_DLY_EN              BIT(15)
 110
 111 #define AT803X_DEBUG_SYSTEM_CTRL_MODE           0x05
 112 #define AT803X_DEBUG_TX_CLK_DLY_EN              BIT(8)
 113
 114 #define AT803X_DEBUG_REG_HIB_CTRL               0x0b
 115 #define   AT803X_DEBUG_HIB_CTRL_SEL_RST_80U     BIT(10)
 116 #define   AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE   BIT(13)
 117 #define   AT803X_DEBUG_HIB_CTRL_PS_HIB_EN       BIT(15)
 118
 119 #define AT803X_DEBUG_REG_3C                     0x3C
 120
 121 #define AT803X_DEBUG_REG_GREEN                  0x3D
 122 #define   AT803X_DEBUG_GATE_CLK_IN1000          BIT(6)
 123
 124 #define AT803X_DEBUG_REG_1F                     0x1F
 125 #define AT803X_DEBUG_PLL_ON                     BIT(2)
 126 #define AT803X_DEBUG_RGMII_1V8                  BIT(3)
 127
 128 #define MDIO_AZ_DEBUG                           0x800D
 129
 130 /* AT803x supports either the XTAL input pad, an internal PLL or the
 131  * DSP as clock reference for the clock output pad. The XTAL reference
 132  * is only used for 25 MHz output, all other frequencies need the PLL.
 133  * The DSP as a clock reference is used in synchronous ethernet
 134  * applications.
 135  *
 136  * By default the PLL is only enabled if there is a link. Otherwise
 137  * the PHY will go into low power state and disabled the PLL. You can
 138  * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
 139  * enabled.
 140  */
 141 #define AT803X_MMD7_CLK25M                      0x8016
 142 #define AT803X_CLK_OUT_MASK                     GENMASK(4, 2)
 143 #define AT803X_CLK_OUT_25MHZ_XTAL               0
 144 #define AT803X_CLK_OUT_25MHZ_DSP                1
 145 #define AT803X_CLK_OUT_50MHZ_PLL                2
 146 #define AT803X_CLK_OUT_50MHZ_DSP                3
 147 #define AT803X_CLK_OUT_62_5MHZ_PLL              4
 148 #define AT803X_CLK_OUT_62_5MHZ_DSP              5
 149 #define AT803X_CLK_OUT_125MHZ_PLL               6
 150 #define AT803X_CLK_OUT_125MHZ_DSP               7
 151
 152 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
 153  * but doesn't support choosing between XTAL/PLL and DSP.
 154  */
 155 #define AT8035_CLK_OUT_MASK                     GENMASK(4, 3)
 156
 157 #define AT803X_CLK_OUT_STRENGTH_MASK            GENMASK(8, 7)
 158 #define AT803X_CLK_OUT_STRENGTH_FULL            0
 159 #define AT803X_CLK_OUT_STRENGTH_HALF            1
 160 #define AT803X_CLK_OUT_STRENGTH_QUARTER         2
 161
 162 #define AT803X_DEFAULT_DOWNSHIFT                5
 163 #define AT803X_MIN_DOWNSHIFT                    2
 164 #define AT803X_MAX_DOWNSHIFT                    9
 165
 166 #define AT803X_MMD3_SMARTEEE_CTL1               0x805b
 167 #define AT803X_MMD3_SMARTEEE_CTL2               0x805c
 168 #define AT803X_MMD3_SMARTEEE_CTL3               0x805d
 169 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN        BIT(8)
 170
 171 #define ATH9331_PHY_ID                          0x004dd041
 172 #define ATH8030_PHY_ID                          0x004dd076
 173 #define ATH8031_PHY_ID                          0x004dd074
 174 #define ATH8032_PHY_ID                          0x004dd023
 175 #define ATH8035_PHY_ID                          0x004dd072
 176 #define AT8030_PHY_ID_MASK                      0xffffffef
 177
 178 #define QCA8081_PHY_ID                          0x004dd101
 179
 180 #define QCA8327_A_PHY_ID                        0x004dd033
 181 #define QCA8327_B_PHY_ID                        0x004dd034
 182 #define QCA8337_PHY_ID                          0x004dd036
 183 #define QCA9561_PHY_ID                          0x004dd042
 184 #define QCA8K_PHY_ID_MASK                       0xffffffff
 185
 186 #define QCA8K_DEVFLAGS_REVISION_MASK            GENMASK(2, 0)
 187
 188 #define AT803X_PAGE_FIBER                       0
 189 #define AT803X_PAGE_COPPER                      1
 190
 191 /* don't turn off internal PLL */
 192 #define AT803X_KEEP_PLL_ENABLED                 BIT(0)
 193 #define AT803X_DISABLE_SMARTEEE                 BIT(1)
 194
 195 /* disable hibernation mode */
 196 #define AT803X_DISABLE_HIBERNATION_MODE         BIT(2)
 197
 198 /* ADC threshold */
 199 #define QCA808X_PHY_DEBUG_ADC_THRESHOLD         0x2c80
 200 #define QCA808X_ADC_THRESHOLD_MASK              GENMASK(7, 0)
 201 #define QCA808X_ADC_THRESHOLD_80MV              0
 202 #define QCA808X_ADC_THRESHOLD_100MV             0xf0
 203 #define QCA808X_ADC_THRESHOLD_200MV             0x0f
 204 #define QCA808X_ADC_THRESHOLD_300MV             0xff
 205
 206 /* CLD control */
 207 #define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7         0x8007
 208 #define QCA808X_8023AZ_AFE_CTRL_MASK            GENMASK(8, 4)
 209 #define QCA808X_8023AZ_AFE_EN                   0x90
 210
 211 /* AZ control */
 212 #define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL       0x8008
 213 #define QCA808X_MMD3_AZ_TRAINING_VAL            0x1c32
 214
 215 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB     0x8014
 216 #define QCA808X_MSE_THRESHOLD_20DB_VALUE        0x529
 217
 218 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB     0x800E
 219 #define QCA808X_MSE_THRESHOLD_17DB_VALUE        0x341
 220
 221 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB     0x801E
 222 #define QCA808X_MSE_THRESHOLD_27DB_VALUE        0x419
 223
 224 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB     0x8020
 225 #define QCA808X_MSE_THRESHOLD_28DB_VALUE        0x341
 226
 227 #define QCA808X_PHY_MMD7_TOP_OPTION1            0x901c
 228 #define QCA808X_TOP_OPTION1_DATA                0x0
 229
 230 #define QCA808X_PHY_MMD3_DEBUG_1                0xa100
 231 #define QCA808X_MMD3_DEBUG_1_VALUE              0x9203
 232 #define QCA808X_PHY_MMD3_DEBUG_2                0xa101
 233 #define QCA808X_MMD3_DEBUG_2_VALUE              0x48ad
 234 #define QCA808X_PHY_MMD3_DEBUG_3                0xa103
 235 #define QCA808X_MMD3_DEBUG_3_VALUE              0x1698
 236 #define QCA808X_PHY_MMD3_DEBUG_4                0xa105
 237 #define QCA808X_MMD3_DEBUG_4_VALUE              0x8001
 238 #define QCA808X_PHY_MMD3_DEBUG_5                0xa106
 239 #define QCA808X_MMD3_DEBUG_5_VALUE              0x1111
 240 #define QCA808X_PHY_MMD3_DEBUG_6                0xa011
 241 #define QCA808X_MMD3_DEBUG_6_VALUE              0x5f85
 242
 243 /* master/slave seed config */
 244 #define QCA808X_PHY_DEBUG_LOCAL_SEED            9
 245 #define QCA808X_MASTER_SLAVE_SEED_ENABLE        BIT(1)
 246 #define QCA808X_MASTER_SLAVE_SEED_CFG           GENMASK(12, 2)
 247 #define QCA808X_MASTER_SLAVE_SEED_RANGE         0x32
 248
 249 /* Hibernation yields lower power consumpiton in contrast with normal operation mode.
 250  * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
 251  */
 252 #define QCA808X_DBG_AN_TEST                     0xb
 253 #define QCA808X_HIBERNATION_EN                  BIT(15)
 254
 255 #define QCA808X_CDT_ENABLE_TEST                 BIT(15)
 256 #define QCA808X_CDT_INTER_CHECK_DIS             BIT(13)
 257 #define QCA808X_CDT_STATUS                      BIT(11)
 258 #define QCA808X_CDT_LENGTH_UNIT                 BIT(10)
 259
 260 #define QCA808X_MMD3_CDT_STATUS                 0x8064
 261 #define QCA808X_MMD3_CDT_DIAG_PAIR_A            0x8065
 262 #define QCA808X_MMD3_CDT_DIAG_PAIR_B            0x8066
 263 #define QCA808X_MMD3_CDT_DIAG_PAIR_C            0x8067
 264 #define QCA808X_MMD3_CDT_DIAG_PAIR_D            0x8068
 265 #define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT      GENMASK(15, 8)
 266 #define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT     GENMASK(7, 0)
 267
 268 #define QCA808X_CDT_CODE_PAIR_A                 GENMASK(15, 12)
 269 #define QCA808X_CDT_CODE_PAIR_B                 GENMASK(11, 8)
 270 #define QCA808X_CDT_CODE_PAIR_C                 GENMASK(7, 4)
 271 #define QCA808X_CDT_CODE_PAIR_D                 GENMASK(3, 0)
 272
 273 #define QCA808X_CDT_STATUS_STAT_TYPE            GENMASK(1, 0)
 274 #define QCA808X_CDT_STATUS_STAT_FAIL            FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0)
 275 #define QCA808X_CDT_STATUS_STAT_NORMAL          FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1)
 276 #define QCA808X_CDT_STATUS_STAT_SAME_OPEN       FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2)
 277 #define QCA808X_CDT_STATUS_STAT_SAME_SHORT      FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3)
 278
 279 #define QCA808X_CDT_STATUS_STAT_MDI             GENMASK(3, 2)
 280 #define QCA808X_CDT_STATUS_STAT_MDI1            FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1)
 281 #define QCA808X_CDT_STATUS_STAT_MDI2            FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2)
 282 #define QCA808X_CDT_STATUS_STAT_MDI3            FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3)
 283
 284 /* NORMAL are MDI with type set to 0 */
 285 #define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL       QCA808X_CDT_STATUS_STAT_MDI1
 286 #define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN         (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
 287                                                                          QCA808X_CDT_STATUS_STAT_MDI1)
 288 #define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT        (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
 289                                                                          QCA808X_CDT_STATUS_STAT_MDI1)
 290 #define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL       QCA808X_CDT_STATUS_STAT_MDI2
 291 #define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN         (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
 292                                                                          QCA808X_CDT_STATUS_STAT_MDI2)
 293 #define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT        (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
 294                                                                          QCA808X_CDT_STATUS_STAT_MDI2)
 295 #define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL       QCA808X_CDT_STATUS_STAT_MDI3
 296 #define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN         (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
 297                                                                          QCA808X_CDT_STATUS_STAT_MDI3)
 298 #define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT        (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
 299                                                                          QCA808X_CDT_STATUS_STAT_MDI3)
 300
 301 /* Added for reference of existence but should be handled by wait_for_completion already */
 302 #define QCA808X_CDT_STATUS_STAT_BUSY            (BIT(1) | BIT(3))
 303
 304 /* QCA808X 1G chip type */
 305 #define QCA808X_PHY_MMD7_CHIP_TYPE              0x901d
 306 #define QCA808X_PHY_CHIP_TYPE_1G                BIT(0)
 307
 308 #define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL       0x9072
 309 #define QCA8081_PHY_FIFO_RSTN                   BIT(11)
 310
 311 MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
 312 MODULE_AUTHOR("Matus Ujhelyi");
 313 MODULE_LICENSE("GPL");
 314
 315 enum stat_access_type {
 316         PHY,
 317         MMD
 318 };
 319
 320 struct at803x_hw_stat {
 321         const char *string;
 322         u8 reg;
 323         u32 mask;
 324         enum stat_access_type access_type;
 325 };
 326
 327 static struct at803x_hw_stat qca83xx_hw_stats[] = {
 328         { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
 329         { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
 330         { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
 331 };
 332
 333 struct at803x_ss_mask {
 334         u16 speed_mask;
 335         u8 speed_shift;
 336 };
 337
 338 struct at803x_priv {
 339         int flags;
 340         u16 clk_25m_reg;
 341         u16 clk_25m_mask;
 342         u8 smarteee_lpi_tw_1g;
 343         u8 smarteee_lpi_tw_100m;
 344         bool is_fiber;
 345         bool is_1000basex;
 346         struct regulator_dev *vddio_rdev;
 347         struct regulator_dev *vddh_rdev;
 348         u64 stats[ARRAY_SIZE(qca83xx_hw_stats)];
 349 };
 350
 351 struct at803x_context {
 352         u16 bmcr;
 353         u16 advertise;
 354         u16 control1000;
 355         u16 int_enable;
 356         u16 smart_speed;
 357         u16 led_control;
 358 };
 359
 360 static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
 361 {
 362         int ret;
 363
 364         ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
 365         if (ret < 0)
 366                 return ret;
 367
 368         return phy_write(phydev, AT803X_DEBUG_DATA, data);
 369 }
 370
 371 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
 372 {
 373         int ret;
 374
 375         ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
 376         if (ret < 0)
 377                 return ret;
 378
 379         return phy_read(phydev, AT803X_DEBUG_DATA);
 380 }
 381
 382 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
 383                                  u16 clear, u16 set)
 384 {
 385         u16 val;
 386         int ret;
 387
 388         ret = at803x_debug_reg_read(phydev, reg);
 389         if (ret < 0)
 390                 return ret;
 391
 392         val = ret & 0xffff;
 393         val &= ~clear;
 394         val |= set;
 395
 396         return phy_write(phydev, AT803X_DEBUG_DATA, val);
 397 }
 398
 399 static int at803x_write_page(struct phy_device *phydev, int page)
 400 {
 401         int mask;
 402         int set;
 403
 404         if (page == AT803X_PAGE_COPPER) {
 405                 set = AT803X_BT_BX_REG_SEL;
 406                 mask = 0;
 407         } else {
 408                 set = 0;
 409                 mask = AT803X_BT_BX_REG_SEL;
 410         }
 411
 412         return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);
 413 }
 414
 415 static int at803x_read_page(struct phy_device *phydev)
 416 {
 417         int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);
 418
 419         if (ccr < 0)
 420                 return ccr;
 421
 422         if (ccr & AT803X_BT_BX_REG_SEL)
 423                 return AT803X_PAGE_COPPER;
 424
 425         return AT803X_PAGE_FIBER;
 426 }
 427
 428 static int at803x_enable_rx_delay(struct phy_device *phydev)
 429 {
 430         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0,
 431                                      AT803X_DEBUG_RX_CLK_DLY_EN);
 432 }
 433
 434 static int at803x_enable_tx_delay(struct phy_device *phydev)
 435 {
 436         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0,
 437                                      AT803X_DEBUG_TX_CLK_DLY_EN);
 438 }
 439
 440 static int at803x_disable_rx_delay(struct phy_device *phydev)
 441 {
 442         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
 443                                      AT803X_DEBUG_RX_CLK_DLY_EN, 0);
 444 }
 445
 446 static int at803x_disable_tx_delay(struct phy_device *phydev)
 447 {
 448         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,
 449                                      AT803X_DEBUG_TX_CLK_DLY_EN, 0);
 450 }
 451
 452 /* save relevant PHY registers to private copy */
 453 static void at803x_context_save(struct phy_device *phydev,
 454                                 struct at803x_context *context)
 455 {
 456         context->bmcr = phy_read(phydev, MII_BMCR);
 457         context->advertise = phy_read(phydev, MII_ADVERTISE);
 458         context->control1000 = phy_read(phydev, MII_CTRL1000);
 459         context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
 460         context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
 461         context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
 462 }
 463
 464 /* restore relevant PHY registers from private copy */
 465 static void at803x_context_restore(struct phy_device *phydev,
 466                                    const struct at803x_context *context)
 467 {
 468         phy_write(phydev, MII_BMCR, context->bmcr);
 469         phy_write(phydev, MII_ADVERTISE, context->advertise);
 470         phy_write(phydev, MII_CTRL1000, context->control1000);
 471         phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
 472         phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
 473         phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
 474 }
 475
 476 static int at803x_set_wol(struct phy_device *phydev,
 477                           struct ethtool_wolinfo *wol)
 478 {
 479         int ret, irq_enabled;
 480
 481         if (wol->wolopts & WAKE_MAGIC) {
 482                 struct net_device *ndev = phydev->attached_dev;
 483                 const u8 *mac;
 484                 unsigned int i;
 485                 static const unsigned int offsets[] = {
 486                         AT803X_LOC_MAC_ADDR_32_47_OFFSET,
 487                         AT803X_LOC_MAC_ADDR_16_31_OFFSET,
 488                         AT803X_LOC_MAC_ADDR_0_15_OFFSET,
 489                 };
 490
 491                 if (!ndev)
 492                         return -ENODEV;
 493
 494                 mac = (const u8 *)ndev->dev_addr;
 495
 496                 if (!is_valid_ether_addr(mac))
 497                         return -EINVAL;
 498
 499                 for (i = 0; i < 3; i++)
 500                         phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i],
 501                                       mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
 502
 503                 /* Enable WOL interrupt */
 504                 ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL);
 505                 if (ret)
 506                         return ret;
 507         } else {
 508                 /* Disable WOL interrupt */
 509                 ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0);
 510                 if (ret)
 511                         return ret;
 512         }
 513
 514         /* Clear WOL status */
 515         ret = phy_read(phydev, AT803X_INTR_STATUS);
 516         if (ret < 0)
 517                 return ret;
 518
 519         /* Check if there are other interrupts except for WOL triggered when PHY is
 520          * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can
 521          * be passed up to the interrupt PIN.
 522          */
 523         irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
 524         if (irq_enabled < 0)
 525                 return irq_enabled;
 526
 527         irq_enabled &= ~AT803X_INTR_ENABLE_WOL;
 528         if (ret & irq_enabled && !phy_polling_mode(phydev))
 529                 phy_trigger_machine(phydev);
 530
 531         return 0;
 532 }
 533
 534 static void at803x_get_wol(struct phy_device *phydev,
 535                            struct ethtool_wolinfo *wol)
 536 {
 537         int value;
 538
 539         wol->supported = WAKE_MAGIC;
 540         wol->wolopts = 0;
 541
 542         value = phy_read(phydev, AT803X_INTR_ENABLE);
 543         if (value < 0)
 544                 return;
 545
 546         if (value & AT803X_INTR_ENABLE_WOL)
 547                 wol->wolopts |= WAKE_MAGIC;
 548 }
 549
 550 static int qca83xx_get_sset_count(struct phy_device *phydev)
 551 {
 552         return ARRAY_SIZE(qca83xx_hw_stats);
 553 }
 554
 555 static void qca83xx_get_strings(struct phy_device *phydev, u8 *data)
 556 {
 557         int i;
 558
 559         for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) {
 560                 strscpy(data + i * ETH_GSTRING_LEN,
 561                         qca83xx_hw_stats[i].string, ETH_GSTRING_LEN);
 562         }
 563 }
 564
 565 static u64 qca83xx_get_stat(struct phy_device *phydev, int i)
 566 {
 567         struct at803x_hw_stat stat = qca83xx_hw_stats[i];
 568         struct at803x_priv *priv = phydev->priv;
 569         int val;
 570         u64 ret;
 571
 572         if (stat.access_type == MMD)
 573                 val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);
 574         else
 575                 val = phy_read(phydev, stat.reg);
 576
 577         if (val < 0) {
 578                 ret = U64_MAX;
 579         } else {
 580                 val = val & stat.mask;
 581                 priv->stats[i] += val;
 582                 ret = priv->stats[i];
 583         }
 584
 585         return ret;
 586 }
 587
 588 static void qca83xx_get_stats(struct phy_device *phydev,
 589                               struct ethtool_stats *stats, u64 *data)
 590 {
 591         int i;
 592
 593         for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++)
 594                 data[i] = qca83xx_get_stat(phydev, i);
 595 }
 596
 597 static int at803x_suspend(struct phy_device *phydev)
 598 {
 599         int value;
 600         int wol_enabled;
 601
 602         value = phy_read(phydev, AT803X_INTR_ENABLE);
 603         wol_enabled = value & AT803X_INTR_ENABLE_WOL;
 604
 605         if (wol_enabled)
 606                 value = BMCR_ISOLATE;
 607         else
 608                 value = BMCR_PDOWN;
 609
 610         phy_modify(phydev, MII_BMCR, 0, value);
 611
 612         return 0;
 613 }
 614
 615 static int at803x_resume(struct phy_device *phydev)
 616 {
 617         return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
 618 }
 619
 620 static int at803x_parse_dt(struct phy_device *phydev)
 621 {
 622         struct device_node *node = phydev->mdio.dev.of_node;
 623         struct at803x_priv *priv = phydev->priv;
 624         u32 freq, strength, tw;
 625         unsigned int sel;
 626         int ret;
 627
 628         if (!IS_ENABLED(CONFIG_OF_MDIO))
 629                 return 0;
 630
 631         if (of_property_read_bool(node, "qca,disable-smarteee"))
 632                 priv->flags |= AT803X_DISABLE_SMARTEEE;
 633
 634         if (of_property_read_bool(node, "qca,disable-hibernation-mode"))
 635                 priv->flags |= AT803X_DISABLE_HIBERNATION_MODE;
 636
 637         if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) {
 638                 if (!tw || tw > 255) {
 639                         phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
 640                         return -EINVAL;
 641                 }
 642                 priv->smarteee_lpi_tw_1g = tw;
 643         }
 644
 645         if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) {
 646                 if (!tw || tw > 255) {
 647                         phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
 648                         return -EINVAL;
 649                 }
 650                 priv->smarteee_lpi_tw_100m = tw;
 651         }
 652
 653         ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
 654         if (!ret) {
 655                 switch (freq) {
 656                 case 25000000:
 657                         sel = AT803X_CLK_OUT_25MHZ_XTAL;
 658                         break;
 659                 case 50000000:
 660                         sel = AT803X_CLK_OUT_50MHZ_PLL;
 661                         break;
 662                 case 62500000:
 663                         sel = AT803X_CLK_OUT_62_5MHZ_PLL;
 664                         break;
 665                 case 125000000:
 666                         sel = AT803X_CLK_OUT_125MHZ_PLL;
 667                         break;
 668                 default:
 669                         phydev_err(phydev, "invalid qca,clk-out-frequency\n");
 670                         return -EINVAL;
 671                 }
 672
 673                 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
 674                 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
 675         }
 676
 677         ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
 678         if (!ret) {
 679                 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
 680                 switch (strength) {
 681                 case AR803X_STRENGTH_FULL:
 682                         priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
 683                         break;
 684                 case AR803X_STRENGTH_HALF:
 685                         priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
 686                         break;
 687                 case AR803X_STRENGTH_QUARTER:
 688                         priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
 689                         break;
 690                 default:
 691                         phydev_err(phydev, "invalid qca,clk-out-strength\n");
 692                         return -EINVAL;
 693                 }
 694         }
 695
 696         return 0;
 697 }
 698
 699 static int at803x_probe(struct phy_device *phydev)
 700 {
 701         struct device *dev = &phydev->mdio.dev;
 702         struct at803x_priv *priv;
 703         int ret;
 704
 705         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 706         if (!priv)
 707                 return -ENOMEM;
 708
 709         phydev->priv = priv;
 710
 711         ret = at803x_parse_dt(phydev);
 712         if (ret)
 713                 return ret;
 714
 715         return 0;
 716 }
 717
 718 static int at803x_get_features(struct phy_device *phydev)
 719 {
 720         struct at803x_priv *priv = phydev->priv;
 721         int err;
 722
 723         err = genphy_read_abilities(phydev);
 724         if (err)
 725                 return err;
 726
 727         if (phydev->drv->phy_id != ATH8031_PHY_ID)
 728                 return 0;
 729
 730         /* AR8031/AR8033 have different status registers
 731          * for copper and fiber operation. However, the
 732          * extended status register is the same for both
 733          * operation modes.
 734          *
 735          * As a result of that, ESTATUS_1000_XFULL is set
 736          * to 1 even when operating in copper TP mode.
 737          *
 738          * Remove this mode from the supported link modes
 739          * when not operating in 1000BaseX mode.
 740          */
 741         if (!priv->is_1000basex)
 742                 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
 743                                    phydev->supported);
 744
 745         return 0;
 746 }
 747
 748 static int at803x_smarteee_config(struct phy_device *phydev)
 749 {
 750         struct at803x_priv *priv = phydev->priv;
 751         u16 mask = 0, val = 0;
 752         int ret;
 753
 754         if (priv->flags & AT803X_DISABLE_SMARTEEE)
 755                 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
 756                                       AT803X_MMD3_SMARTEEE_CTL3,
 757                                       AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0);
 758
 759         if (priv->smarteee_lpi_tw_1g) {
 760                 mask |= 0xff00;
 761                 val |= priv->smarteee_lpi_tw_1g << 8;
 762         }
 763         if (priv->smarteee_lpi_tw_100m) {
 764                 mask |= 0x00ff;
 765                 val |= priv->smarteee_lpi_tw_100m;
 766         }
 767         if (!mask)
 768                 return 0;
 769
 770         ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
 771                              mask, val);
 772         if (ret)
 773                 return ret;
 774
 775         return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
 776                               AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
 777                               AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
 778 }
 779
 780 static int at803x_clk_out_config(struct phy_device *phydev)
 781 {
 782         struct at803x_priv *priv = phydev->priv;
 783
 784         if (!priv->clk_25m_mask)
 785                 return 0;
 786
 787         return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
 788                               priv->clk_25m_mask, priv->clk_25m_reg);
 789 }
 790
 791 static int at8031_pll_config(struct phy_device *phydev)
 792 {
 793         struct at803x_priv *priv = phydev->priv;
 794
 795         /* The default after hardware reset is PLL OFF. After a soft reset, the
 796          * values are retained.
 797          */
 798         if (priv->flags & AT803X_KEEP_PLL_ENABLED)
 799                 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
 800                                              0, AT803X_DEBUG_PLL_ON);
 801         else
 802                 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
 803                                              AT803X_DEBUG_PLL_ON, 0);
 804 }
 805
 806 static int at803x_hibernation_mode_config(struct phy_device *phydev)
 807 {
 808         struct at803x_priv *priv = phydev->priv;
 809
 810         /* The default after hardware reset is hibernation mode enabled. After
 811          * software reset, the value is retained.
 812          */
 813         if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE))
 814                 return 0;
 815
 816         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
 817                                          AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0);
 818 }
 819
 820 static int at803x_config_init(struct phy_device *phydev)
 821 {
 822         int ret;
 823
 824         /* The RX and TX delay default is:
 825          *   after HW reset: RX delay enabled and TX delay disabled
 826          *   after SW reset: RX delay enabled, while TX delay retains the
 827          *   value before reset.
 828          */
 829         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 830             phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 831                 ret = at803x_enable_rx_delay(phydev);
 832         else
 833                 ret = at803x_disable_rx_delay(phydev);
 834         if (ret < 0)
 835                 return ret;
 836
 837         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 838             phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 839                 ret = at803x_enable_tx_delay(phydev);
 840         else
 841                 ret = at803x_disable_tx_delay(phydev);
 842         if (ret < 0)
 843                 return ret;
 844
 845         ret = at803x_smarteee_config(phydev);
 846         if (ret < 0)
 847                 return ret;
 848
 849         ret = at803x_clk_out_config(phydev);
 850         if (ret < 0)
 851                 return ret;
 852
 853         ret = at803x_hibernation_mode_config(phydev);
 854         if (ret < 0)
 855                 return ret;
 856
 857         /* Ar803x extended next page bit is enabled by default. Cisco
 858          * multigig switches read this bit and attempt to negotiate 10Gbps
 859          * rates even if the next page bit is disabled. This is incorrect
 860          * behaviour but we still need to accommodate it. XNP is only needed
 861          * for 10Gbps support, so disable XNP.
 862          */
 863         return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0);
 864 }
 865
 866 static int at803x_ack_interrupt(struct phy_device *phydev)
 867 {
 868         int err;
 869
 870         err = phy_read(phydev, AT803X_INTR_STATUS);
 871
 872         return (err < 0) ? err : 0;
 873 }
 874
 875 static int at803x_config_intr(struct phy_device *phydev)
 876 {
 877         int err;
 878         int value;
 879
 880         value = phy_read(phydev, AT803X_INTR_ENABLE);
 881
 882         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 883                 /* Clear any pending interrupts */
 884                 err = at803x_ack_interrupt(phydev);
 885                 if (err)
 886                         return err;
 887
 888                 value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
 889                 value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
 890                 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
 891                 value |= AT803X_INTR_ENABLE_LINK_FAIL;
 892                 value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
 893
 894                 err = phy_write(phydev, AT803X_INTR_ENABLE, value);
 895         } else {
 896                 err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
 897                 if (err)
 898                         return err;
 899
 900                 /* Clear any pending interrupts */
 901                 err = at803x_ack_interrupt(phydev);
 902         }
 903
 904         return err;
 905 }
 906
 907 static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev)
 908 {
 909         int irq_status, int_enabled;
 910
 911         irq_status = phy_read(phydev, AT803X_INTR_STATUS);
 912         if (irq_status < 0) {
 913                 phy_error(phydev);
 914                 return IRQ_NONE;
 915         }
 916
 917         /* Read the current enabled interrupts */
 918         int_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
 919         if (int_enabled < 0) {
 920                 phy_error(phydev);
 921                 return IRQ_NONE;
 922         }
 923
 924         /* See if this was one of our enabled interrupts */
 925         if (!(irq_status & int_enabled))
 926                 return IRQ_NONE;
 927
 928         phy_trigger_machine(phydev);
 929
 930         return IRQ_HANDLED;
 931 }
 932
 933 static void at803x_link_change_notify(struct phy_device *phydev)
 934 {
 935         /*
 936          * Conduct a hardware reset for AT8030 every time a link loss is
 937          * signalled. This is necessary to circumvent a hardware bug that
 938          * occurs when the cable is unplugged while TX packets are pending
 939          * in the FIFO. In such cases, the FIFO enters an error mode it
 940          * cannot recover from by software.
 941          */
 942         if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
 943                 struct at803x_context context;
 944
 945                 at803x_context_save(phydev, &context);
 946
 947                 phy_device_reset(phydev, 1);
 948                 usleep_range(1000, 2000);
 949                 phy_device_reset(phydev, 0);
 950                 usleep_range(1000, 2000);
 951
 952                 at803x_context_restore(phydev, &context);
 953
 954                 phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
 955         }
 956 }
 957
 958 static int at803x_read_specific_status(struct phy_device *phydev,
 959                                        struct at803x_ss_mask ss_mask)
 960 {
 961         int ss;
 962
 963         /* Read the AT8035 PHY-Specific Status register, which indicates the
 964          * speed and duplex that the PHY is actually using, irrespective of
 965          * whether we are in autoneg mode or not.
 966          */
 967         ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
 968         if (ss < 0)
 969                 return ss;
 970
 971         if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
 972                 int sfc, speed;
 973
 974                 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
 975                 if (sfc < 0)
 976                         return sfc;
 977
 978                 speed = ss & ss_mask.speed_mask;
 979                 speed >>= ss_mask.speed_shift;
 980
 981                 switch (speed) {
 982                 case AT803X_SS_SPEED_10:
 983                         phydev->speed = SPEED_10;
 984                         break;
 985                 case AT803X_SS_SPEED_100:
 986                         phydev->speed = SPEED_100;
 987                         break;
 988                 case AT803X_SS_SPEED_1000:
 989                         phydev->speed = SPEED_1000;
 990                         break;
 991                 case QCA808X_SS_SPEED_2500:
 992                         phydev->speed = SPEED_2500;
 993                         break;
 994                 }
 995                 if (ss & AT803X_SS_DUPLEX)
 996                         phydev->duplex = DUPLEX_FULL;
 997                 else
 998                         phydev->duplex = DUPLEX_HALF;
 999
1000                 if (ss & AT803X_SS_MDIX)
1001                         phydev->mdix = ETH_TP_MDI_X;
1002                 else
1003                         phydev->mdix = ETH_TP_MDI;
1004
1005                 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
1006                 case AT803X_SFC_MANUAL_MDI:
1007                         phydev->mdix_ctrl = ETH_TP_MDI;
1008                         break;
1009                 case AT803X_SFC_MANUAL_MDIX:
1010                         phydev->mdix_ctrl = ETH_TP_MDI_X;
1011                         break;
1012                 case AT803X_SFC_AUTOMATIC_CROSSOVER:
1013                         phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1014                         break;
1015                 }
1016         }
1017
1018         return 0;
1019 }
1020
1021 static int at803x_read_status(struct phy_device *phydev)
1022 {
1023         struct at803x_ss_mask ss_mask = { 0 };
1024         int err, old_link = phydev->link;
1025
1026         /* Update the link, but return if there was an error */
1027         err = genphy_update_link(phydev);
1028         if (err)
1029                 return err;
1030
1031         /* why bother the PHY if nothing can have changed */
1032         if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
1033                 return 0;
1034
1035         phydev->speed = SPEED_UNKNOWN;
1036         phydev->duplex = DUPLEX_UNKNOWN;
1037         phydev->pause = 0;
1038         phydev->asym_pause = 0;
1039
1040         err = genphy_read_lpa(phydev);
1041         if (err < 0)
1042                 return err;
1043
1044         ss_mask.speed_mask = AT803X_SS_SPEED_MASK;
1045         ss_mask.speed_shift = __bf_shf(AT803X_SS_SPEED_MASK);
1046         err = at803x_read_specific_status(phydev, ss_mask);
1047         if (err < 0)
1048                 return err;
1049
1050         if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
1051                 phy_resolve_aneg_pause(phydev);
1052
1053         return 0;
1054 }
1055
1056 static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
1057 {
1058         u16 val;
1059
1060         switch (ctrl) {
1061         case ETH_TP_MDI:
1062                 val = AT803X_SFC_MANUAL_MDI;
1063                 break;
1064         case ETH_TP_MDI_X:
1065                 val = AT803X_SFC_MANUAL_MDIX;
1066                 break;
1067         case ETH_TP_MDI_AUTO:
1068                 val = AT803X_SFC_AUTOMATIC_CROSSOVER;
1069                 break;
1070         default:
1071                 return 0;
1072         }
1073
1074         return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
1075                           AT803X_SFC_MDI_CROSSOVER_MODE_M,
1076                           FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
1077 }
1078
1079 static int at803x_prepare_config_aneg(struct phy_device *phydev)
1080 {
1081         int ret;
1082
1083         ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
1084         if (ret < 0)
1085                 return ret;
1086
1087         /* Changes of the midx bits are disruptive to the normal operation;
1088          * therefore any changes to these registers must be followed by a
1089          * software reset to take effect.
1090          */
1091         if (ret == 1) {
1092                 ret = genphy_soft_reset(phydev);
1093                 if (ret < 0)
1094                         return ret;
1095         }
1096
1097         return 0;
1098 }
1099
1100 static int at803x_config_aneg(struct phy_device *phydev)
1101 {
1102         struct at803x_priv *priv = phydev->priv;
1103         int ret;
1104
1105         ret = at803x_prepare_config_aneg(phydev);
1106         if (ret)
1107                 return ret;
1108
1109         if (priv->is_1000basex)
1110                 return genphy_c37_config_aneg(phydev);
1111
1112         return genphy_config_aneg(phydev);
1113 }
1114
1115 static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
1116 {
1117         int val;
1118
1119         val = phy_read(phydev, AT803X_SMART_SPEED);
1120         if (val < 0)
1121                 return val;
1122
1123         if (val & AT803X_SMART_SPEED_ENABLE)
1124                 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
1125         else
1126                 *d = DOWNSHIFT_DEV_DISABLE;
1127
1128         return 0;
1129 }
1130
1131 static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
1132 {
1133         u16 mask, set;
1134         int ret;
1135
1136         switch (cnt) {
1137         case DOWNSHIFT_DEV_DEFAULT_COUNT:
1138                 cnt = AT803X_DEFAULT_DOWNSHIFT;
1139                 fallthrough;
1140         case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
1141                 set = AT803X_SMART_SPEED_ENABLE |
1142                       AT803X_SMART_SPEED_BYPASS_TIMER |
1143                       FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
1144                 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
1145                 break;
1146         case DOWNSHIFT_DEV_DISABLE:
1147                 set = 0;
1148                 mask = AT803X_SMART_SPEED_ENABLE |
1149                        AT803X_SMART_SPEED_BYPASS_TIMER;
1150                 break;
1151         default:
1152                 return -EINVAL;
1153         }
1154
1155         ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
1156
1157         /* After changing the smart speed settings, we need to perform a
1158          * software reset, use phy_init_hw() to make sure we set the
1159          * reapply any values which might got lost during software reset.
1160          */
1161         if (ret == 1)
1162                 ret = phy_init_hw(phydev);
1163
1164         return ret;
1165 }
1166
1167 static int at803x_get_tunable(struct phy_device *phydev,
1168                               struct ethtool_tunable *tuna, void *data)
1169 {
1170         switch (tuna->id) {
1171         case ETHTOOL_PHY_DOWNSHIFT:
1172                 return at803x_get_downshift(phydev, data);
1173         default:
1174                 return -EOPNOTSUPP;
1175         }
1176 }
1177
1178 static int at803x_set_tunable(struct phy_device *phydev,
1179                               struct ethtool_tunable *tuna, const void *data)
1180 {
1181         switch (tuna->id) {
1182         case ETHTOOL_PHY_DOWNSHIFT:
1183                 return at803x_set_downshift(phydev, *(const u8 *)data);
1184         default:
1185                 return -EOPNOTSUPP;
1186         }
1187 }
1188
1189 static int at803x_cable_test_result_trans(u16 status)
1190 {
1191         switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1192         case AT803X_CDT_STATUS_STAT_NORMAL:
1193                 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1194         case AT803X_CDT_STATUS_STAT_SHORT:
1195                 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1196         case AT803X_CDT_STATUS_STAT_OPEN:
1197                 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1198         case AT803X_CDT_STATUS_STAT_FAIL:
1199         default:
1200                 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1201         }
1202 }
1203
1204 static bool at803x_cdt_test_failed(u16 status)
1205 {
1206         return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
1207                 AT803X_CDT_STATUS_STAT_FAIL;
1208 }
1209
1210 static bool at803x_cdt_fault_length_valid(u16 status)
1211 {
1212         switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1213         case AT803X_CDT_STATUS_STAT_OPEN:
1214         case AT803X_CDT_STATUS_STAT_SHORT:
1215                 return true;
1216         }
1217         return false;
1218 }
1219
1220 static int at803x_cdt_fault_length(int dt)
1221 {
1222         /* According to the datasheet the distance to the fault is
1223          * DELTA_TIME * 0.824 meters.
1224          *
1225          * The author suspect the correct formula is:
1226          *
1227          *   fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
1228          *
1229          * where c is the speed of light, VF is the velocity factor of
1230          * the twisted pair cable, 125MHz the counter frequency and
1231          * we need to divide by 2 because the hardware will measure the
1232          * round trip time to the fault and back to the PHY.
1233          *
1234          * With a VF of 0.69 we get the factor 0.824 mentioned in the
1235          * datasheet.
1236          */
1237         return (dt * 824) / 10;
1238 }
1239
1240 static int at803x_cdt_start(struct phy_device *phydev,
1241                             u32 cdt_start)
1242 {
1243         return phy_write(phydev, AT803X_CDT, cdt_start);
1244 }
1245
1246 static int at803x_cdt_wait_for_completion(struct phy_device *phydev,
1247                                           u32 cdt_en)
1248 {
1249         int val, ret;
1250
1251         /* One test run takes about 25ms */
1252         ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
1253                                     !(val & cdt_en),
1254                                     30000, 100000, true);
1255
1256         return ret < 0 ? ret : 0;
1257 }
1258
1259 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
1260 {
1261         static const int ethtool_pair[] = {
1262                 ETHTOOL_A_CABLE_PAIR_A,
1263                 ETHTOOL_A_CABLE_PAIR_B,
1264                 ETHTOOL_A_CABLE_PAIR_C,
1265                 ETHTOOL_A_CABLE_PAIR_D,
1266         };
1267         int ret, val;
1268
1269         val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
1270               AT803X_CDT_ENABLE_TEST;
1271         ret = at803x_cdt_start(phydev, val);
1272         if (ret)
1273                 return ret;
1274
1275         ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST);
1276         if (ret)
1277                 return ret;
1278
1279         val = phy_read(phydev, AT803X_CDT_STATUS);
1280         if (val < 0)
1281                 return val;
1282
1283         if (at803x_cdt_test_failed(val))
1284                 return 0;
1285
1286         ethnl_cable_test_result(phydev, ethtool_pair[pair],
1287                                 at803x_cable_test_result_trans(val));
1288
1289         if (at803x_cdt_fault_length_valid(val)) {
1290                 val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val);
1291                 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
1292                                               at803x_cdt_fault_length(val));
1293         }
1294
1295         return 1;
1296 }
1297
1298 static int at803x_cable_test_get_status(struct phy_device *phydev,
1299                                         bool *finished, unsigned long pair_mask)
1300 {
1301         int retries = 20;
1302         int pair, ret;
1303
1304         *finished = false;
1305
1306         /* According to the datasheet the CDT can be performed when
1307          * there is no link partner or when the link partner is
1308          * auto-negotiating. Starting the test will restart the AN
1309          * automatically. It seems that doing this repeatedly we will
1310          * get a slot where our link partner won't disturb our
1311          * measurement.
1312          */
1313         while (pair_mask && retries--) {
1314                 for_each_set_bit(pair, &pair_mask, 4) {
1315                         ret = at803x_cable_test_one_pair(phydev, pair);
1316                         if (ret < 0)
1317                                 return ret;
1318                         if (ret)
1319                                 clear_bit(pair, &pair_mask);
1320                 }
1321                 if (pair_mask)
1322                         msleep(250);
1323         }
1324
1325         *finished = true;
1326
1327         return 0;
1328 }
1329
1330 static void at803x_cable_test_autoneg(struct phy_device *phydev)
1331 {
1332         /* Enable auto-negotiation, but advertise no capabilities, no link
1333          * will be established. A restart of the auto-negotiation is not
1334          * required, because the cable test will automatically break the link.
1335          */
1336         phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
1337         phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
1338 }
1339
1340 static int at803x_cable_test_start(struct phy_device *phydev)
1341 {
1342         at803x_cable_test_autoneg(phydev);
1343         /* we do all the (time consuming) work later */
1344         return 0;
1345 }
1346
1347 static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
1348                                             unsigned int selector)
1349 {
1350         struct phy_device *phydev = rdev_get_drvdata(rdev);
1351
1352         if (selector)
1353                 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
1354                                              0, AT803X_DEBUG_RGMII_1V8);
1355         else
1356                 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
1357                                              AT803X_DEBUG_RGMII_1V8, 0);
1358 }
1359
1360 static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
1361 {
1362         struct phy_device *phydev = rdev_get_drvdata(rdev);
1363         int val;
1364
1365         val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
1366         if (val < 0)
1367                 return val;
1368
1369         return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
1370 }
1371
1372 static const struct regulator_ops vddio_regulator_ops = {
1373         .list_voltage = regulator_list_voltage_table,
1374         .set_voltage_sel = at8031_rgmii_reg_set_voltage_sel,
1375         .get_voltage_sel = at8031_rgmii_reg_get_voltage_sel,
1376 };
1377
1378 static const unsigned int vddio_voltage_table[] = {
1379         1500000,
1380         1800000,
1381 };
1382
1383 static const struct regulator_desc vddio_desc = {
1384         .name = "vddio",
1385         .of_match = of_match_ptr("vddio-regulator"),
1386         .n_voltages = ARRAY_SIZE(vddio_voltage_table),
1387         .volt_table = vddio_voltage_table,
1388         .ops = &vddio_regulator_ops,
1389         .type = REGULATOR_VOLTAGE,
1390         .owner = THIS_MODULE,
1391 };
1392
1393 static const struct regulator_ops vddh_regulator_ops = {
1394 };
1395
1396 static const struct regulator_desc vddh_desc = {
1397         .name = "vddh",
1398         .of_match = of_match_ptr("vddh-regulator"),
1399         .n_voltages = 1,
1400         .fixed_uV = 2500000,
1401         .ops = &vddh_regulator_ops,
1402         .type = REGULATOR_VOLTAGE,
1403         .owner = THIS_MODULE,
1404 };
1405
1406 static int at8031_register_regulators(struct phy_device *phydev)
1407 {
1408         struct at803x_priv *priv = phydev->priv;
1409         struct device *dev = &phydev->mdio.dev;
1410         struct regulator_config config = { };
1411
1412         config.dev = dev;
1413         config.driver_data = phydev;
1414
1415         priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
1416         if (IS_ERR(priv->vddio_rdev)) {
1417                 phydev_err(phydev, "failed to register VDDIO regulator\n");
1418                 return PTR_ERR(priv->vddio_rdev);
1419         }
1420
1421         priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
1422         if (IS_ERR(priv->vddh_rdev)) {
1423                 phydev_err(phydev, "failed to register VDDH regulator\n");
1424                 return PTR_ERR(priv->vddh_rdev);
1425         }
1426
1427         return 0;
1428 }
1429
1430 static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
1431 {
1432         struct phy_device *phydev = upstream;
1433         __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support);
1434         __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);
1435         DECLARE_PHY_INTERFACE_MASK(interfaces);
1436         phy_interface_t iface;
1437
1438         linkmode_zero(phy_support);
1439         phylink_set(phy_support, 1000baseX_Full);
1440         phylink_set(phy_support, 1000baseT_Full);
1441         phylink_set(phy_support, Autoneg);
1442         phylink_set(phy_support, Pause);
1443         phylink_set(phy_support, Asym_Pause);
1444
1445         linkmode_zero(sfp_support);
1446         sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces);
1447         /* Some modules support 10G modes as well as others we support.
1448          * Mask out non-supported modes so the correct interface is picked.
1449          */
1450         linkmode_and(sfp_support, phy_support, sfp_support);
1451
1452         if (linkmode_empty(sfp_support)) {
1453                 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
1454                 return -EINVAL;
1455         }
1456
1457         iface = sfp_select_interface(phydev->sfp_bus, sfp_support);
1458
1459         /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes
1460          * interface for use with SFP modules.
1461          * However, some copper modules detected as having a preferred SGMII
1462          * interface do default to and function in 1000Base-X mode, so just
1463          * print a warning and allow such modules, as they may have some chance
1464          * of working.
1465          */
1466         if (iface == PHY_INTERFACE_MODE_SGMII)
1467                 dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n");
1468         else if (iface != PHY_INTERFACE_MODE_1000BASEX)
1469                 return -EINVAL;
1470
1471         return 0;
1472 }
1473
1474 static const struct sfp_upstream_ops at8031_sfp_ops = {
1475         .attach = phy_sfp_attach,
1476         .detach = phy_sfp_detach,
1477         .module_insert = at8031_sfp_insert,
1478 };
1479
1480 static int at8031_parse_dt(struct phy_device *phydev)
1481 {
1482         struct device_node *node = phydev->mdio.dev.of_node;
1483         struct at803x_priv *priv = phydev->priv;
1484         int ret;
1485
1486         if (of_property_read_bool(node, "qca,keep-pll-enabled"))
1487                 priv->flags |= AT803X_KEEP_PLL_ENABLED;
1488
1489         ret = at8031_register_regulators(phydev);
1490         if (ret < 0)
1491                 return ret;
1492
1493         ret = devm_regulator_get_enable_optional(&phydev->mdio.dev,
1494                                                  "vddio");
1495         if (ret) {
1496                 phydev_err(phydev, "failed to get VDDIO regulator\n");
1497                 return ret;
1498         }
1499
1500         /* Only AR8031/8033 support 1000Base-X for SFP modules */
1501         return phy_sfp_probe(phydev, &at8031_sfp_ops);
1502 }
1503
1504 static int at8031_probe(struct phy_device *phydev)
1505 {
1506         struct at803x_priv *priv;
1507         int mode_cfg;
1508         int ccr;
1509         int ret;
1510
1511         ret = at803x_probe(phydev);
1512         if (ret)
1513                 return ret;
1514
1515         priv = phydev->priv;
1516
1517         /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
1518          * options.
1519          */
1520         ret = at8031_parse_dt(phydev);
1521         if (ret)
1522                 return ret;
1523
1524         ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
1525         if (ccr < 0)
1526                 return ccr;
1527         mode_cfg = ccr & AT803X_MODE_CFG_MASK;
1528
1529         switch (mode_cfg) {
1530         case AT803X_MODE_CFG_BX1000_RGMII_50OHM:
1531         case AT803X_MODE_CFG_BX1000_RGMII_75OHM:
1532                 priv->is_1000basex = true;
1533                 fallthrough;
1534         case AT803X_MODE_CFG_FX100_RGMII_50OHM:
1535         case AT803X_MODE_CFG_FX100_RGMII_75OHM:
1536                 priv->is_fiber = true;
1537                 break;
1538         }
1539
1540         /* Disable WoL in 1588 register which is enabled
1541          * by default
1542          */
1543         return phy_modify_mmd(phydev, MDIO_MMD_PCS,
1544                               AT803X_PHY_MMD3_WOL_CTRL,
1545                               AT803X_WOL_EN, 0);
1546 }
1547
1548 static int at8031_config_init(struct phy_device *phydev)
1549 {
1550         struct at803x_priv *priv = phydev->priv;
1551         int ret;
1552
1553         /* Some bootloaders leave the fiber page selected.
1554          * Switch to the appropriate page (fiber or copper), as otherwise we
1555          * read the PHY capabilities from the wrong page.
1556          */
1557         phy_lock_mdio_bus(phydev);
1558         ret = at803x_write_page(phydev,
1559                                 priv->is_fiber ? AT803X_PAGE_FIBER :
1560                                                  AT803X_PAGE_COPPER);
1561         phy_unlock_mdio_bus(phydev);
1562         if (ret)
1563                 return ret;
1564
1565         ret = at8031_pll_config(phydev);
1566         if (ret < 0)
1567                 return ret;
1568
1569         return at803x_config_init(phydev);
1570 }
1571
1572 static int at8031_set_wol(struct phy_device *phydev,
1573                           struct ethtool_wolinfo *wol)
1574 {
1575         int ret;
1576
1577         /* First setup MAC address and enable WOL interrupt */
1578         ret = at803x_set_wol(phydev, wol);
1579         if (ret)
1580                 return ret;
1581
1582         if (wol->wolopts & WAKE_MAGIC)
1583                 /* Enable WOL function for 1588 */
1584                 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
1585                                      AT803X_PHY_MMD3_WOL_CTRL,
1586                                      0, AT803X_WOL_EN);
1587         else
1588                 /* Disable WoL function for 1588 */
1589                 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
1590                                      AT803X_PHY_MMD3_WOL_CTRL,
1591                                      AT803X_WOL_EN, 0);
1592
1593         return ret;
1594 }
1595
1596 static int at8031_config_intr(struct phy_device *phydev)
1597 {
1598         struct at803x_priv *priv = phydev->priv;
1599         int err, value = 0;
1600
1601         if (phydev->interrupts == PHY_INTERRUPT_ENABLED &&
1602             priv->is_fiber) {
1603                 /* Clear any pending interrupts */
1604                 err = at803x_ack_interrupt(phydev);
1605                 if (err)
1606                         return err;
1607
1608                 value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;
1609                 value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;
1610
1611                 err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value);
1612                 if (err)
1613                         return err;
1614         }
1615
1616         return at803x_config_intr(phydev);
1617 }
1618
1619 /* AR8031 and AR8033 share the same read status logic */
1620 static int at8031_read_status(struct phy_device *phydev)
1621 {
1622         struct at803x_priv *priv = phydev->priv;
1623
1624         if (priv->is_1000basex)
1625                 return genphy_c37_read_status(phydev);
1626
1627         return at803x_read_status(phydev);
1628 }
1629
1630 /* AR8031 and AR8035 share the same cable test get status reg */
1631 static int at8031_cable_test_get_status(struct phy_device *phydev,
1632                                         bool *finished)
1633 {
1634         return at803x_cable_test_get_status(phydev, finished, 0xf);
1635 }
1636
1637 /* AR8031 and AR8035 share the same cable test start logic */
1638 static int at8031_cable_test_start(struct phy_device *phydev)
1639 {
1640         at803x_cable_test_autoneg(phydev);
1641         phy_write(phydev, MII_CTRL1000, 0);
1642         /* we do all the (time consuming) work later */
1643         return 0;
1644 }
1645
1646 /* AR8032, AR9331 and QCA9561 share the same cable test get status reg */
1647 static int at8032_cable_test_get_status(struct phy_device *phydev,
1648                                         bool *finished)
1649 {
1650         return at803x_cable_test_get_status(phydev, finished, 0x3);
1651 }
1652
1653 static int at8035_parse_dt(struct phy_device *phydev)
1654 {
1655         struct at803x_priv *priv = phydev->priv;
1656
1657         /* Mask is set by the generic at803x_parse_dt
1658          * if property is set. Assume property is set
1659          * with the mask not zero.
1660          */
1661         if (priv->clk_25m_mask) {
1662                 /* Fixup for the AR8030/AR8035. This chip has another mask and
1663                  * doesn't support the DSP reference. Eg. the lowest bit of the
1664                  * mask. The upper two bits select the same frequencies. Mask
1665                  * the lowest bit here.
1666                  *
1667                  * Warning:
1668                  *   There was no datasheet for the AR8030 available so this is
1669                  *   just a guess. But the AR8035 is listed as pin compatible
1670                  *   to the AR8030 so there might be a good chance it works on
1671                  *   the AR8030 too.
1672                  */
1673                 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
1674                 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
1675         }
1676
1677         return 0;
1678 }
1679
1680 /* AR8030 and AR8035 shared the same special mask for clk_25m */
1681 static int at8035_probe(struct phy_device *phydev)
1682 {
1683         int ret;
1684
1685         ret = at803x_probe(phydev);
1686         if (ret)
1687                 return ret;
1688
1689         return at8035_parse_dt(phydev);
1690 }
1691
1692 static int qca83xx_config_init(struct phy_device *phydev)
1693 {
1694         u8 switch_revision;
1695
1696         switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
1697
1698         switch (switch_revision) {
1699         case 1:
1700                 /* For 100M waveform */
1701                 at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);
1702                 /* Turn on Gigabit clock */
1703                 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);
1704                 break;
1705
1706         case 2:
1707                 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
1708                 fallthrough;
1709         case 4:
1710                 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
1711                 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);
1712                 at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);
1713                 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
1714                 break;
1715         }
1716
1717         /* Following original QCA sourcecode set port to prefer master */
1718         phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
1719
1720         return 0;
1721 }
1722
1723 static int qca8327_config_init(struct phy_device *phydev)
1724 {
1725         /* QCA8327 require DAC amplitude adjustment for 100m set to +6%.
1726          * Disable on init and enable only with 100m speed following
1727          * qca original source code.
1728          */
1729         at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1730                               QCA8327_DEBUG_MANU_CTRL_EN, 0);
1731
1732         return qca83xx_config_init(phydev);
1733 }
1734
1735 static void qca83xx_link_change_notify(struct phy_device *phydev)
1736 {
1737         /* Set DAC Amplitude adjustment to +6% for 100m on link running */
1738         if (phydev->state == PHY_RUNNING) {
1739                 if (phydev->speed == SPEED_100)
1740                         at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1741                                               QCA8327_DEBUG_MANU_CTRL_EN,
1742                                               QCA8327_DEBUG_MANU_CTRL_EN);
1743         } else {
1744                 /* Reset DAC Amplitude adjustment */
1745                 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1746                                       QCA8327_DEBUG_MANU_CTRL_EN, 0);
1747         }
1748 }
1749
1750 static int qca83xx_resume(struct phy_device *phydev)
1751 {
1752         int ret, val;
1753
1754         /* Skip reset if not suspended */
1755         if (!phydev->suspended)
1756                 return 0;
1757
1758         /* Reinit the port, reset values set by suspend */
1759         qca83xx_config_init(phydev);
1760
1761         /* Reset the port on port resume */
1762         phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1763
1764         /* On resume from suspend the switch execute a reset and
1765          * restart auto-negotiation. Wait for reset to complete.
1766          */
1767         ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
1768                                     50000, 600000, true);
1769         if (ret)
1770                 return ret;
1771
1772         usleep_range(1000, 2000);
1773
1774         return 0;
1775 }
1776
1777 static int qca83xx_suspend(struct phy_device *phydev)
1778 {
1779         at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
1780                               AT803X_DEBUG_GATE_CLK_IN1000, 0);
1781
1782         at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
1783                               AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE |
1784                               AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0);
1785
1786         return 0;
1787 }
1788
1789 static int qca8337_suspend(struct phy_device *phydev)
1790 {
1791         /* Only QCA8337 support actual suspend. */
1792         genphy_suspend(phydev);
1793
1794         return qca83xx_suspend(phydev);
1795 }
1796
1797 static int qca8327_suspend(struct phy_device *phydev)
1798 {
1799         u16 mask = 0;
1800
1801         /* QCA8327 cause port unreliability when phy suspend
1802          * is set.
1803          */
1804         mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
1805         phy_modify(phydev, MII_BMCR, mask, 0);
1806
1807         return qca83xx_suspend(phydev);
1808 }
1809
1810 static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
1811 {
1812         int ret;
1813
1814         /* Enable fast retrain */
1815         ret = genphy_c45_fast_retrain(phydev, true);
1816         if (ret)
1817                 return ret;
1818
1819         phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
1820                       QCA808X_TOP_OPTION1_DATA);
1821         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
1822                       QCA808X_MSE_THRESHOLD_20DB_VALUE);
1823         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
1824                       QCA808X_MSE_THRESHOLD_17DB_VALUE);
1825         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
1826                       QCA808X_MSE_THRESHOLD_27DB_VALUE);
1827         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
1828                       QCA808X_MSE_THRESHOLD_28DB_VALUE);
1829         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
1830                       QCA808X_MMD3_DEBUG_1_VALUE);
1831         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
1832                       QCA808X_MMD3_DEBUG_4_VALUE);
1833         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
1834                       QCA808X_MMD3_DEBUG_5_VALUE);
1835         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
1836                       QCA808X_MMD3_DEBUG_3_VALUE);
1837         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
1838                       QCA808X_MMD3_DEBUG_6_VALUE);
1839         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
1840                       QCA808X_MMD3_DEBUG_2_VALUE);
1841
1842         return 0;
1843 }
1844
1845 static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
1846 {
1847         u16 seed_value;
1848
1849         if (!enable)
1850                 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
1851                                 QCA808X_MASTER_SLAVE_SEED_ENABLE, 0);
1852
1853         seed_value = get_random_u32_below(QCA808X_MASTER_SLAVE_SEED_RANGE);
1854         return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
1855                         QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE,
1856                         FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) |
1857                         QCA808X_MASTER_SLAVE_SEED_ENABLE);
1858 }
1859
1860 static bool qca808x_is_prefer_master(struct phy_device *phydev)
1861 {
1862         return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) ||
1863                 (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED);
1864 }
1865
1866 static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
1867 {
1868         return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
1869 }
1870
1871 static int qca808x_config_init(struct phy_device *phydev)
1872 {
1873         int ret;
1874
1875         /* Active adc&vga on 802.3az for the link 1000M and 100M */
1876         ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
1877                              QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
1878         if (ret)
1879                 return ret;
1880
1881         /* Adjust the threshold on 802.3az for the link 1000M */
1882         ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
1883                             QCA808X_PHY_MMD3_AZ_TRAINING_CTRL,
1884                             QCA808X_MMD3_AZ_TRAINING_VAL);
1885         if (ret)
1886                 return ret;
1887
1888         if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
1889                 /* Config the fast retrain for the link 2500M */
1890                 ret = qca808x_phy_fast_retrain_config(phydev);
1891                 if (ret)
1892                         return ret;
1893
1894                 ret = genphy_read_master_slave(phydev);
1895                 if (ret < 0)
1896                         return ret;
1897
1898                 if (!qca808x_is_prefer_master(phydev)) {
1899                         /* Enable seed and configure lower ramdom seed to make phy
1900                          * linked as slave mode.
1901                          */
1902                         ret = qca808x_phy_ms_seed_enable(phydev, true);
1903                         if (ret)
1904                                 return ret;
1905                 }
1906         }
1907
1908         /* Configure adc threshold as 100mv for the link 10M */
1909         return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
1910                                      QCA808X_ADC_THRESHOLD_MASK,
1911                                      QCA808X_ADC_THRESHOLD_100MV);
1912 }
1913
1914 static int qca808x_read_status(struct phy_device *phydev)
1915 {
1916         struct at803x_ss_mask ss_mask = { 0 };
1917         int ret;
1918
1919         ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
1920         if (ret < 0)
1921                 return ret;
1922
1923         linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
1924                          ret & MDIO_AN_10GBT_STAT_LP2_5G);
1925
1926         ret = genphy_read_status(phydev);
1927         if (ret)
1928                 return ret;
1929
1930         /* qca8081 takes the different bits for speed value from at803x */
1931         ss_mask.speed_mask = QCA808X_SS_SPEED_MASK;
1932         ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK);
1933         ret = at803x_read_specific_status(phydev, ss_mask);
1934         if (ret < 0)
1935                 return ret;
1936
1937         if (phydev->link) {
1938                 if (phydev->speed == SPEED_2500)
1939                         phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
1940                 else
1941                         phydev->interface = PHY_INTERFACE_MODE_SGMII;
1942         } else {
1943                 /* generate seed as a lower random value to make PHY linked as SLAVE easily,
1944                  * except for master/slave configuration fault detected or the master mode
1945                  * preferred.
1946                  *
1947                  * the reason for not putting this code into the function link_change_notify is
1948                  * the corner case where the link partner is also the qca8081 PHY and the seed
1949                  * value is configured as the same value, the link can't be up and no link change
1950                  * occurs.
1951                  */
1952                 if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
1953                         if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR ||
1954                             qca808x_is_prefer_master(phydev)) {
1955                                 qca808x_phy_ms_seed_enable(phydev, false);
1956                         } else {
1957                                 qca808x_phy_ms_seed_enable(phydev, true);
1958                         }
1959                 }
1960         }
1961
1962         return 0;
1963 }
1964
1965 static int qca808x_soft_reset(struct phy_device *phydev)
1966 {
1967         int ret;
1968
1969         ret = genphy_soft_reset(phydev);
1970         if (ret < 0)
1971                 return ret;
1972
1973         if (qca808x_has_fast_retrain_or_slave_seed(phydev))
1974                 ret = qca808x_phy_ms_seed_enable(phydev, true);
1975
1976         return ret;
1977 }
1978
1979 static bool qca808x_cdt_fault_length_valid(int cdt_code)
1980 {
1981         switch (cdt_code) {
1982         case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
1983         case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
1984         case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
1985         case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
1986         case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
1987         case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
1988         case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
1989         case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
1990         case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
1991         case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
1992         case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
1993                 return true;
1994         default:
1995                 return false;
1996         }
1997 }
1998
1999 static int qca808x_cable_test_result_trans(int cdt_code)
2000 {
2001         switch (cdt_code) {
2002         case QCA808X_CDT_STATUS_STAT_NORMAL:
2003                 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2004         case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
2005                 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2006         case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
2007                 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2008         case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
2009         case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
2010         case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
2011         case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
2012         case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
2013         case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
2014         case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
2015         case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
2016         case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
2017                 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
2018         case QCA808X_CDT_STATUS_STAT_FAIL:
2019         default:
2020                 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2021         }
2022 }
2023
2024 static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair,
2025                                     int result)
2026 {
2027         int val;
2028         u32 cdt_length_reg = 0;
2029
2030         switch (pair) {
2031         case ETHTOOL_A_CABLE_PAIR_A:
2032                 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
2033                 break;
2034         case ETHTOOL_A_CABLE_PAIR_B:
2035                 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
2036                 break;
2037         case ETHTOOL_A_CABLE_PAIR_C:
2038                 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
2039                 break;
2040         case ETHTOOL_A_CABLE_PAIR_D:
2041                 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
2042                 break;
2043         default:
2044                 return -EINVAL;
2045         }
2046
2047         val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
2048         if (val < 0)
2049                 return val;
2050
2051         if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT)
2052                 val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val);
2053         else
2054                 val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val);
2055
2056         return at803x_cdt_fault_length(val);
2057 }
2058
2059 static int qca808x_cable_test_start(struct phy_device *phydev)
2060 {
2061         int ret;
2062
2063         /* perform CDT with the following configs:
2064          * 1. disable hibernation.
2065          * 2. force PHY working in MDI mode.
2066          * 3. for PHY working in 1000BaseT.
2067          * 4. configure the threshold.
2068          */
2069
2070         ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
2071         if (ret < 0)
2072                 return ret;
2073
2074         ret = at803x_config_mdix(phydev, ETH_TP_MDI);
2075         if (ret < 0)
2076                 return ret;
2077
2078         /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
2079         phydev->duplex = DUPLEX_FULL;
2080         phydev->speed = SPEED_1000;
2081         ret = genphy_c45_pma_setup_forced(phydev);
2082         if (ret < 0)
2083                 return ret;
2084
2085         ret = genphy_setup_forced(phydev);
2086         if (ret < 0)
2087                 return ret;
2088
2089         /* configure the thresholds for open, short, pair ok test */
2090         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
2091         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
2092         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
2093         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
2094         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
2095         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
2096
2097         return 0;
2098 }
2099
2100 static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair,
2101                                               u16 status)
2102 {
2103         int length, result;
2104         u16 pair_code;
2105
2106         switch (pair) {
2107         case ETHTOOL_A_CABLE_PAIR_A:
2108                 pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status);
2109                 break;
2110         case ETHTOOL_A_CABLE_PAIR_B:
2111                 pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status);
2112                 break;
2113         case ETHTOOL_A_CABLE_PAIR_C:
2114                 pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status);
2115                 break;
2116         case ETHTOOL_A_CABLE_PAIR_D:
2117                 pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status);
2118                 break;
2119         default:
2120                 return -EINVAL;
2121         }
2122
2123         result = qca808x_cable_test_result_trans(pair_code);
2124         ethnl_cable_test_result(phydev, pair, result);
2125
2126         if (qca808x_cdt_fault_length_valid(pair_code)) {
2127                 length = qca808x_cdt_fault_length(phydev, pair, result);
2128                 ethnl_cable_test_fault_length(phydev, pair, length);
2129         }
2130
2131         return 0;
2132 }
2133
2134 static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
2135 {
2136         int ret, val;
2137
2138         *finished = false;
2139
2140         val = QCA808X_CDT_ENABLE_TEST |
2141               QCA808X_CDT_LENGTH_UNIT;
2142         ret = at803x_cdt_start(phydev, val);
2143         if (ret)
2144                 return ret;
2145
2146         ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST);
2147         if (ret)
2148                 return ret;
2149
2150         val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
2151         if (val < 0)
2152                 return val;
2153
2154         ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val);
2155         if (ret)
2156                 return ret;
2157
2158         ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val);
2159         if (ret)
2160                 return ret;
2161
2162         ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val);
2163         if (ret)
2164                 return ret;
2165
2166         ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val);
2167         if (ret)
2168                 return ret;
2169
2170         *finished = true;
2171
2172         return 0;
2173 }
2174
2175 static int qca808x_get_features(struct phy_device *phydev)
2176 {
2177         int ret;
2178
2179         ret = genphy_c45_pma_read_abilities(phydev);
2180         if (ret)
2181                 return ret;
2182
2183         /* The autoneg ability is not existed in bit3 of MMD7.1,
2184          * but it is supported by qca808x PHY, so we add it here
2185          * manually.
2186          */
2187         linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
2188
2189         /* As for the qca8081 1G version chip, the 2500baseT ability is also
2190          * existed in the bit0 of MMD1.21, we need to remove it manually if
2191          * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
2192          */
2193         ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
2194         if (ret < 0)
2195                 return ret;
2196
2197         if (QCA808X_PHY_CHIP_TYPE_1G & ret)
2198                 linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
2199
2200         return 0;
2201 }
2202
2203 static int qca808x_config_aneg(struct phy_device *phydev)
2204 {
2205         int phy_ctrl = 0;
2206         int ret;
2207
2208         ret = at803x_prepare_config_aneg(phydev);
2209         if (ret)
2210                 return ret;
2211
2212         /* The reg MII_BMCR also needs to be configured for force mode, the
2213          * genphy_config_aneg is also needed.
2214          */
2215         if (phydev->autoneg == AUTONEG_DISABLE)
2216                 genphy_c45_pma_setup_forced(phydev);
2217
2218         if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
2219                 phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
2220
2221         ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
2222                                      MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
2223         if (ret < 0)
2224                 return ret;
2225
2226         return __genphy_config_aneg(phydev, ret);
2227 }
2228
2229 static void qca808x_link_change_notify(struct phy_device *phydev)
2230 {
2231         /* Assert interface sgmii fifo on link down, deassert it on link up,
2232          * the interface device address is always phy address added by 1.
2233          */
2234         mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
2235                                    MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
2236                                    QCA8081_PHY_FIFO_RSTN,
2237                                    phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
2238 }
2239
2240 static struct phy_driver at803x_driver[] = {
2241 {
2242         /* Qualcomm Atheros AR8035 */
2243         PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
2244         .name                   = "Qualcomm Atheros AR8035",
2245         .flags                  = PHY_POLL_CABLE_TEST,
2246         .probe                  = at8035_probe,
2247         .config_aneg            = at803x_config_aneg,
2248         .config_init            = at803x_config_init,
2249         .soft_reset             = genphy_soft_reset,
2250         .set_wol                = at803x_set_wol,
2251         .get_wol                = at803x_get_wol,
2252         .suspend                = at803x_suspend,
2253         .resume                 = at803x_resume,
2254         /* PHY_GBIT_FEATURES */
2255         .read_status            = at803x_read_status,
2256         .config_intr            = at803x_config_intr,
2257         .handle_interrupt       = at803x_handle_interrupt,
2258         .get_tunable            = at803x_get_tunable,
2259         .set_tunable            = at803x_set_tunable,
2260         .cable_test_start       = at8031_cable_test_start,
2261         .cable_test_get_status  = at8031_cable_test_get_status,
2262 }, {
2263         /* Qualcomm Atheros AR8030 */
2264         .phy_id                 = ATH8030_PHY_ID,
2265         .name                   = "Qualcomm Atheros AR8030",
2266         .phy_id_mask            = AT8030_PHY_ID_MASK,
2267         .probe                  = at8035_probe,
2268         .config_init            = at803x_config_init,
2269         .link_change_notify     = at803x_link_change_notify,
2270         .set_wol                = at803x_set_wol,
2271         .get_wol                = at803x_get_wol,
2272         .suspend                = at803x_suspend,
2273         .resume                 = at803x_resume,
2274         /* PHY_BASIC_FEATURES */
2275         .config_intr            = at803x_config_intr,
2276         .handle_interrupt       = at803x_handle_interrupt,
2277 }, {
2278         /* Qualcomm Atheros AR8031/AR8033 */
2279         PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
2280         .name                   = "Qualcomm Atheros AR8031/AR8033",
2281         .flags                  = PHY_POLL_CABLE_TEST,
2282         .probe                  = at8031_probe,
2283         .config_init            = at8031_config_init,
2284         .config_aneg            = at803x_config_aneg,
2285         .soft_reset             = genphy_soft_reset,
2286         .set_wol                = at8031_set_wol,
2287         .get_wol                = at803x_get_wol,
2288         .suspend                = at803x_suspend,
2289         .resume                 = at803x_resume,
2290         .read_page              = at803x_read_page,
2291         .write_page             = at803x_write_page,
2292         .get_features           = at803x_get_features,
2293         .read_status            = at8031_read_status,
2294         .config_intr            = at8031_config_intr,
2295         .handle_interrupt       = at803x_handle_interrupt,
2296         .get_tunable            = at803x_get_tunable,
2297         .set_tunable            = at803x_set_tunable,
2298         .cable_test_start       = at8031_cable_test_start,
2299         .cable_test_get_status  = at8031_cable_test_get_status,
2300 }, {
2301         /* Qualcomm Atheros AR8032 */
2302         PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
2303         .name                   = "Qualcomm Atheros AR8032",
2304         .probe                  = at803x_probe,
2305         .flags                  = PHY_POLL_CABLE_TEST,
2306         .config_init            = at803x_config_init,
2307         .link_change_notify     = at803x_link_change_notify,
2308         .suspend                = at803x_suspend,
2309         .resume                 = at803x_resume,
2310         /* PHY_BASIC_FEATURES */
2311         .config_intr            = at803x_config_intr,
2312         .handle_interrupt       = at803x_handle_interrupt,
2313         .cable_test_start       = at803x_cable_test_start,
2314         .cable_test_get_status  = at8032_cable_test_get_status,
2315 }, {
2316         /* ATHEROS AR9331 */
2317         PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
2318         .name                   = "Qualcomm Atheros AR9331 built-in PHY",
2319         .probe                  = at803x_probe,
2320         .suspend                = at803x_suspend,
2321         .resume                 = at803x_resume,
2322         .flags                  = PHY_POLL_CABLE_TEST,
2323         /* PHY_BASIC_FEATURES */
2324         .config_intr            = at803x_config_intr,
2325         .handle_interrupt       = at803x_handle_interrupt,
2326         .cable_test_start       = at803x_cable_test_start,
2327         .cable_test_get_status  = at8032_cable_test_get_status,
2328         .read_status            = at803x_read_status,
2329         .soft_reset             = genphy_soft_reset,
2330         .config_aneg            = at803x_config_aneg,
2331 }, {
2332         /* Qualcomm Atheros QCA9561 */
2333         PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
2334         .name                   = "Qualcomm Atheros QCA9561 built-in PHY",
2335         .probe                  = at803x_probe,
2336         .suspend                = at803x_suspend,
2337         .resume                 = at803x_resume,
2338         .flags                  = PHY_POLL_CABLE_TEST,
2339         /* PHY_BASIC_FEATURES */
2340         .config_intr            = at803x_config_intr,
2341         .handle_interrupt       = at803x_handle_interrupt,
2342         .cable_test_start       = at803x_cable_test_start,
2343         .cable_test_get_status  = at8032_cable_test_get_status,
2344         .read_status            = at803x_read_status,
2345         .soft_reset             = genphy_soft_reset,
2346         .config_aneg            = at803x_config_aneg,
2347 }, {
2348         /* QCA8337 */
2349         .phy_id                 = QCA8337_PHY_ID,
2350         .phy_id_mask            = QCA8K_PHY_ID_MASK,
2351         .name                   = "Qualcomm Atheros 8337 internal PHY",
2352         /* PHY_GBIT_FEATURES */
2353         .probe                  = at803x_probe,
2354         .flags                  = PHY_IS_INTERNAL,
2355         .config_init            = qca83xx_config_init,
2356         .soft_reset             = genphy_soft_reset,
2357         .get_sset_count         = qca83xx_get_sset_count,
2358         .get_strings            = qca83xx_get_strings,
2359         .get_stats              = qca83xx_get_stats,
2360         .suspend                = qca8337_suspend,
2361         .resume                 = qca83xx_resume,
2362 }, {
2363         /* QCA8327-A from switch QCA8327-AL1A */
2364         .phy_id                 = QCA8327_A_PHY_ID,
2365         .phy_id_mask            = QCA8K_PHY_ID_MASK,
2366         .name                   = "Qualcomm Atheros 8327-A internal PHY",
2367         /* PHY_GBIT_FEATURES */
2368         .link_change_notify     = qca83xx_link_change_notify,
2369         .probe                  = at803x_probe,
2370         .flags                  = PHY_IS_INTERNAL,
2371         .config_init            = qca8327_config_init,
2372         .soft_reset             = genphy_soft_reset,
2373         .get_sset_count         = qca83xx_get_sset_count,
2374         .get_strings            = qca83xx_get_strings,
2375         .get_stats              = qca83xx_get_stats,
2376         .suspend                = qca8327_suspend,
2377         .resume                 = qca83xx_resume,
2378 }, {
2379         /* QCA8327-B from switch QCA8327-BL1A */
2380         .phy_id                 = QCA8327_B_PHY_ID,
2381         .phy_id_mask            = QCA8K_PHY_ID_MASK,
2382         .name                   = "Qualcomm Atheros 8327-B internal PHY",
2383         /* PHY_GBIT_FEATURES */
2384         .link_change_notify     = qca83xx_link_change_notify,
2385         .probe                  = at803x_probe,
2386         .flags                  = PHY_IS_INTERNAL,
2387         .config_init            = qca8327_config_init,
2388         .soft_reset             = genphy_soft_reset,
2389         .get_sset_count         = qca83xx_get_sset_count,
2390         .get_strings            = qca83xx_get_strings,
2391         .get_stats              = qca83xx_get_stats,
2392         .suspend                = qca8327_suspend,
2393         .resume                 = qca83xx_resume,
2394 }, {
2395         /* Qualcomm QCA8081 */
2396         PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
2397         .name                   = "Qualcomm QCA8081",
2398         .flags                  = PHY_POLL_CABLE_TEST,
2399         .probe                  = at803x_probe,
2400         .config_intr            = at803x_config_intr,
2401         .handle_interrupt       = at803x_handle_interrupt,
2402         .get_tunable            = at803x_get_tunable,
2403         .set_tunable            = at803x_set_tunable,
2404         .set_wol                = at803x_set_wol,
2405         .get_wol                = at803x_get_wol,
2406         .get_features           = qca808x_get_features,
2407         .config_aneg            = qca808x_config_aneg,
2408         .suspend                = genphy_suspend,
2409         .resume                 = genphy_resume,
2410         .read_status            = qca808x_read_status,
2411         .config_init            = qca808x_config_init,
2412         .soft_reset             = qca808x_soft_reset,
2413         .cable_test_start       = qca808x_cable_test_start,
2414         .cable_test_get_status  = qca808x_cable_test_get_status,
2415         .link_change_notify     = qca808x_link_change_notify,
2416 }, };
2417
2418 module_phy_driver(at803x_driver);
2419
2420 static struct mdio_device_id __maybe_unused atheros_tbl[] = {
2421         { ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
2422         { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
2423         { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
2424         { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
2425         { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
2426         { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },
2427         { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },
2428         { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
2429         { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
2430         { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
2431         { }
2432 };
2433
2434 MODULE_DEVICE_TABLE(mdio, atheros_tbl);