1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/at803x.c
5 * Driver for Qualcomm Atheros AR803x PHY
7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
10 #include <linux/phy.h>
11 #include <linux/module.h>
12 #include <linux/string.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/ethtool_netlink.h>
16 #include <linux/of_gpio.h>
17 #include <linux/bitfield.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/regulator/of_regulator.h>
20 #include <linux/regulator/driver.h>
21 #include <linux/regulator/consumer.h>
22 #include <dt-bindings/net/qca-ar803x.h>
24 #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10
25 #define AT803X_SFC_ASSERT_CRS BIT(11)
26 #define AT803X_SFC_FORCE_LINK BIT(10)
27 #define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5)
28 #define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3
29 #define AT803X_SFC_MANUAL_MDIX 0x1
30 #define AT803X_SFC_MANUAL_MDI 0x0
31 #define AT803X_SFC_SQE_TEST BIT(2)
32 #define AT803X_SFC_POLARITY_REVERSAL BIT(1)
33 #define AT803X_SFC_DISABLE_JABBER BIT(0)
35 #define AT803X_SPECIFIC_STATUS 0x11
36 #define AT803X_SS_SPEED_MASK (3 << 14)
37 #define AT803X_SS_SPEED_1000 (2 << 14)
38 #define AT803X_SS_SPEED_100 (1 << 14)
39 #define AT803X_SS_SPEED_10 (0 << 14)
40 #define AT803X_SS_DUPLEX BIT(13)
41 #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11)
42 #define AT803X_SS_MDIX BIT(6)
44 #define AT803X_INTR_ENABLE 0x12
45 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15)
46 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14)
47 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13)
48 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12)
49 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11)
50 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10)
51 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5)
52 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1)
53 #define AT803X_INTR_ENABLE_WOL BIT(0)
55 #define AT803X_INTR_STATUS 0x13
57 #define AT803X_SMART_SPEED 0x14
58 #define AT803X_SMART_SPEED_ENABLE BIT(5)
59 #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2)
60 #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1)
61 #define AT803X_CDT 0x16
62 #define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8)
63 #define AT803X_CDT_ENABLE_TEST BIT(0)
64 #define AT803X_CDT_STATUS 0x1c
65 #define AT803X_CDT_STATUS_STAT_NORMAL 0
66 #define AT803X_CDT_STATUS_STAT_SHORT 1
67 #define AT803X_CDT_STATUS_STAT_OPEN 2
68 #define AT803X_CDT_STATUS_STAT_FAIL 3
69 #define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8)
70 #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0)
71 #define AT803X_LED_CONTROL 0x18
73 #define AT803X_DEVICE_ADDR 0x03
74 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
75 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
76 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
77 #define AT803X_REG_CHIP_CONFIG 0x1f
78 #define AT803X_BT_BX_REG_SEL 0x8000
80 #define AT803X_DEBUG_ADDR 0x1D
81 #define AT803X_DEBUG_DATA 0x1E
83 #define AT803X_MODE_CFG_MASK 0x0F
84 #define AT803X_MODE_CFG_SGMII 0x01
86 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
87 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200
89 #define AT803X_DEBUG_REG_0 0x00
90 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
92 #define AT803X_DEBUG_REG_5 0x05
93 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
95 #define AT803X_DEBUG_REG_3C 0x3C
97 #define AT803X_DEBUG_REG_3D 0x3D
99 #define AT803X_DEBUG_REG_1F 0x1F
100 #define AT803X_DEBUG_PLL_ON BIT(2)
101 #define AT803X_DEBUG_RGMII_1V8 BIT(3)
103 #define MDIO_AZ_DEBUG 0x800D
105 /* AT803x supports either the XTAL input pad, an internal PLL or the
106 * DSP as clock reference for the clock output pad. The XTAL reference
107 * is only used for 25 MHz output, all other frequencies need the PLL.
108 * The DSP as a clock reference is used in synchronous ethernet
111 * By default the PLL is only enabled if there is a link. Otherwise
112 * the PHY will go into low power state and disabled the PLL. You can
113 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
116 #define AT803X_MMD7_CLK25M 0x8016
117 #define AT803X_CLK_OUT_MASK GENMASK(4, 2)
118 #define AT803X_CLK_OUT_25MHZ_XTAL 0
119 #define AT803X_CLK_OUT_25MHZ_DSP 1
120 #define AT803X_CLK_OUT_50MHZ_PLL 2
121 #define AT803X_CLK_OUT_50MHZ_DSP 3
122 #define AT803X_CLK_OUT_62_5MHZ_PLL 4
123 #define AT803X_CLK_OUT_62_5MHZ_DSP 5
124 #define AT803X_CLK_OUT_125MHZ_PLL 6
125 #define AT803X_CLK_OUT_125MHZ_DSP 7
127 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
128 * but doesn't support choosing between XTAL/PLL and DSP.
130 #define AT8035_CLK_OUT_MASK GENMASK(4, 3)
132 #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7)
133 #define AT803X_CLK_OUT_STRENGTH_FULL 0
134 #define AT803X_CLK_OUT_STRENGTH_HALF 1
135 #define AT803X_CLK_OUT_STRENGTH_QUARTER 2
137 #define AT803X_DEFAULT_DOWNSHIFT 5
138 #define AT803X_MIN_DOWNSHIFT 2
139 #define AT803X_MAX_DOWNSHIFT 9
141 #define AT803X_MMD3_SMARTEEE_CTL1 0x805b
142 #define AT803X_MMD3_SMARTEEE_CTL2 0x805c
143 #define AT803X_MMD3_SMARTEEE_CTL3 0x805d
144 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8)
146 #define ATH9331_PHY_ID 0x004dd041
147 #define ATH8030_PHY_ID 0x004dd076
148 #define ATH8031_PHY_ID 0x004dd074
149 #define ATH8032_PHY_ID 0x004dd023
150 #define ATH8035_PHY_ID 0x004dd072
151 #define AT8030_PHY_ID_MASK 0xffffffef
153 #define QCA8327_PHY_ID 0x004dd034
154 #define QCA8337_PHY_ID 0x004dd036
155 #define QCA8K_PHY_ID_MASK 0xffffffff
157 #define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0)
159 #define AT803X_PAGE_FIBER 0
160 #define AT803X_PAGE_COPPER 1
162 /* don't turn off internal PLL */
163 #define AT803X_KEEP_PLL_ENABLED BIT(0)
164 #define AT803X_DISABLE_SMARTEEE BIT(1)
166 MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver");
167 MODULE_AUTHOR("Matus Ujhelyi");
168 MODULE_LICENSE("GPL");
170 enum stat_access_type {
175 struct at803x_hw_stat {
179 enum stat_access_type access_type;
182 static struct at803x_hw_stat at803x_hw_stats[] = {
183 { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
184 { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
185 { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
192 u8 smarteee_lpi_tw_1g;
193 u8 smarteee_lpi_tw_100m;
194 struct regulator_dev *vddio_rdev;
195 struct regulator_dev *vddh_rdev;
196 struct regulator *vddio;
197 u64 stats[ARRAY_SIZE(at803x_hw_stats)];
200 struct at803x_context {
209 static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
213 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
217 return phy_write(phydev, AT803X_DEBUG_DATA, data);
220 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
224 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
228 return phy_read(phydev, AT803X_DEBUG_DATA);
231 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
237 ret = at803x_debug_reg_read(phydev, reg);
245 return phy_write(phydev, AT803X_DEBUG_DATA, val);
248 static int at803x_write_page(struct phy_device *phydev, int page)
253 if (page == AT803X_PAGE_COPPER) {
254 set = AT803X_BT_BX_REG_SEL;
258 mask = AT803X_BT_BX_REG_SEL;
261 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);
264 static int at803x_read_page(struct phy_device *phydev)
266 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);
271 if (ccr & AT803X_BT_BX_REG_SEL)
272 return AT803X_PAGE_COPPER;
274 return AT803X_PAGE_FIBER;
277 static int at803x_enable_rx_delay(struct phy_device *phydev)
279 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
280 AT803X_DEBUG_RX_CLK_DLY_EN);
283 static int at803x_enable_tx_delay(struct phy_device *phydev)
285 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
286 AT803X_DEBUG_TX_CLK_DLY_EN);
289 static int at803x_disable_rx_delay(struct phy_device *phydev)
291 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
292 AT803X_DEBUG_RX_CLK_DLY_EN, 0);
295 static int at803x_disable_tx_delay(struct phy_device *phydev)
297 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
298 AT803X_DEBUG_TX_CLK_DLY_EN, 0);
301 /* save relevant PHY registers to private copy */
302 static void at803x_context_save(struct phy_device *phydev,
303 struct at803x_context *context)
305 context->bmcr = phy_read(phydev, MII_BMCR);
306 context->advertise = phy_read(phydev, MII_ADVERTISE);
307 context->control1000 = phy_read(phydev, MII_CTRL1000);
308 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
309 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
310 context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
313 /* restore relevant PHY registers from private copy */
314 static void at803x_context_restore(struct phy_device *phydev,
315 const struct at803x_context *context)
317 phy_write(phydev, MII_BMCR, context->bmcr);
318 phy_write(phydev, MII_ADVERTISE, context->advertise);
319 phy_write(phydev, MII_CTRL1000, context->control1000);
320 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
321 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
322 phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
325 static int at803x_set_wol(struct phy_device *phydev,
326 struct ethtool_wolinfo *wol)
328 struct net_device *ndev = phydev->attached_dev;
332 unsigned int i, offsets[] = {
333 AT803X_LOC_MAC_ADDR_32_47_OFFSET,
334 AT803X_LOC_MAC_ADDR_16_31_OFFSET,
335 AT803X_LOC_MAC_ADDR_0_15_OFFSET,
341 if (wol->wolopts & WAKE_MAGIC) {
342 mac = (const u8 *) ndev->dev_addr;
344 if (!is_valid_ether_addr(mac))
347 for (i = 0; i < 3; i++)
348 phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i],
349 mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
351 value = phy_read(phydev, AT803X_INTR_ENABLE);
352 value |= AT803X_INTR_ENABLE_WOL;
353 ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
356 value = phy_read(phydev, AT803X_INTR_STATUS);
358 value = phy_read(phydev, AT803X_INTR_ENABLE);
359 value &= (~AT803X_INTR_ENABLE_WOL);
360 ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
363 value = phy_read(phydev, AT803X_INTR_STATUS);
369 static void at803x_get_wol(struct phy_device *phydev,
370 struct ethtool_wolinfo *wol)
374 wol->supported = WAKE_MAGIC;
377 value = phy_read(phydev, AT803X_INTR_ENABLE);
378 if (value & AT803X_INTR_ENABLE_WOL)
379 wol->wolopts |= WAKE_MAGIC;
382 static int at803x_get_sset_count(struct phy_device *phydev)
384 return ARRAY_SIZE(at803x_hw_stats);
387 static void at803x_get_strings(struct phy_device *phydev, u8 *data)
391 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) {
392 strscpy(data + i * ETH_GSTRING_LEN,
393 at803x_hw_stats[i].string, ETH_GSTRING_LEN);
397 static u64 at803x_get_stat(struct phy_device *phydev, int i)
399 struct at803x_hw_stat stat = at803x_hw_stats[i];
400 struct at803x_priv *priv = phydev->priv;
404 if (stat.access_type == MMD)
405 val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);
407 val = phy_read(phydev, stat.reg);
412 val = val & stat.mask;
413 priv->stats[i] += val;
414 ret = priv->stats[i];
420 static void at803x_get_stats(struct phy_device *phydev,
421 struct ethtool_stats *stats, u64 *data)
425 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++)
426 data[i] = at803x_get_stat(phydev, i);
429 static int at803x_suspend(struct phy_device *phydev)
434 value = phy_read(phydev, AT803X_INTR_ENABLE);
435 wol_enabled = value & AT803X_INTR_ENABLE_WOL;
438 value = BMCR_ISOLATE;
442 phy_modify(phydev, MII_BMCR, 0, value);
447 static int at803x_resume(struct phy_device *phydev)
449 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
452 static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
453 unsigned int selector)
455 struct phy_device *phydev = rdev_get_drvdata(rdev);
458 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
459 0, AT803X_DEBUG_RGMII_1V8);
461 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
462 AT803X_DEBUG_RGMII_1V8, 0);
465 static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
467 struct phy_device *phydev = rdev_get_drvdata(rdev);
470 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
474 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
477 static const struct regulator_ops vddio_regulator_ops = {
478 .list_voltage = regulator_list_voltage_table,
479 .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel,
480 .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel,
483 static const unsigned int vddio_voltage_table[] = {
488 static const struct regulator_desc vddio_desc = {
490 .of_match = of_match_ptr("vddio-regulator"),
491 .n_voltages = ARRAY_SIZE(vddio_voltage_table),
492 .volt_table = vddio_voltage_table,
493 .ops = &vddio_regulator_ops,
494 .type = REGULATOR_VOLTAGE,
495 .owner = THIS_MODULE,
498 static const struct regulator_ops vddh_regulator_ops = {
501 static const struct regulator_desc vddh_desc = {
503 .of_match = of_match_ptr("vddh-regulator"),
506 .ops = &vddh_regulator_ops,
507 .type = REGULATOR_VOLTAGE,
508 .owner = THIS_MODULE,
511 static int at8031_register_regulators(struct phy_device *phydev)
513 struct at803x_priv *priv = phydev->priv;
514 struct device *dev = &phydev->mdio.dev;
515 struct regulator_config config = { };
518 config.driver_data = phydev;
520 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
521 if (IS_ERR(priv->vddio_rdev)) {
522 phydev_err(phydev, "failed to register VDDIO regulator\n");
523 return PTR_ERR(priv->vddio_rdev);
526 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
527 if (IS_ERR(priv->vddh_rdev)) {
528 phydev_err(phydev, "failed to register VDDH regulator\n");
529 return PTR_ERR(priv->vddh_rdev);
535 static int at803x_parse_dt(struct phy_device *phydev)
537 struct device_node *node = phydev->mdio.dev.of_node;
538 struct at803x_priv *priv = phydev->priv;
539 u32 freq, strength, tw;
543 if (!IS_ENABLED(CONFIG_OF_MDIO))
546 if (of_property_read_bool(node, "qca,disable-smarteee"))
547 priv->flags |= AT803X_DISABLE_SMARTEEE;
549 if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) {
550 if (!tw || tw > 255) {
551 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
554 priv->smarteee_lpi_tw_1g = tw;
557 if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) {
558 if (!tw || tw > 255) {
559 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
562 priv->smarteee_lpi_tw_100m = tw;
565 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
569 sel = AT803X_CLK_OUT_25MHZ_XTAL;
572 sel = AT803X_CLK_OUT_50MHZ_PLL;
575 sel = AT803X_CLK_OUT_62_5MHZ_PLL;
578 sel = AT803X_CLK_OUT_125MHZ_PLL;
581 phydev_err(phydev, "invalid qca,clk-out-frequency\n");
585 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
586 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
588 /* Fixup for the AR8030/AR8035. This chip has another mask and
589 * doesn't support the DSP reference. Eg. the lowest bit of the
590 * mask. The upper two bits select the same frequencies. Mask
591 * the lowest bit here.
594 * There was no datasheet for the AR8030 available so this is
595 * just a guess. But the AR8035 is listed as pin compatible
596 * to the AR8030 so there might be a good chance it works on
599 if (phydev->drv->phy_id == ATH8030_PHY_ID ||
600 phydev->drv->phy_id == ATH8035_PHY_ID) {
601 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
602 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
606 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
608 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
610 case AR803X_STRENGTH_FULL:
611 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
613 case AR803X_STRENGTH_HALF:
614 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
616 case AR803X_STRENGTH_QUARTER:
617 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
620 phydev_err(phydev, "invalid qca,clk-out-strength\n");
625 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
628 if (phydev->drv->phy_id == ATH8031_PHY_ID) {
629 if (of_property_read_bool(node, "qca,keep-pll-enabled"))
630 priv->flags |= AT803X_KEEP_PLL_ENABLED;
632 ret = at8031_register_regulators(phydev);
636 priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev,
638 if (IS_ERR(priv->vddio)) {
639 phydev_err(phydev, "failed to get VDDIO regulator\n");
640 return PTR_ERR(priv->vddio);
647 static int at803x_probe(struct phy_device *phydev)
649 struct device *dev = &phydev->mdio.dev;
650 struct at803x_priv *priv;
653 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
659 ret = at803x_parse_dt(phydev);
664 ret = regulator_enable(priv->vddio);
672 static void at803x_remove(struct phy_device *phydev)
674 struct at803x_priv *priv = phydev->priv;
677 regulator_disable(priv->vddio);
680 static int at803x_get_features(struct phy_device *phydev)
684 err = genphy_read_abilities(phydev);
688 if (phydev->drv->phy_id != ATH8031_PHY_ID)
691 /* AR8031/AR8033 have different status registers
692 * for copper and fiber operation. However, the
693 * extended status register is the same for both
696 * As a result of that, ESTATUS_1000_XFULL is set
697 * to 1 even when operating in copper TP mode.
699 * Remove this mode from the supported link modes,
700 * as this driver currently only supports copper
703 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
708 static int at803x_smarteee_config(struct phy_device *phydev)
710 struct at803x_priv *priv = phydev->priv;
711 u16 mask = 0, val = 0;
714 if (priv->flags & AT803X_DISABLE_SMARTEEE)
715 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
716 AT803X_MMD3_SMARTEEE_CTL3,
717 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0);
719 if (priv->smarteee_lpi_tw_1g) {
721 val |= priv->smarteee_lpi_tw_1g << 8;
723 if (priv->smarteee_lpi_tw_100m) {
725 val |= priv->smarteee_lpi_tw_100m;
730 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
735 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
736 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
737 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
740 static int at803x_clk_out_config(struct phy_device *phydev)
742 struct at803x_priv *priv = phydev->priv;
744 if (!priv->clk_25m_mask)
747 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
748 priv->clk_25m_mask, priv->clk_25m_reg);
751 static int at8031_pll_config(struct phy_device *phydev)
753 struct at803x_priv *priv = phydev->priv;
755 /* The default after hardware reset is PLL OFF. After a soft reset, the
756 * values are retained.
758 if (priv->flags & AT803X_KEEP_PLL_ENABLED)
759 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
760 0, AT803X_DEBUG_PLL_ON);
762 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
763 AT803X_DEBUG_PLL_ON, 0);
766 static int at803x_config_init(struct phy_device *phydev)
770 if (phydev->drv->phy_id == ATH8031_PHY_ID) {
771 /* Some bootloaders leave the fiber page selected.
772 * Switch to the copper page, as otherwise we read
773 * the PHY capabilities from the fiber side.
775 phy_lock_mdio_bus(phydev);
776 ret = at803x_write_page(phydev, AT803X_PAGE_COPPER);
777 phy_unlock_mdio_bus(phydev);
781 ret = at8031_pll_config(phydev);
786 /* The RX and TX delay default is:
787 * after HW reset: RX delay enabled and TX delay disabled
788 * after SW reset: RX delay enabled, while TX delay retains the
789 * value before reset.
791 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
792 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
793 ret = at803x_enable_rx_delay(phydev);
795 ret = at803x_disable_rx_delay(phydev);
799 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
800 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
801 ret = at803x_enable_tx_delay(phydev);
803 ret = at803x_disable_tx_delay(phydev);
807 ret = at803x_smarteee_config(phydev);
811 ret = at803x_clk_out_config(phydev);
815 /* Ar803x extended next page bit is enabled by default. Cisco
816 * multigig switches read this bit and attempt to negotiate 10Gbps
817 * rates even if the next page bit is disabled. This is incorrect
818 * behaviour but we still need to accommodate it. XNP is only needed
819 * for 10Gbps support, so disable XNP.
821 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0);
824 static int at803x_ack_interrupt(struct phy_device *phydev)
828 err = phy_read(phydev, AT803X_INTR_STATUS);
830 return (err < 0) ? err : 0;
833 static int at803x_config_intr(struct phy_device *phydev)
838 value = phy_read(phydev, AT803X_INTR_ENABLE);
840 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
841 /* Clear any pending interrupts */
842 err = at803x_ack_interrupt(phydev);
846 value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
847 value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
848 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
849 value |= AT803X_INTR_ENABLE_LINK_FAIL;
850 value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
852 err = phy_write(phydev, AT803X_INTR_ENABLE, value);
854 err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
858 /* Clear any pending interrupts */
859 err = at803x_ack_interrupt(phydev);
865 static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev)
867 int irq_status, int_enabled;
869 irq_status = phy_read(phydev, AT803X_INTR_STATUS);
870 if (irq_status < 0) {
875 /* Read the current enabled interrupts */
876 int_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
877 if (int_enabled < 0) {
882 /* See if this was one of our enabled interrupts */
883 if (!(irq_status & int_enabled))
886 phy_trigger_machine(phydev);
891 static void at803x_link_change_notify(struct phy_device *phydev)
894 * Conduct a hardware reset for AT8030 every time a link loss is
895 * signalled. This is necessary to circumvent a hardware bug that
896 * occurs when the cable is unplugged while TX packets are pending
897 * in the FIFO. In such cases, the FIFO enters an error mode it
898 * cannot recover from by software.
900 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
901 struct at803x_context context;
903 at803x_context_save(phydev, &context);
905 phy_device_reset(phydev, 1);
907 phy_device_reset(phydev, 0);
910 at803x_context_restore(phydev, &context);
912 phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
916 static int at803x_read_status(struct phy_device *phydev)
918 int ss, err, old_link = phydev->link;
920 /* Update the link, but return if there was an error */
921 err = genphy_update_link(phydev);
925 /* why bother the PHY if nothing can have changed */
926 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
929 phydev->speed = SPEED_UNKNOWN;
930 phydev->duplex = DUPLEX_UNKNOWN;
932 phydev->asym_pause = 0;
934 err = genphy_read_lpa(phydev);
938 /* Read the AT8035 PHY-Specific Status register, which indicates the
939 * speed and duplex that the PHY is actually using, irrespective of
940 * whether we are in autoneg mode or not.
942 ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
946 if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
949 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
953 switch (ss & AT803X_SS_SPEED_MASK) {
954 case AT803X_SS_SPEED_10:
955 phydev->speed = SPEED_10;
957 case AT803X_SS_SPEED_100:
958 phydev->speed = SPEED_100;
960 case AT803X_SS_SPEED_1000:
961 phydev->speed = SPEED_1000;
964 if (ss & AT803X_SS_DUPLEX)
965 phydev->duplex = DUPLEX_FULL;
967 phydev->duplex = DUPLEX_HALF;
969 if (ss & AT803X_SS_MDIX)
970 phydev->mdix = ETH_TP_MDI_X;
972 phydev->mdix = ETH_TP_MDI;
974 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
975 case AT803X_SFC_MANUAL_MDI:
976 phydev->mdix_ctrl = ETH_TP_MDI;
978 case AT803X_SFC_MANUAL_MDIX:
979 phydev->mdix_ctrl = ETH_TP_MDI_X;
981 case AT803X_SFC_AUTOMATIC_CROSSOVER:
982 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
987 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
988 phy_resolve_aneg_pause(phydev);
993 static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
999 val = AT803X_SFC_MANUAL_MDI;
1002 val = AT803X_SFC_MANUAL_MDIX;
1004 case ETH_TP_MDI_AUTO:
1005 val = AT803X_SFC_AUTOMATIC_CROSSOVER;
1011 return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
1012 AT803X_SFC_MDI_CROSSOVER_MODE_M,
1013 FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
1016 static int at803x_config_aneg(struct phy_device *phydev)
1020 ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
1024 /* Changes of the midx bits are disruptive to the normal operation;
1025 * therefore any changes to these registers must be followed by a
1026 * software reset to take effect.
1029 ret = genphy_soft_reset(phydev);
1034 return genphy_config_aneg(phydev);
1037 static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
1041 val = phy_read(phydev, AT803X_SMART_SPEED);
1045 if (val & AT803X_SMART_SPEED_ENABLE)
1046 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
1048 *d = DOWNSHIFT_DEV_DISABLE;
1053 static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
1059 case DOWNSHIFT_DEV_DEFAULT_COUNT:
1060 cnt = AT803X_DEFAULT_DOWNSHIFT;
1062 case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
1063 set = AT803X_SMART_SPEED_ENABLE |
1064 AT803X_SMART_SPEED_BYPASS_TIMER |
1065 FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
1066 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
1068 case DOWNSHIFT_DEV_DISABLE:
1070 mask = AT803X_SMART_SPEED_ENABLE |
1071 AT803X_SMART_SPEED_BYPASS_TIMER;
1077 ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
1079 /* After changing the smart speed settings, we need to perform a
1080 * software reset, use phy_init_hw() to make sure we set the
1081 * reapply any values which might got lost during software reset.
1084 ret = phy_init_hw(phydev);
1089 static int at803x_get_tunable(struct phy_device *phydev,
1090 struct ethtool_tunable *tuna, void *data)
1093 case ETHTOOL_PHY_DOWNSHIFT:
1094 return at803x_get_downshift(phydev, data);
1100 static int at803x_set_tunable(struct phy_device *phydev,
1101 struct ethtool_tunable *tuna, const void *data)
1104 case ETHTOOL_PHY_DOWNSHIFT:
1105 return at803x_set_downshift(phydev, *(const u8 *)data);
1111 static int at803x_cable_test_result_trans(u16 status)
1113 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1114 case AT803X_CDT_STATUS_STAT_NORMAL:
1115 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1116 case AT803X_CDT_STATUS_STAT_SHORT:
1117 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1118 case AT803X_CDT_STATUS_STAT_OPEN:
1119 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1120 case AT803X_CDT_STATUS_STAT_FAIL:
1122 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1126 static bool at803x_cdt_test_failed(u16 status)
1128 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
1129 AT803X_CDT_STATUS_STAT_FAIL;
1132 static bool at803x_cdt_fault_length_valid(u16 status)
1134 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1135 case AT803X_CDT_STATUS_STAT_OPEN:
1136 case AT803X_CDT_STATUS_STAT_SHORT:
1142 static int at803x_cdt_fault_length(u16 status)
1146 /* According to the datasheet the distance to the fault is
1147 * DELTA_TIME * 0.824 meters.
1149 * The author suspect the correct formula is:
1151 * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
1153 * where c is the speed of light, VF is the velocity factor of
1154 * the twisted pair cable, 125MHz the counter frequency and
1155 * we need to divide by 2 because the hardware will measure the
1156 * round trip time to the fault and back to the PHY.
1158 * With a VF of 0.69 we get the factor 0.824 mentioned in the
1161 dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status);
1163 return (dt * 824) / 10;
1166 static int at803x_cdt_start(struct phy_device *phydev, int pair)
1170 cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
1171 AT803X_CDT_ENABLE_TEST;
1173 return phy_write(phydev, AT803X_CDT, cdt);
1176 static int at803x_cdt_wait_for_completion(struct phy_device *phydev)
1180 /* One test run takes about 25ms */
1181 ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
1182 !(val & AT803X_CDT_ENABLE_TEST),
1183 30000, 100000, true);
1185 return ret < 0 ? ret : 0;
1188 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
1190 static const int ethtool_pair[] = {
1191 ETHTOOL_A_CABLE_PAIR_A,
1192 ETHTOOL_A_CABLE_PAIR_B,
1193 ETHTOOL_A_CABLE_PAIR_C,
1194 ETHTOOL_A_CABLE_PAIR_D,
1198 ret = at803x_cdt_start(phydev, pair);
1202 ret = at803x_cdt_wait_for_completion(phydev);
1206 val = phy_read(phydev, AT803X_CDT_STATUS);
1210 if (at803x_cdt_test_failed(val))
1213 ethnl_cable_test_result(phydev, ethtool_pair[pair],
1214 at803x_cable_test_result_trans(val));
1216 if (at803x_cdt_fault_length_valid(val))
1217 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
1218 at803x_cdt_fault_length(val));
1223 static int at803x_cable_test_get_status(struct phy_device *phydev,
1226 unsigned long pair_mask;
1230 if (phydev->phy_id == ATH9331_PHY_ID ||
1231 phydev->phy_id == ATH8032_PHY_ID)
1238 /* According to the datasheet the CDT can be performed when
1239 * there is no link partner or when the link partner is
1240 * auto-negotiating. Starting the test will restart the AN
1241 * automatically. It seems that doing this repeatedly we will
1242 * get a slot where our link partner won't disturb our
1245 while (pair_mask && retries--) {
1246 for_each_set_bit(pair, &pair_mask, 4) {
1247 ret = at803x_cable_test_one_pair(phydev, pair);
1251 clear_bit(pair, &pair_mask);
1262 static int at803x_cable_test_start(struct phy_device *phydev)
1264 /* Enable auto-negotiation, but advertise no capabilities, no link
1265 * will be established. A restart of the auto-negotiation is not
1266 * required, because the cable test will automatically break the link.
1268 phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
1269 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
1270 if (phydev->phy_id != ATH9331_PHY_ID &&
1271 phydev->phy_id != ATH8032_PHY_ID)
1272 phy_write(phydev, MII_CTRL1000, 0);
1274 /* we do all the (time consuming) work later */
1278 static int qca83xx_config_init(struct phy_device *phydev)
1282 switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
1284 switch (switch_revision) {
1286 /* For 100M waveform */
1287 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_0, 0x02ea);
1288 /* Turn on Gigabit clock */
1289 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x68a0);
1293 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
1296 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
1297 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x6860);
1298 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_5, 0x2c46);
1299 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
1306 static struct phy_driver at803x_driver[] = {
1308 /* Qualcomm Atheros AR8035 */
1309 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
1310 .name = "Qualcomm Atheros AR8035",
1311 .flags = PHY_POLL_CABLE_TEST,
1312 .probe = at803x_probe,
1313 .remove = at803x_remove,
1314 .config_aneg = at803x_config_aneg,
1315 .config_init = at803x_config_init,
1316 .soft_reset = genphy_soft_reset,
1317 .set_wol = at803x_set_wol,
1318 .get_wol = at803x_get_wol,
1319 .suspend = at803x_suspend,
1320 .resume = at803x_resume,
1321 /* PHY_GBIT_FEATURES */
1322 .read_status = at803x_read_status,
1323 .config_intr = at803x_config_intr,
1324 .handle_interrupt = at803x_handle_interrupt,
1325 .get_tunable = at803x_get_tunable,
1326 .set_tunable = at803x_set_tunable,
1327 .cable_test_start = at803x_cable_test_start,
1328 .cable_test_get_status = at803x_cable_test_get_status,
1330 /* Qualcomm Atheros AR8030 */
1331 .phy_id = ATH8030_PHY_ID,
1332 .name = "Qualcomm Atheros AR8030",
1333 .phy_id_mask = AT8030_PHY_ID_MASK,
1334 .probe = at803x_probe,
1335 .remove = at803x_remove,
1336 .config_init = at803x_config_init,
1337 .link_change_notify = at803x_link_change_notify,
1338 .set_wol = at803x_set_wol,
1339 .get_wol = at803x_get_wol,
1340 .suspend = at803x_suspend,
1341 .resume = at803x_resume,
1342 /* PHY_BASIC_FEATURES */
1343 .config_intr = at803x_config_intr,
1344 .handle_interrupt = at803x_handle_interrupt,
1346 /* Qualcomm Atheros AR8031/AR8033 */
1347 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
1348 .name = "Qualcomm Atheros AR8031/AR8033",
1349 .flags = PHY_POLL_CABLE_TEST,
1350 .probe = at803x_probe,
1351 .remove = at803x_remove,
1352 .config_init = at803x_config_init,
1353 .config_aneg = at803x_config_aneg,
1354 .soft_reset = genphy_soft_reset,
1355 .set_wol = at803x_set_wol,
1356 .get_wol = at803x_get_wol,
1357 .suspend = at803x_suspend,
1358 .resume = at803x_resume,
1359 .read_page = at803x_read_page,
1360 .write_page = at803x_write_page,
1361 .get_features = at803x_get_features,
1362 .read_status = at803x_read_status,
1363 .config_intr = &at803x_config_intr,
1364 .handle_interrupt = at803x_handle_interrupt,
1365 .get_tunable = at803x_get_tunable,
1366 .set_tunable = at803x_set_tunable,
1367 .cable_test_start = at803x_cable_test_start,
1368 .cable_test_get_status = at803x_cable_test_get_status,
1370 /* Qualcomm Atheros AR8032 */
1371 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
1372 .name = "Qualcomm Atheros AR8032",
1373 .probe = at803x_probe,
1374 .remove = at803x_remove,
1375 .flags = PHY_POLL_CABLE_TEST,
1376 .config_init = at803x_config_init,
1377 .link_change_notify = at803x_link_change_notify,
1378 .set_wol = at803x_set_wol,
1379 .get_wol = at803x_get_wol,
1380 .suspend = at803x_suspend,
1381 .resume = at803x_resume,
1382 /* PHY_BASIC_FEATURES */
1383 .config_intr = at803x_config_intr,
1384 .handle_interrupt = at803x_handle_interrupt,
1385 .cable_test_start = at803x_cable_test_start,
1386 .cable_test_get_status = at803x_cable_test_get_status,
1388 /* ATHEROS AR9331 */
1389 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
1390 .name = "Qualcomm Atheros AR9331 built-in PHY",
1391 .suspend = at803x_suspend,
1392 .resume = at803x_resume,
1393 .flags = PHY_POLL_CABLE_TEST,
1394 /* PHY_BASIC_FEATURES */
1395 .config_intr = &at803x_config_intr,
1396 .handle_interrupt = at803x_handle_interrupt,
1397 .cable_test_start = at803x_cable_test_start,
1398 .cable_test_get_status = at803x_cable_test_get_status,
1399 .read_status = at803x_read_status,
1400 .soft_reset = genphy_soft_reset,
1401 .config_aneg = at803x_config_aneg,
1404 .phy_id = QCA8337_PHY_ID,
1405 .phy_id_mask = QCA8K_PHY_ID_MASK,
1406 .name = "QCA PHY 8337",
1407 /* PHY_GBIT_FEATURES */
1408 .probe = at803x_probe,
1409 .flags = PHY_IS_INTERNAL,
1410 .config_init = qca83xx_config_init,
1411 .soft_reset = genphy_soft_reset,
1412 .get_sset_count = at803x_get_sset_count,
1413 .get_strings = at803x_get_strings,
1414 .get_stats = at803x_get_stats,
1417 module_phy_driver(at803x_driver);
1419 static struct mdio_device_id __maybe_unused atheros_tbl[] = {
1420 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
1421 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
1422 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
1423 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
1424 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
1428 MODULE_DEVICE_TABLE(mdio, atheros_tbl);