1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Aquantia PHY
5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com>
7 * Copyright 2015 Freescale Semiconductor, Inc.
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/delay.h>
13 #include <linux/bitfield.h>
14 #include <linux/phy.h>
18 #define PHY_ID_AQ1202 0x03a1b445
19 #define PHY_ID_AQ2104 0x03a1b460
20 #define PHY_ID_AQR105 0x03a1b4a2
21 #define PHY_ID_AQR106 0x03a1b4d0
22 #define PHY_ID_AQR107 0x03a1b4e0
23 #define PHY_ID_AQCS109 0x03a1b5c2
24 #define PHY_ID_AQR405 0x03a1b4b0
25 #define PHY_ID_AQR112 0x03a1b662
26 #define PHY_ID_AQR412 0x03a1b712
27 #define PHY_ID_AQR113C 0x31c31c12
29 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812
30 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
31 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
32 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1
33 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2
34 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3
35 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4
36 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
37 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7
38 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
40 #define MDIO_AN_VEND_PROV 0xc400
41 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
42 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
43 #define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11)
44 #define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10)
45 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4)
46 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0)
47 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4
49 #define MDIO_AN_TX_VEND_STATUS1 0xc800
50 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1)
51 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0
52 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1
53 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2
54 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3
55 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4
56 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5
57 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0)
59 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00
60 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1)
62 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01
63 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0)
65 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401
66 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0)
68 #define MDIO_AN_RX_LP_STAT1 0xe820
69 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15)
70 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14)
71 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13)
72 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12)
73 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2)
75 #define MDIO_AN_RX_LP_STAT4 0xe823
76 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8)
77 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0)
79 #define MDIO_AN_RX_VEND_STAT3 0xe832
80 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0)
83 #define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292
84 #define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294
85 #define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297
86 #define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313
87 #define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315
88 #define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317
89 #define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318
90 #define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319
91 #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
92 #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
94 /* Sleep and timeout for checking if the Processor-Intensive
95 * MDIO operation is finished
97 #define AQR107_OP_IN_PROG_SLEEP 1000
98 #define AQR107_OP_IN_PROG_TIMEOUT 100000
100 struct aqr107_hw_stat {
106 #define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
107 static const struct aqr107_hw_stat aqr107_hw_stats[] = {
108 SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26),
109 SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26),
110 SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8),
111 SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26),
112 SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26),
113 SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8),
114 SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8),
115 SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8),
116 SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16),
117 SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22),
119 #define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
122 u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
125 static int aqr107_get_sset_count(struct phy_device *phydev)
127 return AQR107_SGMII_STAT_SZ;
130 static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
134 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)
135 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name,
139 static u64 aqr107_get_stat(struct phy_device *phydev, int index)
141 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index;
142 int len_l = min(stat->size, 16);
143 int len_h = stat->size - len_l;
147 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
151 ret = val & GENMASK(len_l - 1, 0);
153 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
157 ret += (val & GENMASK(len_h - 1, 0)) << 16;
163 static void aqr107_get_stats(struct phy_device *phydev,
164 struct ethtool_stats *stats, u64 *data)
166 struct aqr107_priv *priv = phydev->priv;
170 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {
171 val = aqr107_get_stat(phydev, i);
173 phydev_err(phydev, "Reading HW Statistics failed for %s\n",
174 aqr107_hw_stats[i].name);
176 priv->sgmii_stats[i] += val;
178 data[i] = priv->sgmii_stats[i];
182 static int aqr_config_aneg(struct phy_device *phydev)
184 bool changed = false;
188 if (phydev->autoneg == AUTONEG_DISABLE)
189 return genphy_c45_pma_setup_forced(phydev);
191 ret = genphy_c45_an_config_aneg(phydev);
197 /* Clause 45 has no standardized support for 1000BaseT, therefore
198 * use vendor registers for this mode.
201 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
202 phydev->advertising))
203 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
205 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
206 phydev->advertising))
207 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
209 /* Handle the case when the 2.5G and 5G speeds are not advertised */
210 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
211 phydev->advertising))
212 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL;
214 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
215 phydev->advertising))
216 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL;
218 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
219 MDIO_AN_VEND_PROV_1000BASET_HALF |
220 MDIO_AN_VEND_PROV_1000BASET_FULL |
221 MDIO_AN_VEND_PROV_2500BASET_FULL |
222 MDIO_AN_VEND_PROV_5000BASET_FULL, reg);
228 return genphy_c45_check_and_restart_aneg(phydev, changed);
231 static int aqr_config_intr(struct phy_device *phydev)
233 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
237 /* Clear any pending interrupts before enabling them */
238 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
243 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
244 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);
248 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
249 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);
253 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
254 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
255 VEND1_GLOBAL_INT_VEND_MASK_AN : 0);
260 /* Clear any pending interrupts after we have disabled them */
261 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
269 static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev)
273 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN,
274 MDIO_AN_TX_VEND_INT_STATUS2);
275 if (irq_status < 0) {
280 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK))
283 phy_trigger_machine(phydev);
288 static int aqr_read_status(struct phy_device *phydev)
292 if (phydev->autoneg == AUTONEG_ENABLE) {
293 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
297 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
298 phydev->lp_advertising,
299 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL);
300 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
301 phydev->lp_advertising,
302 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF);
305 return genphy_c45_read_status(phydev);
308 static int aqr107_read_rate(struct phy_device *phydev)
313 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
317 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
318 phydev->duplex = DUPLEX_FULL;
320 phydev->duplex = DUPLEX_HALF;
322 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
323 case MDIO_AN_TX_VEND_STATUS1_10BASET:
324 phydev->speed = SPEED_10;
325 config_reg = VEND1_GLOBAL_CFG_10M;
327 case MDIO_AN_TX_VEND_STATUS1_100BASETX:
328 phydev->speed = SPEED_100;
329 config_reg = VEND1_GLOBAL_CFG_100M;
331 case MDIO_AN_TX_VEND_STATUS1_1000BASET:
332 phydev->speed = SPEED_1000;
333 config_reg = VEND1_GLOBAL_CFG_1G;
335 case MDIO_AN_TX_VEND_STATUS1_2500BASET:
336 phydev->speed = SPEED_2500;
337 config_reg = VEND1_GLOBAL_CFG_2_5G;
339 case MDIO_AN_TX_VEND_STATUS1_5000BASET:
340 phydev->speed = SPEED_5000;
341 config_reg = VEND1_GLOBAL_CFG_5G;
343 case MDIO_AN_TX_VEND_STATUS1_10GBASET:
344 phydev->speed = SPEED_10000;
345 config_reg = VEND1_GLOBAL_CFG_10G;
348 phydev->speed = SPEED_UNKNOWN;
352 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg);
356 if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) ==
357 VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE)
358 phydev->rate_matching = RATE_MATCH_PAUSE;
360 phydev->rate_matching = RATE_MATCH_NONE;
365 static int aqr107_read_status(struct phy_device *phydev)
369 ret = aqr_read_status(phydev);
373 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
376 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
380 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
381 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
382 phydev->interface = PHY_INTERFACE_MODE_10GKR;
384 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX:
385 phydev->interface = PHY_INTERFACE_MODE_1000BASEKX;
387 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
388 phydev->interface = PHY_INTERFACE_MODE_10GBASER;
390 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
391 phydev->interface = PHY_INTERFACE_MODE_USXGMII;
393 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI:
394 phydev->interface = PHY_INTERFACE_MODE_XAUI;
396 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
397 phydev->interface = PHY_INTERFACE_MODE_SGMII;
399 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI:
400 phydev->interface = PHY_INTERFACE_MODE_RXAUI;
402 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
403 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
406 phydev->interface = PHY_INTERFACE_MODE_NA;
410 /* Read possibly downshifted rate from vendor register */
411 return aqr107_read_rate(phydev);
414 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
416 int val, cnt, enable;
418 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
422 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
423 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
425 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
430 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
434 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt))
437 if (cnt != DOWNSHIFT_DEV_DISABLE) {
438 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN;
439 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt);
442 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
443 MDIO_AN_VEND_PROV_DOWNSHIFT_EN |
444 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
447 static int aqr107_get_tunable(struct phy_device *phydev,
448 struct ethtool_tunable *tuna, void *data)
451 case ETHTOOL_PHY_DOWNSHIFT:
452 return aqr107_get_downshift(phydev, data);
458 static int aqr107_set_tunable(struct phy_device *phydev,
459 struct ethtool_tunable *tuna, const void *data)
462 case ETHTOOL_PHY_DOWNSHIFT:
463 return aqr107_set_downshift(phydev, *(const u8 *)data);
469 /* If we configure settings whilst firmware is still initializing the chip,
470 * then these settings may be overwritten. Therefore make sure chip
471 * initialization has completed. Use presence of the firmware ID as
472 * indicator for initialization having completed.
473 * The chip also provides a "reset completed" bit, but it's cleared after
474 * read. Therefore function would time out if called again.
476 static int aqr107_wait_reset_complete(struct phy_device *phydev)
480 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
481 VEND1_GLOBAL_FW_ID, val, val != 0,
482 20000, 2000000, false);
485 static void aqr107_chip_info(struct phy_device *phydev)
487 u8 fw_major, fw_minor, build_id, prov_id;
490 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
494 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val);
495 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val);
497 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
501 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
502 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
504 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
505 fw_major, fw_minor, build_id, prov_id);
508 static int aqr107_config_init(struct phy_device *phydev)
512 /* Check that the PHY interface type is compatible */
513 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
514 phydev->interface != PHY_INTERFACE_MODE_1000BASEKX &&
515 phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
516 phydev->interface != PHY_INTERFACE_MODE_XGMII &&
517 phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
518 phydev->interface != PHY_INTERFACE_MODE_10GKR &&
519 phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
520 phydev->interface != PHY_INTERFACE_MODE_XAUI &&
521 phydev->interface != PHY_INTERFACE_MODE_RXAUI)
524 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
525 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n");
527 ret = aqr107_wait_reset_complete(phydev);
529 aqr107_chip_info(phydev);
531 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
534 static int aqcs109_config_init(struct phy_device *phydev)
538 /* Check that the PHY interface type is compatible */
539 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
540 phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
543 ret = aqr107_wait_reset_complete(phydev);
545 aqr107_chip_info(phydev);
547 /* AQCS109 belongs to a chip family partially supporting 10G and 5G.
548 * PMA speed ability bits are the same for all members of the family,
549 * AQCS109 however supports speeds up to 2.5G only.
551 phy_set_max_speed(phydev, SPEED_2500);
553 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
556 static void aqr107_link_change_notify(struct phy_device *phydev)
558 u8 fw_major, fw_minor;
559 bool downshift, short_reach, afr;
562 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
565 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
566 /* call failed or link partner is no Aquantia PHY */
567 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))
570 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH;
571 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT;
573 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
577 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val);
578 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val);
580 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
584 afr = val & MDIO_AN_RX_VEND_STAT3_AFR;
586 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
588 short_reach ? ", short reach mode" : "",
589 downshift ? ", fast-retrain downshift advertised" : "",
590 afr ? ", fast reframe advertised" : "");
592 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
596 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val);
597 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2)
598 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
601 static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
605 /* The datasheet notes to wait at least 1ms after issuing a
606 * processor intensive operation before checking.
607 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout
608 * because that just determines the maximum time slept, not the minimum.
610 usleep_range(1000, 5000);
612 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
613 VEND1_GLOBAL_GEN_STAT2, val,
614 !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG),
615 AQR107_OP_IN_PROG_SLEEP,
616 AQR107_OP_IN_PROG_TIMEOUT, false);
618 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n");
625 static int aqr107_get_rate_matching(struct phy_device *phydev,
626 phy_interface_t iface)
628 if (iface == PHY_INTERFACE_MODE_10GBASER ||
629 iface == PHY_INTERFACE_MODE_2500BASEX ||
630 iface == PHY_INTERFACE_MODE_NA)
631 return RATE_MATCH_PAUSE;
632 return RATE_MATCH_NONE;
635 static int aqr107_suspend(struct phy_device *phydev)
639 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
644 return aqr107_wait_processor_intensive_op(phydev);
647 static int aqr107_resume(struct phy_device *phydev)
651 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
656 return aqr107_wait_processor_intensive_op(phydev);
659 static const u16 aqr_global_cfg_regs[] = {
660 VEND1_GLOBAL_CFG_10M,
661 VEND1_GLOBAL_CFG_100M,
663 VEND1_GLOBAL_CFG_2_5G,
668 static int aqr107_fill_interface_modes(struct phy_device *phydev)
670 unsigned long *possible = phydev->possible_interfaces;
671 unsigned int serdes_mode, rate_adapt;
672 phy_interface_t interface;
675 /* Walk the media-speed configuration registers to determine which
676 * host-side serdes modes may be used by the PHY depending on the
677 * negotiated media speed.
679 for (i = 0; i < ARRAY_SIZE(aqr_global_cfg_regs); i++) {
680 val = phy_read_mmd(phydev, MDIO_MMD_VEND1,
681 aqr_global_cfg_regs[i]);
685 serdes_mode = FIELD_GET(VEND1_GLOBAL_CFG_SERDES_MODE, val);
686 rate_adapt = FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val);
688 switch (serdes_mode) {
689 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI:
690 if (rate_adapt == VEND1_GLOBAL_CFG_RATE_ADAPT_USX)
691 interface = PHY_INTERFACE_MODE_USXGMII;
693 interface = PHY_INTERFACE_MODE_10GBASER;
696 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G:
697 interface = PHY_INTERFACE_MODE_5GBASER;
700 case VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII:
701 interface = PHY_INTERFACE_MODE_2500BASEX;
704 case VEND1_GLOBAL_CFG_SERDES_MODE_SGMII:
705 interface = PHY_INTERFACE_MODE_SGMII;
709 phydev_warn(phydev, "unrecognised serdes mode %u\n",
711 interface = PHY_INTERFACE_MODE_NA;
715 if (interface != PHY_INTERFACE_MODE_NA)
716 __set_bit(interface, possible);
722 static int aqr113c_config_init(struct phy_device *phydev)
726 ret = aqr107_config_init(phydev);
730 return aqr107_fill_interface_modes(phydev);
733 static int aqr107_probe(struct phy_device *phydev)
737 phydev->priv = devm_kzalloc(&phydev->mdio.dev,
738 sizeof(struct aqr107_priv), GFP_KERNEL);
742 ret = aqr_firmware_load(phydev);
746 return aqr_hwmon_probe(phydev);
749 static struct phy_driver aqr_driver[] = {
751 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
752 .name = "Aquantia AQ1202",
753 .config_aneg = aqr_config_aneg,
754 .config_intr = aqr_config_intr,
755 .handle_interrupt = aqr_handle_interrupt,
756 .read_status = aqr_read_status,
759 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
760 .name = "Aquantia AQ2104",
761 .config_aneg = aqr_config_aneg,
762 .config_intr = aqr_config_intr,
763 .handle_interrupt = aqr_handle_interrupt,
764 .read_status = aqr_read_status,
767 PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
768 .name = "Aquantia AQR105",
769 .config_aneg = aqr_config_aneg,
770 .config_intr = aqr_config_intr,
771 .handle_interrupt = aqr_handle_interrupt,
772 .read_status = aqr_read_status,
773 .suspend = aqr107_suspend,
774 .resume = aqr107_resume,
777 PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
778 .name = "Aquantia AQR106",
779 .config_aneg = aqr_config_aneg,
780 .config_intr = aqr_config_intr,
781 .handle_interrupt = aqr_handle_interrupt,
782 .read_status = aqr_read_status,
785 PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
786 .name = "Aquantia AQR107",
787 .probe = aqr107_probe,
788 .get_rate_matching = aqr107_get_rate_matching,
789 .config_init = aqr107_config_init,
790 .config_aneg = aqr_config_aneg,
791 .config_intr = aqr_config_intr,
792 .handle_interrupt = aqr_handle_interrupt,
793 .read_status = aqr107_read_status,
794 .get_tunable = aqr107_get_tunable,
795 .set_tunable = aqr107_set_tunable,
796 .suspend = aqr107_suspend,
797 .resume = aqr107_resume,
798 .get_sset_count = aqr107_get_sset_count,
799 .get_strings = aqr107_get_strings,
800 .get_stats = aqr107_get_stats,
801 .link_change_notify = aqr107_link_change_notify,
804 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
805 .name = "Aquantia AQCS109",
806 .probe = aqr107_probe,
807 .get_rate_matching = aqr107_get_rate_matching,
808 .config_init = aqcs109_config_init,
809 .config_aneg = aqr_config_aneg,
810 .config_intr = aqr_config_intr,
811 .handle_interrupt = aqr_handle_interrupt,
812 .read_status = aqr107_read_status,
813 .get_tunable = aqr107_get_tunable,
814 .set_tunable = aqr107_set_tunable,
815 .suspend = aqr107_suspend,
816 .resume = aqr107_resume,
817 .get_sset_count = aqr107_get_sset_count,
818 .get_strings = aqr107_get_strings,
819 .get_stats = aqr107_get_stats,
820 .link_change_notify = aqr107_link_change_notify,
823 PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
824 .name = "Aquantia AQR405",
825 .config_aneg = aqr_config_aneg,
826 .config_intr = aqr_config_intr,
827 .handle_interrupt = aqr_handle_interrupt,
828 .read_status = aqr_read_status,
831 PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
832 .name = "Aquantia AQR112",
833 .probe = aqr107_probe,
834 .config_aneg = aqr_config_aneg,
835 .config_intr = aqr_config_intr,
836 .handle_interrupt = aqr_handle_interrupt,
837 .get_tunable = aqr107_get_tunable,
838 .set_tunable = aqr107_set_tunable,
839 .suspend = aqr107_suspend,
840 .resume = aqr107_resume,
841 .read_status = aqr107_read_status,
842 .get_rate_matching = aqr107_get_rate_matching,
843 .get_sset_count = aqr107_get_sset_count,
844 .get_strings = aqr107_get_strings,
845 .get_stats = aqr107_get_stats,
846 .link_change_notify = aqr107_link_change_notify,
849 PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
850 .name = "Aquantia AQR412",
851 .probe = aqr107_probe,
852 .config_aneg = aqr_config_aneg,
853 .config_intr = aqr_config_intr,
854 .handle_interrupt = aqr_handle_interrupt,
855 .get_tunable = aqr107_get_tunable,
856 .set_tunable = aqr107_set_tunable,
857 .suspend = aqr107_suspend,
858 .resume = aqr107_resume,
859 .read_status = aqr107_read_status,
860 .get_rate_matching = aqr107_get_rate_matching,
861 .get_sset_count = aqr107_get_sset_count,
862 .get_strings = aqr107_get_strings,
863 .get_stats = aqr107_get_stats,
864 .link_change_notify = aqr107_link_change_notify,
867 PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
868 .name = "Aquantia AQR113C",
869 .probe = aqr107_probe,
870 .get_rate_matching = aqr107_get_rate_matching,
871 .config_init = aqr113c_config_init,
872 .config_aneg = aqr_config_aneg,
873 .config_intr = aqr_config_intr,
874 .handle_interrupt = aqr_handle_interrupt,
875 .read_status = aqr107_read_status,
876 .get_tunable = aqr107_get_tunable,
877 .set_tunable = aqr107_set_tunable,
878 .suspend = aqr107_suspend,
879 .resume = aqr107_resume,
880 .get_sset_count = aqr107_get_sset_count,
881 .get_strings = aqr107_get_strings,
882 .get_stats = aqr107_get_stats,
883 .link_change_notify = aqr107_link_change_notify,
887 module_phy_driver(aqr_driver);
889 static struct mdio_device_id __maybe_unused aqr_tbl[] = {
890 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
891 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
892 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
893 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
894 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
895 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
896 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
897 { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
898 { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
899 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
903 MODULE_DEVICE_TABLE(mdio, aqr_tbl);
905 MODULE_DESCRIPTION("Aquantia PHY driver");
906 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
907 MODULE_LICENSE("GPL v2");