1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Analog Devices Industrial Ethernet PHYs
5 * Copyright 2019 Analog Devices Inc.
7 #include <linux/kernel.h>
8 #include <linux/bitfield.h>
9 #include <linux/delay.h>
10 #include <linux/errno.h>
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/mii.h>
14 #include <linux/phy.h>
15 #include <linux/property.h>
17 #define PHY_ID_ADIN1200 0x0283bc20
18 #define PHY_ID_ADIN1300 0x0283bc30
20 #define ADIN1300_MII_EXT_REG_PTR 0x0010
21 #define ADIN1300_MII_EXT_REG_DATA 0x0011
23 #define ADIN1300_PHY_CTRL1 0x0012
24 #define ADIN1300_AUTO_MDI_EN BIT(10)
25 #define ADIN1300_MAN_MDIX_EN BIT(9)
27 #define ADIN1300_RX_ERR_CNT 0x0014
29 #define ADIN1300_PHY_CTRL_STATUS2 0x0015
30 #define ADIN1300_NRG_PD_EN BIT(3)
31 #define ADIN1300_NRG_PD_TX_EN BIT(2)
32 #define ADIN1300_NRG_PD_STATUS BIT(1)
34 #define ADIN1300_PHY_CTRL2 0x0016
35 #define ADIN1300_DOWNSPEED_AN_100_EN BIT(11)
36 #define ADIN1300_DOWNSPEED_AN_10_EN BIT(10)
37 #define ADIN1300_GROUP_MDIO_EN BIT(6)
38 #define ADIN1300_DOWNSPEEDS_EN \
39 (ADIN1300_DOWNSPEED_AN_100_EN | ADIN1300_DOWNSPEED_AN_10_EN)
41 #define ADIN1300_PHY_CTRL3 0x0017
42 #define ADIN1300_LINKING_EN BIT(13)
43 #define ADIN1300_DOWNSPEED_RETRIES_MSK GENMASK(12, 10)
45 #define ADIN1300_INT_MASK_REG 0x0018
46 #define ADIN1300_INT_MDIO_SYNC_EN BIT(9)
47 #define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8)
48 #define ADIN1300_INT_ANEG_PAGE_RX_EN BIT(6)
49 #define ADIN1300_INT_IDLE_ERR_CNT_EN BIT(5)
50 #define ADIN1300_INT_MAC_FIFO_OU_EN BIT(4)
51 #define ADIN1300_INT_RX_STAT_CHNG_EN BIT(3)
52 #define ADIN1300_INT_LINK_STAT_CHNG_EN BIT(2)
53 #define ADIN1300_INT_SPEED_CHNG_EN BIT(1)
54 #define ADIN1300_INT_HW_IRQ_EN BIT(0)
55 #define ADIN1300_INT_MASK_EN \
56 (ADIN1300_INT_LINK_STAT_CHNG_EN | ADIN1300_INT_HW_IRQ_EN)
57 #define ADIN1300_INT_STATUS_REG 0x0019
59 #define ADIN1300_PHY_STATUS1 0x001a
60 #define ADIN1300_PAIR_01_SWAP BIT(11)
62 /* EEE register addresses, accessible via Clause 22 access using
63 * ADIN1300_MII_EXT_REG_PTR & ADIN1300_MII_EXT_REG_DATA.
64 * The bit-fields are the same as specified by IEEE for EEE.
66 #define ADIN1300_EEE_CAP_REG 0x8000
67 #define ADIN1300_EEE_ADV_REG 0x8001
68 #define ADIN1300_EEE_LPABLE_REG 0x8002
69 #define ADIN1300_CLOCK_STOP_REG 0x9400
70 #define ADIN1300_LPI_WAKE_ERR_CNT_REG 0xa000
72 #define ADIN1300_GE_SOFT_RESET_REG 0xff0c
73 #define ADIN1300_GE_SOFT_RESET BIT(0)
75 #define ADIN1300_GE_RGMII_CFG_REG 0xff23
76 #define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6)
77 #define ADIN1300_GE_RGMII_RX_SEL(x) \
78 FIELD_PREP(ADIN1300_GE_RGMII_RX_MSK, x)
79 #define ADIN1300_GE_RGMII_GTX_MSK GENMASK(5, 3)
80 #define ADIN1300_GE_RGMII_GTX_SEL(x) \
81 FIELD_PREP(ADIN1300_GE_RGMII_GTX_MSK, x)
82 #define ADIN1300_GE_RGMII_RXID_EN BIT(2)
83 #define ADIN1300_GE_RGMII_TXID_EN BIT(1)
84 #define ADIN1300_GE_RGMII_EN BIT(0)
86 /* RGMII internal delay settings for rx and tx for ADIN1300 */
87 #define ADIN1300_RGMII_1_60_NS 0x0001
88 #define ADIN1300_RGMII_1_80_NS 0x0002
89 #define ADIN1300_RGMII_2_00_NS 0x0000
90 #define ADIN1300_RGMII_2_20_NS 0x0006
91 #define ADIN1300_RGMII_2_40_NS 0x0007
93 #define ADIN1300_GE_RMII_CFG_REG 0xff24
94 #define ADIN1300_GE_RMII_FIFO_DEPTH_MSK GENMASK(6, 4)
95 #define ADIN1300_GE_RMII_FIFO_DEPTH_SEL(x) \
96 FIELD_PREP(ADIN1300_GE_RMII_FIFO_DEPTH_MSK, x)
97 #define ADIN1300_GE_RMII_EN BIT(0)
99 /* RMII fifo depth values */
100 #define ADIN1300_RMII_4_BITS 0x0000
101 #define ADIN1300_RMII_8_BITS 0x0001
102 #define ADIN1300_RMII_12_BITS 0x0002
103 #define ADIN1300_RMII_16_BITS 0x0003
104 #define ADIN1300_RMII_20_BITS 0x0004
105 #define ADIN1300_RMII_24_BITS 0x0005
108 * struct adin_cfg_reg_map - map a config value to aregister value
109 * @cfg: value in device configuration
110 * @reg: value in the register
112 struct adin_cfg_reg_map {
117 static const struct adin_cfg_reg_map adin_rgmii_delays[] = {
118 { 1600, ADIN1300_RGMII_1_60_NS },
119 { 1800, ADIN1300_RGMII_1_80_NS },
120 { 2000, ADIN1300_RGMII_2_00_NS },
121 { 2200, ADIN1300_RGMII_2_20_NS },
122 { 2400, ADIN1300_RGMII_2_40_NS },
126 static const struct adin_cfg_reg_map adin_rmii_fifo_depths[] = {
127 { 4, ADIN1300_RMII_4_BITS },
128 { 8, ADIN1300_RMII_8_BITS },
129 { 12, ADIN1300_RMII_12_BITS },
130 { 16, ADIN1300_RMII_16_BITS },
131 { 20, ADIN1300_RMII_20_BITS },
132 { 24, ADIN1300_RMII_24_BITS },
137 * struct adin_clause45_mmd_map - map to convert Clause 45 regs to Clause 22
138 * @devad: device address used in Clause 45 access
139 * @cl45_regnum: register address defined by Clause 45
140 * @adin_regnum: equivalent register address accessible via Clause 22
142 struct adin_clause45_mmd_map {
148 static const struct adin_clause45_mmd_map adin_clause45_mmd_map[] = {
149 { MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE, ADIN1300_EEE_CAP_REG },
150 { MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, ADIN1300_EEE_LPABLE_REG },
151 { MDIO_MMD_AN, MDIO_AN_EEE_ADV, ADIN1300_EEE_ADV_REG },
152 { MDIO_MMD_PCS, MDIO_CTRL1, ADIN1300_CLOCK_STOP_REG },
153 { MDIO_MMD_PCS, MDIO_PCS_EEE_WK_ERR, ADIN1300_LPI_WAKE_ERR_CNT_REG },
156 struct adin_hw_stat {
162 static const struct adin_hw_stat adin_hw_stats[] = {
163 { "total_frames_checked_count", 0x940A, 0x940B }, /* hi + lo */
164 { "length_error_frames_count", 0x940C },
165 { "alignment_error_frames_count", 0x940D },
166 { "symbol_error_count", 0x940E },
167 { "oversized_frames_count", 0x940F },
168 { "undersized_frames_count", 0x9410 },
169 { "odd_nibble_frames_count", 0x9411 },
170 { "odd_preamble_packet_count", 0x9412 },
171 { "dribble_bits_frames_count", 0x9413 },
172 { "false_carrier_events_count", 0x9414 },
176 * struct adin_priv - ADIN PHY driver private data
177 * @stats: statistic counters for the PHY
180 u64 stats[ARRAY_SIZE(adin_hw_stats)];
183 static int adin_lookup_reg_value(const struct adin_cfg_reg_map *tbl, int cfg)
187 for (i = 0; tbl[i].cfg; i++) {
188 if (tbl[i].cfg == cfg)
195 static u32 adin_get_reg_value(struct phy_device *phydev,
196 const char *prop_name,
197 const struct adin_cfg_reg_map *tbl,
200 struct device *dev = &phydev->mdio.dev;
204 if (device_property_read_u32(dev, prop_name, &val))
207 rc = adin_lookup_reg_value(tbl, val);
210 "Unsupported value %u for %s using default (%u)\n",
211 val, prop_name, dflt);
218 static int adin_config_rgmii_mode(struct phy_device *phydev)
223 if (!phy_interface_is_rgmii(phydev))
224 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
225 ADIN1300_GE_RGMII_CFG_REG,
226 ADIN1300_GE_RGMII_EN);
228 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG);
232 reg |= ADIN1300_GE_RGMII_EN;
234 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
235 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
236 reg |= ADIN1300_GE_RGMII_RXID_EN;
238 val = adin_get_reg_value(phydev, "adi,rx-internal-delay-ps",
240 ADIN1300_RGMII_2_00_NS);
241 reg &= ~ADIN1300_GE_RGMII_RX_MSK;
242 reg |= ADIN1300_GE_RGMII_RX_SEL(val);
244 reg &= ~ADIN1300_GE_RGMII_RXID_EN;
247 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
248 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
249 reg |= ADIN1300_GE_RGMII_TXID_EN;
251 val = adin_get_reg_value(phydev, "adi,tx-internal-delay-ps",
253 ADIN1300_RGMII_2_00_NS);
254 reg &= ~ADIN1300_GE_RGMII_GTX_MSK;
255 reg |= ADIN1300_GE_RGMII_GTX_SEL(val);
257 reg &= ~ADIN1300_GE_RGMII_TXID_EN;
260 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
261 ADIN1300_GE_RGMII_CFG_REG, reg);
264 static int adin_config_rmii_mode(struct phy_device *phydev)
269 if (phydev->interface != PHY_INTERFACE_MODE_RMII)
270 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
271 ADIN1300_GE_RMII_CFG_REG,
272 ADIN1300_GE_RMII_EN);
274 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG);
278 reg |= ADIN1300_GE_RMII_EN;
280 val = adin_get_reg_value(phydev, "adi,fifo-depth-bits",
281 adin_rmii_fifo_depths,
282 ADIN1300_RMII_8_BITS);
284 reg &= ~ADIN1300_GE_RMII_FIFO_DEPTH_MSK;
285 reg |= ADIN1300_GE_RMII_FIFO_DEPTH_SEL(val);
287 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
288 ADIN1300_GE_RMII_CFG_REG, reg);
291 static int adin_get_downshift(struct phy_device *phydev, u8 *data)
293 int val, cnt, enable;
295 val = phy_read(phydev, ADIN1300_PHY_CTRL2);
299 cnt = phy_read(phydev, ADIN1300_PHY_CTRL3);
303 enable = FIELD_GET(ADIN1300_DOWNSPEEDS_EN, val);
304 cnt = FIELD_GET(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt);
306 *data = (enable && cnt) ? cnt : DOWNSHIFT_DEV_DISABLE;
311 static int adin_set_downshift(struct phy_device *phydev, u8 cnt)
316 if (cnt == DOWNSHIFT_DEV_DISABLE)
317 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL2,
318 ADIN1300_DOWNSPEEDS_EN);
323 val = FIELD_PREP(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt);
324 val |= ADIN1300_LINKING_EN;
326 rc = phy_modify(phydev, ADIN1300_PHY_CTRL3,
327 ADIN1300_LINKING_EN | ADIN1300_DOWNSPEED_RETRIES_MSK,
332 return phy_set_bits(phydev, ADIN1300_PHY_CTRL2,
333 ADIN1300_DOWNSPEEDS_EN);
336 static int adin_get_edpd(struct phy_device *phydev, u16 *tx_interval)
340 val = phy_read(phydev, ADIN1300_PHY_CTRL_STATUS2);
344 if (ADIN1300_NRG_PD_EN & val) {
345 if (val & ADIN1300_NRG_PD_TX_EN)
346 /* default is 1 second */
347 *tx_interval = ETHTOOL_PHY_EDPD_DFLT_TX_MSECS;
349 *tx_interval = ETHTOOL_PHY_EDPD_NO_TX;
351 *tx_interval = ETHTOOL_PHY_EDPD_DISABLE;
357 static int adin_set_edpd(struct phy_device *phydev, u16 tx_interval)
361 if (tx_interval == ETHTOOL_PHY_EDPD_DISABLE)
362 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL_STATUS2,
363 (ADIN1300_NRG_PD_EN | ADIN1300_NRG_PD_TX_EN));
365 val = ADIN1300_NRG_PD_EN;
367 switch (tx_interval) {
368 case 1000: /* 1 second */
370 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
371 val |= ADIN1300_NRG_PD_TX_EN;
373 case ETHTOOL_PHY_EDPD_NO_TX:
379 return phy_modify(phydev, ADIN1300_PHY_CTRL_STATUS2,
380 (ADIN1300_NRG_PD_EN | ADIN1300_NRG_PD_TX_EN),
384 static int adin_get_tunable(struct phy_device *phydev,
385 struct ethtool_tunable *tuna, void *data)
388 case ETHTOOL_PHY_DOWNSHIFT:
389 return adin_get_downshift(phydev, data);
390 case ETHTOOL_PHY_EDPD:
391 return adin_get_edpd(phydev, data);
397 static int adin_set_tunable(struct phy_device *phydev,
398 struct ethtool_tunable *tuna, const void *data)
401 case ETHTOOL_PHY_DOWNSHIFT:
402 return adin_set_downshift(phydev, *(const u8 *)data);
403 case ETHTOOL_PHY_EDPD:
404 return adin_set_edpd(phydev, *(const u16 *)data);
410 static int adin_config_init(struct phy_device *phydev)
414 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
416 rc = adin_config_rgmii_mode(phydev);
420 rc = adin_config_rmii_mode(phydev);
424 rc = adin_set_downshift(phydev, 4);
428 rc = adin_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
432 phydev_dbg(phydev, "PHY is using mode '%s'\n",
433 phy_modes(phydev->interface));
438 static int adin_phy_ack_intr(struct phy_device *phydev)
440 /* Clear pending interrupts */
441 int rc = phy_read(phydev, ADIN1300_INT_STATUS_REG);
443 return rc < 0 ? rc : 0;
446 static int adin_phy_config_intr(struct phy_device *phydev)
448 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
449 return phy_set_bits(phydev, ADIN1300_INT_MASK_REG,
450 ADIN1300_INT_MASK_EN);
452 return phy_clear_bits(phydev, ADIN1300_INT_MASK_REG,
453 ADIN1300_INT_MASK_EN);
456 static int adin_cl45_to_adin_reg(struct phy_device *phydev, int devad,
459 const struct adin_clause45_mmd_map *m;
462 if (devad == MDIO_MMD_VEND1)
465 for (i = 0; i < ARRAY_SIZE(adin_clause45_mmd_map); i++) {
466 m = &adin_clause45_mmd_map[i];
467 if (m->devad == devad && m->cl45_regnum == cl45_regnum)
468 return m->adin_regnum;
472 "No translation available for devad: %d reg: %04x\n",
478 static int adin_read_mmd(struct phy_device *phydev, int devad, u16 regnum)
480 struct mii_bus *bus = phydev->mdio.bus;
481 int phy_addr = phydev->mdio.addr;
485 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);
489 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR,
494 return __mdiobus_read(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA);
497 static int adin_write_mmd(struct phy_device *phydev, int devad, u16 regnum,
500 struct mii_bus *bus = phydev->mdio.bus;
501 int phy_addr = phydev->mdio.addr;
505 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);
509 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR,
514 return __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA, val);
517 static int adin_config_mdix(struct phy_device *phydev)
519 bool auto_en, mdix_en;
524 switch (phydev->mdix_ctrl) {
530 case ETH_TP_MDI_AUTO:
537 reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
542 reg |= ADIN1300_MAN_MDIX_EN;
544 reg &= ~ADIN1300_MAN_MDIX_EN;
547 reg |= ADIN1300_AUTO_MDI_EN;
549 reg &= ~ADIN1300_AUTO_MDI_EN;
551 return phy_write(phydev, ADIN1300_PHY_CTRL1, reg);
554 static int adin_config_aneg(struct phy_device *phydev)
558 ret = adin_config_mdix(phydev);
562 return genphy_config_aneg(phydev);
565 static int adin_mdix_update(struct phy_device *phydev)
567 bool auto_en, mdix_en;
571 reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
575 auto_en = !!(reg & ADIN1300_AUTO_MDI_EN);
576 mdix_en = !!(reg & ADIN1300_MAN_MDIX_EN);
578 /* If MDI/MDIX is forced, just read it from the control reg */
581 phydev->mdix = ETH_TP_MDI_X;
583 phydev->mdix = ETH_TP_MDI;
588 * Otherwise, we need to deduce it from the PHY status2 reg.
589 * When Auto-MDI is enabled, the ADIN1300_MAN_MDIX_EN bit implies
590 * a preference for MDIX when it is set.
592 reg = phy_read(phydev, ADIN1300_PHY_STATUS1);
596 swapped = !!(reg & ADIN1300_PAIR_01_SWAP);
598 if (mdix_en != swapped)
599 phydev->mdix = ETH_TP_MDI_X;
601 phydev->mdix = ETH_TP_MDI;
606 static int adin_read_status(struct phy_device *phydev)
610 ret = adin_mdix_update(phydev);
614 return genphy_read_status(phydev);
617 static int adin_soft_reset(struct phy_device *phydev)
621 /* The reset bit is self-clearing, set it and wait */
622 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
623 ADIN1300_GE_SOFT_RESET_REG,
624 ADIN1300_GE_SOFT_RESET);
630 /* If we get a read error something may be wrong */
631 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
632 ADIN1300_GE_SOFT_RESET_REG);
634 return rc < 0 ? rc : 0;
637 static int adin_get_sset_count(struct phy_device *phydev)
639 return ARRAY_SIZE(adin_hw_stats);
642 static void adin_get_strings(struct phy_device *phydev, u8 *data)
646 for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++) {
647 strlcpy(&data[i * ETH_GSTRING_LEN],
648 adin_hw_stats[i].string, ETH_GSTRING_LEN);
652 static int adin_read_mmd_stat_regs(struct phy_device *phydev,
653 const struct adin_hw_stat *stat,
658 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg1);
662 *val = (ret & 0xffff);
667 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg2);
672 *val |= (ret & 0xffff);
677 static u64 adin_get_stat(struct phy_device *phydev, int i)
679 const struct adin_hw_stat *stat = &adin_hw_stats[i];
680 struct adin_priv *priv = phydev->priv;
684 if (stat->reg1 > 0x1f) {
685 ret = adin_read_mmd_stat_regs(phydev, stat, &val);
689 ret = phy_read(phydev, stat->reg1);
692 val = (ret & 0xffff);
695 priv->stats[i] += val;
697 return priv->stats[i];
700 static void adin_get_stats(struct phy_device *phydev,
701 struct ethtool_stats *stats, u64 *data)
705 /* latch copies of all the frame-checker counters */
706 rc = phy_read(phydev, ADIN1300_RX_ERR_CNT);
710 for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++)
711 data[i] = adin_get_stat(phydev, i);
714 static int adin_probe(struct phy_device *phydev)
716 struct device *dev = &phydev->mdio.dev;
717 struct adin_priv *priv;
719 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
728 static struct phy_driver adin_driver[] = {
730 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200),
733 .config_init = adin_config_init,
734 .soft_reset = adin_soft_reset,
735 .config_aneg = adin_config_aneg,
736 .read_status = adin_read_status,
737 .get_tunable = adin_get_tunable,
738 .set_tunable = adin_set_tunable,
739 .ack_interrupt = adin_phy_ack_intr,
740 .config_intr = adin_phy_config_intr,
741 .get_sset_count = adin_get_sset_count,
742 .get_strings = adin_get_strings,
743 .get_stats = adin_get_stats,
744 .resume = genphy_resume,
745 .suspend = genphy_suspend,
746 .read_mmd = adin_read_mmd,
747 .write_mmd = adin_write_mmd,
750 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300),
753 .config_init = adin_config_init,
754 .soft_reset = adin_soft_reset,
755 .config_aneg = adin_config_aneg,
756 .read_status = adin_read_status,
757 .get_tunable = adin_get_tunable,
758 .set_tunable = adin_set_tunable,
759 .ack_interrupt = adin_phy_ack_intr,
760 .config_intr = adin_phy_config_intr,
761 .get_sset_count = adin_get_sset_count,
762 .get_strings = adin_get_strings,
763 .get_stats = adin_get_stats,
764 .resume = genphy_resume,
765 .suspend = genphy_suspend,
766 .read_mmd = adin_read_mmd,
767 .write_mmd = adin_write_mmd,
771 module_phy_driver(adin_driver);
773 static struct mdio_device_id __maybe_unused adin_tbl[] = {
774 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200) },
775 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300) },
779 MODULE_DEVICE_TABLE(mdio, adin_tbl);
780 MODULE_DESCRIPTION("Analog Devices Industrial Ethernet PHY driver");
781 MODULE_LICENSE("GPL");