1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare XPCS helpers
6 * Author: Jose Abreu <Jose.Abreu@synopsys.com>
9 #include <linux/delay.h>
10 #include <linux/pcs/pcs-xpcs.h>
11 #include <linux/mdio.h>
12 #include <linux/phylink.h>
13 #include <linux/workqueue.h>
16 #define phylink_pcs_to_xpcs(pl_pcs) \
17 container_of((pl_pcs), struct dw_xpcs, pcs)
19 static const int xpcs_usxgmii_features[] = {
20 ETHTOOL_LINK_MODE_Pause_BIT,
21 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
22 ETHTOOL_LINK_MODE_Autoneg_BIT,
23 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
24 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
25 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
26 ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
27 __ETHTOOL_LINK_MODE_MASK_NBITS,
30 static const int xpcs_10gkr_features[] = {
31 ETHTOOL_LINK_MODE_Pause_BIT,
32 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
33 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
34 __ETHTOOL_LINK_MODE_MASK_NBITS,
37 static const int xpcs_xlgmii_features[] = {
38 ETHTOOL_LINK_MODE_Pause_BIT,
39 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
40 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
41 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
42 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
43 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
44 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
45 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
46 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
47 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
48 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
49 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
50 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
51 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
52 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
53 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
54 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
55 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
56 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
57 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
58 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
59 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
60 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
61 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
62 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
63 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
64 __ETHTOOL_LINK_MODE_MASK_NBITS,
67 static const int xpcs_sgmii_features[] = {
68 ETHTOOL_LINK_MODE_Pause_BIT,
69 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
70 ETHTOOL_LINK_MODE_Autoneg_BIT,
71 ETHTOOL_LINK_MODE_10baseT_Half_BIT,
72 ETHTOOL_LINK_MODE_10baseT_Full_BIT,
73 ETHTOOL_LINK_MODE_100baseT_Half_BIT,
74 ETHTOOL_LINK_MODE_100baseT_Full_BIT,
75 ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
76 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
77 __ETHTOOL_LINK_MODE_MASK_NBITS,
80 static const int xpcs_2500basex_features[] = {
81 ETHTOOL_LINK_MODE_Pause_BIT,
82 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
83 ETHTOOL_LINK_MODE_Autoneg_BIT,
84 ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
85 ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
86 __ETHTOOL_LINK_MODE_MASK_NBITS,
89 static const phy_interface_t xpcs_usxgmii_interfaces[] = {
90 PHY_INTERFACE_MODE_USXGMII,
93 static const phy_interface_t xpcs_10gkr_interfaces[] = {
94 PHY_INTERFACE_MODE_10GKR,
97 static const phy_interface_t xpcs_xlgmii_interfaces[] = {
98 PHY_INTERFACE_MODE_XLGMII,
101 static const phy_interface_t xpcs_sgmii_interfaces[] = {
102 PHY_INTERFACE_MODE_SGMII,
105 static const phy_interface_t xpcs_2500basex_interfaces[] = {
106 PHY_INTERFACE_MODE_2500BASEX,
107 PHY_INTERFACE_MODE_MAX,
116 DW_XPCS_INTERFACE_MAX,
120 const int *supported;
121 const phy_interface_t *interface;
124 int (*pma_config)(struct dw_xpcs *xpcs);
130 const struct xpcs_compat *compat;
133 static const struct xpcs_compat *xpcs_find_compat(const struct xpcs_id *id,
134 phy_interface_t interface)
138 for (i = 0; i < DW_XPCS_INTERFACE_MAX; i++) {
139 const struct xpcs_compat *compat = &id->compat[i];
141 for (j = 0; j < compat->num_interfaces; j++)
142 if (compat->interface[j] == interface)
149 int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface)
151 const struct xpcs_compat *compat;
153 compat = xpcs_find_compat(xpcs->id, interface);
157 return compat->an_mode;
159 EXPORT_SYMBOL_GPL(xpcs_get_an_mode);
161 static bool __xpcs_linkmode_supported(const struct xpcs_compat *compat,
162 enum ethtool_link_mode_bit_indices linkmode)
166 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++)
167 if (compat->supported[i] == linkmode)
173 #define xpcs_linkmode_supported(compat, mode) \
174 __xpcs_linkmode_supported(compat, ETHTOOL_LINK_MODE_ ## mode ## _BIT)
176 int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg)
178 u32 reg_addr = mdiobus_c45_addr(dev, reg);
179 struct mii_bus *bus = xpcs->mdiodev->bus;
180 int addr = xpcs->mdiodev->addr;
182 return mdiobus_read(bus, addr, reg_addr);
185 int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val)
187 u32 reg_addr = mdiobus_c45_addr(dev, reg);
188 struct mii_bus *bus = xpcs->mdiodev->bus;
189 int addr = xpcs->mdiodev->addr;
191 return mdiobus_write(bus, addr, reg_addr, val);
194 static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg)
196 return xpcs_read(xpcs, dev, DW_VENDOR | reg);
199 static int xpcs_write_vendor(struct dw_xpcs *xpcs, int dev, int reg,
202 return xpcs_write(xpcs, dev, DW_VENDOR | reg, val);
205 static int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg)
207 return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg);
210 static int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val)
212 return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val);
215 static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev)
217 /* Poll until the reset bit clears (50ms per retry == 0.6 sec) */
218 unsigned int retries = 12;
223 ret = xpcs_read(xpcs, dev, MDIO_CTRL1);
226 } while (ret & MDIO_CTRL1_RESET && --retries);
228 return (ret & MDIO_CTRL1_RESET) ? -ETIMEDOUT : 0;
231 static int xpcs_soft_reset(struct dw_xpcs *xpcs,
232 const struct xpcs_compat *compat)
236 switch (compat->an_mode) {
240 case DW_AN_C37_SGMII:
242 dev = MDIO_MMD_VEND2;
248 ret = xpcs_write(xpcs, dev, MDIO_CTRL1, MDIO_CTRL1_RESET);
252 return xpcs_poll_reset(xpcs, dev);
255 #define xpcs_warn(__xpcs, __state, __args...) \
257 if ((__state)->link) \
258 dev_warn(&(__xpcs)->mdiodev->dev, ##__args); \
261 static int xpcs_read_fault_c73(struct dw_xpcs *xpcs,
262 struct phylink_link_state *state)
266 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1);
270 if (ret & MDIO_STAT1_FAULT) {
271 xpcs_warn(xpcs, state, "Link fault condition detected!\n");
275 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2);
279 if (ret & MDIO_STAT2_RXFAULT)
280 xpcs_warn(xpcs, state, "Receiver fault detected!\n");
281 if (ret & MDIO_STAT2_TXFAULT)
282 xpcs_warn(xpcs, state, "Transmitter fault detected!\n");
284 ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS);
288 if (ret & DW_RXFIFO_ERR) {
289 xpcs_warn(xpcs, state, "FIFO fault condition detected!\n");
293 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1);
297 if (!(ret & MDIO_PCS_10GBRT_STAT1_BLKLK))
298 xpcs_warn(xpcs, state, "Link is not locked!\n");
300 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2);
304 if (ret & MDIO_PCS_10GBRT_STAT2_ERR) {
305 xpcs_warn(xpcs, state, "Link has errors!\n");
312 static int xpcs_read_link_c73(struct dw_xpcs *xpcs, bool an)
317 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1);
321 if (!(ret & MDIO_STAT1_LSTATUS))
325 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
329 if (!(ret & MDIO_STAT1_LSTATUS))
336 static int xpcs_get_max_usxgmii_speed(const unsigned long *supported)
338 int max = SPEED_UNKNOWN;
340 if (phylink_test(supported, 1000baseKX_Full))
342 if (phylink_test(supported, 2500baseX_Full))
344 if (phylink_test(supported, 10000baseKX4_Full))
346 if (phylink_test(supported, 10000baseKR_Full))
352 static void xpcs_config_usxgmii(struct dw_xpcs *xpcs, int speed)
358 speed_sel = DW_USXGMII_10;
361 speed_sel = DW_USXGMII_100;
364 speed_sel = DW_USXGMII_1000;
367 speed_sel = DW_USXGMII_2500;
370 speed_sel = DW_USXGMII_5000;
373 speed_sel = DW_USXGMII_10000;
376 /* Nothing to do here */
380 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1);
384 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_EN);
388 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
392 ret &= ~DW_USXGMII_SS_MASK;
393 ret |= speed_sel | DW_USXGMII_FULL;
395 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret);
399 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1);
403 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_RST);
410 pr_err("%s: XPCS access returned %pe\n", __func__, ERR_PTR(ret));
413 static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
414 const struct xpcs_compat *compat)
418 /* By default, in USXGMII mode XPCS operates at 10G baud and
419 * replicates data to achieve lower speeds. Hereby, in this
420 * default configuration we need to advertise all supported
421 * modes and not only the ones we want to use.
426 if (xpcs_linkmode_supported(compat, 2500baseX_Full))
427 adv |= DW_C73_2500KX;
429 /* TODO: 5000baseKR */
431 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv);
437 if (xpcs_linkmode_supported(compat, 1000baseKX_Full))
438 adv |= DW_C73_1000KX;
439 if (xpcs_linkmode_supported(compat, 10000baseKX4_Full))
440 adv |= DW_C73_10000KX4;
441 if (xpcs_linkmode_supported(compat, 10000baseKR_Full))
442 adv |= DW_C73_10000KR;
444 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv);
449 adv = DW_C73_AN_ADV_SF;
450 if (xpcs_linkmode_supported(compat, Pause))
452 if (xpcs_linkmode_supported(compat, Asym_Pause))
453 adv |= DW_C73_ASYM_PAUSE;
455 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv);
458 static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
459 const struct xpcs_compat *compat)
463 ret = _xpcs_config_aneg_c73(xpcs, compat);
467 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_CTRL1);
471 ret |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART;
473 return xpcs_write(xpcs, MDIO_MMD_AN, MDIO_CTRL1, ret);
476 static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs,
477 struct phylink_link_state *state,
478 const struct xpcs_compat *compat)
482 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
486 if (ret & MDIO_AN_STAT1_COMPLETE) {
487 ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL1);
491 /* Check if Aneg outcome is valid */
492 if (!(ret & DW_C73_AN_ADV_SF)) {
493 xpcs_config_aneg_c73(xpcs, compat);
503 static int xpcs_read_lpa_c73(struct dw_xpcs *xpcs,
504 struct phylink_link_state *state)
508 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
512 if (!(ret & MDIO_AN_STAT1_LPABLE)) {
513 phylink_clear(state->lp_advertising, Autoneg);
517 phylink_set(state->lp_advertising, Autoneg);
519 /* Clause 73 outcome */
520 ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL3);
524 if (ret & DW_C73_2500KX)
525 phylink_set(state->lp_advertising, 2500baseX_Full);
527 ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL2);
531 if (ret & DW_C73_1000KX)
532 phylink_set(state->lp_advertising, 1000baseKX_Full);
533 if (ret & DW_C73_10000KX4)
534 phylink_set(state->lp_advertising, 10000baseKX4_Full);
535 if (ret & DW_C73_10000KR)
536 phylink_set(state->lp_advertising, 10000baseKR_Full);
538 ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL1);
542 if (ret & DW_C73_PAUSE)
543 phylink_set(state->lp_advertising, Pause);
544 if (ret & DW_C73_ASYM_PAUSE)
545 phylink_set(state->lp_advertising, Asym_Pause);
547 linkmode_and(state->lp_advertising, state->lp_advertising,
552 static void xpcs_resolve_lpa_c73(struct dw_xpcs *xpcs,
553 struct phylink_link_state *state)
555 int max_speed = xpcs_get_max_usxgmii_speed(state->lp_advertising);
557 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX;
558 state->speed = max_speed;
559 state->duplex = DUPLEX_FULL;
562 static int xpcs_get_max_xlgmii_speed(struct dw_xpcs *xpcs,
563 struct phylink_link_state *state)
565 unsigned long *adv = state->advertising;
566 int speed = SPEED_UNKNOWN;
569 for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) {
570 int new_speed = SPEED_UNKNOWN;
573 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT:
574 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT:
575 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT:
576 new_speed = SPEED_25000;
578 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT:
579 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT:
580 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT:
581 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT:
582 new_speed = SPEED_40000;
584 case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT:
585 case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT:
586 case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT:
587 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT:
588 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT:
589 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT:
590 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT:
591 case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT:
592 new_speed = SPEED_50000;
594 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT:
595 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT:
596 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT:
597 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT:
598 case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT:
599 case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT:
600 case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT:
601 case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT:
602 case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT:
603 new_speed = SPEED_100000;
609 if (new_speed > speed)
616 static void xpcs_resolve_pma(struct dw_xpcs *xpcs,
617 struct phylink_link_state *state)
619 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX;
620 state->duplex = DUPLEX_FULL;
622 switch (state->interface) {
623 case PHY_INTERFACE_MODE_10GKR:
624 state->speed = SPEED_10000;
626 case PHY_INTERFACE_MODE_XLGMII:
627 state->speed = xpcs_get_max_xlgmii_speed(xpcs, state);
630 state->speed = SPEED_UNKNOWN;
635 void xpcs_validate(struct dw_xpcs *xpcs, unsigned long *supported,
636 struct phylink_link_state *state)
638 __ETHTOOL_DECLARE_LINK_MODE_MASK(xpcs_supported);
639 const struct xpcs_compat *compat;
642 /* phylink expects us to report all supported modes with
643 * PHY_INTERFACE_MODE_NA, just don't limit the supported and
644 * advertising masks and exit.
646 if (state->interface == PHY_INTERFACE_MODE_NA)
649 bitmap_zero(xpcs_supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
651 compat = xpcs_find_compat(xpcs->id, state->interface);
653 /* Populate the supported link modes for this
657 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++)
658 set_bit(compat->supported[i], xpcs_supported);
660 linkmode_and(supported, supported, xpcs_supported);
661 linkmode_and(state->advertising, state->advertising, xpcs_supported);
663 EXPORT_SYMBOL_GPL(xpcs_validate);
665 int xpcs_config_eee(struct dw_xpcs *xpcs, int mult_fact_100ns, int enable)
669 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0);
675 ret = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
676 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
677 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
678 mult_fact_100ns << DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT;
680 ret &= ~(DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
681 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
682 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
683 DW_VR_MII_EEE_MULT_FACT_100NS);
686 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, ret);
690 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1);
695 ret |= DW_VR_MII_EEE_TRN_LPI;
697 ret &= ~DW_VR_MII_EEE_TRN_LPI;
699 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, ret);
701 EXPORT_SYMBOL_GPL(xpcs_config_eee);
703 static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, unsigned int mode)
707 /* For AN for C37 SGMII mode, the settings are :-
708 * 1) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 0b (Disable SGMII AN in case
709 it is already enabled)
710 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 10b (SGMII AN)
711 * 3) VR_MII_AN_CTRL Bit(3) [TX_CONFIG] = 0b (MAC side SGMII)
712 * DW xPCS used with DW EQoS MAC is always MAC side SGMII.
713 * 4) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] = 1b (Automatic
714 * speed/duplex mode change by HW after SGMII AN complete)
715 * 5) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN)
717 * Note: Since it is MAC side SGMII, there is no need to set
718 * SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from
719 * PHY about the link state change after C28 AN is completed
720 * between PHY and Link Partner. There is also no need to
721 * trigger AN restart for MAC-side SGMII.
723 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
727 if (mdio_ctrl & AN_CL37_EN) {
728 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
729 mdio_ctrl & ~AN_CL37_EN);
734 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL);
738 ret &= ~(DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK);
739 ret |= (DW_VR_MII_PCS_MODE_C37_SGMII <<
740 DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT &
741 DW_VR_MII_PCS_MODE_MASK);
742 ret |= (DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII <<
743 DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT &
744 DW_VR_MII_TX_CONFIG_MASK);
745 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret);
749 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
753 if (phylink_autoneg_inband(mode))
754 ret |= DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
756 ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
758 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
762 if (phylink_autoneg_inband(mode))
763 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
764 mdio_ctrl | AN_CL37_EN);
769 static int xpcs_config_2500basex(struct dw_xpcs *xpcs)
773 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
776 ret |= DW_VR_MII_DIG_CTRL1_2G5_EN;
777 ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
778 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
782 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
786 ret |= SGMII_SPEED_SS6;
787 ret &= ~SGMII_SPEED_SS13;
788 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, ret);
791 int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface,
794 const struct xpcs_compat *compat;
797 compat = xpcs_find_compat(xpcs->id, interface);
801 switch (compat->an_mode) {
803 if (phylink_autoneg_inband(mode)) {
804 ret = xpcs_config_aneg_c73(xpcs, compat);
809 case DW_AN_C37_SGMII:
810 ret = xpcs_config_aneg_c37_sgmii(xpcs, mode);
815 ret = xpcs_config_2500basex(xpcs);
823 if (compat->pma_config) {
824 ret = compat->pma_config(xpcs);
831 EXPORT_SYMBOL_GPL(xpcs_do_config);
833 static int xpcs_config(struct phylink_pcs *pcs, unsigned int mode,
834 phy_interface_t interface,
835 const unsigned long *advertising,
836 bool permit_pause_to_mac)
838 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
840 return xpcs_do_config(xpcs, interface, mode);
843 static int xpcs_get_state_c73(struct dw_xpcs *xpcs,
844 struct phylink_link_state *state,
845 const struct xpcs_compat *compat)
849 /* Link needs to be read first ... */
850 state->link = xpcs_read_link_c73(xpcs, state->an_enabled) > 0 ? 1 : 0;
852 /* ... and then we check the faults. */
853 ret = xpcs_read_fault_c73(xpcs, state);
855 ret = xpcs_soft_reset(xpcs, compat);
861 return xpcs_do_config(xpcs, state->interface, MLO_AN_INBAND);
864 if (state->an_enabled && xpcs_aneg_done_c73(xpcs, state, compat)) {
865 state->an_complete = true;
866 xpcs_read_lpa_c73(xpcs, state);
867 xpcs_resolve_lpa_c73(xpcs, state);
868 } else if (state->an_enabled) {
870 } else if (state->link) {
871 xpcs_resolve_pma(xpcs, state);
877 static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs,
878 struct phylink_link_state *state)
882 /* Reset link_state */
884 state->speed = SPEED_UNKNOWN;
885 state->duplex = DUPLEX_UNKNOWN;
888 /* For C37 SGMII mode, we check DW_VR_MII_AN_INTR_STS for link
889 * status, speed and duplex.
891 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS);
895 if (ret & DW_VR_MII_C37_ANSGM_SP_LNKSTS) {
900 speed_value = (ret & DW_VR_MII_AN_STS_C37_ANSGM_SP) >>
901 DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT;
902 if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000)
903 state->speed = SPEED_1000;
904 else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100)
905 state->speed = SPEED_100;
907 state->speed = SPEED_10;
909 if (ret & DW_VR_MII_AN_STS_C37_ANSGM_FD)
910 state->duplex = DUPLEX_FULL;
912 state->duplex = DUPLEX_HALF;
918 static void xpcs_get_state(struct phylink_pcs *pcs,
919 struct phylink_link_state *state)
921 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
922 const struct xpcs_compat *compat;
925 compat = xpcs_find_compat(xpcs->id, state->interface);
929 switch (compat->an_mode) {
931 ret = xpcs_get_state_c73(xpcs, state, compat);
933 pr_err("xpcs_get_state_c73 returned %pe\n",
938 case DW_AN_C37_SGMII:
939 ret = xpcs_get_state_c37_sgmii(xpcs, state);
941 pr_err("xpcs_get_state_c37_sgmii returned %pe\n",
950 static void xpcs_link_up_sgmii(struct dw_xpcs *xpcs, unsigned int mode,
951 int speed, int duplex)
955 if (phylink_autoneg_inband(mode))
960 val = BMCR_SPEED1000;
972 if (duplex == DUPLEX_FULL)
973 val |= BMCR_FULLDPLX;
975 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
977 pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret));
980 void xpcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
981 phy_interface_t interface, int speed, int duplex)
983 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
985 if (interface == PHY_INTERFACE_MODE_USXGMII)
986 return xpcs_config_usxgmii(xpcs, speed);
987 if (interface == PHY_INTERFACE_MODE_SGMII)
988 return xpcs_link_up_sgmii(xpcs, mode, speed, duplex);
990 EXPORT_SYMBOL_GPL(xpcs_link_up);
992 static u32 xpcs_get_id(struct dw_xpcs *xpcs)
997 /* First, search C73 PCS using PCS MMD */
998 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1);
1004 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2);
1008 /* If Device IDs are not all zeros or all ones,
1009 * we found C73 AN-type device
1011 if ((id | ret) && (id | ret) != 0xffffffff)
1014 /* Next, search C37 PCS using Vendor-Specific MII MMD */
1015 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1);
1021 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2);
1025 /* If Device IDs are not all zeros, we found C37 AN-type device */
1032 static const struct xpcs_compat synopsys_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1033 [DW_XPCS_USXGMII] = {
1034 .supported = xpcs_usxgmii_features,
1035 .interface = xpcs_usxgmii_interfaces,
1036 .num_interfaces = ARRAY_SIZE(xpcs_usxgmii_interfaces),
1037 .an_mode = DW_AN_C73,
1040 .supported = xpcs_10gkr_features,
1041 .interface = xpcs_10gkr_interfaces,
1042 .num_interfaces = ARRAY_SIZE(xpcs_10gkr_interfaces),
1043 .an_mode = DW_AN_C73,
1045 [DW_XPCS_XLGMII] = {
1046 .supported = xpcs_xlgmii_features,
1047 .interface = xpcs_xlgmii_interfaces,
1048 .num_interfaces = ARRAY_SIZE(xpcs_xlgmii_interfaces),
1049 .an_mode = DW_AN_C73,
1052 .supported = xpcs_sgmii_features,
1053 .interface = xpcs_sgmii_interfaces,
1054 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1055 .an_mode = DW_AN_C37_SGMII,
1057 [DW_XPCS_2500BASEX] = {
1058 .supported = xpcs_2500basex_features,
1059 .interface = xpcs_2500basex_interfaces,
1060 .num_interfaces = ARRAY_SIZE(xpcs_2500basex_features),
1061 .an_mode = DW_2500BASEX,
1065 static const struct xpcs_compat nxp_sja1105_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1067 .supported = xpcs_sgmii_features,
1068 .interface = xpcs_sgmii_interfaces,
1069 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1070 .an_mode = DW_AN_C37_SGMII,
1071 .pma_config = nxp_sja1105_sgmii_pma_config,
1075 static const struct xpcs_compat nxp_sja1110_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1077 .supported = xpcs_sgmii_features,
1078 .interface = xpcs_sgmii_interfaces,
1079 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1080 .an_mode = DW_AN_C37_SGMII,
1081 .pma_config = nxp_sja1110_sgmii_pma_config,
1083 [DW_XPCS_2500BASEX] = {
1084 .supported = xpcs_2500basex_features,
1085 .interface = xpcs_2500basex_interfaces,
1086 .num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces),
1087 .an_mode = DW_2500BASEX,
1088 .pma_config = nxp_sja1110_2500basex_pma_config,
1092 static const struct xpcs_id xpcs_id_list[] = {
1094 .id = SYNOPSYS_XPCS_ID,
1095 .mask = SYNOPSYS_XPCS_MASK,
1096 .compat = synopsys_xpcs_compat,
1098 .id = NXP_SJA1105_XPCS_ID,
1099 .mask = SYNOPSYS_XPCS_MASK,
1100 .compat = nxp_sja1105_xpcs_compat,
1102 .id = NXP_SJA1110_XPCS_ID,
1103 .mask = SYNOPSYS_XPCS_MASK,
1104 .compat = nxp_sja1110_xpcs_compat,
1108 static const struct phylink_pcs_ops xpcs_phylink_ops = {
1109 .pcs_config = xpcs_config,
1110 .pcs_get_state = xpcs_get_state,
1111 .pcs_link_up = xpcs_link_up,
1114 struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev,
1115 phy_interface_t interface)
1117 struct dw_xpcs *xpcs;
1121 xpcs = kzalloc(sizeof(*xpcs), GFP_KERNEL);
1123 return ERR_PTR(-ENOMEM);
1125 xpcs->mdiodev = mdiodev;
1127 xpcs_id = xpcs_get_id(xpcs);
1129 for (i = 0; i < ARRAY_SIZE(xpcs_id_list); i++) {
1130 const struct xpcs_id *entry = &xpcs_id_list[i];
1131 const struct xpcs_compat *compat;
1133 if ((xpcs_id & entry->mask) != entry->id)
1138 compat = xpcs_find_compat(entry, interface);
1144 xpcs->pcs.ops = &xpcs_phylink_ops;
1145 xpcs->pcs.poll = true;
1147 ret = xpcs_soft_reset(xpcs, compat);
1159 return ERR_PTR(ret);
1161 EXPORT_SYMBOL_GPL(xpcs_create);
1163 void xpcs_destroy(struct dw_xpcs *xpcs)
1167 EXPORT_SYMBOL_GPL(xpcs_destroy);
1169 MODULE_LICENSE("GPL v2");