1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Lynx PCS MDIO helpers
6 #include <linux/mdio.h>
7 #include <linux/phylink.h>
8 #include <linux/pcs-lynx.h>
10 #define SGMII_CLOCK_PERIOD_NS 8 /* PCS is clocked at 125 MHz */
11 #define LINK_TIMER_VAL(ns) ((u32)((ns) / SGMII_CLOCK_PERIOD_NS))
13 #define SGMII_AN_LINK_TIMER_NS 1600000 /* defined by SGMII spec */
14 #define IEEE8023_LINK_TIMER_NS 10000000
16 #define LINK_TIMER_LO 0x12
17 #define LINK_TIMER_HI 0x13
19 #define IF_MODE_SGMII_EN BIT(0)
20 #define IF_MODE_USE_SGMII_AN BIT(1)
21 #define IF_MODE_SPEED(x) (((x) << 2) & GENMASK(3, 2))
22 #define IF_MODE_SPEED_MSK GENMASK(3, 2)
23 #define IF_MODE_HALF_DUPLEX BIT(4)
26 struct phylink_pcs pcs;
27 struct mdio_device *mdio;
37 #define phylink_pcs_to_lynx(pl_pcs) container_of((pl_pcs), struct lynx_pcs, pcs)
38 #define lynx_to_phylink_pcs(lynx) (&(lynx)->pcs)
40 struct mdio_device *lynx_get_mdio_device(struct phylink_pcs *pcs)
42 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
46 EXPORT_SYMBOL(lynx_get_mdio_device);
48 static void lynx_pcs_get_state_usxgmii(struct mdio_device *pcs,
49 struct phylink_link_state *state)
51 struct mii_bus *bus = pcs->bus;
55 status = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_BMSR);
59 state->link = !!(status & MDIO_STAT1_LSTATUS);
60 state->an_complete = !!(status & MDIO_AN_STAT1_COMPLETE);
61 if (!state->link || !state->an_complete)
64 lpa = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_LPA);
68 phylink_decode_usxgmii_word(state, lpa);
71 static void lynx_pcs_get_state_2500basex(struct mdio_device *pcs,
72 struct phylink_link_state *state)
74 struct mii_bus *bus = pcs->bus;
78 bmsr = mdiobus_read(bus, addr, MII_BMSR);
79 lpa = mdiobus_read(bus, addr, MII_LPA);
80 if (bmsr < 0 || lpa < 0) {
85 state->link = !!(bmsr & BMSR_LSTATUS);
86 state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE);
90 state->speed = SPEED_2500;
91 state->pause |= MLO_PAUSE_TX | MLO_PAUSE_RX;
92 state->duplex = DUPLEX_FULL;
95 static void lynx_pcs_get_state(struct phylink_pcs *pcs,
96 struct phylink_link_state *state)
98 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
100 switch (state->interface) {
101 case PHY_INTERFACE_MODE_1000BASEX:
102 case PHY_INTERFACE_MODE_SGMII:
103 case PHY_INTERFACE_MODE_QSGMII:
104 phylink_mii_c22_pcs_get_state(lynx->mdio, state);
106 case PHY_INTERFACE_MODE_2500BASEX:
107 lynx_pcs_get_state_2500basex(lynx->mdio, state);
109 case PHY_INTERFACE_MODE_USXGMII:
110 lynx_pcs_get_state_usxgmii(lynx->mdio, state);
112 case PHY_INTERFACE_MODE_10GBASER:
113 phylink_mii_c45_pcs_get_state(lynx->mdio, state);
119 dev_dbg(&lynx->mdio->dev,
120 "mode=%s/%s/%s link=%u an_enabled=%u an_complete=%u\n",
121 phy_modes(state->interface),
122 phy_speed_to_str(state->speed),
123 phy_duplex_to_str(state->duplex),
124 state->link, state->an_enabled, state->an_complete);
127 static int lynx_pcs_config_1000basex(struct mdio_device *pcs,
129 const unsigned long *advertising)
131 struct mii_bus *bus = pcs->bus;
132 int addr = pcs->addr;
136 link_timer = LINK_TIMER_VAL(IEEE8023_LINK_TIMER_NS);
137 mdiobus_write(bus, addr, LINK_TIMER_LO, link_timer & 0xffff);
138 mdiobus_write(bus, addr, LINK_TIMER_HI, link_timer >> 16);
140 err = mdiobus_modify(bus, addr, IF_MODE,
141 IF_MODE_SGMII_EN | IF_MODE_USE_SGMII_AN,
146 return phylink_mii_c22_pcs_config(pcs, mode,
147 PHY_INTERFACE_MODE_1000BASEX,
151 static int lynx_pcs_config_sgmii(struct mdio_device *pcs, unsigned int mode,
152 const unsigned long *advertising)
154 struct mii_bus *bus = pcs->bus;
155 int addr = pcs->addr;
159 if_mode = IF_MODE_SGMII_EN;
160 if (mode == MLO_AN_INBAND) {
163 if_mode |= IF_MODE_USE_SGMII_AN;
165 /* Adjust link timer for SGMII */
166 link_timer = LINK_TIMER_VAL(SGMII_AN_LINK_TIMER_NS);
167 mdiobus_write(bus, addr, LINK_TIMER_LO, link_timer & 0xffff);
168 mdiobus_write(bus, addr, LINK_TIMER_HI, link_timer >> 16);
170 err = mdiobus_modify(bus, addr, IF_MODE,
171 IF_MODE_SGMII_EN | IF_MODE_USE_SGMII_AN,
176 return phylink_mii_c22_pcs_config(pcs, mode, PHY_INTERFACE_MODE_SGMII,
180 static int lynx_pcs_config_usxgmii(struct mdio_device *pcs, unsigned int mode,
181 const unsigned long *advertising)
183 struct mii_bus *bus = pcs->bus;
184 int addr = pcs->addr;
186 if (!phylink_autoneg_inband(mode)) {
187 dev_err(&pcs->dev, "USXGMII only supports in-band AN for now\n");
191 /* Configure device ability for the USXGMII Replicator */
192 return mdiobus_c45_write(bus, addr, MDIO_MMD_VEND2, MII_ADVERTISE,
193 MDIO_USXGMII_10G | MDIO_USXGMII_LINK |
194 MDIO_USXGMII_FULL_DUPLEX |
195 ADVERTISE_SGMII | ADVERTISE_LPACK);
198 static int lynx_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
199 phy_interface_t ifmode,
200 const unsigned long *advertising,
203 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
206 case PHY_INTERFACE_MODE_1000BASEX:
207 return lynx_pcs_config_1000basex(lynx->mdio, mode, advertising);
208 case PHY_INTERFACE_MODE_SGMII:
209 case PHY_INTERFACE_MODE_QSGMII:
210 return lynx_pcs_config_sgmii(lynx->mdio, mode, advertising);
211 case PHY_INTERFACE_MODE_2500BASEX:
212 if (phylink_autoneg_inband(mode)) {
213 dev_err(&lynx->mdio->dev,
214 "AN not supported on 3.125GHz SerDes lane\n");
218 case PHY_INTERFACE_MODE_USXGMII:
219 return lynx_pcs_config_usxgmii(lynx->mdio, mode, advertising);
220 case PHY_INTERFACE_MODE_10GBASER:
221 /* Nothing to do here for 10GBASER */
230 static void lynx_pcs_an_restart(struct phylink_pcs *pcs)
232 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
234 phylink_mii_c22_pcs_an_restart(lynx->mdio);
237 static void lynx_pcs_link_up_sgmii(struct mdio_device *pcs, unsigned int mode,
238 int speed, int duplex)
240 struct mii_bus *bus = pcs->bus;
241 u16 if_mode = 0, sgmii_speed;
242 int addr = pcs->addr;
244 /* The PCS needs to be configured manually only
245 * when not operating on in-band mode
247 if (mode == MLO_AN_INBAND)
250 if (duplex == DUPLEX_HALF)
251 if_mode |= IF_MODE_HALF_DUPLEX;
255 sgmii_speed = SGMII_SPEED_1000;
258 sgmii_speed = SGMII_SPEED_100;
261 sgmii_speed = SGMII_SPEED_10;
264 /* Silently don't do anything */
267 dev_err(&pcs->dev, "Invalid PCS speed %d\n", speed);
270 if_mode |= IF_MODE_SPEED(sgmii_speed);
272 mdiobus_modify(bus, addr, IF_MODE,
273 IF_MODE_HALF_DUPLEX | IF_MODE_SPEED_MSK,
277 /* 2500Base-X is SerDes protocol 7 on Felix and 6 on ENETC. It is a SerDes lane
278 * clocked at 3.125 GHz which encodes symbols with 8b/10b and does not have
279 * auto-negotiation of any link parameters. Electrically it is compatible with
280 * a single lane of XAUI.
281 * The hardware reference manual wants to call this mode SGMII, but it isn't
282 * really, since the fundamental features of SGMII:
283 * - Downgrading the link speed by duplicating symbols
286 * The speed is configured at 1000 in the IF_MODE because the clock frequency
287 * is actually given by a PLL configured in the Reset Configuration Word (RCW).
288 * Since there is no difference between fixed speed SGMII w/o AN and 802.3z w/o
289 * AN, we call this PHY interface type 2500Base-X. In case a PHY negotiates a
290 * lower link speed on line side, the system-side interface remains fixed at
291 * 2500 Mbps and we do rate adaptation through pause frames.
293 static void lynx_pcs_link_up_2500basex(struct mdio_device *pcs,
295 int speed, int duplex)
297 struct mii_bus *bus = pcs->bus;
298 int addr = pcs->addr;
301 if (mode == MLO_AN_INBAND) {
302 dev_err(&pcs->dev, "AN not supported for 2500BaseX\n");
306 if (duplex == DUPLEX_HALF)
307 if_mode |= IF_MODE_HALF_DUPLEX;
308 if_mode |= IF_MODE_SPEED(SGMII_SPEED_2500);
310 mdiobus_modify(bus, addr, IF_MODE,
311 IF_MODE_HALF_DUPLEX | IF_MODE_SPEED_MSK,
315 static void lynx_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
316 phy_interface_t interface,
317 int speed, int duplex)
319 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
322 case PHY_INTERFACE_MODE_SGMII:
323 case PHY_INTERFACE_MODE_QSGMII:
324 lynx_pcs_link_up_sgmii(lynx->mdio, mode, speed, duplex);
326 case PHY_INTERFACE_MODE_2500BASEX:
327 lynx_pcs_link_up_2500basex(lynx->mdio, mode, speed, duplex);
329 case PHY_INTERFACE_MODE_USXGMII:
330 /* At the moment, only in-band AN is supported for USXGMII
331 * so nothing to do in link_up
339 static const struct phylink_pcs_ops lynx_pcs_phylink_ops = {
340 .pcs_get_state = lynx_pcs_get_state,
341 .pcs_config = lynx_pcs_config,
342 .pcs_an_restart = lynx_pcs_an_restart,
343 .pcs_link_up = lynx_pcs_link_up,
346 struct phylink_pcs *lynx_pcs_create(struct mdio_device *mdio)
348 struct lynx_pcs *lynx;
350 lynx = kzalloc(sizeof(*lynx), GFP_KERNEL);
355 lynx->pcs.ops = &lynx_pcs_phylink_ops;
356 lynx->pcs.poll = true;
358 return lynx_to_phylink_pcs(lynx);
360 EXPORT_SYMBOL(lynx_pcs_create);
362 void lynx_pcs_destroy(struct phylink_pcs *pcs)
364 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
368 EXPORT_SYMBOL(lynx_pcs_destroy);
370 MODULE_LICENSE("Dual BSD/GPL");