1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Lynx PCS MDIO helpers
6 #include <linux/mdio.h>
7 #include <linux/phylink.h>
8 #include <linux/pcs-lynx.h>
10 #define SGMII_CLOCK_PERIOD_NS 8 /* PCS is clocked at 125 MHz */
11 #define LINK_TIMER_VAL(ns) ((u32)((ns) / SGMII_CLOCK_PERIOD_NS))
13 #define SGMII_AN_LINK_TIMER_NS 1600000 /* defined by SGMII spec */
14 #define IEEE8023_LINK_TIMER_NS 10000000
16 #define LINK_TIMER_LO 0x12
17 #define LINK_TIMER_HI 0x13
19 #define IF_MODE_SGMII_EN BIT(0)
20 #define IF_MODE_USE_SGMII_AN BIT(1)
21 #define IF_MODE_SPEED(x) (((x) << 2) & GENMASK(3, 2))
22 #define IF_MODE_SPEED_MSK GENMASK(3, 2)
23 #define IF_MODE_HALF_DUPLEX BIT(4)
32 #define phylink_pcs_to_lynx(pl_pcs) container_of((pl_pcs), struct lynx_pcs, pcs)
34 static void lynx_pcs_get_state_usxgmii(struct mdio_device *pcs,
35 struct phylink_link_state *state)
37 struct mii_bus *bus = pcs->bus;
41 status = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_BMSR);
45 state->link = !!(status & MDIO_STAT1_LSTATUS);
46 state->an_complete = !!(status & MDIO_AN_STAT1_COMPLETE);
47 if (!state->link || !state->an_complete)
50 lpa = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_LPA);
54 phylink_decode_usxgmii_word(state, lpa);
57 static void lynx_pcs_get_state_2500basex(struct mdio_device *pcs,
58 struct phylink_link_state *state)
60 struct mii_bus *bus = pcs->bus;
64 bmsr = mdiobus_read(bus, addr, MII_BMSR);
65 lpa = mdiobus_read(bus, addr, MII_LPA);
66 if (bmsr < 0 || lpa < 0) {
71 state->link = !!(bmsr & BMSR_LSTATUS);
72 state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE);
76 state->speed = SPEED_2500;
77 state->pause |= MLO_PAUSE_TX | MLO_PAUSE_RX;
78 state->duplex = DUPLEX_FULL;
81 static void lynx_pcs_get_state(struct phylink_pcs *pcs,
82 struct phylink_link_state *state)
84 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
86 switch (state->interface) {
87 case PHY_INTERFACE_MODE_1000BASEX:
88 case PHY_INTERFACE_MODE_SGMII:
89 case PHY_INTERFACE_MODE_QSGMII:
90 phylink_mii_c22_pcs_get_state(lynx->mdio, state);
92 case PHY_INTERFACE_MODE_2500BASEX:
93 lynx_pcs_get_state_2500basex(lynx->mdio, state);
95 case PHY_INTERFACE_MODE_USXGMII:
96 lynx_pcs_get_state_usxgmii(lynx->mdio, state);
98 case PHY_INTERFACE_MODE_10GBASER:
99 phylink_mii_c45_pcs_get_state(lynx->mdio, state);
105 dev_dbg(&lynx->mdio->dev,
106 "mode=%s/%s/%s link=%u an_enabled=%u an_complete=%u\n",
107 phy_modes(state->interface),
108 phy_speed_to_str(state->speed),
109 phy_duplex_to_str(state->duplex),
110 state->link, state->an_enabled, state->an_complete);
113 static int lynx_pcs_config_1000basex(struct mdio_device *pcs,
115 const unsigned long *advertising)
117 struct mii_bus *bus = pcs->bus;
118 int addr = pcs->addr;
122 link_timer = LINK_TIMER_VAL(IEEE8023_LINK_TIMER_NS);
123 mdiobus_write(bus, addr, LINK_TIMER_LO, link_timer & 0xffff);
124 mdiobus_write(bus, addr, LINK_TIMER_HI, link_timer >> 16);
126 err = mdiobus_modify(bus, addr, IF_MODE,
127 IF_MODE_SGMII_EN | IF_MODE_USE_SGMII_AN,
132 return phylink_mii_c22_pcs_config(pcs, mode,
133 PHY_INTERFACE_MODE_1000BASEX,
137 static int lynx_pcs_config_sgmii(struct mdio_device *pcs, unsigned int mode,
138 const unsigned long *advertising)
140 struct mii_bus *bus = pcs->bus;
141 int addr = pcs->addr;
145 if_mode = IF_MODE_SGMII_EN;
146 if (mode == MLO_AN_INBAND) {
149 if_mode |= IF_MODE_USE_SGMII_AN;
151 /* Adjust link timer for SGMII */
152 link_timer = LINK_TIMER_VAL(SGMII_AN_LINK_TIMER_NS);
153 mdiobus_write(bus, addr, LINK_TIMER_LO, link_timer & 0xffff);
154 mdiobus_write(bus, addr, LINK_TIMER_HI, link_timer >> 16);
156 err = mdiobus_modify(bus, addr, IF_MODE,
157 IF_MODE_SGMII_EN | IF_MODE_USE_SGMII_AN,
162 return phylink_mii_c22_pcs_config(pcs, mode, PHY_INTERFACE_MODE_SGMII,
166 static int lynx_pcs_config_usxgmii(struct mdio_device *pcs, unsigned int mode,
167 const unsigned long *advertising)
169 struct mii_bus *bus = pcs->bus;
170 int addr = pcs->addr;
172 if (!phylink_autoneg_inband(mode)) {
173 dev_err(&pcs->dev, "USXGMII only supports in-band AN for now\n");
177 /* Configure device ability for the USXGMII Replicator */
178 return mdiobus_c45_write(bus, addr, MDIO_MMD_VEND2, MII_ADVERTISE,
179 MDIO_USXGMII_10G | MDIO_USXGMII_LINK |
180 MDIO_USXGMII_FULL_DUPLEX |
181 ADVERTISE_SGMII | ADVERTISE_LPACK);
184 static int lynx_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
185 phy_interface_t ifmode,
186 const unsigned long *advertising,
189 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
192 case PHY_INTERFACE_MODE_1000BASEX:
193 return lynx_pcs_config_1000basex(lynx->mdio, mode, advertising);
194 case PHY_INTERFACE_MODE_SGMII:
195 case PHY_INTERFACE_MODE_QSGMII:
196 return lynx_pcs_config_sgmii(lynx->mdio, mode, advertising);
197 case PHY_INTERFACE_MODE_2500BASEX:
198 if (phylink_autoneg_inband(mode)) {
199 dev_err(&lynx->mdio->dev,
200 "AN not supported on 3.125GHz SerDes lane\n");
204 case PHY_INTERFACE_MODE_USXGMII:
205 return lynx_pcs_config_usxgmii(lynx->mdio, mode, advertising);
206 case PHY_INTERFACE_MODE_10GBASER:
207 /* Nothing to do here for 10GBASER */
216 static void lynx_pcs_an_restart(struct phylink_pcs *pcs)
218 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
220 phylink_mii_c22_pcs_an_restart(lynx->mdio);
223 static void lynx_pcs_link_up_sgmii(struct mdio_device *pcs, unsigned int mode,
224 int speed, int duplex)
226 struct mii_bus *bus = pcs->bus;
227 u16 if_mode = 0, sgmii_speed;
228 int addr = pcs->addr;
230 /* The PCS needs to be configured manually only
231 * when not operating on in-band mode
233 if (mode == MLO_AN_INBAND)
236 if (duplex == DUPLEX_HALF)
237 if_mode |= IF_MODE_HALF_DUPLEX;
241 sgmii_speed = SGMII_SPEED_1000;
244 sgmii_speed = SGMII_SPEED_100;
247 sgmii_speed = SGMII_SPEED_10;
250 /* Silently don't do anything */
253 dev_err(&pcs->dev, "Invalid PCS speed %d\n", speed);
256 if_mode |= IF_MODE_SPEED(sgmii_speed);
258 mdiobus_modify(bus, addr, IF_MODE,
259 IF_MODE_HALF_DUPLEX | IF_MODE_SPEED_MSK,
263 /* 2500Base-X is SerDes protocol 7 on Felix and 6 on ENETC. It is a SerDes lane
264 * clocked at 3.125 GHz which encodes symbols with 8b/10b and does not have
265 * auto-negotiation of any link parameters. Electrically it is compatible with
266 * a single lane of XAUI.
267 * The hardware reference manual wants to call this mode SGMII, but it isn't
268 * really, since the fundamental features of SGMII:
269 * - Downgrading the link speed by duplicating symbols
272 * The speed is configured at 1000 in the IF_MODE because the clock frequency
273 * is actually given by a PLL configured in the Reset Configuration Word (RCW).
274 * Since there is no difference between fixed speed SGMII w/o AN and 802.3z w/o
275 * AN, we call this PHY interface type 2500Base-X. In case a PHY negotiates a
276 * lower link speed on line side, the system-side interface remains fixed at
277 * 2500 Mbps and we do rate adaptation through pause frames.
279 static void lynx_pcs_link_up_2500basex(struct mdio_device *pcs,
281 int speed, int duplex)
283 struct mii_bus *bus = pcs->bus;
284 int addr = pcs->addr;
287 if (mode == MLO_AN_INBAND) {
288 dev_err(&pcs->dev, "AN not supported for 2500BaseX\n");
292 if (duplex == DUPLEX_HALF)
293 if_mode |= IF_MODE_HALF_DUPLEX;
294 if_mode |= IF_MODE_SPEED(SGMII_SPEED_2500);
296 mdiobus_modify(bus, addr, IF_MODE,
297 IF_MODE_HALF_DUPLEX | IF_MODE_SPEED_MSK,
301 static void lynx_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
302 phy_interface_t interface,
303 int speed, int duplex)
305 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
308 case PHY_INTERFACE_MODE_SGMII:
309 case PHY_INTERFACE_MODE_QSGMII:
310 lynx_pcs_link_up_sgmii(lynx->mdio, mode, speed, duplex);
312 case PHY_INTERFACE_MODE_2500BASEX:
313 lynx_pcs_link_up_2500basex(lynx->mdio, mode, speed, duplex);
315 case PHY_INTERFACE_MODE_USXGMII:
316 /* At the moment, only in-band AN is supported for USXGMII
317 * so nothing to do in link_up
325 static const struct phylink_pcs_ops lynx_pcs_phylink_ops = {
326 .pcs_get_state = lynx_pcs_get_state,
327 .pcs_config = lynx_pcs_config,
328 .pcs_an_restart = lynx_pcs_an_restart,
329 .pcs_link_up = lynx_pcs_link_up,
332 struct lynx_pcs *lynx_pcs_create(struct mdio_device *mdio)
334 struct lynx_pcs *lynx_pcs;
336 lynx_pcs = kzalloc(sizeof(*lynx_pcs), GFP_KERNEL);
340 lynx_pcs->mdio = mdio;
341 lynx_pcs->pcs.ops = &lynx_pcs_phylink_ops;
342 lynx_pcs->pcs.poll = true;
346 EXPORT_SYMBOL(lynx_pcs_create);
348 void lynx_pcs_destroy(struct lynx_pcs *pcs)
352 EXPORT_SYMBOL(lynx_pcs_destroy);
354 MODULE_LICENSE("Dual BSD/GPL");