drivers/net/ieee802154/cc2520.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* Driver for TI CC2520 802.15.4 Wireless-PAN Networking controller
   3  *
   4  * Copyright (C) 2014 Varka Bhadram <varkab@cdac.in>
   5  *                    Md.Jamal Mohiuddin <mjmohiuddin@cdac.in>
   6  *                    P Sowjanya <sowjanyap@cdac.in>
   7  */
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/gpio.h>
  11 #include <linux/delay.h>
  12 #include <linux/spi/spi.h>
  13 #include <linux/spi/cc2520.h>
  14 #include <linux/workqueue.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/skbuff.h>
  17 #include <linux/of_gpio.h>
  18 #include <linux/ieee802154.h>
  19 #include <linux/crc-ccitt.h>
  20 #include <asm/unaligned.h>
  21
  22 #include <net/mac802154.h>
  23 #include <net/cfg802154.h>
  24
  25 #define SPI_COMMAND_BUFFER      3
  26 #define HIGH                    1
  27 #define LOW                     0
  28 #define STATE_IDLE              0
  29 #define RSSI_VALID              0
  30 #define RSSI_OFFSET             78
  31
  32 #define CC2520_RAM_SIZE         640
  33 #define CC2520_FIFO_SIZE        128
  34
  35 #define CC2520RAM_TXFIFO        0x100
  36 #define CC2520RAM_RXFIFO        0x180
  37 #define CC2520RAM_IEEEADDR      0x3EA
  38 #define CC2520RAM_PANID         0x3F2
  39 #define CC2520RAM_SHORTADDR     0x3F4
  40
  41 #define CC2520_FREG_MASK        0x3F
  42
  43 /* status byte values */
  44 #define CC2520_STATUS_XOSC32M_STABLE    BIT(7)
  45 #define CC2520_STATUS_RSSI_VALID        BIT(6)
  46 #define CC2520_STATUS_TX_UNDERFLOW      BIT(3)
  47
  48 /* IEEE-802.15.4 defined constants (2.4 GHz logical channels) */
  49 #define CC2520_MINCHANNEL               11
  50 #define CC2520_MAXCHANNEL               26
  51 #define CC2520_CHANNEL_SPACING          5
  52
  53 /* command strobes */
  54 #define CC2520_CMD_SNOP                 0x00
  55 #define CC2520_CMD_IBUFLD               0x02
  56 #define CC2520_CMD_SIBUFEX              0x03
  57 #define CC2520_CMD_SSAMPLECCA           0x04
  58 #define CC2520_CMD_SRES                 0x0f
  59 #define CC2520_CMD_MEMORY_MASK          0x0f
  60 #define CC2520_CMD_MEMORY_READ          0x10
  61 #define CC2520_CMD_MEMORY_WRITE         0x20
  62 #define CC2520_CMD_RXBUF                0x30
  63 #define CC2520_CMD_RXBUFCP              0x38
  64 #define CC2520_CMD_RXBUFMOV             0x32
  65 #define CC2520_CMD_TXBUF                0x3A
  66 #define CC2520_CMD_TXBUFCP              0x3E
  67 #define CC2520_CMD_RANDOM               0x3C
  68 #define CC2520_CMD_SXOSCON              0x40
  69 #define CC2520_CMD_STXCAL               0x41
  70 #define CC2520_CMD_SRXON                0x42
  71 #define CC2520_CMD_STXON                0x43
  72 #define CC2520_CMD_STXONCCA             0x44
  73 #define CC2520_CMD_SRFOFF               0x45
  74 #define CC2520_CMD_SXOSCOFF             0x46
  75 #define CC2520_CMD_SFLUSHRX             0x47
  76 #define CC2520_CMD_SFLUSHTX             0x48
  77 #define CC2520_CMD_SACK                 0x49
  78 #define CC2520_CMD_SACKPEND             0x4A
  79 #define CC2520_CMD_SNACK                0x4B
  80 #define CC2520_CMD_SRXMASKBITSET        0x4C
  81 #define CC2520_CMD_SRXMASKBITCLR        0x4D
  82 #define CC2520_CMD_RXMASKAND            0x4E
  83 #define CC2520_CMD_RXMASKOR             0x4F
  84 #define CC2520_CMD_MEMCP                0x50
  85 #define CC2520_CMD_MEMCPR               0x52
  86 #define CC2520_CMD_MEMXCP               0x54
  87 #define CC2520_CMD_MEMXWR               0x56
  88 #define CC2520_CMD_BCLR                 0x58
  89 #define CC2520_CMD_BSET                 0x59
  90 #define CC2520_CMD_CTR_UCTR             0x60
  91 #define CC2520_CMD_CBCMAC               0x64
  92 #define CC2520_CMD_UCBCMAC              0x66
  93 #define CC2520_CMD_CCM                  0x68
  94 #define CC2520_CMD_UCCM                 0x6A
  95 #define CC2520_CMD_ECB                  0x70
  96 #define CC2520_CMD_ECBO                 0x72
  97 #define CC2520_CMD_ECBX                 0x74
  98 #define CC2520_CMD_INC                  0x78
  99 #define CC2520_CMD_ABORT                0x7F
 100 #define CC2520_CMD_REGISTER_READ        0x80
 101 #define CC2520_CMD_REGISTER_WRITE       0xC0
 102
 103 /* status registers */
 104 #define CC2520_CHIPID                   0x40
 105 #define CC2520_VERSION                  0x42
 106 #define CC2520_EXTCLOCK                 0x44
 107 #define CC2520_MDMCTRL0                 0x46
 108 #define CC2520_MDMCTRL1                 0x47
 109 #define CC2520_FREQEST                  0x48
 110 #define CC2520_RXCTRL                   0x4A
 111 #define CC2520_FSCTRL                   0x4C
 112 #define CC2520_FSCAL0                   0x4E
 113 #define CC2520_FSCAL1                   0x4F
 114 #define CC2520_FSCAL2                   0x50
 115 #define CC2520_FSCAL3                   0x51
 116 #define CC2520_AGCCTRL0                 0x52
 117 #define CC2520_AGCCTRL1                 0x53
 118 #define CC2520_AGCCTRL2                 0x54
 119 #define CC2520_AGCCTRL3                 0x55
 120 #define CC2520_ADCTEST0                 0x56
 121 #define CC2520_ADCTEST1                 0x57
 122 #define CC2520_ADCTEST2                 0x58
 123 #define CC2520_MDMTEST0                 0x5A
 124 #define CC2520_MDMTEST1                 0x5B
 125 #define CC2520_DACTEST0                 0x5C
 126 #define CC2520_DACTEST1                 0x5D
 127 #define CC2520_ATEST                    0x5E
 128 #define CC2520_DACTEST2                 0x5F
 129 #define CC2520_PTEST0                   0x60
 130 #define CC2520_PTEST1                   0x61
 131 #define CC2520_RESERVED                 0x62
 132 #define CC2520_DPUBIST                  0x7A
 133 #define CC2520_ACTBIST                  0x7C
 134 #define CC2520_RAMBIST                  0x7E
 135
 136 /* frame registers */
 137 #define CC2520_FRMFILT0                 0x00
 138 #define CC2520_FRMFILT1                 0x01
 139 #define CC2520_SRCMATCH                 0x02
 140 #define CC2520_SRCSHORTEN0              0x04
 141 #define CC2520_SRCSHORTEN1              0x05
 142 #define CC2520_SRCSHORTEN2              0x06
 143 #define CC2520_SRCEXTEN0                0x08
 144 #define CC2520_SRCEXTEN1                0x09
 145 #define CC2520_SRCEXTEN2                0x0A
 146 #define CC2520_FRMCTRL0                 0x0C
 147 #define CC2520_FRMCTRL1                 0x0D
 148 #define CC2520_RXENABLE0                0x0E
 149 #define CC2520_RXENABLE1                0x0F
 150 #define CC2520_EXCFLAG0                 0x10
 151 #define CC2520_EXCFLAG1                 0x11
 152 #define CC2520_EXCFLAG2                 0x12
 153 #define CC2520_EXCMASKA0                0x14
 154 #define CC2520_EXCMASKA1                0x15
 155 #define CC2520_EXCMASKA2                0x16
 156 #define CC2520_EXCMASKB0                0x18
 157 #define CC2520_EXCMASKB1                0x19
 158 #define CC2520_EXCMASKB2                0x1A
 159 #define CC2520_EXCBINDX0                0x1C
 160 #define CC2520_EXCBINDX1                0x1D
 161 #define CC2520_EXCBINDY0                0x1E
 162 #define CC2520_EXCBINDY1                0x1F
 163 #define CC2520_GPIOCTRL0                0x20
 164 #define CC2520_GPIOCTRL1                0x21
 165 #define CC2520_GPIOCTRL2                0x22
 166 #define CC2520_GPIOCTRL3                0x23
 167 #define CC2520_GPIOCTRL4                0x24
 168 #define CC2520_GPIOCTRL5                0x25
 169 #define CC2520_GPIOPOLARITY             0x26
 170 #define CC2520_GPIOCTRL                 0x28
 171 #define CC2520_DPUCON                   0x2A
 172 #define CC2520_DPUSTAT                  0x2C
 173 #define CC2520_FREQCTRL                 0x2E
 174 #define CC2520_FREQTUNE                 0x2F
 175 #define CC2520_TXPOWER                  0x30
 176 #define CC2520_TXCTRL                   0x31
 177 #define CC2520_FSMSTAT0                 0x32
 178 #define CC2520_FSMSTAT1                 0x33
 179 #define CC2520_FIFOPCTRL                0x34
 180 #define CC2520_FSMCTRL                  0x35
 181 #define CC2520_CCACTRL0                 0x36
 182 #define CC2520_CCACTRL1                 0x37
 183 #define CC2520_RSSI                     0x38
 184 #define CC2520_RSSISTAT                 0x39
 185 #define CC2520_RXFIRST                  0x3C
 186 #define CC2520_RXFIFOCNT                0x3E
 187 #define CC2520_TXFIFOCNT                0x3F
 188
 189 /* CC2520_FRMFILT0 */
 190 #define FRMFILT0_FRAME_FILTER_EN        BIT(0)
 191 #define FRMFILT0_PAN_COORDINATOR        BIT(1)
 192
 193 /* CC2520_FRMCTRL0 */
 194 #define FRMCTRL0_AUTOACK                BIT(5)
 195 #define FRMCTRL0_AUTOCRC                BIT(6)
 196
 197 /* CC2520_FRMCTRL1 */
 198 #define FRMCTRL1_SET_RXENMASK_ON_TX     BIT(0)
 199 #define FRMCTRL1_IGNORE_TX_UNDERF       BIT(1)
 200
 201 /* Driver private information */
 202 struct cc2520_private {
 203         struct spi_device *spi;         /* SPI device structure */
 204         struct ieee802154_hw *hw;       /* IEEE-802.15.4 device */
 205         u8 *buf;                        /* SPI TX/Rx data buffer */
 206         struct mutex buffer_mutex;      /* SPI buffer mutex */
 207         bool is_tx;                     /* Flag for sync b/w Tx and Rx */
 208         bool amplified;                 /* Flag for CC2591 */
 209         int fifo_pin;                   /* FIFO GPIO pin number */
 210         struct work_struct fifop_irqwork;/* Workqueue for FIFOP */
 211         spinlock_t lock;                /* Lock for is_tx*/
 212         struct completion tx_complete;  /* Work completion for Tx */
 213         bool promiscuous;               /* Flag for promiscuous mode */
 214 };
 215
 216 /* Generic Functions */
 217 static int
 218 cc2520_cmd_strobe(struct cc2520_private *priv, u8 cmd)
 219 {
 220         int ret;
 221         struct spi_message msg;
 222         struct spi_transfer xfer = {
 223                 .len = 0,
 224                 .tx_buf = priv->buf,
 225                 .rx_buf = priv->buf,
 226         };
 227
 228         spi_message_init(&msg);
 229         spi_message_add_tail(&xfer, &msg);
 230
 231         mutex_lock(&priv->buffer_mutex);
 232         priv->buf[xfer.len++] = cmd;
 233         dev_vdbg(&priv->spi->dev,
 234                  "command strobe buf[0] = %02x\n",
 235                  priv->buf[0]);
 236
 237         ret = spi_sync(priv->spi, &msg);
 238         dev_vdbg(&priv->spi->dev,
 239                  "buf[0] = %02x\n", priv->buf[0]);
 240         mutex_unlock(&priv->buffer_mutex);
 241
 242         return ret;
 243 }
 244
 245 static int
 246 cc2520_get_status(struct cc2520_private *priv, u8 *status)
 247 {
 248         int ret;
 249         struct spi_message msg;
 250         struct spi_transfer xfer = {
 251                 .len = 0,
 252                 .tx_buf = priv->buf,
 253                 .rx_buf = priv->buf,
 254         };
 255
 256         spi_message_init(&msg);
 257         spi_message_add_tail(&xfer, &msg);
 258
 259         mutex_lock(&priv->buffer_mutex);
 260         priv->buf[xfer.len++] = CC2520_CMD_SNOP;
 261         dev_vdbg(&priv->spi->dev,
 262                  "get status command buf[0] = %02x\n", priv->buf[0]);
 263
 264         ret = spi_sync(priv->spi, &msg);
 265         if (!ret)
 266                 *status = priv->buf[0];
 267         dev_vdbg(&priv->spi->dev,
 268                  "buf[0] = %02x\n", priv->buf[0]);
 269         mutex_unlock(&priv->buffer_mutex);
 270
 271         return ret;
 272 }
 273
 274 static int
 275 cc2520_write_register(struct cc2520_private *priv, u8 reg, u8 value)
 276 {
 277         int status;
 278         struct spi_message msg;
 279         struct spi_transfer xfer = {
 280                 .len = 0,
 281                 .tx_buf = priv->buf,
 282                 .rx_buf = priv->buf,
 283         };
 284
 285         spi_message_init(&msg);
 286         spi_message_add_tail(&xfer, &msg);
 287
 288         mutex_lock(&priv->buffer_mutex);
 289
 290         if (reg <= CC2520_FREG_MASK) {
 291                 priv->buf[xfer.len++] = CC2520_CMD_REGISTER_WRITE | reg;
 292                 priv->buf[xfer.len++] = value;
 293         } else {
 294                 priv->buf[xfer.len++] = CC2520_CMD_MEMORY_WRITE;
 295                 priv->buf[xfer.len++] = reg;
 296                 priv->buf[xfer.len++] = value;
 297         }
 298         status = spi_sync(priv->spi, &msg);
 299         if (msg.status)
 300                 status = msg.status;
 301
 302         mutex_unlock(&priv->buffer_mutex);
 303
 304         return status;
 305 }
 306
 307 static int
 308 cc2520_write_ram(struct cc2520_private *priv, u16 reg, u8 len, u8 *data)
 309 {
 310         int status;
 311         struct spi_message msg;
 312         struct spi_transfer xfer_head = {
 313                 .len        = 0,
 314                 .tx_buf        = priv->buf,
 315                 .rx_buf        = priv->buf,
 316         };
 317
 318         struct spi_transfer xfer_buf = {
 319                 .len = len,
 320                 .tx_buf = data,
 321         };
 322
 323         mutex_lock(&priv->buffer_mutex);
 324         priv->buf[xfer_head.len++] = (CC2520_CMD_MEMORY_WRITE |
 325                                                 ((reg >> 8) & 0xff));
 326         priv->buf[xfer_head.len++] = reg & 0xff;
 327
 328         spi_message_init(&msg);
 329         spi_message_add_tail(&xfer_head, &msg);
 330         spi_message_add_tail(&xfer_buf, &msg);
 331
 332         status = spi_sync(priv->spi, &msg);
 333         dev_dbg(&priv->spi->dev, "spi status = %d\n", status);
 334         if (msg.status)
 335                 status = msg.status;
 336
 337         mutex_unlock(&priv->buffer_mutex);
 338         return status;
 339 }
 340
 341 static int
 342 cc2520_read_register(struct cc2520_private *priv, u8 reg, u8 *data)
 343 {
 344         int status;
 345         struct spi_message msg;
 346         struct spi_transfer xfer1 = {
 347                 .len = 0,
 348                 .tx_buf = priv->buf,
 349                 .rx_buf = priv->buf,
 350         };
 351
 352         struct spi_transfer xfer2 = {
 353                 .len = 1,
 354                 .rx_buf = data,
 355         };
 356
 357         spi_message_init(&msg);
 358         spi_message_add_tail(&xfer1, &msg);
 359         spi_message_add_tail(&xfer2, &msg);
 360
 361         mutex_lock(&priv->buffer_mutex);
 362         priv->buf[xfer1.len++] = CC2520_CMD_MEMORY_READ;
 363         priv->buf[xfer1.len++] = reg;
 364
 365         status = spi_sync(priv->spi, &msg);
 366         dev_dbg(&priv->spi->dev,
 367                 "spi status = %d\n", status);
 368         if (msg.status)
 369                 status = msg.status;
 370
 371         mutex_unlock(&priv->buffer_mutex);
 372
 373         return status;
 374 }
 375
 376 static int
 377 cc2520_write_txfifo(struct cc2520_private *priv, u8 pkt_len, u8 *data, u8 len)
 378 {
 379         int status;
 380
 381         /* length byte must include FCS even
 382          * if it is calculated in the hardware
 383          */
 384         int len_byte = pkt_len;
 385
 386         struct spi_message msg;
 387
 388         struct spi_transfer xfer_head = {
 389                 .len = 0,
 390                 .tx_buf = priv->buf,
 391                 .rx_buf = priv->buf,
 392         };
 393         struct spi_transfer xfer_len = {
 394                 .len = 1,
 395                 .tx_buf = &len_byte,
 396         };
 397         struct spi_transfer xfer_buf = {
 398                 .len = len,
 399                 .tx_buf = data,
 400         };
 401
 402         spi_message_init(&msg);
 403         spi_message_add_tail(&xfer_head, &msg);
 404         spi_message_add_tail(&xfer_len, &msg);
 405         spi_message_add_tail(&xfer_buf, &msg);
 406
 407         mutex_lock(&priv->buffer_mutex);
 408         priv->buf[xfer_head.len++] = CC2520_CMD_TXBUF;
 409         dev_vdbg(&priv->spi->dev,
 410                  "TX_FIFO cmd buf[0] = %02x\n", priv->buf[0]);
 411
 412         status = spi_sync(priv->spi, &msg);
 413         dev_vdbg(&priv->spi->dev, "status = %d\n", status);
 414         if (msg.status)
 415                 status = msg.status;
 416         dev_vdbg(&priv->spi->dev, "status = %d\n", status);
 417         dev_vdbg(&priv->spi->dev, "buf[0] = %02x\n", priv->buf[0]);
 418         mutex_unlock(&priv->buffer_mutex);
 419
 420         return status;
 421 }
 422
 423 static int
 424 cc2520_read_rxfifo(struct cc2520_private *priv, u8 *data, u8 len)
 425 {
 426         int status;
 427         struct spi_message msg;
 428
 429         struct spi_transfer xfer_head = {
 430                 .len = 0,
 431                 .tx_buf = priv->buf,
 432                 .rx_buf = priv->buf,
 433         };
 434         struct spi_transfer xfer_buf = {
 435                 .len = len,
 436                 .rx_buf = data,
 437         };
 438
 439         spi_message_init(&msg);
 440         spi_message_add_tail(&xfer_head, &msg);
 441         spi_message_add_tail(&xfer_buf, &msg);
 442
 443         mutex_lock(&priv->buffer_mutex);
 444         priv->buf[xfer_head.len++] = CC2520_CMD_RXBUF;
 445
 446         dev_vdbg(&priv->spi->dev, "read rxfifo buf[0] = %02x\n", priv->buf[0]);
 447         dev_vdbg(&priv->spi->dev, "buf[1] = %02x\n", priv->buf[1]);
 448
 449         status = spi_sync(priv->spi, &msg);
 450         dev_vdbg(&priv->spi->dev, "status = %d\n", status);
 451         if (msg.status)
 452                 status = msg.status;
 453         dev_vdbg(&priv->spi->dev, "status = %d\n", status);
 454         dev_vdbg(&priv->spi->dev,
 455                  "return status buf[0] = %02x\n", priv->buf[0]);
 456         dev_vdbg(&priv->spi->dev, "length buf[1] = %02x\n", priv->buf[1]);
 457
 458         mutex_unlock(&priv->buffer_mutex);
 459
 460         return status;
 461 }
 462
 463 static int cc2520_start(struct ieee802154_hw *hw)
 464 {
 465         return cc2520_cmd_strobe(hw->priv, CC2520_CMD_SRXON);
 466 }
 467
 468 static void cc2520_stop(struct ieee802154_hw *hw)
 469 {
 470         cc2520_cmd_strobe(hw->priv, CC2520_CMD_SRFOFF);
 471 }
 472
 473 static int
 474 cc2520_tx(struct ieee802154_hw *hw, struct sk_buff *skb)
 475 {
 476         struct cc2520_private *priv = hw->priv;
 477         unsigned long flags;
 478         int rc;
 479         u8 status = 0;
 480         u8 pkt_len;
 481
 482         /* In promiscuous mode we disable AUTOCRC so we can get the raw CRC
 483          * values on RX. This means we need to manually add the CRC on TX.
 484          */
 485         if (priv->promiscuous) {
 486                 u16 crc = crc_ccitt(0, skb->data, skb->len);
 487
 488                 put_unaligned_le16(crc, skb_put(skb, 2));
 489                 pkt_len = skb->len;
 490         } else {
 491                 pkt_len = skb->len + 2;
 492         }
 493
 494         rc = cc2520_cmd_strobe(priv, CC2520_CMD_SFLUSHTX);
 495         if (rc)
 496                 goto err_tx;
 497
 498         rc = cc2520_write_txfifo(priv, pkt_len, skb->data, skb->len);
 499         if (rc)
 500                 goto err_tx;
 501
 502         rc = cc2520_get_status(priv, &status);
 503         if (rc)
 504                 goto err_tx;
 505
 506         if (status & CC2520_STATUS_TX_UNDERFLOW) {
 507                 rc = -EINVAL;
 508                 dev_err(&priv->spi->dev, "cc2520 tx underflow exception\n");
 509                 goto err_tx;
 510         }
 511
 512         spin_lock_irqsave(&priv->lock, flags);
 513         WARN_ON(priv->is_tx);
 514         priv->is_tx = 1;
 515         spin_unlock_irqrestore(&priv->lock, flags);
 516
 517         rc = cc2520_cmd_strobe(priv, CC2520_CMD_STXONCCA);
 518         if (rc)
 519                 goto err;
 520
 521         rc = wait_for_completion_interruptible(&priv->tx_complete);
 522         if (rc < 0)
 523                 goto err;
 524
 525         cc2520_cmd_strobe(priv, CC2520_CMD_SFLUSHTX);
 526         cc2520_cmd_strobe(priv, CC2520_CMD_SRXON);
 527
 528         return rc;
 529 err:
 530         spin_lock_irqsave(&priv->lock, flags);
 531         priv->is_tx = 0;
 532         spin_unlock_irqrestore(&priv->lock, flags);
 533 err_tx:
 534         return rc;
 535 }
 536
 537 static int cc2520_rx(struct cc2520_private *priv)
 538 {
 539         u8 len = 0, lqi = 0, bytes = 1;
 540         struct sk_buff *skb;
 541
 542         /* Read single length byte from the radio. */
 543         cc2520_read_rxfifo(priv, &len, bytes);
 544
 545         if (!ieee802154_is_valid_psdu_len(len)) {
 546                 /* Corrupted frame received, clear frame buffer by
 547                  * reading entire buffer.
 548                  */
 549                 dev_dbg(&priv->spi->dev, "corrupted frame received\n");
 550                 len = IEEE802154_MTU;
 551         }
 552
 553         skb = dev_alloc_skb(len);
 554         if (!skb)
 555                 return -ENOMEM;
 556
 557         if (cc2520_read_rxfifo(priv, skb_put(skb, len), len)) {
 558                 dev_dbg(&priv->spi->dev, "frame reception failed\n");
 559                 kfree_skb(skb);
 560                 return -EINVAL;
 561         }
 562
 563         /* In promiscuous mode, we configure the radio to include the
 564          * CRC (AUTOCRC==0) and we pass on the packet unconditionally. If not
 565          * in promiscuous mode, we check the CRC here, but leave the
 566          * RSSI/LQI/CRC_OK bytes as they will get removed in the mac layer.
 567          */
 568         if (!priv->promiscuous) {
 569                 bool crc_ok;
 570
 571                 /* Check if the CRC is valid. With AUTOCRC set, the most
 572                  * significant bit of the last byte returned from the CC2520
 573                  * is CRC_OK flag. See section 20.3.4 of the datasheet.
 574                  */
 575                 crc_ok = skb->data[len - 1] & BIT(7);
 576
 577                 /* If we failed CRC drop the packet in the driver layer. */
 578                 if (!crc_ok) {
 579                         dev_dbg(&priv->spi->dev, "CRC check failed\n");
 580                         kfree_skb(skb);
 581                         return -EINVAL;
 582                 }
 583
 584                 /* To calculate LQI, the lower 7 bits of the last byte (the
 585                  * correlation value provided by the radio) must be scaled to
 586                  * the range 0-255. According to section 20.6, the correlation
 587                  * value ranges from 50-110. Ideally this would be calibrated
 588                  * per hardware design, but we use roughly the datasheet values
 589                  * to get close enough while avoiding floating point.
 590                  */
 591                 lqi = skb->data[len - 1] & 0x7f;
 592                 if (lqi < 50)
 593                         lqi = 50;
 594                 else if (lqi > 113)
 595                         lqi = 113;
 596                 lqi = (lqi - 50) * 4;
 597         }
 598
 599         ieee802154_rx_irqsafe(priv->hw, skb, lqi);
 600
 601         dev_vdbg(&priv->spi->dev, "RXFIFO: %x %x\n", len, lqi);
 602
 603         return 0;
 604 }
 605
 606 static int
 607 cc2520_ed(struct ieee802154_hw *hw, u8 *level)
 608 {
 609         struct cc2520_private *priv = hw->priv;
 610         u8 status = 0xff;
 611         u8 rssi;
 612         int ret;
 613
 614         ret = cc2520_read_register(priv, CC2520_RSSISTAT, &status);
 615         if (ret)
 616                 return ret;
 617
 618         if (status != RSSI_VALID)
 619                 return -EINVAL;
 620
 621         ret = cc2520_read_register(priv, CC2520_RSSI, &rssi);
 622         if (ret)
 623                 return ret;
 624
 625         /* level = RSSI(rssi) - OFFSET [dBm] : offset is 76dBm */
 626         *level = rssi - RSSI_OFFSET;
 627
 628         return 0;
 629 }
 630
 631 static int
 632 cc2520_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
 633 {
 634         struct cc2520_private *priv = hw->priv;
 635         int ret;
 636
 637         dev_dbg(&priv->spi->dev, "trying to set channel\n");
 638
 639         WARN_ON(page != 0);
 640         WARN_ON(channel < CC2520_MINCHANNEL);
 641         WARN_ON(channel > CC2520_MAXCHANNEL);
 642
 643         ret = cc2520_write_register(priv, CC2520_FREQCTRL,
 644                                     11 + 5 * (channel - 11));
 645
 646         return ret;
 647 }
 648
 649 static int
 650 cc2520_filter(struct ieee802154_hw *hw,
 651               struct ieee802154_hw_addr_filt *filt, unsigned long changed)
 652 {
 653         struct cc2520_private *priv = hw->priv;
 654         int ret = 0;
 655
 656         if (changed & IEEE802154_AFILT_PANID_CHANGED) {
 657                 u16 panid = le16_to_cpu(filt->pan_id);
 658
 659                 dev_vdbg(&priv->spi->dev, "%s called for pan id\n", __func__);
 660                 ret = cc2520_write_ram(priv, CC2520RAM_PANID,
 661                                        sizeof(panid), (u8 *)&panid);
 662         }
 663
 664         if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
 665                 dev_vdbg(&priv->spi->dev,
 666                          "%s called for IEEE addr\n", __func__);
 667                 ret = cc2520_write_ram(priv, CC2520RAM_IEEEADDR,
 668                                        sizeof(filt->ieee_addr),
 669                                        (u8 *)&filt->ieee_addr);
 670         }
 671
 672         if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
 673                 u16 addr = le16_to_cpu(filt->short_addr);
 674
 675                 dev_vdbg(&priv->spi->dev, "%s called for saddr\n", __func__);
 676                 ret = cc2520_write_ram(priv, CC2520RAM_SHORTADDR,
 677                                        sizeof(addr), (u8 *)&addr);
 678         }
 679
 680         if (changed & IEEE802154_AFILT_PANC_CHANGED) {
 681                 u8 frmfilt0;
 682
 683                 dev_vdbg(&priv->spi->dev,
 684                          "%s called for panc change\n", __func__);
 685
 686                 cc2520_read_register(priv, CC2520_FRMFILT0, &frmfilt0);
 687
 688                 if (filt->pan_coord)
 689                         frmfilt0 |= FRMFILT0_PAN_COORDINATOR;
 690                 else
 691                         frmfilt0 &= ~FRMFILT0_PAN_COORDINATOR;
 692
 693                 ret = cc2520_write_register(priv, CC2520_FRMFILT0, frmfilt0);
 694         }
 695
 696         return ret;
 697 }
 698
 699 static inline int cc2520_set_tx_power(struct cc2520_private *priv, s32 mbm)
 700 {
 701         u8 power;
 702
 703         switch (mbm) {
 704         case 500:
 705                 power = 0xF7;
 706                 break;
 707         case 300:
 708                 power = 0xF2;
 709                 break;
 710         case 200:
 711                 power = 0xAB;
 712                 break;
 713         case 100:
 714                 power = 0x13;
 715                 break;
 716         case 0:
 717                 power = 0x32;
 718                 break;
 719         case -200:
 720                 power = 0x81;
 721                 break;
 722         case -400:
 723                 power = 0x88;
 724                 break;
 725         case -700:
 726                 power = 0x2C;
 727                 break;
 728         case -1800:
 729                 power = 0x03;
 730                 break;
 731         default:
 732                 return -EINVAL;
 733         }
 734
 735         return cc2520_write_register(priv, CC2520_TXPOWER, power);
 736 }
 737
 738 static inline int cc2520_cc2591_set_tx_power(struct cc2520_private *priv,
 739                                              s32 mbm)
 740 {
 741         u8 power;
 742
 743         switch (mbm) {
 744         case 1700:
 745                 power = 0xF9;
 746                 break;
 747         case 1600:
 748                 power = 0xF0;
 749                 break;
 750         case 1400:
 751                 power = 0xA0;
 752                 break;
 753         case 1100:
 754                 power = 0x2C;
 755                 break;
 756         case -100:
 757                 power = 0x03;
 758                 break;
 759         case -800:
 760                 power = 0x01;
 761                 break;
 762         default:
 763                 return -EINVAL;
 764         }
 765
 766         return cc2520_write_register(priv, CC2520_TXPOWER, power);
 767 }
 768
 769 #define CC2520_MAX_TX_POWERS 0x8
 770 static const s32 cc2520_powers[CC2520_MAX_TX_POWERS + 1] = {
 771         500, 300, 200, 100, 0, -200, -400, -700, -1800,
 772 };
 773
 774 #define CC2520_CC2591_MAX_TX_POWERS 0x5
 775 static const s32 cc2520_cc2591_powers[CC2520_CC2591_MAX_TX_POWERS + 1] = {
 776         1700, 1600, 1400, 1100, -100, -800,
 777 };
 778
 779 static int
 780 cc2520_set_txpower(struct ieee802154_hw *hw, s32 mbm)
 781 {
 782         struct cc2520_private *priv = hw->priv;
 783
 784         if (!priv->amplified)
 785                 return cc2520_set_tx_power(priv, mbm);
 786
 787         return cc2520_cc2591_set_tx_power(priv, mbm);
 788 }
 789
 790 static int
 791 cc2520_set_promiscuous_mode(struct ieee802154_hw *hw, bool on)
 792 {
 793         struct cc2520_private *priv = hw->priv;
 794         u8 frmfilt0;
 795
 796         dev_dbg(&priv->spi->dev, "%s : mode %d\n", __func__, on);
 797
 798         priv->promiscuous = on;
 799
 800         cc2520_read_register(priv, CC2520_FRMFILT0, &frmfilt0);
 801
 802         if (on) {
 803                 /* Disable automatic ACK, automatic CRC, and frame filtering. */
 804                 cc2520_write_register(priv, CC2520_FRMCTRL0, 0);
 805                 frmfilt0 &= ~FRMFILT0_FRAME_FILTER_EN;
 806         } else {
 807                 cc2520_write_register(priv, CC2520_FRMCTRL0, FRMCTRL0_AUTOACK |
 808                                                              FRMCTRL0_AUTOCRC);
 809                 frmfilt0 |= FRMFILT0_FRAME_FILTER_EN;
 810         }
 811         return cc2520_write_register(priv, CC2520_FRMFILT0, frmfilt0);
 812 }
 813
 814 static const struct ieee802154_ops cc2520_ops = {
 815         .owner = THIS_MODULE,
 816         .start = cc2520_start,
 817         .stop = cc2520_stop,
 818         .xmit_sync = cc2520_tx,
 819         .ed = cc2520_ed,
 820         .set_channel = cc2520_set_channel,
 821         .set_hw_addr_filt = cc2520_filter,
 822         .set_txpower = cc2520_set_txpower,
 823         .set_promiscuous_mode = cc2520_set_promiscuous_mode,
 824 };
 825
 826 static int cc2520_register(struct cc2520_private *priv)
 827 {
 828         int ret = -ENOMEM;
 829
 830         priv->hw = ieee802154_alloc_hw(sizeof(*priv), &cc2520_ops);
 831         if (!priv->hw)
 832                 goto err_ret;
 833
 834         priv->hw->priv = priv;
 835         priv->hw->parent = &priv->spi->dev;
 836         priv->hw->extra_tx_headroom = 0;
 837         ieee802154_random_extended_addr(&priv->hw->phy->perm_extended_addr);
 838
 839         /* We do support only 2.4 Ghz */
 840         priv->hw->phy->supported.channels[0] = 0x7FFF800;
 841         priv->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AFILT |
 842                           IEEE802154_HW_PROMISCUOUS;
 843
 844         priv->hw->phy->flags = WPAN_PHY_FLAG_TXPOWER;
 845
 846         if (!priv->amplified) {
 847                 priv->hw->phy->supported.tx_powers = cc2520_powers;
 848                 priv->hw->phy->supported.tx_powers_size = ARRAY_SIZE(cc2520_powers);
 849                 priv->hw->phy->transmit_power = priv->hw->phy->supported.tx_powers[4];
 850         } else {
 851                 priv->hw->phy->supported.tx_powers = cc2520_cc2591_powers;
 852                 priv->hw->phy->supported.tx_powers_size = ARRAY_SIZE(cc2520_cc2591_powers);
 853                 priv->hw->phy->transmit_power = priv->hw->phy->supported.tx_powers[0];
 854         }
 855
 856         priv->hw->phy->current_channel = 11;
 857
 858         dev_vdbg(&priv->spi->dev, "registered cc2520\n");
 859         ret = ieee802154_register_hw(priv->hw);
 860         if (ret)
 861                 goto err_free_device;
 862
 863         return 0;
 864
 865 err_free_device:
 866         ieee802154_free_hw(priv->hw);
 867 err_ret:
 868         return ret;
 869 }
 870
 871 static void cc2520_fifop_irqwork(struct work_struct *work)
 872 {
 873         struct cc2520_private *priv
 874                 = container_of(work, struct cc2520_private, fifop_irqwork);
 875
 876         dev_dbg(&priv->spi->dev, "fifop interrupt received\n");
 877
 878         if (gpio_get_value(priv->fifo_pin))
 879                 cc2520_rx(priv);
 880         else
 881                 dev_dbg(&priv->spi->dev, "rxfifo overflow\n");
 882
 883         cc2520_cmd_strobe(priv, CC2520_CMD_SFLUSHRX);
 884         cc2520_cmd_strobe(priv, CC2520_CMD_SFLUSHRX);
 885 }
 886
 887 static irqreturn_t cc2520_fifop_isr(int irq, void *data)
 888 {
 889         struct cc2520_private *priv = data;
 890
 891         schedule_work(&priv->fifop_irqwork);
 892
 893         return IRQ_HANDLED;
 894 }
 895
 896 static irqreturn_t cc2520_sfd_isr(int irq, void *data)
 897 {
 898         struct cc2520_private *priv = data;
 899         unsigned long flags;
 900
 901         spin_lock_irqsave(&priv->lock, flags);
 902         if (priv->is_tx) {
 903                 priv->is_tx = 0;
 904                 spin_unlock_irqrestore(&priv->lock, flags);
 905                 dev_dbg(&priv->spi->dev, "SFD for TX\n");
 906                 complete(&priv->tx_complete);
 907         } else {
 908                 spin_unlock_irqrestore(&priv->lock, flags);
 909                 dev_dbg(&priv->spi->dev, "SFD for RX\n");
 910         }
 911
 912         return IRQ_HANDLED;
 913 }
 914
 915 static int cc2520_get_platform_data(struct spi_device *spi,
 916                                     struct cc2520_platform_data *pdata)
 917 {
 918         struct device_node *np = spi->dev.of_node;
 919         struct cc2520_private *priv = spi_get_drvdata(spi);
 920
 921         if (!np) {
 922                 struct cc2520_platform_data *spi_pdata = spi->dev.platform_data;
 923
 924                 if (!spi_pdata)
 925                         return -ENOENT;
 926                 *pdata = *spi_pdata;
 927                 priv->fifo_pin = pdata->fifo;
 928                 return 0;
 929         }
 930
 931         pdata->fifo = of_get_named_gpio(np, "fifo-gpio", 0);
 932         priv->fifo_pin = pdata->fifo;
 933
 934         pdata->fifop = of_get_named_gpio(np, "fifop-gpio", 0);
 935
 936         pdata->sfd = of_get_named_gpio(np, "sfd-gpio", 0);
 937         pdata->cca = of_get_named_gpio(np, "cca-gpio", 0);
 938         pdata->vreg = of_get_named_gpio(np, "vreg-gpio", 0);
 939         pdata->reset = of_get_named_gpio(np, "reset-gpio", 0);
 940
 941         /* CC2591 front end for CC2520 */
 942         if (of_property_read_bool(np, "amplified"))
 943                 priv->amplified = true;
 944
 945         return 0;
 946 }
 947
 948 static int cc2520_hw_init(struct cc2520_private *priv)
 949 {
 950         u8 status = 0, state = 0xff;
 951         int ret;
 952         int timeout = 100;
 953         struct cc2520_platform_data pdata;
 954
 955         ret = cc2520_get_platform_data(priv->spi, &pdata);
 956         if (ret)
 957                 goto err_ret;
 958
 959         ret = cc2520_read_register(priv, CC2520_FSMSTAT1, &state);
 960         if (ret)
 961                 goto err_ret;
 962
 963         if (state != STATE_IDLE)
 964                 return -EINVAL;
 965
 966         do {
 967                 ret = cc2520_get_status(priv, &status);
 968                 if (ret)
 969                         goto err_ret;
 970
 971                 if (timeout-- <= 0) {
 972                         dev_err(&priv->spi->dev, "oscillator start failed!\n");
 973                         return ret;
 974                 }
 975                 udelay(1);
 976         } while (!(status & CC2520_STATUS_XOSC32M_STABLE));
 977
 978         dev_vdbg(&priv->spi->dev, "oscillator brought up\n");
 979
 980         /* If the CC2520 is connected to a CC2591 amplifier, we must both
 981          * configure GPIOs on the CC2520 to correctly configure the CC2591
 982          * and change a couple settings of the CC2520 to work with the
 983          * amplifier. See section 8 page 17 of TI application note AN065.
 984          * http://www.ti.com/lit/an/swra229a/swra229a.pdf
 985          */
 986         if (priv->amplified) {
 987                 ret = cc2520_write_register(priv, CC2520_AGCCTRL1, 0x16);
 988                 if (ret)
 989                         goto err_ret;
 990
 991                 ret = cc2520_write_register(priv, CC2520_GPIOCTRL0, 0x46);
 992                 if (ret)
 993                         goto err_ret;
 994
 995                 ret = cc2520_write_register(priv, CC2520_GPIOCTRL5, 0x47);
 996                 if (ret)
 997                         goto err_ret;
 998
 999                 ret = cc2520_write_register(priv, CC2520_GPIOPOLARITY, 0x1e);
1000                 if (ret)
1001                         goto err_ret;
1002
1003                 ret = cc2520_write_register(priv, CC2520_TXCTRL, 0xc1);
1004                 if (ret)
1005                         goto err_ret;
1006         } else {
1007                 ret = cc2520_write_register(priv, CC2520_AGCCTRL1, 0x11);
1008                 if (ret)
1009                         goto err_ret;
1010         }
1011
1012         /* Registers default value: section 28.1 in Datasheet */
1013
1014         /* Set the CCA threshold to -50 dBm. This seems to have been copied
1015          * from the TinyOS CC2520 driver and is much higher than the -84 dBm
1016          * threshold suggested in the datasheet.
1017          */
1018         ret = cc2520_write_register(priv, CC2520_CCACTRL0, 0x1A);
1019         if (ret)
1020                 goto err_ret;
1021
1022         ret = cc2520_write_register(priv, CC2520_MDMCTRL0, 0x85);
1023         if (ret)
1024                 goto err_ret;
1025
1026         ret = cc2520_write_register(priv, CC2520_MDMCTRL1, 0x14);
1027         if (ret)
1028                 goto err_ret;
1029
1030         ret = cc2520_write_register(priv, CC2520_RXCTRL, 0x3f);
1031         if (ret)
1032                 goto err_ret;
1033
1034         ret = cc2520_write_register(priv, CC2520_FSCTRL, 0x5a);
1035         if (ret)
1036                 goto err_ret;
1037
1038         ret = cc2520_write_register(priv, CC2520_FSCAL1, 0x2b);
1039         if (ret)
1040                 goto err_ret;
1041
1042         ret = cc2520_write_register(priv, CC2520_ADCTEST0, 0x10);
1043         if (ret)
1044                 goto err_ret;
1045
1046         ret = cc2520_write_register(priv, CC2520_ADCTEST1, 0x0e);
1047         if (ret)
1048                 goto err_ret;
1049
1050         ret = cc2520_write_register(priv, CC2520_ADCTEST2, 0x03);
1051         if (ret)
1052                 goto err_ret;
1053
1054         /* Configure registers correctly for this driver. */
1055         ret = cc2520_write_register(priv, CC2520_FRMCTRL1,
1056                                     FRMCTRL1_SET_RXENMASK_ON_TX |
1057                                     FRMCTRL1_IGNORE_TX_UNDERF);
1058         if (ret)
1059                 goto err_ret;
1060
1061         ret = cc2520_write_register(priv, CC2520_FIFOPCTRL, 127);
1062         if (ret)
1063                 goto err_ret;
1064
1065         return 0;
1066
1067 err_ret:
1068         return ret;
1069 }
1070
1071 static int cc2520_probe(struct spi_device *spi)
1072 {
1073         struct cc2520_private *priv;
1074         struct cc2520_platform_data pdata;
1075         int ret;
1076
1077         priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
1078         if (!priv)
1079                 return -ENOMEM;
1080
1081         spi_set_drvdata(spi, priv);
1082
1083         ret = cc2520_get_platform_data(spi, &pdata);
1084         if (ret < 0) {
1085                 dev_err(&spi->dev, "no platform data\n");
1086                 return -EINVAL;
1087         }
1088
1089         priv->spi = spi;
1090
1091         priv->buf = devm_kzalloc(&spi->dev,
1092                                  SPI_COMMAND_BUFFER, GFP_KERNEL);
1093         if (!priv->buf)
1094                 return -ENOMEM;
1095
1096         mutex_init(&priv->buffer_mutex);
1097         INIT_WORK(&priv->fifop_irqwork, cc2520_fifop_irqwork);
1098         spin_lock_init(&priv->lock);
1099         init_completion(&priv->tx_complete);
1100
1101         /* Assumption that CC2591 is not connected */
1102         priv->amplified = false;
1103
1104         /* Request all the gpio's */
1105         if (!gpio_is_valid(pdata.fifo)) {
1106                 dev_err(&spi->dev, "fifo gpio is not valid\n");
1107                 ret = -EINVAL;
1108                 goto err_hw_init;
1109         }
1110
1111         ret = devm_gpio_request_one(&spi->dev, pdata.fifo,
1112                                     GPIOF_IN, "fifo");
1113         if (ret)
1114                 goto err_hw_init;
1115
1116         if (!gpio_is_valid(pdata.cca)) {
1117                 dev_err(&spi->dev, "cca gpio is not valid\n");
1118                 ret = -EINVAL;
1119                 goto err_hw_init;
1120         }
1121
1122         ret = devm_gpio_request_one(&spi->dev, pdata.cca,
1123                                     GPIOF_IN, "cca");
1124         if (ret)
1125                 goto err_hw_init;
1126
1127         if (!gpio_is_valid(pdata.fifop)) {
1128                 dev_err(&spi->dev, "fifop gpio is not valid\n");
1129                 ret = -EINVAL;
1130                 goto err_hw_init;
1131         }
1132
1133         ret = devm_gpio_request_one(&spi->dev, pdata.fifop,
1134                                     GPIOF_IN, "fifop");
1135         if (ret)
1136                 goto err_hw_init;
1137
1138         if (!gpio_is_valid(pdata.sfd)) {
1139                 dev_err(&spi->dev, "sfd gpio is not valid\n");
1140                 ret = -EINVAL;
1141                 goto err_hw_init;
1142         }
1143
1144         ret = devm_gpio_request_one(&spi->dev, pdata.sfd,
1145                                     GPIOF_IN, "sfd");
1146         if (ret)
1147                 goto err_hw_init;
1148
1149         if (!gpio_is_valid(pdata.reset)) {
1150                 dev_err(&spi->dev, "reset gpio is not valid\n");
1151                 ret = -EINVAL;
1152                 goto err_hw_init;
1153         }
1154
1155         ret = devm_gpio_request_one(&spi->dev, pdata.reset,
1156                                     GPIOF_OUT_INIT_LOW, "reset");
1157         if (ret)
1158                 goto err_hw_init;
1159
1160         if (!gpio_is_valid(pdata.vreg)) {
1161                 dev_err(&spi->dev, "vreg gpio is not valid\n");
1162                 ret = -EINVAL;
1163                 goto err_hw_init;
1164         }
1165
1166         ret = devm_gpio_request_one(&spi->dev, pdata.vreg,
1167                                     GPIOF_OUT_INIT_LOW, "vreg");
1168         if (ret)
1169                 goto err_hw_init;
1170
1171         gpio_set_value(pdata.vreg, HIGH);
1172         usleep_range(100, 150);
1173
1174         gpio_set_value(pdata.reset, HIGH);
1175         usleep_range(200, 250);
1176
1177         ret = cc2520_hw_init(priv);
1178         if (ret)
1179                 goto err_hw_init;
1180
1181         /* Set up fifop interrupt */
1182         ret = devm_request_irq(&spi->dev,
1183                                gpio_to_irq(pdata.fifop),
1184                                cc2520_fifop_isr,
1185                                IRQF_TRIGGER_RISING,
1186                                dev_name(&spi->dev),
1187                                priv);
1188         if (ret) {
1189                 dev_err(&spi->dev, "could not get fifop irq\n");
1190                 goto err_hw_init;
1191         }
1192
1193         /* Set up sfd interrupt */
1194         ret = devm_request_irq(&spi->dev,
1195                                gpio_to_irq(pdata.sfd),
1196                                cc2520_sfd_isr,
1197                                IRQF_TRIGGER_FALLING,
1198                                dev_name(&spi->dev),
1199                                priv);
1200         if (ret) {
1201                 dev_err(&spi->dev, "could not get sfd irq\n");
1202                 goto err_hw_init;
1203         }
1204
1205         ret = cc2520_register(priv);
1206         if (ret)
1207                 goto err_hw_init;
1208
1209         return 0;
1210
1211 err_hw_init:
1212         mutex_destroy(&priv->buffer_mutex);
1213         flush_work(&priv->fifop_irqwork);
1214         return ret;
1215 }
1216
1217 static int cc2520_remove(struct spi_device *spi)
1218 {
1219         struct cc2520_private *priv = spi_get_drvdata(spi);
1220
1221         mutex_destroy(&priv->buffer_mutex);
1222         flush_work(&priv->fifop_irqwork);
1223
1224         ieee802154_unregister_hw(priv->hw);
1225         ieee802154_free_hw(priv->hw);
1226
1227         return 0;
1228 }
1229
1230 static const struct spi_device_id cc2520_ids[] = {
1231         {"cc2520", },
1232         {},
1233 };
1234 MODULE_DEVICE_TABLE(spi, cc2520_ids);
1235
1236 static const struct of_device_id cc2520_of_ids[] = {
1237         {.compatible = "ti,cc2520", },
1238         {},
1239 };
1240 MODULE_DEVICE_TABLE(of, cc2520_of_ids);
1241
1242 /* SPI driver structure */
1243 static struct spi_driver cc2520_driver = {
1244         .driver = {
1245                 .name = "cc2520",
1246                 .of_match_table = of_match_ptr(cc2520_of_ids),
1247         },
1248         .id_table = cc2520_ids,
1249         .probe = cc2520_probe,
1250         .remove = cc2520_remove,
1251 };
1252 module_spi_driver(cc2520_driver);
1253
1254 MODULE_AUTHOR("Varka Bhadram <varkab@cdac.in>");
1255 MODULE_DESCRIPTION("CC2520 Transceiver Driver");
1256 MODULE_LICENSE("GPL v2");