1 // SPDX-License-Identifier: GPL-2.0
3 * MDIO bus driver for the Xilinx Axi Ethernet device
5 * Copyright (c) 2009 Secret Lab Technologies, Ltd.
6 * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
7 * Copyright (c) 2010 - 2011 PetaLogix
8 * Copyright (c) 2019 SED Systems, a division of Calian Ltd.
9 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
12 #include <linux/clk.h>
13 #include <linux/of_address.h>
14 #include <linux/of_mdio.h>
15 #include <linux/jiffies.h>
16 #include <linux/iopoll.h>
18 #include "xilinx_axienet.h"
20 #define DEFAULT_MDIO_FREQ 2500000 /* 2.5 MHz */
21 #define DEFAULT_HOST_CLOCK 150000000 /* 150 MHz */
23 /* Wait till MDIO interface is ready to accept a new transaction.*/
24 static int axienet_mdio_wait_until_ready(struct axienet_local *lp)
28 return readx_poll_timeout(axinet_ior_read_mcr, lp,
29 val, val & XAE_MDIO_MCR_READY_MASK,
33 /* Enable the MDIO MDC. Called prior to a read/write operation */
34 static void axienet_mdio_mdc_enable(struct axienet_local *lp)
36 axienet_iow(lp, XAE_MDIO_MC_OFFSET,
37 ((u32)lp->mii_clk_div | XAE_MDIO_MC_MDIOEN_MASK));
40 /* Disable the MDIO MDC. Called after a read/write operation*/
41 static void axienet_mdio_mdc_disable(struct axienet_local *lp)
45 mc_reg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
46 axienet_iow(lp, XAE_MDIO_MC_OFFSET,
47 (mc_reg & ~XAE_MDIO_MC_MDIOEN_MASK));
51 * axienet_mdio_read - MDIO interface read function
52 * @bus: Pointer to mii bus structure
53 * @phy_id: Address of the PHY device
54 * @reg: PHY register to read
56 * Return: The register contents on success, -ETIMEDOUT on a timeout
58 * Reads the contents of the requested register from the requested PHY
59 * address by first writing the details into MCR register. After a while
60 * the register MRD is read to obtain the PHY register content.
62 static int axienet_mdio_read(struct mii_bus *bus, int phy_id, int reg)
66 struct axienet_local *lp = bus->priv;
68 axienet_mdio_mdc_enable(lp);
70 ret = axienet_mdio_wait_until_ready(lp);
72 axienet_mdio_mdc_disable(lp);
76 axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
77 (((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) &
78 XAE_MDIO_MCR_PHYAD_MASK) |
79 ((reg << XAE_MDIO_MCR_REGAD_SHIFT) &
80 XAE_MDIO_MCR_REGAD_MASK) |
81 XAE_MDIO_MCR_INITIATE_MASK |
82 XAE_MDIO_MCR_OP_READ_MASK));
84 ret = axienet_mdio_wait_until_ready(lp);
86 axienet_mdio_mdc_disable(lp);
90 rc = axienet_ior(lp, XAE_MDIO_MRD_OFFSET) & 0x0000FFFF;
92 dev_dbg(lp->dev, "axienet_mdio_read(phy_id=%i, reg=%x) == %x\n",
95 axienet_mdio_mdc_disable(lp);
100 * axienet_mdio_write - MDIO interface write function
101 * @bus: Pointer to mii bus structure
102 * @phy_id: Address of the PHY device
103 * @reg: PHY register to write to
104 * @val: Value to be written into the register
106 * Return: 0 on success, -ETIMEDOUT on a timeout
108 * Writes the value to the requested register by first writing the value
109 * into MWD register. The MCR register is then appropriately setup
110 * to finish the write operation.
112 static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg,
116 struct axienet_local *lp = bus->priv;
118 dev_dbg(lp->dev, "axienet_mdio_write(phy_id=%i, reg=%x, val=%x)\n",
121 axienet_mdio_mdc_enable(lp);
123 ret = axienet_mdio_wait_until_ready(lp);
125 axienet_mdio_mdc_disable(lp);
129 axienet_iow(lp, XAE_MDIO_MWD_OFFSET, (u32)val);
130 axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
131 (((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) &
132 XAE_MDIO_MCR_PHYAD_MASK) |
133 ((reg << XAE_MDIO_MCR_REGAD_SHIFT) &
134 XAE_MDIO_MCR_REGAD_MASK) |
135 XAE_MDIO_MCR_INITIATE_MASK |
136 XAE_MDIO_MCR_OP_WRITE_MASK));
138 ret = axienet_mdio_wait_until_ready(lp);
140 axienet_mdio_mdc_disable(lp);
143 axienet_mdio_mdc_disable(lp);
148 * axienet_mdio_enable - MDIO hardware setup function
149 * @lp: Pointer to axienet local data structure.
150 * @np: Pointer to mdio device tree node.
152 * Return: 0 on success, -ETIMEDOUT on a timeout, -EOVERFLOW on a clock
155 * Sets up the MDIO interface by initializing the MDIO clock and enabling the
156 * MDIO interface in hardware.
158 static int axienet_mdio_enable(struct axienet_local *lp, struct device_node *np)
160 u32 mdio_freq = DEFAULT_MDIO_FREQ;
168 host_clock = clk_get_rate(lp->axi_clk);
170 struct device_node *np1;
172 /* Legacy fallback: detect CPU clock frequency and use as AXI
173 * bus clock frequency. This only works on certain platforms.
175 np1 = of_find_node_by_name(NULL, "cpu");
177 netdev_warn(lp->ndev, "Could not find CPU device node.\n");
178 host_clock = DEFAULT_HOST_CLOCK;
180 int ret = of_property_read_u32(np1, "clock-frequency",
183 netdev_warn(lp->ndev, "CPU clock-frequency property not found.\n");
184 host_clock = DEFAULT_HOST_CLOCK;
188 netdev_info(lp->ndev, "Setting assumed host clock to %u\n",
193 of_property_read_u32(np, "clock-frequency", &mdio_freq);
194 if (mdio_freq != DEFAULT_MDIO_FREQ)
195 netdev_info(lp->ndev, "Setting non-standard mdio bus frequency to %u Hz\n",
198 /* clk_div can be calculated by deriving it from the equation:
199 * fMDIO = fHOST / ((1 + clk_div) * 2)
201 * Where fMDIO <= 2500000, so we get:
202 * fHOST / ((1 + clk_div) * 2) <= 2500000
205 * 1 / ((1 + clk_div) * 2) <= (2500000 / fHOST)
208 * 1 / (1 + clk_div) <= ((2500000 * 2) / fHOST)
211 * 1 / (1 + clk_div) <= (5000000 / fHOST)
214 * (1 + clk_div) >= (fHOST / 5000000)
217 * clk_div >= (fHOST / 5000000) - 1
219 * fHOST can be read from the flattened device tree as property
220 * "clock-frequency" from the CPU
223 clk_div = (host_clock / (mdio_freq * 2)) - 1;
224 /* If there is any remainder from the division of
225 * fHOST / (mdio_freq * 2), then we need to add
226 * 1 to the clock divisor or we will surely be
227 * above the requested frequency
229 if (host_clock % (mdio_freq * 2))
232 /* Check for overflow of mii_clk_div */
233 if (clk_div & ~XAE_MDIO_MC_CLOCK_DIVIDE_MAX) {
234 netdev_warn(lp->ndev, "MDIO clock divisor overflow\n");
237 lp->mii_clk_div = (u8)clk_div;
240 "Setting MDIO clock divisor to %u/%u Hz host clock.\n",
241 lp->mii_clk_div, host_clock);
243 axienet_mdio_mdc_enable(lp);
245 ret = axienet_mdio_wait_until_ready(lp);
247 axienet_mdio_mdc_disable(lp);
253 * axienet_mdio_setup - MDIO setup function
254 * @lp: Pointer to axienet local data structure.
256 * Return: 0 on success, -ETIMEDOUT on a timeout, -EOVERFLOW on a clock
257 * divisor overflow, -ENOMEM when mdiobus_alloc (to allocate
258 * memory for mii bus structure) fails.
260 * Sets up the MDIO interface by initializing the MDIO clock.
261 * Register the MDIO interface.
263 int axienet_mdio_setup(struct axienet_local *lp)
265 struct device_node *mdio_node;
269 bus = mdiobus_alloc();
273 snprintf(bus->id, MII_BUS_ID_SIZE, "axienet-%.8llx",
274 (unsigned long long)lp->regs_start);
277 bus->name = "Xilinx Axi Ethernet MDIO";
278 bus->read = axienet_mdio_read;
279 bus->write = axienet_mdio_write;
280 bus->parent = lp->dev;
283 mdio_node = of_get_child_by_name(lp->dev->of_node, "mdio");
284 ret = axienet_mdio_enable(lp, mdio_node);
287 ret = of_mdiobus_register(bus, mdio_node);
289 goto unregister_mdio_enabled;
290 of_node_put(mdio_node);
291 axienet_mdio_mdc_disable(lp);
294 unregister_mdio_enabled:
295 axienet_mdio_mdc_disable(lp);
297 of_node_put(mdio_node);
304 * axienet_mdio_teardown - MDIO remove function
305 * @lp: Pointer to axienet local data structure.
307 * Unregisters the MDIO and frees any associate memory for mii bus.
309 void axienet_mdio_teardown(struct axienet_local *lp)
311 mdiobus_unregister(lp->mii_bus);
312 mdiobus_free(lp->mii_bus);