2 * Xilinx Axi Ethernet device driver
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
7 * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
8 * Copyright (c) 2010 - 2011 PetaLogix
9 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
11 * This is a driver for the Xilinx Axi Ethernet which is used in the Virtex6
15 * - Add Axi Fifo support.
16 * - Factor out Axi DMA code into separate driver.
17 * - Test and fix basic multicast filtering.
18 * - Add support for extended multicast filtering.
19 * - Test basic VLAN support.
20 * - Add support for extended VLAN support.
23 #include <linux/delay.h>
24 #include <linux/etherdevice.h>
25 #include <linux/module.h>
26 #include <linux/netdevice.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/of_platform.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_address.h>
32 #include <linux/skbuff.h>
33 #include <linux/spinlock.h>
34 #include <linux/phy.h>
35 #include <linux/mii.h>
36 #include <linux/ethtool.h>
38 #include "xilinx_axienet.h"
40 /* Descriptors defines for Tx and Rx DMA - 2^n for the best performance */
44 /* Must be shorter than length of ethtool_drvinfo.driver field to fit */
45 #define DRIVER_NAME "xaxienet"
46 #define DRIVER_DESCRIPTION "Xilinx Axi Ethernet driver"
47 #define DRIVER_VERSION "1.00a"
49 #define AXIENET_REGS_N 32
51 /* Match table for of_platform binding */
52 static const struct of_device_id axienet_of_match[] = {
53 { .compatible = "xlnx,axi-ethernet-1.00.a", },
54 { .compatible = "xlnx,axi-ethernet-1.01.a", },
55 { .compatible = "xlnx,axi-ethernet-2.01.a", },
59 MODULE_DEVICE_TABLE(of, axienet_of_match);
61 /* Option table for setting up Axi Ethernet hardware options */
62 static struct axienet_option axienet_options[] = {
63 /* Turn on jumbo packet support for both Rx and Tx */
65 .opt = XAE_OPTION_JUMBO,
67 .m_or = XAE_TC_JUM_MASK,
69 .opt = XAE_OPTION_JUMBO,
70 .reg = XAE_RCW1_OFFSET,
71 .m_or = XAE_RCW1_JUM_MASK,
72 }, { /* Turn on VLAN packet support for both Rx and Tx */
73 .opt = XAE_OPTION_VLAN,
75 .m_or = XAE_TC_VLAN_MASK,
77 .opt = XAE_OPTION_VLAN,
78 .reg = XAE_RCW1_OFFSET,
79 .m_or = XAE_RCW1_VLAN_MASK,
80 }, { /* Turn on FCS stripping on receive packets */
81 .opt = XAE_OPTION_FCS_STRIP,
82 .reg = XAE_RCW1_OFFSET,
83 .m_or = XAE_RCW1_FCS_MASK,
84 }, { /* Turn on FCS insertion on transmit packets */
85 .opt = XAE_OPTION_FCS_INSERT,
87 .m_or = XAE_TC_FCS_MASK,
88 }, { /* Turn off length/type field checking on receive packets */
89 .opt = XAE_OPTION_LENTYPE_ERR,
90 .reg = XAE_RCW1_OFFSET,
91 .m_or = XAE_RCW1_LT_DIS_MASK,
92 }, { /* Turn on Rx flow control */
93 .opt = XAE_OPTION_FLOW_CONTROL,
94 .reg = XAE_FCC_OFFSET,
95 .m_or = XAE_FCC_FCRX_MASK,
96 }, { /* Turn on Tx flow control */
97 .opt = XAE_OPTION_FLOW_CONTROL,
98 .reg = XAE_FCC_OFFSET,
99 .m_or = XAE_FCC_FCTX_MASK,
100 }, { /* Turn on promiscuous frame filtering */
101 .opt = XAE_OPTION_PROMISC,
102 .reg = XAE_FMI_OFFSET,
103 .m_or = XAE_FMI_PM_MASK,
104 }, { /* Enable transmitter */
105 .opt = XAE_OPTION_TXEN,
106 .reg = XAE_TC_OFFSET,
107 .m_or = XAE_TC_TX_MASK,
108 }, { /* Enable receiver */
109 .opt = XAE_OPTION_RXEN,
110 .reg = XAE_RCW1_OFFSET,
111 .m_or = XAE_RCW1_RX_MASK,
117 * axienet_dma_in32 - Memory mapped Axi DMA register read
118 * @lp: Pointer to axienet local structure
119 * @reg: Address offset from the base address of the Axi DMA core
121 * Return: The contents of the Axi DMA register
123 * This function returns the contents of the corresponding Axi DMA register.
125 static inline u32 axienet_dma_in32(struct axienet_local *lp, off_t reg)
127 return in_be32(lp->dma_regs + reg);
131 * axienet_dma_out32 - Memory mapped Axi DMA register write.
132 * @lp: Pointer to axienet local structure
133 * @reg: Address offset from the base address of the Axi DMA core
134 * @value: Value to be written into the Axi DMA register
136 * This function writes the desired value into the corresponding Axi DMA
139 static inline void axienet_dma_out32(struct axienet_local *lp,
140 off_t reg, u32 value)
142 out_be32((lp->dma_regs + reg), value);
146 * axienet_dma_bd_release - Release buffer descriptor rings
147 * @ndev: Pointer to the net_device structure
149 * This function is used to release the descriptors allocated in
150 * axienet_dma_bd_init. axienet_dma_bd_release is called when Axi Ethernet
151 * driver stop api is called.
153 static void axienet_dma_bd_release(struct net_device *ndev)
156 struct axienet_local *lp = netdev_priv(ndev);
158 for (i = 0; i < RX_BD_NUM; i++) {
159 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
160 lp->max_frm_size, DMA_FROM_DEVICE);
161 dev_kfree_skb((struct sk_buff *)
162 (lp->rx_bd_v[i].sw_id_offset));
166 dma_free_coherent(ndev->dev.parent,
167 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
172 dma_free_coherent(ndev->dev.parent,
173 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
180 * axienet_dma_bd_init - Setup buffer descriptor rings for Axi DMA
181 * @ndev: Pointer to the net_device structure
183 * Return: 0, on success -ENOMEM, on failure
185 * This function is called to initialize the Rx and Tx DMA descriptor
186 * rings. This initializes the descriptors with required default values
187 * and is called when Axi Ethernet driver reset is called.
189 static int axienet_dma_bd_init(struct net_device *ndev)
194 struct axienet_local *lp = netdev_priv(ndev);
196 /* Reset the indexes which are used for accessing the BDs */
201 /* Allocate the Tx and Rx buffer descriptors. */
202 lp->tx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
203 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
204 &lp->tx_bd_p, GFP_KERNEL);
208 lp->rx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
209 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
210 &lp->rx_bd_p, GFP_KERNEL);
214 for (i = 0; i < TX_BD_NUM; i++) {
215 lp->tx_bd_v[i].next = lp->tx_bd_p +
216 sizeof(*lp->tx_bd_v) *
217 ((i + 1) % TX_BD_NUM);
220 for (i = 0; i < RX_BD_NUM; i++) {
221 lp->rx_bd_v[i].next = lp->rx_bd_p +
222 sizeof(*lp->rx_bd_v) *
223 ((i + 1) % RX_BD_NUM);
225 skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size);
229 lp->rx_bd_v[i].sw_id_offset = (u32) skb;
230 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
234 lp->rx_bd_v[i].cntrl = lp->max_frm_size;
237 /* Start updating the Rx channel control register */
238 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
239 /* Update the interrupt coalesce count */
240 cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
241 ((lp->coalesce_count_rx) << XAXIDMA_COALESCE_SHIFT));
242 /* Update the delay timer count */
243 cr = ((cr & ~XAXIDMA_DELAY_MASK) |
244 (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
245 /* Enable coalesce, delay timer and error interrupts */
246 cr |= XAXIDMA_IRQ_ALL_MASK;
247 /* Write to the Rx channel control register */
248 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
250 /* Start updating the Tx channel control register */
251 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
252 /* Update the interrupt coalesce count */
253 cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
254 ((lp->coalesce_count_tx) << XAXIDMA_COALESCE_SHIFT));
255 /* Update the delay timer count */
256 cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
257 (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
258 /* Enable coalesce, delay timer and error interrupts */
259 cr |= XAXIDMA_IRQ_ALL_MASK;
260 /* Write to the Tx channel control register */
261 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
263 /* Populate the tail pointer and bring the Rx Axi DMA engine out of
264 * halted state. This will make the Rx side ready for reception.
266 axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
267 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
268 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
269 cr | XAXIDMA_CR_RUNSTOP_MASK);
270 axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
271 (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
273 /* Write to the RS (Run-stop) bit in the Tx channel control register.
274 * Tx channel is now ready to run. But only after we write to the
275 * tail pointer register that the Tx channel will start transmitting.
277 axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
278 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
279 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
280 cr | XAXIDMA_CR_RUNSTOP_MASK);
282 /* Wait for PhyRstCmplt bit to be set, indicating the PHY reset has finished */
283 ret = read_poll_timeout(axienet_ior, value,
284 value & XAE_INT_PHYRSTCMPLT_MASK,
285 DELAY_OF_ONE_MILLISEC, 50000, false, lp,
288 dev_err(lp->dev, "%s: timeout waiting for PhyRstCmplt\n", __func__);
294 axienet_dma_bd_release(ndev);
299 * axienet_set_mac_address - Write the MAC address
300 * @ndev: Pointer to the net_device structure
301 * @address: 6 byte Address to be written as MAC address
303 * This function is called to initialize the MAC address of the Axi Ethernet
304 * core. It writes to the UAW0 and UAW1 registers of the core.
306 static void axienet_set_mac_address(struct net_device *ndev,
309 struct axienet_local *lp = netdev_priv(ndev);
312 memcpy(ndev->dev_addr, address, ETH_ALEN);
313 if (!is_valid_ether_addr(ndev->dev_addr))
314 eth_hw_addr_random(ndev);
316 /* Set up unicast MAC address filter set its mac address */
317 axienet_iow(lp, XAE_UAW0_OFFSET,
318 (ndev->dev_addr[0]) |
319 (ndev->dev_addr[1] << 8) |
320 (ndev->dev_addr[2] << 16) |
321 (ndev->dev_addr[3] << 24));
322 axienet_iow(lp, XAE_UAW1_OFFSET,
323 (((axienet_ior(lp, XAE_UAW1_OFFSET)) &
324 ~XAE_UAW1_UNICASTADDR_MASK) |
326 (ndev->dev_addr[5] << 8))));
330 * netdev_set_mac_address - Write the MAC address (from outside the driver)
331 * @ndev: Pointer to the net_device structure
332 * @p: 6 byte Address to be written as MAC address
334 * Return: 0 for all conditions. Presently, there is no failure case.
336 * This function is called to initialize the MAC address of the Axi Ethernet
337 * core. It calls the core specific axienet_set_mac_address. This is the
338 * function that goes into net_device_ops structure entry ndo_set_mac_address.
340 static int netdev_set_mac_address(struct net_device *ndev, void *p)
342 struct sockaddr *addr = p;
343 axienet_set_mac_address(ndev, addr->sa_data);
348 * axienet_set_multicast_list - Prepare the multicast table
349 * @ndev: Pointer to the net_device structure
351 * This function is called to initialize the multicast table during
352 * initialization. The Axi Ethernet basic multicast support has a four-entry
353 * multicast table which is initialized here. Additionally this function
354 * goes into the net_device_ops structure entry ndo_set_multicast_list. This
355 * means whenever the multicast table entries need to be updated this
356 * function gets called.
358 static void axienet_set_multicast_list(struct net_device *ndev)
361 u32 reg, af0reg, af1reg;
362 struct axienet_local *lp = netdev_priv(ndev);
364 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
365 netdev_mc_count(ndev) > XAE_MULTICAST_CAM_TABLE_NUM) {
366 /* We must make the kernel realize we had to move into
367 * promiscuous mode. If it was a promiscuous mode request
368 * the flag is already set. If not we set it.
370 ndev->flags |= IFF_PROMISC;
371 reg = axienet_ior(lp, XAE_FMI_OFFSET);
372 reg |= XAE_FMI_PM_MASK;
373 axienet_iow(lp, XAE_FMI_OFFSET, reg);
374 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
375 } else if (!netdev_mc_empty(ndev)) {
376 struct netdev_hw_addr *ha;
379 netdev_for_each_mc_addr(ha, ndev) {
380 if (i >= XAE_MULTICAST_CAM_TABLE_NUM)
383 af0reg = (ha->addr[0]);
384 af0reg |= (ha->addr[1] << 8);
385 af0reg |= (ha->addr[2] << 16);
386 af0reg |= (ha->addr[3] << 24);
388 af1reg = (ha->addr[4]);
389 af1reg |= (ha->addr[5] << 8);
391 reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
394 axienet_iow(lp, XAE_FMI_OFFSET, reg);
395 axienet_iow(lp, XAE_AF0_OFFSET, af0reg);
396 axienet_iow(lp, XAE_AF1_OFFSET, af1reg);
400 reg = axienet_ior(lp, XAE_FMI_OFFSET);
401 reg &= ~XAE_FMI_PM_MASK;
403 axienet_iow(lp, XAE_FMI_OFFSET, reg);
405 for (i = 0; i < XAE_MULTICAST_CAM_TABLE_NUM; i++) {
406 reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
409 axienet_iow(lp, XAE_FMI_OFFSET, reg);
410 axienet_iow(lp, XAE_AF0_OFFSET, 0);
411 axienet_iow(lp, XAE_AF1_OFFSET, 0);
414 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
419 * axienet_setoptions - Set an Axi Ethernet option
420 * @ndev: Pointer to the net_device structure
421 * @options: Option to be enabled/disabled
423 * The Axi Ethernet core has multiple features which can be selectively turned
424 * on or off. The typical options could be jumbo frame option, basic VLAN
425 * option, promiscuous mode option etc. This function is used to set or clear
426 * these options in the Axi Ethernet hardware. This is done through
427 * axienet_option structure .
429 static void axienet_setoptions(struct net_device *ndev, u32 options)
432 struct axienet_local *lp = netdev_priv(ndev);
433 struct axienet_option *tp = &axienet_options[0];
436 reg = ((axienet_ior(lp, tp->reg)) & ~(tp->m_or));
437 if (options & tp->opt)
439 axienet_iow(lp, tp->reg, reg);
443 lp->options |= options;
446 static void __axienet_device_reset(struct axienet_local *lp, off_t offset)
449 /* Reset Axi DMA. This would reset Axi Ethernet core as well. The reset
450 * process of Axi DMA takes a while to complete as all pending
451 * commands/transfers will be flushed or completed during this
454 axienet_dma_out32(lp, offset, XAXIDMA_CR_RESET_MASK);
455 timeout = DELAY_OF_ONE_MILLISEC;
456 while (axienet_dma_in32(lp, offset) & XAXIDMA_CR_RESET_MASK) {
458 if (--timeout == 0) {
459 netdev_err(lp->ndev, "%s: DMA reset timeout!\n",
467 * axienet_device_reset - Reset and initialize the Axi Ethernet hardware.
468 * @ndev: Pointer to the net_device structure
470 * This function is called to reset and initialize the Axi Ethernet core. This
471 * is typically called during initialization. It does a reset of the Axi DMA
472 * Rx/Tx channels and initializes the Axi DMA BDs. Since Axi DMA reset lines
473 * areconnected to Axi Ethernet reset lines, this in turn resets the Axi
474 * Ethernet core. No separate hardware reset is done for the Axi Ethernet
477 static void axienet_device_reset(struct net_device *ndev)
480 struct axienet_local *lp = netdev_priv(ndev);
482 __axienet_device_reset(lp, XAXIDMA_TX_CR_OFFSET);
483 __axienet_device_reset(lp, XAXIDMA_RX_CR_OFFSET);
485 lp->max_frm_size = XAE_MAX_VLAN_FRAME_SIZE;
486 lp->options |= XAE_OPTION_VLAN;
487 lp->options &= (~XAE_OPTION_JUMBO);
489 if ((ndev->mtu > XAE_MTU) &&
490 (ndev->mtu <= XAE_JUMBO_MTU)) {
491 lp->max_frm_size = ndev->mtu + VLAN_ETH_HLEN +
494 if (lp->max_frm_size <= lp->rxmem)
495 lp->options |= XAE_OPTION_JUMBO;
498 if (axienet_dma_bd_init(ndev)) {
499 netdev_err(ndev, "%s: descriptor allocation failed\n",
503 axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);
504 axienet_status &= ~XAE_RCW1_RX_MASK;
505 axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
507 axienet_status = axienet_ior(lp, XAE_IP_OFFSET);
508 if (axienet_status & XAE_INT_RXRJECT_MASK)
509 axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
511 axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
513 /* Sync default options with HW but leave receiver and
514 * transmitter disabled.
516 axienet_setoptions(ndev, lp->options &
517 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
518 axienet_set_mac_address(ndev, NULL);
519 axienet_set_multicast_list(ndev);
520 axienet_setoptions(ndev, lp->options);
522 netif_trans_update(ndev);
526 * axienet_adjust_link - Adjust the PHY link speed/duplex.
527 * @ndev: Pointer to the net_device structure
529 * This function is called to change the speed and duplex setting after
530 * auto negotiation is done by the PHY. This is the function that gets
531 * registered with the PHY interface through the "of_phy_connect" call.
533 static void axienet_adjust_link(struct net_device *ndev)
538 struct axienet_local *lp = netdev_priv(ndev);
539 struct phy_device *phy = ndev->phydev;
541 link_state = phy->speed | (phy->duplex << 1) | phy->link;
542 if (lp->last_link != link_state) {
543 if ((phy->speed == SPEED_10) || (phy->speed == SPEED_100)) {
544 if (lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX)
547 if ((phy->speed == SPEED_1000) &&
548 (lp->phy_mode == PHY_INTERFACE_MODE_MII))
553 emmc_reg = axienet_ior(lp, XAE_EMMC_OFFSET);
554 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
556 switch (phy->speed) {
558 emmc_reg |= XAE_EMMC_LINKSPD_1000;
561 emmc_reg |= XAE_EMMC_LINKSPD_100;
564 emmc_reg |= XAE_EMMC_LINKSPD_10;
567 dev_err(&ndev->dev, "Speed other than 10, 100 "
568 "or 1Gbps is not supported\n");
572 axienet_iow(lp, XAE_EMMC_OFFSET, emmc_reg);
573 lp->last_link = link_state;
574 phy_print_status(phy);
577 "Error setting Axi Ethernet mac speed\n");
583 * axienet_start_xmit_done - Invoked once a transmit is completed by the
584 * Axi DMA Tx channel.
585 * @ndev: Pointer to the net_device structure
587 * This function is invoked from the Axi DMA Tx isr to notify the completion
588 * of transmit operation. It clears fields in the corresponding Tx BDs and
589 * unmaps the corresponding buffer so that CPU can regain ownership of the
590 * buffer. It finally invokes "netif_wake_queue" to restart transmission if
593 static void axienet_start_xmit_done(struct net_device *ndev)
597 struct axienet_local *lp = netdev_priv(ndev);
598 struct axidma_bd *cur_p;
599 unsigned int status = 0;
601 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
602 status = cur_p->status;
603 while (status & XAXIDMA_BD_STS_COMPLETE_MASK) {
604 dma_unmap_single(ndev->dev.parent, cur_p->phys,
605 (cur_p->cntrl & XAXIDMA_BD_CTRL_LENGTH_MASK),
608 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
616 size += status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
620 lp->tx_bd_ci %= TX_BD_NUM;
621 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
622 status = cur_p->status;
625 ndev->stats.tx_packets += packets;
626 ndev->stats.tx_bytes += size;
628 /* Matches barrier in axienet_start_xmit */
631 netif_wake_queue(ndev);
635 * axienet_check_tx_bd_space - Checks if a BD/group of BDs are currently busy
636 * @lp: Pointer to the axienet_local structure
637 * @num_frag: The number of BDs to check for
639 * Return: 0, on success
640 * NETDEV_TX_BUSY, if any of the descriptors are not free
642 * This function is invoked before BDs are allocated and transmission starts.
643 * This function returns 0 if a BD or group of BDs can be allocated for
644 * transmission. If the BD or any of the BDs are not free the function
645 * returns a busy status. This is invoked from axienet_start_xmit.
647 static inline int axienet_check_tx_bd_space(struct axienet_local *lp,
650 struct axidma_bd *cur_p;
651 cur_p = &lp->tx_bd_v[(lp->tx_bd_tail + num_frag) % TX_BD_NUM];
652 if (cur_p->status & XAXIDMA_BD_STS_ALL_MASK)
653 return NETDEV_TX_BUSY;
658 * axienet_start_xmit - Starts the transmission.
659 * @skb: sk_buff pointer that contains data to be Txed.
660 * @ndev: Pointer to net_device structure.
662 * Return: NETDEV_TX_OK, on success
663 * NETDEV_TX_BUSY, if any of the descriptors are not free
665 * This function is invoked from upper layers to initiate transmission. The
666 * function uses the next available free BDs and populates their fields to
667 * start the transmission. Additionally if checksum offloading is supported,
668 * it populates AXI Stream Control fields with appropriate values.
671 axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
679 struct axienet_local *lp = netdev_priv(ndev);
680 struct axidma_bd *cur_p;
682 num_frag = skb_shinfo(skb)->nr_frags;
683 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
685 if (axienet_check_tx_bd_space(lp, num_frag + 1)) {
686 if (netif_queue_stopped(ndev))
687 return NETDEV_TX_BUSY;
689 netif_stop_queue(ndev);
691 /* Matches barrier in axienet_start_xmit_done */
694 /* Space might have just been freed - check again */
695 if (axienet_check_tx_bd_space(lp, num_frag + 1))
696 return NETDEV_TX_BUSY;
698 netif_wake_queue(ndev);
701 if (skb->ip_summed == CHECKSUM_PARTIAL) {
702 if (lp->features & XAE_FEATURE_FULL_TX_CSUM) {
703 /* Tx Full Checksum Offload Enabled */
705 } else if (lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) {
706 csum_start_off = skb_transport_offset(skb);
707 csum_index_off = csum_start_off + skb->csum_offset;
708 /* Tx Partial Checksum Offload Enabled */
710 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
712 } else if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
713 cur_p->app0 |= 2; /* Tx Full Checksum Offload Enabled */
716 cur_p->cntrl = skb_headlen(skb) | XAXIDMA_BD_CTRL_TXSOF_MASK;
717 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data,
718 skb_headlen(skb), DMA_TO_DEVICE);
720 for (ii = 0; ii < num_frag; ii++) {
722 lp->tx_bd_tail %= TX_BD_NUM;
723 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
724 frag = &skb_shinfo(skb)->frags[ii];
725 cur_p->phys = dma_map_single(ndev->dev.parent,
726 skb_frag_address(frag),
729 cur_p->cntrl = skb_frag_size(frag);
732 cur_p->cntrl |= XAXIDMA_BD_CTRL_TXEOF_MASK;
733 cur_p->app4 = (unsigned long)skb;
735 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
736 /* Start the transfer */
737 axienet_dma_out32(lp, XAXIDMA_TX_TDESC_OFFSET, tail_p);
739 lp->tx_bd_tail %= TX_BD_NUM;
745 * axienet_recv - Is called from Axi DMA Rx Isr to complete the received
747 * @ndev: Pointer to net_device structure.
749 * This function is invoked from the Axi DMA Rx isr to process the Rx BDs. It
750 * does minimal processing and invokes "netif_rx" to complete further
753 static void axienet_recv(struct net_device *ndev)
759 dma_addr_t tail_p = 0;
760 struct axienet_local *lp = netdev_priv(ndev);
761 struct sk_buff *skb, *new_skb;
762 struct axidma_bd *cur_p;
764 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
766 while ((cur_p->status & XAXIDMA_BD_STS_COMPLETE_MASK)) {
767 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
768 skb = (struct sk_buff *) (cur_p->sw_id_offset);
769 length = cur_p->app4 & 0x0000FFFF;
771 dma_unmap_single(ndev->dev.parent, cur_p->phys,
775 skb_put(skb, length);
776 skb->protocol = eth_type_trans(skb, ndev);
777 /*skb_checksum_none_assert(skb);*/
778 skb->ip_summed = CHECKSUM_NONE;
780 /* if we're doing Rx csum offload, set it up */
781 if (lp->features & XAE_FEATURE_FULL_RX_CSUM) {
782 csumstatus = (cur_p->app2 &
783 XAE_FULL_CSUM_STATUS_MASK) >> 3;
784 if ((csumstatus == XAE_IP_TCP_CSUM_VALIDATED) ||
785 (csumstatus == XAE_IP_UDP_CSUM_VALIDATED)) {
786 skb->ip_summed = CHECKSUM_UNNECESSARY;
788 } else if ((lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) != 0 &&
789 skb->protocol == htons(ETH_P_IP) &&
791 skb->csum = be32_to_cpu(cur_p->app3 & 0xFFFF);
792 skb->ip_summed = CHECKSUM_COMPLETE;
800 new_skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size);
804 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
807 cur_p->cntrl = lp->max_frm_size;
809 cur_p->sw_id_offset = (u32) new_skb;
812 lp->rx_bd_ci %= RX_BD_NUM;
813 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
816 ndev->stats.rx_packets += packets;
817 ndev->stats.rx_bytes += size;
820 axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, tail_p);
824 * axienet_tx_irq - Tx Done Isr.
826 * @_ndev: net_device pointer
828 * Return: IRQ_HANDLED for all cases.
830 * This is the Axi DMA Tx done Isr. It invokes "axienet_start_xmit_done"
831 * to complete the BD processing.
833 static irqreturn_t axienet_tx_irq(int irq, void *_ndev)
837 struct net_device *ndev = _ndev;
838 struct axienet_local *lp = netdev_priv(ndev);
840 status = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);
841 if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
842 axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status);
843 axienet_start_xmit_done(lp->ndev);
846 if (!(status & XAXIDMA_IRQ_ALL_MASK))
847 dev_err(&ndev->dev, "No interrupts asserted in Tx path\n");
848 if (status & XAXIDMA_IRQ_ERROR_MASK) {
849 dev_err(&ndev->dev, "DMA Tx error 0x%x\n", status);
850 dev_err(&ndev->dev, "Current BD is at: 0x%x\n",
851 (lp->tx_bd_v[lp->tx_bd_ci]).phys);
853 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
854 /* Disable coalesce, delay timer and error interrupts */
855 cr &= (~XAXIDMA_IRQ_ALL_MASK);
856 /* Write to the Tx channel control register */
857 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
859 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
860 /* Disable coalesce, delay timer and error interrupts */
861 cr &= (~XAXIDMA_IRQ_ALL_MASK);
862 /* Write to the Rx channel control register */
863 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
865 tasklet_schedule(&lp->dma_err_tasklet);
866 axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status);
873 * axienet_rx_irq - Rx Isr.
875 * @_ndev: net_device pointer
877 * Return: IRQ_HANDLED for all cases.
879 * This is the Axi DMA Rx Isr. It invokes "axienet_recv" to complete the BD
882 static irqreturn_t axienet_rx_irq(int irq, void *_ndev)
886 struct net_device *ndev = _ndev;
887 struct axienet_local *lp = netdev_priv(ndev);
889 status = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);
890 if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
891 axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status);
892 axienet_recv(lp->ndev);
895 if (!(status & XAXIDMA_IRQ_ALL_MASK))
896 dev_err(&ndev->dev, "No interrupts asserted in Rx path\n");
897 if (status & XAXIDMA_IRQ_ERROR_MASK) {
898 dev_err(&ndev->dev, "DMA Rx error 0x%x\n", status);
899 dev_err(&ndev->dev, "Current BD is at: 0x%x\n",
900 (lp->rx_bd_v[lp->rx_bd_ci]).phys);
902 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
903 /* Disable coalesce, delay timer and error interrupts */
904 cr &= (~XAXIDMA_IRQ_ALL_MASK);
905 /* Finally write to the Tx channel control register */
906 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
908 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
909 /* Disable coalesce, delay timer and error interrupts */
910 cr &= (~XAXIDMA_IRQ_ALL_MASK);
911 /* write to the Rx channel control register */
912 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
914 tasklet_schedule(&lp->dma_err_tasklet);
915 axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status);
921 static void axienet_dma_err_handler(unsigned long data);
924 * axienet_open - Driver open routine.
925 * @ndev: Pointer to net_device structure
927 * Return: 0, on success.
928 * non-zero error value on failure
930 * This is the driver open routine. It calls phy_start to start the PHY device.
931 * It also allocates interrupt service routines, enables the interrupt lines
932 * and ISR handling. Axi Ethernet core is reset through Axi DMA core. Buffer
933 * descriptors are initialized.
935 static int axienet_open(struct net_device *ndev)
938 struct axienet_local *lp = netdev_priv(ndev);
939 struct phy_device *phydev = NULL;
941 dev_dbg(&ndev->dev, "axienet_open()\n");
943 mdio_mcreg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
944 ret = axienet_mdio_wait_until_ready(lp);
947 /* Disable the MDIO interface till Axi Ethernet Reset is completed.
948 * When we do an Axi Ethernet reset, it resets the complete core
949 * including the MDIO. If MDIO is not disabled when the reset
950 * process is started, MDIO will be broken afterwards.
952 axienet_iow(lp, XAE_MDIO_MC_OFFSET,
953 (mdio_mcreg & (~XAE_MDIO_MC_MDIOEN_MASK)));
954 axienet_device_reset(ndev);
955 /* Enable the MDIO */
956 axienet_iow(lp, XAE_MDIO_MC_OFFSET, mdio_mcreg);
957 ret = axienet_mdio_wait_until_ready(lp);
962 phydev = of_phy_connect(lp->ndev, lp->phy_node,
963 axienet_adjust_link, 0, lp->phy_mode);
966 dev_err(lp->dev, "of_phy_connect() failed\n");
971 /* Enable tasklets for Axi DMA error handling */
972 tasklet_init(&lp->dma_err_tasklet, axienet_dma_err_handler,
975 /* Enable interrupts for Axi DMA Tx */
976 ret = request_irq(lp->tx_irq, axienet_tx_irq, 0, ndev->name, ndev);
979 /* Enable interrupts for Axi DMA Rx */
980 ret = request_irq(lp->rx_irq, axienet_rx_irq, 0, ndev->name, ndev);
987 free_irq(lp->tx_irq, ndev);
990 phy_disconnect(phydev);
991 tasklet_kill(&lp->dma_err_tasklet);
992 dev_err(lp->dev, "request_irq() failed\n");
997 * axienet_stop - Driver stop routine.
998 * @ndev: Pointer to net_device structure
1000 * Return: 0, on success.
1002 * This is the driver stop routine. It calls phy_disconnect to stop the PHY
1003 * device. It also removes the interrupt handlers and disables the interrupts.
1004 * The Axi DMA Tx/Rx BDs are released.
1006 static int axienet_stop(struct net_device *ndev)
1009 struct axienet_local *lp = netdev_priv(ndev);
1011 dev_dbg(&ndev->dev, "axienet_close()\n");
1013 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1014 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
1015 cr & (~XAXIDMA_CR_RUNSTOP_MASK));
1016 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1017 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
1018 cr & (~XAXIDMA_CR_RUNSTOP_MASK));
1019 axienet_setoptions(ndev, lp->options &
1020 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1022 tasklet_kill(&lp->dma_err_tasklet);
1024 free_irq(lp->tx_irq, ndev);
1025 free_irq(lp->rx_irq, ndev);
1028 phy_disconnect(ndev->phydev);
1030 axienet_dma_bd_release(ndev);
1035 * axienet_change_mtu - Driver change mtu routine.
1036 * @ndev: Pointer to net_device structure
1037 * @new_mtu: New mtu value to be applied
1039 * Return: Always returns 0 (success).
1041 * This is the change mtu driver routine. It checks if the Axi Ethernet
1042 * hardware supports jumbo frames before changing the mtu. This can be
1043 * called only when the device is not up.
1045 static int axienet_change_mtu(struct net_device *ndev, int new_mtu)
1047 struct axienet_local *lp = netdev_priv(ndev);
1049 if (netif_running(ndev))
1052 if ((new_mtu + VLAN_ETH_HLEN +
1053 XAE_TRL_SIZE) > lp->rxmem)
1056 ndev->mtu = new_mtu;
1061 #ifdef CONFIG_NET_POLL_CONTROLLER
1063 * axienet_poll_controller - Axi Ethernet poll mechanism.
1064 * @ndev: Pointer to net_device structure
1066 * This implements Rx/Tx ISR poll mechanisms. The interrupts are disabled prior
1067 * to polling the ISRs and are enabled back after the polling is done.
1069 static void axienet_poll_controller(struct net_device *ndev)
1071 struct axienet_local *lp = netdev_priv(ndev);
1072 disable_irq(lp->tx_irq);
1073 disable_irq(lp->rx_irq);
1074 axienet_rx_irq(lp->tx_irq, ndev);
1075 axienet_tx_irq(lp->rx_irq, ndev);
1076 enable_irq(lp->tx_irq);
1077 enable_irq(lp->rx_irq);
1081 static const struct net_device_ops axienet_netdev_ops = {
1082 .ndo_open = axienet_open,
1083 .ndo_stop = axienet_stop,
1084 .ndo_start_xmit = axienet_start_xmit,
1085 .ndo_change_mtu = axienet_change_mtu,
1086 .ndo_set_mac_address = netdev_set_mac_address,
1087 .ndo_validate_addr = eth_validate_addr,
1088 .ndo_set_rx_mode = axienet_set_multicast_list,
1089 #ifdef CONFIG_NET_POLL_CONTROLLER
1090 .ndo_poll_controller = axienet_poll_controller,
1095 * axienet_ethtools_get_drvinfo - Get various Axi Ethernet driver information.
1096 * @ndev: Pointer to net_device structure
1097 * @ed: Pointer to ethtool_drvinfo structure
1099 * This implements ethtool command for getting the driver information.
1100 * Issue "ethtool -i ethX" under linux prompt to execute this function.
1102 static void axienet_ethtools_get_drvinfo(struct net_device *ndev,
1103 struct ethtool_drvinfo *ed)
1105 strlcpy(ed->driver, DRIVER_NAME, sizeof(ed->driver));
1106 strlcpy(ed->version, DRIVER_VERSION, sizeof(ed->version));
1110 * axienet_ethtools_get_regs_len - Get the total regs length present in the
1112 * @ndev: Pointer to net_device structure
1114 * This implements ethtool command for getting the total register length
1117 * Return: the total regs length
1119 static int axienet_ethtools_get_regs_len(struct net_device *ndev)
1121 return sizeof(u32) * AXIENET_REGS_N;
1125 * axienet_ethtools_get_regs - Dump the contents of all registers present
1126 * in AxiEthernet core.
1127 * @ndev: Pointer to net_device structure
1128 * @regs: Pointer to ethtool_regs structure
1129 * @ret: Void pointer used to return the contents of the registers.
1131 * This implements ethtool command for getting the Axi Ethernet register dump.
1132 * Issue "ethtool -d ethX" to execute this function.
1134 static void axienet_ethtools_get_regs(struct net_device *ndev,
1135 struct ethtool_regs *regs, void *ret)
1137 u32 *data = (u32 *) ret;
1138 size_t len = sizeof(u32) * AXIENET_REGS_N;
1139 struct axienet_local *lp = netdev_priv(ndev);
1144 memset(data, 0, len);
1145 data[0] = axienet_ior(lp, XAE_RAF_OFFSET);
1146 data[1] = axienet_ior(lp, XAE_TPF_OFFSET);
1147 data[2] = axienet_ior(lp, XAE_IFGP_OFFSET);
1148 data[3] = axienet_ior(lp, XAE_IS_OFFSET);
1149 data[4] = axienet_ior(lp, XAE_IP_OFFSET);
1150 data[5] = axienet_ior(lp, XAE_IE_OFFSET);
1151 data[6] = axienet_ior(lp, XAE_TTAG_OFFSET);
1152 data[7] = axienet_ior(lp, XAE_RTAG_OFFSET);
1153 data[8] = axienet_ior(lp, XAE_UAWL_OFFSET);
1154 data[9] = axienet_ior(lp, XAE_UAWU_OFFSET);
1155 data[10] = axienet_ior(lp, XAE_TPID0_OFFSET);
1156 data[11] = axienet_ior(lp, XAE_TPID1_OFFSET);
1157 data[12] = axienet_ior(lp, XAE_PPST_OFFSET);
1158 data[13] = axienet_ior(lp, XAE_RCW0_OFFSET);
1159 data[14] = axienet_ior(lp, XAE_RCW1_OFFSET);
1160 data[15] = axienet_ior(lp, XAE_TC_OFFSET);
1161 data[16] = axienet_ior(lp, XAE_FCC_OFFSET);
1162 data[17] = axienet_ior(lp, XAE_EMMC_OFFSET);
1163 data[18] = axienet_ior(lp, XAE_PHYC_OFFSET);
1164 data[19] = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
1165 data[20] = axienet_ior(lp, XAE_MDIO_MCR_OFFSET);
1166 data[21] = axienet_ior(lp, XAE_MDIO_MWD_OFFSET);
1167 data[22] = axienet_ior(lp, XAE_MDIO_MRD_OFFSET);
1168 data[23] = axienet_ior(lp, XAE_MDIO_MIS_OFFSET);
1169 data[24] = axienet_ior(lp, XAE_MDIO_MIP_OFFSET);
1170 data[25] = axienet_ior(lp, XAE_MDIO_MIE_OFFSET);
1171 data[26] = axienet_ior(lp, XAE_MDIO_MIC_OFFSET);
1172 data[27] = axienet_ior(lp, XAE_UAW0_OFFSET);
1173 data[28] = axienet_ior(lp, XAE_UAW1_OFFSET);
1174 data[29] = axienet_ior(lp, XAE_FMI_OFFSET);
1175 data[30] = axienet_ior(lp, XAE_AF0_OFFSET);
1176 data[31] = axienet_ior(lp, XAE_AF1_OFFSET);
1180 * axienet_ethtools_get_pauseparam - Get the pause parameter setting for
1182 * @ndev: Pointer to net_device structure
1183 * @epauseparm: Pointer to ethtool_pauseparam structure.
1185 * This implements ethtool command for getting axi ethernet pause frame
1186 * setting. Issue "ethtool -a ethX" to execute this function.
1189 axienet_ethtools_get_pauseparam(struct net_device *ndev,
1190 struct ethtool_pauseparam *epauseparm)
1193 struct axienet_local *lp = netdev_priv(ndev);
1194 epauseparm->autoneg = 0;
1195 regval = axienet_ior(lp, XAE_FCC_OFFSET);
1196 epauseparm->tx_pause = regval & XAE_FCC_FCTX_MASK;
1197 epauseparm->rx_pause = regval & XAE_FCC_FCRX_MASK;
1201 * axienet_ethtools_set_pauseparam - Set device pause parameter(flow control)
1203 * @ndev: Pointer to net_device structure
1204 * @epauseparm:Pointer to ethtool_pauseparam structure
1206 * This implements ethtool command for enabling flow control on Rx and Tx
1207 * paths. Issue "ethtool -A ethX tx on|off" under linux prompt to execute this
1210 * Return: 0 on success, -EFAULT if device is running
1213 axienet_ethtools_set_pauseparam(struct net_device *ndev,
1214 struct ethtool_pauseparam *epauseparm)
1217 struct axienet_local *lp = netdev_priv(ndev);
1219 if (netif_running(ndev)) {
1221 "Please stop netif before applying configuration\n");
1225 regval = axienet_ior(lp, XAE_FCC_OFFSET);
1226 if (epauseparm->tx_pause)
1227 regval |= XAE_FCC_FCTX_MASK;
1229 regval &= ~XAE_FCC_FCTX_MASK;
1230 if (epauseparm->rx_pause)
1231 regval |= XAE_FCC_FCRX_MASK;
1233 regval &= ~XAE_FCC_FCRX_MASK;
1234 axienet_iow(lp, XAE_FCC_OFFSET, regval);
1240 * axienet_ethtools_get_coalesce - Get DMA interrupt coalescing count.
1241 * @ndev: Pointer to net_device structure
1242 * @ecoalesce: Pointer to ethtool_coalesce structure
1244 * This implements ethtool command for getting the DMA interrupt coalescing
1245 * count on Tx and Rx paths. Issue "ethtool -c ethX" under linux prompt to
1246 * execute this function.
1250 static int axienet_ethtools_get_coalesce(struct net_device *ndev,
1251 struct ethtool_coalesce *ecoalesce)
1254 struct axienet_local *lp = netdev_priv(ndev);
1255 regval = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1256 ecoalesce->rx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1257 >> XAXIDMA_COALESCE_SHIFT;
1258 regval = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1259 ecoalesce->tx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1260 >> XAXIDMA_COALESCE_SHIFT;
1265 * axienet_ethtools_set_coalesce - Set DMA interrupt coalescing count.
1266 * @ndev: Pointer to net_device structure
1267 * @ecoalesce: Pointer to ethtool_coalesce structure
1269 * This implements ethtool command for setting the DMA interrupt coalescing
1270 * count on Tx and Rx paths. Issue "ethtool -C ethX rx-frames 5" under linux
1271 * prompt to execute this function.
1273 * Return: 0, on success, Non-zero error value on failure.
1275 static int axienet_ethtools_set_coalesce(struct net_device *ndev,
1276 struct ethtool_coalesce *ecoalesce)
1278 struct axienet_local *lp = netdev_priv(ndev);
1280 if (netif_running(ndev)) {
1282 "Please stop netif before applying configuration\n");
1286 if ((ecoalesce->rx_coalesce_usecs) ||
1287 (ecoalesce->rx_coalesce_usecs_irq) ||
1288 (ecoalesce->rx_max_coalesced_frames_irq) ||
1289 (ecoalesce->tx_coalesce_usecs) ||
1290 (ecoalesce->tx_coalesce_usecs_irq) ||
1291 (ecoalesce->tx_max_coalesced_frames_irq) ||
1292 (ecoalesce->stats_block_coalesce_usecs) ||
1293 (ecoalesce->use_adaptive_rx_coalesce) ||
1294 (ecoalesce->use_adaptive_tx_coalesce) ||
1295 (ecoalesce->pkt_rate_low) ||
1296 (ecoalesce->rx_coalesce_usecs_low) ||
1297 (ecoalesce->rx_max_coalesced_frames_low) ||
1298 (ecoalesce->tx_coalesce_usecs_low) ||
1299 (ecoalesce->tx_max_coalesced_frames_low) ||
1300 (ecoalesce->pkt_rate_high) ||
1301 (ecoalesce->rx_coalesce_usecs_high) ||
1302 (ecoalesce->rx_max_coalesced_frames_high) ||
1303 (ecoalesce->tx_coalesce_usecs_high) ||
1304 (ecoalesce->tx_max_coalesced_frames_high) ||
1305 (ecoalesce->rate_sample_interval))
1307 if (ecoalesce->rx_max_coalesced_frames)
1308 lp->coalesce_count_rx = ecoalesce->rx_max_coalesced_frames;
1309 if (ecoalesce->tx_max_coalesced_frames)
1310 lp->coalesce_count_tx = ecoalesce->tx_max_coalesced_frames;
1315 static const struct ethtool_ops axienet_ethtool_ops = {
1316 .get_drvinfo = axienet_ethtools_get_drvinfo,
1317 .get_regs_len = axienet_ethtools_get_regs_len,
1318 .get_regs = axienet_ethtools_get_regs,
1319 .get_link = ethtool_op_get_link,
1320 .get_pauseparam = axienet_ethtools_get_pauseparam,
1321 .set_pauseparam = axienet_ethtools_set_pauseparam,
1322 .get_coalesce = axienet_ethtools_get_coalesce,
1323 .set_coalesce = axienet_ethtools_set_coalesce,
1324 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1325 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1329 * axienet_dma_err_handler - Tasklet handler for Axi DMA Error
1330 * @data: Data passed
1332 * Resets the Axi DMA and Axi Ethernet devices, and reconfigures the
1335 static void axienet_dma_err_handler(unsigned long data)
1340 struct axienet_local *lp = (struct axienet_local *) data;
1341 struct net_device *ndev = lp->ndev;
1342 struct axidma_bd *cur_p;
1344 axienet_setoptions(ndev, lp->options &
1345 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1346 mdio_mcreg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
1347 axienet_mdio_wait_until_ready(lp);
1348 /* Disable the MDIO interface till Axi Ethernet Reset is completed.
1349 * When we do an Axi Ethernet reset, it resets the complete core
1350 * including the MDIO. So if MDIO is not disabled when the reset
1351 * process is started, MDIO will be broken afterwards.
1353 axienet_iow(lp, XAE_MDIO_MC_OFFSET, (mdio_mcreg &
1354 ~XAE_MDIO_MC_MDIOEN_MASK));
1356 __axienet_device_reset(lp, XAXIDMA_TX_CR_OFFSET);
1357 __axienet_device_reset(lp, XAXIDMA_RX_CR_OFFSET);
1359 axienet_iow(lp, XAE_MDIO_MC_OFFSET, mdio_mcreg);
1360 axienet_mdio_wait_until_ready(lp);
1362 for (i = 0; i < TX_BD_NUM; i++) {
1363 cur_p = &lp->tx_bd_v[i];
1365 dma_unmap_single(ndev->dev.parent, cur_p->phys,
1367 XAXIDMA_BD_CTRL_LENGTH_MASK),
1370 dev_kfree_skb_irq((struct sk_buff *) cur_p->app4);
1379 cur_p->sw_id_offset = 0;
1382 for (i = 0; i < RX_BD_NUM; i++) {
1383 cur_p = &lp->rx_bd_v[i];
1396 /* Start updating the Rx channel control register */
1397 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1398 /* Update the interrupt coalesce count */
1399 cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
1400 (XAXIDMA_DFT_RX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
1401 /* Update the delay timer count */
1402 cr = ((cr & ~XAXIDMA_DELAY_MASK) |
1403 (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
1404 /* Enable coalesce, delay timer and error interrupts */
1405 cr |= XAXIDMA_IRQ_ALL_MASK;
1406 /* Finally write to the Rx channel control register */
1407 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
1409 /* Start updating the Tx channel control register */
1410 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1411 /* Update the interrupt coalesce count */
1412 cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
1413 (XAXIDMA_DFT_TX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
1414 /* Update the delay timer count */
1415 cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
1416 (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
1417 /* Enable coalesce, delay timer and error interrupts */
1418 cr |= XAXIDMA_IRQ_ALL_MASK;
1419 /* Finally write to the Tx channel control register */
1420 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
1422 /* Populate the tail pointer and bring the Rx Axi DMA engine out of
1423 * halted state. This will make the Rx side ready for reception.
1425 axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
1426 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1427 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
1428 cr | XAXIDMA_CR_RUNSTOP_MASK);
1429 axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
1430 (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
1432 /* Write to the RS (Run-stop) bit in the Tx channel control register.
1433 * Tx channel is now ready to run. But only after we write to the
1434 * tail pointer register that the Tx channel will start transmitting
1436 axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
1437 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1438 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
1439 cr | XAXIDMA_CR_RUNSTOP_MASK);
1441 axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);
1442 axienet_status &= ~XAE_RCW1_RX_MASK;
1443 axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
1445 axienet_status = axienet_ior(lp, XAE_IP_OFFSET);
1446 if (axienet_status & XAE_INT_RXRJECT_MASK)
1447 axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
1448 axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
1450 /* Sync default options with HW but leave receiver and
1451 * transmitter disabled.
1453 axienet_setoptions(ndev, lp->options &
1454 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1455 axienet_set_mac_address(ndev, NULL);
1456 axienet_set_multicast_list(ndev);
1457 axienet_setoptions(ndev, lp->options);
1461 * axienet_probe - Axi Ethernet probe function.
1462 * @pdev: Pointer to platform device structure.
1464 * Return: 0, on success
1465 * Non-zero error value on failure.
1467 * This is the probe routine for Axi Ethernet driver. This is called before
1468 * any other driver routines are invoked. It allocates and sets up the Ethernet
1469 * device. Parses through device tree and populates fields of
1470 * axienet_local. It registers the Ethernet device.
1472 static int axienet_probe(struct platform_device *pdev)
1475 struct device_node *np;
1476 struct axienet_local *lp;
1477 struct net_device *ndev;
1478 const void *mac_addr;
1479 struct resource *ethres, dmares;
1482 ndev = alloc_etherdev(sizeof(*lp));
1486 platform_set_drvdata(pdev, ndev);
1488 SET_NETDEV_DEV(ndev, &pdev->dev);
1489 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
1490 ndev->features = NETIF_F_SG;
1491 ndev->netdev_ops = &axienet_netdev_ops;
1492 ndev->ethtool_ops = &axienet_ethtool_ops;
1494 /* MTU range: 64 - 9000 */
1496 ndev->max_mtu = XAE_JUMBO_MTU;
1498 lp = netdev_priv(ndev);
1500 lp->dev = &pdev->dev;
1501 lp->options = XAE_OPTION_DEFAULTS;
1502 /* Map device registers */
1503 ethres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1504 lp->regs = devm_ioremap_resource(&pdev->dev, ethres);
1505 if (IS_ERR(lp->regs)) {
1506 dev_err(&pdev->dev, "could not map Axi Ethernet regs.\n");
1507 ret = PTR_ERR(lp->regs);
1511 /* Setup checksum offload, but default to off if not specified */
1514 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,txcsum", &value);
1518 lp->csum_offload_on_tx_path =
1519 XAE_FEATURE_PARTIAL_TX_CSUM;
1520 lp->features |= XAE_FEATURE_PARTIAL_TX_CSUM;
1521 /* Can checksum TCP/UDP over IPv4. */
1522 ndev->features |= NETIF_F_IP_CSUM;
1525 lp->csum_offload_on_tx_path =
1526 XAE_FEATURE_FULL_TX_CSUM;
1527 lp->features |= XAE_FEATURE_FULL_TX_CSUM;
1528 /* Can checksum TCP/UDP over IPv4. */
1529 ndev->features |= NETIF_F_IP_CSUM;
1532 lp->csum_offload_on_tx_path = XAE_NO_CSUM_OFFLOAD;
1535 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,rxcsum", &value);
1539 lp->csum_offload_on_rx_path =
1540 XAE_FEATURE_PARTIAL_RX_CSUM;
1541 lp->features |= XAE_FEATURE_PARTIAL_RX_CSUM;
1544 lp->csum_offload_on_rx_path =
1545 XAE_FEATURE_FULL_RX_CSUM;
1546 lp->features |= XAE_FEATURE_FULL_RX_CSUM;
1549 lp->csum_offload_on_rx_path = XAE_NO_CSUM_OFFLOAD;
1552 /* For supporting jumbo frames, the Axi Ethernet hardware must have
1553 * a larger Rx/Tx Memory. Typically, the size must be large so that
1554 * we can enable jumbo option and start supporting jumbo frames.
1555 * Here we check for memory allocated for Rx/Tx in the hardware from
1556 * the device-tree and accordingly set flags.
1558 of_property_read_u32(pdev->dev.of_node, "xlnx,rxmem", &lp->rxmem);
1560 /* Start with the proprietary, and broken phy_type */
1561 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &value);
1563 netdev_warn(ndev, "Please upgrade your device tree binary blob to use phy-mode");
1565 case XAE_PHY_TYPE_MII:
1566 lp->phy_mode = PHY_INTERFACE_MODE_MII;
1568 case XAE_PHY_TYPE_GMII:
1569 lp->phy_mode = PHY_INTERFACE_MODE_GMII;
1571 case XAE_PHY_TYPE_RGMII_2_0:
1572 lp->phy_mode = PHY_INTERFACE_MODE_RGMII_ID;
1574 case XAE_PHY_TYPE_SGMII:
1575 lp->phy_mode = PHY_INTERFACE_MODE_SGMII;
1577 case XAE_PHY_TYPE_1000BASE_X:
1578 lp->phy_mode = PHY_INTERFACE_MODE_1000BASEX;
1585 lp->phy_mode = of_get_phy_mode(pdev->dev.of_node);
1586 if ((int)lp->phy_mode < 0) {
1592 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
1593 np = of_parse_phandle(pdev->dev.of_node, "axistream-connected", 0);
1595 dev_err(&pdev->dev, "could not find DMA node\n");
1599 ret = of_address_to_resource(np, 0, &dmares);
1601 dev_err(&pdev->dev, "unable to get DMA resource\n");
1605 lp->dma_regs = devm_ioremap_resource(&pdev->dev, &dmares);
1606 if (IS_ERR(lp->dma_regs)) {
1607 dev_err(&pdev->dev, "could not map DMA regs\n");
1608 ret = PTR_ERR(lp->dma_regs);
1612 lp->rx_irq = irq_of_parse_and_map(np, 1);
1613 lp->tx_irq = irq_of_parse_and_map(np, 0);
1615 if ((lp->rx_irq <= 0) || (lp->tx_irq <= 0)) {
1616 dev_err(&pdev->dev, "could not determine irqs\n");
1621 /* Retrieve the MAC address */
1622 mac_addr = of_get_mac_address(pdev->dev.of_node);
1624 dev_err(&pdev->dev, "could not find MAC address\n");
1627 axienet_set_mac_address(ndev, mac_addr);
1629 lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
1630 lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
1632 lp->phy_node = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1634 ret = axienet_mdio_setup(lp, pdev->dev.of_node);
1636 dev_warn(&pdev->dev, "error registering MDIO bus\n");
1639 ret = register_netdev(lp->ndev);
1641 dev_err(lp->dev, "register_netdev() error (%i)\n", ret);
1653 static int axienet_remove(struct platform_device *pdev)
1655 struct net_device *ndev = platform_get_drvdata(pdev);
1656 struct axienet_local *lp = netdev_priv(ndev);
1658 axienet_mdio_teardown(lp);
1659 unregister_netdev(ndev);
1661 of_node_put(lp->phy_node);
1662 lp->phy_node = NULL;
1669 static struct platform_driver axienet_driver = {
1670 .probe = axienet_probe,
1671 .remove = axienet_remove,
1673 .name = "xilinx_axienet",
1674 .of_match_table = axienet_of_match,
1678 module_platform_driver(axienet_driver);
1680 MODULE_DESCRIPTION("Xilinx Axi Ethernet driver");
1681 MODULE_AUTHOR("Xilinx");
1682 MODULE_LICENSE("GPL");