2 * Xilinx Axi Ethernet device driver
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
7 * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
8 * Copyright (c) 2010 - 2011 PetaLogix
9 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
11 * This is a driver for the Xilinx Axi Ethernet which is used in the Virtex6
15 * - Add Axi Fifo support.
16 * - Factor out Axi DMA code into separate driver.
17 * - Test and fix basic multicast filtering.
18 * - Add support for extended multicast filtering.
19 * - Test basic VLAN support.
20 * - Add support for extended VLAN support.
23 #include <linux/delay.h>
24 #include <linux/etherdevice.h>
25 #include <linux/module.h>
26 #include <linux/netdevice.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_platform.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_address.h>
31 #include <linux/skbuff.h>
32 #include <linux/spinlock.h>
33 #include <linux/phy.h>
34 #include <linux/mii.h>
35 #include <linux/ethtool.h>
37 #include "xilinx_axienet.h"
39 /* Descriptors defines for Tx and Rx DMA - 2^n for the best performance */
43 /* Must be shorter than length of ethtool_drvinfo.driver field to fit */
44 #define DRIVER_NAME "xaxienet"
45 #define DRIVER_DESCRIPTION "Xilinx Axi Ethernet driver"
46 #define DRIVER_VERSION "1.00a"
48 #define AXIENET_REGS_N 32
50 /* Match table for of_platform binding */
51 static const struct of_device_id axienet_of_match[] = {
52 { .compatible = "xlnx,axi-ethernet-1.00.a", },
53 { .compatible = "xlnx,axi-ethernet-1.01.a", },
54 { .compatible = "xlnx,axi-ethernet-2.01.a", },
58 MODULE_DEVICE_TABLE(of, axienet_of_match);
60 /* Option table for setting up Axi Ethernet hardware options */
61 static struct axienet_option axienet_options[] = {
62 /* Turn on jumbo packet support for both Rx and Tx */
64 .opt = XAE_OPTION_JUMBO,
66 .m_or = XAE_TC_JUM_MASK,
68 .opt = XAE_OPTION_JUMBO,
69 .reg = XAE_RCW1_OFFSET,
70 .m_or = XAE_RCW1_JUM_MASK,
71 }, { /* Turn on VLAN packet support for both Rx and Tx */
72 .opt = XAE_OPTION_VLAN,
74 .m_or = XAE_TC_VLAN_MASK,
76 .opt = XAE_OPTION_VLAN,
77 .reg = XAE_RCW1_OFFSET,
78 .m_or = XAE_RCW1_VLAN_MASK,
79 }, { /* Turn on FCS stripping on receive packets */
80 .opt = XAE_OPTION_FCS_STRIP,
81 .reg = XAE_RCW1_OFFSET,
82 .m_or = XAE_RCW1_FCS_MASK,
83 }, { /* Turn on FCS insertion on transmit packets */
84 .opt = XAE_OPTION_FCS_INSERT,
86 .m_or = XAE_TC_FCS_MASK,
87 }, { /* Turn off length/type field checking on receive packets */
88 .opt = XAE_OPTION_LENTYPE_ERR,
89 .reg = XAE_RCW1_OFFSET,
90 .m_or = XAE_RCW1_LT_DIS_MASK,
91 }, { /* Turn on Rx flow control */
92 .opt = XAE_OPTION_FLOW_CONTROL,
93 .reg = XAE_FCC_OFFSET,
94 .m_or = XAE_FCC_FCRX_MASK,
95 }, { /* Turn on Tx flow control */
96 .opt = XAE_OPTION_FLOW_CONTROL,
97 .reg = XAE_FCC_OFFSET,
98 .m_or = XAE_FCC_FCTX_MASK,
99 }, { /* Turn on promiscuous frame filtering */
100 .opt = XAE_OPTION_PROMISC,
101 .reg = XAE_FMI_OFFSET,
102 .m_or = XAE_FMI_PM_MASK,
103 }, { /* Enable transmitter */
104 .opt = XAE_OPTION_TXEN,
105 .reg = XAE_TC_OFFSET,
106 .m_or = XAE_TC_TX_MASK,
107 }, { /* Enable receiver */
108 .opt = XAE_OPTION_RXEN,
109 .reg = XAE_RCW1_OFFSET,
110 .m_or = XAE_RCW1_RX_MASK,
116 * axienet_dma_in32 - Memory mapped Axi DMA register read
117 * @lp: Pointer to axienet local structure
118 * @reg: Address offset from the base address of the Axi DMA core
120 * Return: The contents of the Axi DMA register
122 * This function returns the contents of the corresponding Axi DMA register.
124 static inline u32 axienet_dma_in32(struct axienet_local *lp, off_t reg)
126 return in_be32(lp->dma_regs + reg);
130 * axienet_dma_out32 - Memory mapped Axi DMA register write.
131 * @lp: Pointer to axienet local structure
132 * @reg: Address offset from the base address of the Axi DMA core
133 * @value: Value to be written into the Axi DMA register
135 * This function writes the desired value into the corresponding Axi DMA
138 static inline void axienet_dma_out32(struct axienet_local *lp,
139 off_t reg, u32 value)
141 out_be32((lp->dma_regs + reg), value);
145 * axienet_dma_bd_release - Release buffer descriptor rings
146 * @ndev: Pointer to the net_device structure
148 * This function is used to release the descriptors allocated in
149 * axienet_dma_bd_init. axienet_dma_bd_release is called when Axi Ethernet
150 * driver stop api is called.
152 static void axienet_dma_bd_release(struct net_device *ndev)
155 struct axienet_local *lp = netdev_priv(ndev);
157 for (i = 0; i < RX_BD_NUM; i++) {
158 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
159 lp->max_frm_size, DMA_FROM_DEVICE);
160 dev_kfree_skb((struct sk_buff *)
161 (lp->rx_bd_v[i].sw_id_offset));
165 dma_free_coherent(ndev->dev.parent,
166 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
171 dma_free_coherent(ndev->dev.parent,
172 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
179 * axienet_dma_bd_init - Setup buffer descriptor rings for Axi DMA
180 * @ndev: Pointer to the net_device structure
182 * Return: 0, on success -ENOMEM, on failure
184 * This function is called to initialize the Rx and Tx DMA descriptor
185 * rings. This initializes the descriptors with required default values
186 * and is called when Axi Ethernet driver reset is called.
188 static int axienet_dma_bd_init(struct net_device *ndev)
193 struct axienet_local *lp = netdev_priv(ndev);
195 /* Reset the indexes which are used for accessing the BDs */
200 /* Allocate the Tx and Rx buffer descriptors. */
201 lp->tx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
202 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
203 &lp->tx_bd_p, GFP_KERNEL);
207 lp->rx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
208 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
209 &lp->rx_bd_p, GFP_KERNEL);
213 for (i = 0; i < TX_BD_NUM; i++) {
214 lp->tx_bd_v[i].next = lp->tx_bd_p +
215 sizeof(*lp->tx_bd_v) *
216 ((i + 1) % TX_BD_NUM);
219 for (i = 0; i < RX_BD_NUM; i++) {
220 lp->rx_bd_v[i].next = lp->rx_bd_p +
221 sizeof(*lp->rx_bd_v) *
222 ((i + 1) % RX_BD_NUM);
224 skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size);
228 lp->rx_bd_v[i].sw_id_offset = (u32) skb;
229 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
233 lp->rx_bd_v[i].cntrl = lp->max_frm_size;
236 /* Start updating the Rx channel control register */
237 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
238 /* Update the interrupt coalesce count */
239 cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
240 ((lp->coalesce_count_rx) << XAXIDMA_COALESCE_SHIFT));
241 /* Update the delay timer count */
242 cr = ((cr & ~XAXIDMA_DELAY_MASK) |
243 (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
244 /* Enable coalesce, delay timer and error interrupts */
245 cr |= XAXIDMA_IRQ_ALL_MASK;
246 /* Write to the Rx channel control register */
247 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
249 /* Start updating the Tx channel control register */
250 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
251 /* Update the interrupt coalesce count */
252 cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
253 ((lp->coalesce_count_tx) << XAXIDMA_COALESCE_SHIFT));
254 /* Update the delay timer count */
255 cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
256 (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
257 /* Enable coalesce, delay timer and error interrupts */
258 cr |= XAXIDMA_IRQ_ALL_MASK;
259 /* Write to the Tx channel control register */
260 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
262 /* Populate the tail pointer and bring the Rx Axi DMA engine out of
263 * halted state. This will make the Rx side ready for reception.
265 axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
266 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
267 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
268 cr | XAXIDMA_CR_RUNSTOP_MASK);
269 axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
270 (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
272 /* Write to the RS (Run-stop) bit in the Tx channel control register.
273 * Tx channel is now ready to run. But only after we write to the
274 * tail pointer register that the Tx channel will start transmitting.
276 axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
277 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
278 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
279 cr | XAXIDMA_CR_RUNSTOP_MASK);
283 axienet_dma_bd_release(ndev);
288 * axienet_set_mac_address - Write the MAC address
289 * @ndev: Pointer to the net_device structure
290 * @address: 6 byte Address to be written as MAC address
292 * This function is called to initialize the MAC address of the Axi Ethernet
293 * core. It writes to the UAW0 and UAW1 registers of the core.
295 static void axienet_set_mac_address(struct net_device *ndev, void *address)
297 struct axienet_local *lp = netdev_priv(ndev);
300 memcpy(ndev->dev_addr, address, ETH_ALEN);
301 if (!is_valid_ether_addr(ndev->dev_addr))
302 eth_random_addr(ndev->dev_addr);
304 /* Set up unicast MAC address filter set its mac address */
305 axienet_iow(lp, XAE_UAW0_OFFSET,
306 (ndev->dev_addr[0]) |
307 (ndev->dev_addr[1] << 8) |
308 (ndev->dev_addr[2] << 16) |
309 (ndev->dev_addr[3] << 24));
310 axienet_iow(lp, XAE_UAW1_OFFSET,
311 (((axienet_ior(lp, XAE_UAW1_OFFSET)) &
312 ~XAE_UAW1_UNICASTADDR_MASK) |
314 (ndev->dev_addr[5] << 8))));
318 * netdev_set_mac_address - Write the MAC address (from outside the driver)
319 * @ndev: Pointer to the net_device structure
320 * @p: 6 byte Address to be written as MAC address
322 * Return: 0 for all conditions. Presently, there is no failure case.
324 * This function is called to initialize the MAC address of the Axi Ethernet
325 * core. It calls the core specific axienet_set_mac_address. This is the
326 * function that goes into net_device_ops structure entry ndo_set_mac_address.
328 static int netdev_set_mac_address(struct net_device *ndev, void *p)
330 struct sockaddr *addr = p;
331 axienet_set_mac_address(ndev, addr->sa_data);
336 * axienet_set_multicast_list - Prepare the multicast table
337 * @ndev: Pointer to the net_device structure
339 * This function is called to initialize the multicast table during
340 * initialization. The Axi Ethernet basic multicast support has a four-entry
341 * multicast table which is initialized here. Additionally this function
342 * goes into the net_device_ops structure entry ndo_set_multicast_list. This
343 * means whenever the multicast table entries need to be updated this
344 * function gets called.
346 static void axienet_set_multicast_list(struct net_device *ndev)
349 u32 reg, af0reg, af1reg;
350 struct axienet_local *lp = netdev_priv(ndev);
352 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
353 netdev_mc_count(ndev) > XAE_MULTICAST_CAM_TABLE_NUM) {
354 /* We must make the kernel realize we had to move into
355 * promiscuous mode. If it was a promiscuous mode request
356 * the flag is already set. If not we set it.
358 ndev->flags |= IFF_PROMISC;
359 reg = axienet_ior(lp, XAE_FMI_OFFSET);
360 reg |= XAE_FMI_PM_MASK;
361 axienet_iow(lp, XAE_FMI_OFFSET, reg);
362 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
363 } else if (!netdev_mc_empty(ndev)) {
364 struct netdev_hw_addr *ha;
367 netdev_for_each_mc_addr(ha, ndev) {
368 if (i >= XAE_MULTICAST_CAM_TABLE_NUM)
371 af0reg = (ha->addr[0]);
372 af0reg |= (ha->addr[1] << 8);
373 af0reg |= (ha->addr[2] << 16);
374 af0reg |= (ha->addr[3] << 24);
376 af1reg = (ha->addr[4]);
377 af1reg |= (ha->addr[5] << 8);
379 reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
382 axienet_iow(lp, XAE_FMI_OFFSET, reg);
383 axienet_iow(lp, XAE_AF0_OFFSET, af0reg);
384 axienet_iow(lp, XAE_AF1_OFFSET, af1reg);
388 reg = axienet_ior(lp, XAE_FMI_OFFSET);
389 reg &= ~XAE_FMI_PM_MASK;
391 axienet_iow(lp, XAE_FMI_OFFSET, reg);
393 for (i = 0; i < XAE_MULTICAST_CAM_TABLE_NUM; i++) {
394 reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
397 axienet_iow(lp, XAE_FMI_OFFSET, reg);
398 axienet_iow(lp, XAE_AF0_OFFSET, 0);
399 axienet_iow(lp, XAE_AF1_OFFSET, 0);
402 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
407 * axienet_setoptions - Set an Axi Ethernet option
408 * @ndev: Pointer to the net_device structure
409 * @options: Option to be enabled/disabled
411 * The Axi Ethernet core has multiple features which can be selectively turned
412 * on or off. The typical options could be jumbo frame option, basic VLAN
413 * option, promiscuous mode option etc. This function is used to set or clear
414 * these options in the Axi Ethernet hardware. This is done through
415 * axienet_option structure .
417 static void axienet_setoptions(struct net_device *ndev, u32 options)
420 struct axienet_local *lp = netdev_priv(ndev);
421 struct axienet_option *tp = &axienet_options[0];
424 reg = ((axienet_ior(lp, tp->reg)) & ~(tp->m_or));
425 if (options & tp->opt)
427 axienet_iow(lp, tp->reg, reg);
431 lp->options |= options;
434 static void __axienet_device_reset(struct axienet_local *lp,
435 struct device *dev, off_t offset)
438 /* Reset Axi DMA. This would reset Axi Ethernet core as well. The reset
439 * process of Axi DMA takes a while to complete as all pending
440 * commands/transfers will be flushed or completed during this
443 axienet_dma_out32(lp, offset, XAXIDMA_CR_RESET_MASK);
444 timeout = DELAY_OF_ONE_MILLISEC;
445 while (axienet_dma_in32(lp, offset) & XAXIDMA_CR_RESET_MASK) {
447 if (--timeout == 0) {
448 netdev_err(lp->ndev, "%s: DMA reset timeout!\n",
456 * axienet_device_reset - Reset and initialize the Axi Ethernet hardware.
457 * @ndev: Pointer to the net_device structure
459 * This function is called to reset and initialize the Axi Ethernet core. This
460 * is typically called during initialization. It does a reset of the Axi DMA
461 * Rx/Tx channels and initializes the Axi DMA BDs. Since Axi DMA reset lines
462 * areconnected to Axi Ethernet reset lines, this in turn resets the Axi
463 * Ethernet core. No separate hardware reset is done for the Axi Ethernet
466 static void axienet_device_reset(struct net_device *ndev)
469 struct axienet_local *lp = netdev_priv(ndev);
471 __axienet_device_reset(lp, &ndev->dev, XAXIDMA_TX_CR_OFFSET);
472 __axienet_device_reset(lp, &ndev->dev, XAXIDMA_RX_CR_OFFSET);
474 lp->max_frm_size = XAE_MAX_VLAN_FRAME_SIZE;
475 lp->options |= XAE_OPTION_VLAN;
476 lp->options &= (~XAE_OPTION_JUMBO);
478 if ((ndev->mtu > XAE_MTU) &&
479 (ndev->mtu <= XAE_JUMBO_MTU)) {
480 lp->max_frm_size = ndev->mtu + VLAN_ETH_HLEN +
483 if (lp->max_frm_size <= lp->rxmem)
484 lp->options |= XAE_OPTION_JUMBO;
487 if (axienet_dma_bd_init(ndev)) {
488 netdev_err(ndev, "%s: descriptor allocation failed\n",
492 axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);
493 axienet_status &= ~XAE_RCW1_RX_MASK;
494 axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
496 axienet_status = axienet_ior(lp, XAE_IP_OFFSET);
497 if (axienet_status & XAE_INT_RXRJECT_MASK)
498 axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
500 axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
502 /* Sync default options with HW but leave receiver and
503 * transmitter disabled.
505 axienet_setoptions(ndev, lp->options &
506 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
507 axienet_set_mac_address(ndev, NULL);
508 axienet_set_multicast_list(ndev);
509 axienet_setoptions(ndev, lp->options);
511 ndev->trans_start = jiffies;
515 * axienet_adjust_link - Adjust the PHY link speed/duplex.
516 * @ndev: Pointer to the net_device structure
518 * This function is called to change the speed and duplex setting after
519 * auto negotiation is done by the PHY. This is the function that gets
520 * registered with the PHY interface through the "of_phy_connect" call.
522 static void axienet_adjust_link(struct net_device *ndev)
527 struct axienet_local *lp = netdev_priv(ndev);
528 struct phy_device *phy = lp->phy_dev;
530 link_state = phy->speed | (phy->duplex << 1) | phy->link;
531 if (lp->last_link != link_state) {
532 if ((phy->speed == SPEED_10) || (phy->speed == SPEED_100)) {
533 if (lp->phy_type == XAE_PHY_TYPE_1000BASE_X)
536 if ((phy->speed == SPEED_1000) &&
537 (lp->phy_type == XAE_PHY_TYPE_MII))
542 emmc_reg = axienet_ior(lp, XAE_EMMC_OFFSET);
543 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
545 switch (phy->speed) {
547 emmc_reg |= XAE_EMMC_LINKSPD_1000;
550 emmc_reg |= XAE_EMMC_LINKSPD_100;
553 emmc_reg |= XAE_EMMC_LINKSPD_10;
556 dev_err(&ndev->dev, "Speed other than 10, 100 "
557 "or 1Gbps is not supported\n");
561 axienet_iow(lp, XAE_EMMC_OFFSET, emmc_reg);
562 lp->last_link = link_state;
563 phy_print_status(phy);
566 "Error setting Axi Ethernet mac speed\n");
572 * axienet_start_xmit_done - Invoked once a transmit is completed by the
573 * Axi DMA Tx channel.
574 * @ndev: Pointer to the net_device structure
576 * This function is invoked from the Axi DMA Tx isr to notify the completion
577 * of transmit operation. It clears fields in the corresponding Tx BDs and
578 * unmaps the corresponding buffer so that CPU can regain ownership of the
579 * buffer. It finally invokes "netif_wake_queue" to restart transmission if
582 static void axienet_start_xmit_done(struct net_device *ndev)
586 struct axienet_local *lp = netdev_priv(ndev);
587 struct axidma_bd *cur_p;
588 unsigned int status = 0;
590 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
591 status = cur_p->status;
592 while (status & XAXIDMA_BD_STS_COMPLETE_MASK) {
593 dma_unmap_single(ndev->dev.parent, cur_p->phys,
594 (cur_p->cntrl & XAXIDMA_BD_CTRL_LENGTH_MASK),
597 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
605 size += status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
609 lp->tx_bd_ci %= TX_BD_NUM;
610 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
611 status = cur_p->status;
614 ndev->stats.tx_packets += packets;
615 ndev->stats.tx_bytes += size;
617 /* Matches barrier in axienet_start_xmit */
620 netif_wake_queue(ndev);
624 * axienet_check_tx_bd_space - Checks if a BD/group of BDs are currently busy
625 * @lp: Pointer to the axienet_local structure
626 * @num_frag: The number of BDs to check for
628 * Return: 0, on success
629 * NETDEV_TX_BUSY, if any of the descriptors are not free
631 * This function is invoked before BDs are allocated and transmission starts.
632 * This function returns 0 if a BD or group of BDs can be allocated for
633 * transmission. If the BD or any of the BDs are not free the function
634 * returns a busy status. This is invoked from axienet_start_xmit.
636 static inline int axienet_check_tx_bd_space(struct axienet_local *lp,
639 struct axidma_bd *cur_p;
640 cur_p = &lp->tx_bd_v[(lp->tx_bd_tail + num_frag) % TX_BD_NUM];
641 if (cur_p->status & XAXIDMA_BD_STS_ALL_MASK)
642 return NETDEV_TX_BUSY;
647 * axienet_start_xmit - Starts the transmission.
648 * @skb: sk_buff pointer that contains data to be Txed.
649 * @ndev: Pointer to net_device structure.
651 * Return: NETDEV_TX_OK, on success
652 * NETDEV_TX_BUSY, if any of the descriptors are not free
654 * This function is invoked from upper layers to initiate transmission. The
655 * function uses the next available free BDs and populates their fields to
656 * start the transmission. Additionally if checksum offloading is supported,
657 * it populates AXI Stream Control fields with appropriate values.
660 axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
668 struct axienet_local *lp = netdev_priv(ndev);
669 struct axidma_bd *cur_p;
671 num_frag = skb_shinfo(skb)->nr_frags;
672 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
674 if (axienet_check_tx_bd_space(lp, num_frag)) {
675 if (netif_queue_stopped(ndev))
676 return NETDEV_TX_BUSY;
678 netif_stop_queue(ndev);
680 /* Matches barrier in axienet_start_xmit_done */
683 /* Space might have just been freed - check again */
684 if (axienet_check_tx_bd_space(lp, num_frag))
685 return NETDEV_TX_BUSY;
687 netif_wake_queue(ndev);
690 if (skb->ip_summed == CHECKSUM_PARTIAL) {
691 if (lp->features & XAE_FEATURE_FULL_TX_CSUM) {
692 /* Tx Full Checksum Offload Enabled */
694 } else if (lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) {
695 csum_start_off = skb_transport_offset(skb);
696 csum_index_off = csum_start_off + skb->csum_offset;
697 /* Tx Partial Checksum Offload Enabled */
699 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
701 } else if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
702 cur_p->app0 |= 2; /* Tx Full Checksum Offload Enabled */
705 cur_p->cntrl = skb_headlen(skb) | XAXIDMA_BD_CTRL_TXSOF_MASK;
706 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data,
707 skb_headlen(skb), DMA_TO_DEVICE);
709 for (ii = 0; ii < num_frag; ii++) {
711 lp->tx_bd_tail %= TX_BD_NUM;
712 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
713 frag = &skb_shinfo(skb)->frags[ii];
714 cur_p->phys = dma_map_single(ndev->dev.parent,
715 skb_frag_address(frag),
718 cur_p->cntrl = skb_frag_size(frag);
721 cur_p->cntrl |= XAXIDMA_BD_CTRL_TXEOF_MASK;
722 cur_p->app4 = (unsigned long)skb;
724 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
725 /* Start the transfer */
726 axienet_dma_out32(lp, XAXIDMA_TX_TDESC_OFFSET, tail_p);
728 lp->tx_bd_tail %= TX_BD_NUM;
734 * axienet_recv - Is called from Axi DMA Rx Isr to complete the received
736 * @ndev: Pointer to net_device structure.
738 * This function is invoked from the Axi DMA Rx isr to process the Rx BDs. It
739 * does minimal processing and invokes "netif_rx" to complete further
742 static void axienet_recv(struct net_device *ndev)
748 dma_addr_t tail_p = 0;
749 struct axienet_local *lp = netdev_priv(ndev);
750 struct sk_buff *skb, *new_skb;
751 struct axidma_bd *cur_p;
753 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
755 while ((cur_p->status & XAXIDMA_BD_STS_COMPLETE_MASK)) {
756 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
757 skb = (struct sk_buff *) (cur_p->sw_id_offset);
758 length = cur_p->app4 & 0x0000FFFF;
760 dma_unmap_single(ndev->dev.parent, cur_p->phys,
764 skb_put(skb, length);
765 skb->protocol = eth_type_trans(skb, ndev);
766 /*skb_checksum_none_assert(skb);*/
767 skb->ip_summed = CHECKSUM_NONE;
769 /* if we're doing Rx csum offload, set it up */
770 if (lp->features & XAE_FEATURE_FULL_RX_CSUM) {
771 csumstatus = (cur_p->app2 &
772 XAE_FULL_CSUM_STATUS_MASK) >> 3;
773 if ((csumstatus == XAE_IP_TCP_CSUM_VALIDATED) ||
774 (csumstatus == XAE_IP_UDP_CSUM_VALIDATED)) {
775 skb->ip_summed = CHECKSUM_UNNECESSARY;
777 } else if ((lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) != 0 &&
778 skb->protocol == htons(ETH_P_IP) &&
780 skb->csum = be32_to_cpu(cur_p->app3 & 0xFFFF);
781 skb->ip_summed = CHECKSUM_COMPLETE;
789 new_skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size);
793 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
796 cur_p->cntrl = lp->max_frm_size;
798 cur_p->sw_id_offset = (u32) new_skb;
801 lp->rx_bd_ci %= RX_BD_NUM;
802 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
805 ndev->stats.rx_packets += packets;
806 ndev->stats.rx_bytes += size;
809 axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, tail_p);
813 * axienet_tx_irq - Tx Done Isr.
815 * @_ndev: net_device pointer
817 * Return: IRQ_HANDLED for all cases.
819 * This is the Axi DMA Tx done Isr. It invokes "axienet_start_xmit_done"
820 * to complete the BD processing.
822 static irqreturn_t axienet_tx_irq(int irq, void *_ndev)
826 struct net_device *ndev = _ndev;
827 struct axienet_local *lp = netdev_priv(ndev);
829 status = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);
830 if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
831 axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status);
832 axienet_start_xmit_done(lp->ndev);
835 if (!(status & XAXIDMA_IRQ_ALL_MASK))
836 dev_err(&ndev->dev, "No interrupts asserted in Tx path");
837 if (status & XAXIDMA_IRQ_ERROR_MASK) {
838 dev_err(&ndev->dev, "DMA Tx error 0x%x\n", status);
839 dev_err(&ndev->dev, "Current BD is at: 0x%x\n",
840 (lp->tx_bd_v[lp->tx_bd_ci]).phys);
842 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
843 /* Disable coalesce, delay timer and error interrupts */
844 cr &= (~XAXIDMA_IRQ_ALL_MASK);
845 /* Write to the Tx channel control register */
846 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
848 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
849 /* Disable coalesce, delay timer and error interrupts */
850 cr &= (~XAXIDMA_IRQ_ALL_MASK);
851 /* Write to the Rx channel control register */
852 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
854 tasklet_schedule(&lp->dma_err_tasklet);
855 axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status);
862 * axienet_rx_irq - Rx Isr.
864 * @_ndev: net_device pointer
866 * Return: IRQ_HANDLED for all cases.
868 * This is the Axi DMA Rx Isr. It invokes "axienet_recv" to complete the BD
871 static irqreturn_t axienet_rx_irq(int irq, void *_ndev)
875 struct net_device *ndev = _ndev;
876 struct axienet_local *lp = netdev_priv(ndev);
878 status = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);
879 if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
880 axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status);
881 axienet_recv(lp->ndev);
884 if (!(status & XAXIDMA_IRQ_ALL_MASK))
885 dev_err(&ndev->dev, "No interrupts asserted in Rx path");
886 if (status & XAXIDMA_IRQ_ERROR_MASK) {
887 dev_err(&ndev->dev, "DMA Rx error 0x%x\n", status);
888 dev_err(&ndev->dev, "Current BD is at: 0x%x\n",
889 (lp->rx_bd_v[lp->rx_bd_ci]).phys);
891 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
892 /* Disable coalesce, delay timer and error interrupts */
893 cr &= (~XAXIDMA_IRQ_ALL_MASK);
894 /* Finally write to the Tx channel control register */
895 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
897 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
898 /* Disable coalesce, delay timer and error interrupts */
899 cr &= (~XAXIDMA_IRQ_ALL_MASK);
900 /* write to the Rx channel control register */
901 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
903 tasklet_schedule(&lp->dma_err_tasklet);
904 axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status);
910 static void axienet_dma_err_handler(unsigned long data);
913 * axienet_open - Driver open routine.
914 * @ndev: Pointer to net_device structure
916 * Return: 0, on success.
917 * -ENODEV, if PHY cannot be connected to
918 * non-zero error value on failure
920 * This is the driver open routine. It calls phy_start to start the PHY device.
921 * It also allocates interrupt service routines, enables the interrupt lines
922 * and ISR handling. Axi Ethernet core is reset through Axi DMA core. Buffer
923 * descriptors are initialized.
925 static int axienet_open(struct net_device *ndev)
928 struct axienet_local *lp = netdev_priv(ndev);
930 dev_dbg(&ndev->dev, "axienet_open()\n");
932 mdio_mcreg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
933 ret = axienet_mdio_wait_until_ready(lp);
936 /* Disable the MDIO interface till Axi Ethernet Reset is completed.
937 * When we do an Axi Ethernet reset, it resets the complete core
938 * including the MDIO. If MDIO is not disabled when the reset
939 * process is started, MDIO will be broken afterwards.
941 axienet_iow(lp, XAE_MDIO_MC_OFFSET,
942 (mdio_mcreg & (~XAE_MDIO_MC_MDIOEN_MASK)));
943 axienet_device_reset(ndev);
944 /* Enable the MDIO */
945 axienet_iow(lp, XAE_MDIO_MC_OFFSET, mdio_mcreg);
946 ret = axienet_mdio_wait_until_ready(lp);
951 if (lp->phy_type == XAE_PHY_TYPE_GMII) {
952 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
953 axienet_adjust_link, 0,
954 PHY_INTERFACE_MODE_GMII);
955 } else if (lp->phy_type == XAE_PHY_TYPE_RGMII_2_0) {
956 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
957 axienet_adjust_link, 0,
958 PHY_INTERFACE_MODE_RGMII_ID);
962 dev_err(lp->dev, "of_phy_connect() failed\n");
964 phy_start(lp->phy_dev);
967 /* Enable tasklets for Axi DMA error handling */
968 tasklet_init(&lp->dma_err_tasklet, axienet_dma_err_handler,
971 /* Enable interrupts for Axi DMA Tx */
972 ret = request_irq(lp->tx_irq, axienet_tx_irq, 0, ndev->name, ndev);
975 /* Enable interrupts for Axi DMA Rx */
976 ret = request_irq(lp->rx_irq, axienet_rx_irq, 0, ndev->name, ndev);
983 free_irq(lp->tx_irq, ndev);
986 phy_disconnect(lp->phy_dev);
988 tasklet_kill(&lp->dma_err_tasklet);
989 dev_err(lp->dev, "request_irq() failed\n");
994 * axienet_stop - Driver stop routine.
995 * @ndev: Pointer to net_device structure
997 * Return: 0, on success.
999 * This is the driver stop routine. It calls phy_disconnect to stop the PHY
1000 * device. It also removes the interrupt handlers and disables the interrupts.
1001 * The Axi DMA Tx/Rx BDs are released.
1003 static int axienet_stop(struct net_device *ndev)
1006 struct axienet_local *lp = netdev_priv(ndev);
1008 dev_dbg(&ndev->dev, "axienet_close()\n");
1010 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1011 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
1012 cr & (~XAXIDMA_CR_RUNSTOP_MASK));
1013 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1014 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
1015 cr & (~XAXIDMA_CR_RUNSTOP_MASK));
1016 axienet_setoptions(ndev, lp->options &
1017 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1019 tasklet_kill(&lp->dma_err_tasklet);
1021 free_irq(lp->tx_irq, ndev);
1022 free_irq(lp->rx_irq, ndev);
1025 phy_disconnect(lp->phy_dev);
1028 axienet_dma_bd_release(ndev);
1033 * axienet_change_mtu - Driver change mtu routine.
1034 * @ndev: Pointer to net_device structure
1035 * @new_mtu: New mtu value to be applied
1037 * Return: Always returns 0 (success).
1039 * This is the change mtu driver routine. It checks if the Axi Ethernet
1040 * hardware supports jumbo frames before changing the mtu. This can be
1041 * called only when the device is not up.
1043 static int axienet_change_mtu(struct net_device *ndev, int new_mtu)
1045 struct axienet_local *lp = netdev_priv(ndev);
1047 if (netif_running(ndev))
1050 if ((new_mtu + VLAN_ETH_HLEN +
1051 XAE_TRL_SIZE) > lp->rxmem)
1054 if ((new_mtu > XAE_JUMBO_MTU) || (new_mtu < 64))
1057 ndev->mtu = new_mtu;
1062 #ifdef CONFIG_NET_POLL_CONTROLLER
1064 * axienet_poll_controller - Axi Ethernet poll mechanism.
1065 * @ndev: Pointer to net_device structure
1067 * This implements Rx/Tx ISR poll mechanisms. The interrupts are disabled prior
1068 * to polling the ISRs and are enabled back after the polling is done.
1070 static void axienet_poll_controller(struct net_device *ndev)
1072 struct axienet_local *lp = netdev_priv(ndev);
1073 disable_irq(lp->tx_irq);
1074 disable_irq(lp->rx_irq);
1075 axienet_rx_irq(lp->tx_irq, ndev);
1076 axienet_tx_irq(lp->rx_irq, ndev);
1077 enable_irq(lp->tx_irq);
1078 enable_irq(lp->rx_irq);
1082 static const struct net_device_ops axienet_netdev_ops = {
1083 .ndo_open = axienet_open,
1084 .ndo_stop = axienet_stop,
1085 .ndo_start_xmit = axienet_start_xmit,
1086 .ndo_change_mtu = axienet_change_mtu,
1087 .ndo_set_mac_address = netdev_set_mac_address,
1088 .ndo_validate_addr = eth_validate_addr,
1089 .ndo_set_rx_mode = axienet_set_multicast_list,
1090 #ifdef CONFIG_NET_POLL_CONTROLLER
1091 .ndo_poll_controller = axienet_poll_controller,
1096 * axienet_ethtools_get_settings - Get Axi Ethernet settings related to PHY.
1097 * @ndev: Pointer to net_device structure
1098 * @ecmd: Pointer to ethtool_cmd structure
1100 * This implements ethtool command for getting PHY settings. If PHY could
1101 * not be found, the function returns -ENODEV. This function calls the
1102 * relevant PHY ethtool API to get the PHY settings.
1103 * Issue "ethtool ethX" under linux prompt to execute this function.
1105 * Return: 0 on success, -ENODEV if PHY doesn't exist
1107 static int axienet_ethtools_get_settings(struct net_device *ndev,
1108 struct ethtool_cmd *ecmd)
1110 struct axienet_local *lp = netdev_priv(ndev);
1111 struct phy_device *phydev = lp->phy_dev;
1114 return phy_ethtool_gset(phydev, ecmd);
1118 * axienet_ethtools_set_settings - Set PHY settings as passed in the argument.
1119 * @ndev: Pointer to net_device structure
1120 * @ecmd: Pointer to ethtool_cmd structure
1122 * This implements ethtool command for setting various PHY settings. If PHY
1123 * could not be found, the function returns -ENODEV. This function calls the
1124 * relevant PHY ethtool API to set the PHY.
1125 * Issue e.g. "ethtool -s ethX speed 1000" under linux prompt to execute this
1128 * Return: 0 on success, -ENODEV if PHY doesn't exist
1130 static int axienet_ethtools_set_settings(struct net_device *ndev,
1131 struct ethtool_cmd *ecmd)
1133 struct axienet_local *lp = netdev_priv(ndev);
1134 struct phy_device *phydev = lp->phy_dev;
1137 return phy_ethtool_sset(phydev, ecmd);
1141 * axienet_ethtools_get_drvinfo - Get various Axi Ethernet driver information.
1142 * @ndev: Pointer to net_device structure
1143 * @ed: Pointer to ethtool_drvinfo structure
1145 * This implements ethtool command for getting the driver information.
1146 * Issue "ethtool -i ethX" under linux prompt to execute this function.
1148 static void axienet_ethtools_get_drvinfo(struct net_device *ndev,
1149 struct ethtool_drvinfo *ed)
1151 strlcpy(ed->driver, DRIVER_NAME, sizeof(ed->driver));
1152 strlcpy(ed->version, DRIVER_VERSION, sizeof(ed->version));
1156 * axienet_ethtools_get_regs_len - Get the total regs length present in the
1158 * @ndev: Pointer to net_device structure
1160 * This implements ethtool command for getting the total register length
1163 * Return: the total regs length
1165 static int axienet_ethtools_get_regs_len(struct net_device *ndev)
1167 return sizeof(u32) * AXIENET_REGS_N;
1171 * axienet_ethtools_get_regs - Dump the contents of all registers present
1172 * in AxiEthernet core.
1173 * @ndev: Pointer to net_device structure
1174 * @regs: Pointer to ethtool_regs structure
1175 * @ret: Void pointer used to return the contents of the registers.
1177 * This implements ethtool command for getting the Axi Ethernet register dump.
1178 * Issue "ethtool -d ethX" to execute this function.
1180 static void axienet_ethtools_get_regs(struct net_device *ndev,
1181 struct ethtool_regs *regs, void *ret)
1183 u32 *data = (u32 *) ret;
1184 size_t len = sizeof(u32) * AXIENET_REGS_N;
1185 struct axienet_local *lp = netdev_priv(ndev);
1190 memset(data, 0, len);
1191 data[0] = axienet_ior(lp, XAE_RAF_OFFSET);
1192 data[1] = axienet_ior(lp, XAE_TPF_OFFSET);
1193 data[2] = axienet_ior(lp, XAE_IFGP_OFFSET);
1194 data[3] = axienet_ior(lp, XAE_IS_OFFSET);
1195 data[4] = axienet_ior(lp, XAE_IP_OFFSET);
1196 data[5] = axienet_ior(lp, XAE_IE_OFFSET);
1197 data[6] = axienet_ior(lp, XAE_TTAG_OFFSET);
1198 data[7] = axienet_ior(lp, XAE_RTAG_OFFSET);
1199 data[8] = axienet_ior(lp, XAE_UAWL_OFFSET);
1200 data[9] = axienet_ior(lp, XAE_UAWU_OFFSET);
1201 data[10] = axienet_ior(lp, XAE_TPID0_OFFSET);
1202 data[11] = axienet_ior(lp, XAE_TPID1_OFFSET);
1203 data[12] = axienet_ior(lp, XAE_PPST_OFFSET);
1204 data[13] = axienet_ior(lp, XAE_RCW0_OFFSET);
1205 data[14] = axienet_ior(lp, XAE_RCW1_OFFSET);
1206 data[15] = axienet_ior(lp, XAE_TC_OFFSET);
1207 data[16] = axienet_ior(lp, XAE_FCC_OFFSET);
1208 data[17] = axienet_ior(lp, XAE_EMMC_OFFSET);
1209 data[18] = axienet_ior(lp, XAE_PHYC_OFFSET);
1210 data[19] = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
1211 data[20] = axienet_ior(lp, XAE_MDIO_MCR_OFFSET);
1212 data[21] = axienet_ior(lp, XAE_MDIO_MWD_OFFSET);
1213 data[22] = axienet_ior(lp, XAE_MDIO_MRD_OFFSET);
1214 data[23] = axienet_ior(lp, XAE_MDIO_MIS_OFFSET);
1215 data[24] = axienet_ior(lp, XAE_MDIO_MIP_OFFSET);
1216 data[25] = axienet_ior(lp, XAE_MDIO_MIE_OFFSET);
1217 data[26] = axienet_ior(lp, XAE_MDIO_MIC_OFFSET);
1218 data[27] = axienet_ior(lp, XAE_UAW0_OFFSET);
1219 data[28] = axienet_ior(lp, XAE_UAW1_OFFSET);
1220 data[29] = axienet_ior(lp, XAE_FMI_OFFSET);
1221 data[30] = axienet_ior(lp, XAE_AF0_OFFSET);
1222 data[31] = axienet_ior(lp, XAE_AF1_OFFSET);
1226 * axienet_ethtools_get_pauseparam - Get the pause parameter setting for
1228 * @ndev: Pointer to net_device structure
1229 * @epauseparm: Pointer to ethtool_pauseparam structure.
1231 * This implements ethtool command for getting axi ethernet pause frame
1232 * setting. Issue "ethtool -a ethX" to execute this function.
1235 axienet_ethtools_get_pauseparam(struct net_device *ndev,
1236 struct ethtool_pauseparam *epauseparm)
1239 struct axienet_local *lp = netdev_priv(ndev);
1240 epauseparm->autoneg = 0;
1241 regval = axienet_ior(lp, XAE_FCC_OFFSET);
1242 epauseparm->tx_pause = regval & XAE_FCC_FCTX_MASK;
1243 epauseparm->rx_pause = regval & XAE_FCC_FCRX_MASK;
1247 * axienet_ethtools_set_pauseparam - Set device pause parameter(flow control)
1249 * @ndev: Pointer to net_device structure
1250 * @epauseparm:Pointer to ethtool_pauseparam structure
1252 * This implements ethtool command for enabling flow control on Rx and Tx
1253 * paths. Issue "ethtool -A ethX tx on|off" under linux prompt to execute this
1256 * Return: 0 on success, -EFAULT if device is running
1259 axienet_ethtools_set_pauseparam(struct net_device *ndev,
1260 struct ethtool_pauseparam *epauseparm)
1263 struct axienet_local *lp = netdev_priv(ndev);
1265 if (netif_running(ndev)) {
1267 "Please stop netif before applying configuration\n");
1271 regval = axienet_ior(lp, XAE_FCC_OFFSET);
1272 if (epauseparm->tx_pause)
1273 regval |= XAE_FCC_FCTX_MASK;
1275 regval &= ~XAE_FCC_FCTX_MASK;
1276 if (epauseparm->rx_pause)
1277 regval |= XAE_FCC_FCRX_MASK;
1279 regval &= ~XAE_FCC_FCRX_MASK;
1280 axienet_iow(lp, XAE_FCC_OFFSET, regval);
1286 * axienet_ethtools_get_coalesce - Get DMA interrupt coalescing count.
1287 * @ndev: Pointer to net_device structure
1288 * @ecoalesce: Pointer to ethtool_coalesce structure
1290 * This implements ethtool command for getting the DMA interrupt coalescing
1291 * count on Tx and Rx paths. Issue "ethtool -c ethX" under linux prompt to
1292 * execute this function.
1296 static int axienet_ethtools_get_coalesce(struct net_device *ndev,
1297 struct ethtool_coalesce *ecoalesce)
1300 struct axienet_local *lp = netdev_priv(ndev);
1301 regval = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1302 ecoalesce->rx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1303 >> XAXIDMA_COALESCE_SHIFT;
1304 regval = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1305 ecoalesce->tx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1306 >> XAXIDMA_COALESCE_SHIFT;
1311 * axienet_ethtools_set_coalesce - Set DMA interrupt coalescing count.
1312 * @ndev: Pointer to net_device structure
1313 * @ecoalesce: Pointer to ethtool_coalesce structure
1315 * This implements ethtool command for setting the DMA interrupt coalescing
1316 * count on Tx and Rx paths. Issue "ethtool -C ethX rx-frames 5" under linux
1317 * prompt to execute this function.
1319 * Return: 0, on success, Non-zero error value on failure.
1321 static int axienet_ethtools_set_coalesce(struct net_device *ndev,
1322 struct ethtool_coalesce *ecoalesce)
1324 struct axienet_local *lp = netdev_priv(ndev);
1326 if (netif_running(ndev)) {
1328 "Please stop netif before applying configuration\n");
1332 if ((ecoalesce->rx_coalesce_usecs) ||
1333 (ecoalesce->rx_coalesce_usecs_irq) ||
1334 (ecoalesce->rx_max_coalesced_frames_irq) ||
1335 (ecoalesce->tx_coalesce_usecs) ||
1336 (ecoalesce->tx_coalesce_usecs_irq) ||
1337 (ecoalesce->tx_max_coalesced_frames_irq) ||
1338 (ecoalesce->stats_block_coalesce_usecs) ||
1339 (ecoalesce->use_adaptive_rx_coalesce) ||
1340 (ecoalesce->use_adaptive_tx_coalesce) ||
1341 (ecoalesce->pkt_rate_low) ||
1342 (ecoalesce->rx_coalesce_usecs_low) ||
1343 (ecoalesce->rx_max_coalesced_frames_low) ||
1344 (ecoalesce->tx_coalesce_usecs_low) ||
1345 (ecoalesce->tx_max_coalesced_frames_low) ||
1346 (ecoalesce->pkt_rate_high) ||
1347 (ecoalesce->rx_coalesce_usecs_high) ||
1348 (ecoalesce->rx_max_coalesced_frames_high) ||
1349 (ecoalesce->tx_coalesce_usecs_high) ||
1350 (ecoalesce->tx_max_coalesced_frames_high) ||
1351 (ecoalesce->rate_sample_interval))
1353 if (ecoalesce->rx_max_coalesced_frames)
1354 lp->coalesce_count_rx = ecoalesce->rx_max_coalesced_frames;
1355 if (ecoalesce->tx_max_coalesced_frames)
1356 lp->coalesce_count_tx = ecoalesce->tx_max_coalesced_frames;
1361 static struct ethtool_ops axienet_ethtool_ops = {
1362 .get_settings = axienet_ethtools_get_settings,
1363 .set_settings = axienet_ethtools_set_settings,
1364 .get_drvinfo = axienet_ethtools_get_drvinfo,
1365 .get_regs_len = axienet_ethtools_get_regs_len,
1366 .get_regs = axienet_ethtools_get_regs,
1367 .get_link = ethtool_op_get_link,
1368 .get_pauseparam = axienet_ethtools_get_pauseparam,
1369 .set_pauseparam = axienet_ethtools_set_pauseparam,
1370 .get_coalesce = axienet_ethtools_get_coalesce,
1371 .set_coalesce = axienet_ethtools_set_coalesce,
1375 * axienet_dma_err_handler - Tasklet handler for Axi DMA Error
1376 * @data: Data passed
1378 * Resets the Axi DMA and Axi Ethernet devices, and reconfigures the
1381 static void axienet_dma_err_handler(unsigned long data)
1386 struct axienet_local *lp = (struct axienet_local *) data;
1387 struct net_device *ndev = lp->ndev;
1388 struct axidma_bd *cur_p;
1390 axienet_setoptions(ndev, lp->options &
1391 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1392 mdio_mcreg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
1393 axienet_mdio_wait_until_ready(lp);
1394 /* Disable the MDIO interface till Axi Ethernet Reset is completed.
1395 * When we do an Axi Ethernet reset, it resets the complete core
1396 * including the MDIO. So if MDIO is not disabled when the reset
1397 * process is started, MDIO will be broken afterwards.
1399 axienet_iow(lp, XAE_MDIO_MC_OFFSET, (mdio_mcreg &
1400 ~XAE_MDIO_MC_MDIOEN_MASK));
1402 __axienet_device_reset(lp, &ndev->dev, XAXIDMA_TX_CR_OFFSET);
1403 __axienet_device_reset(lp, &ndev->dev, XAXIDMA_RX_CR_OFFSET);
1405 axienet_iow(lp, XAE_MDIO_MC_OFFSET, mdio_mcreg);
1406 axienet_mdio_wait_until_ready(lp);
1408 for (i = 0; i < TX_BD_NUM; i++) {
1409 cur_p = &lp->tx_bd_v[i];
1411 dma_unmap_single(ndev->dev.parent, cur_p->phys,
1413 XAXIDMA_BD_CTRL_LENGTH_MASK),
1416 dev_kfree_skb_irq((struct sk_buff *) cur_p->app4);
1425 cur_p->sw_id_offset = 0;
1428 for (i = 0; i < RX_BD_NUM; i++) {
1429 cur_p = &lp->rx_bd_v[i];
1442 /* Start updating the Rx channel control register */
1443 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1444 /* Update the interrupt coalesce count */
1445 cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
1446 (XAXIDMA_DFT_RX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
1447 /* Update the delay timer count */
1448 cr = ((cr & ~XAXIDMA_DELAY_MASK) |
1449 (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
1450 /* Enable coalesce, delay timer and error interrupts */
1451 cr |= XAXIDMA_IRQ_ALL_MASK;
1452 /* Finally write to the Rx channel control register */
1453 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
1455 /* Start updating the Tx channel control register */
1456 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1457 /* Update the interrupt coalesce count */
1458 cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
1459 (XAXIDMA_DFT_TX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
1460 /* Update the delay timer count */
1461 cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
1462 (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
1463 /* Enable coalesce, delay timer and error interrupts */
1464 cr |= XAXIDMA_IRQ_ALL_MASK;
1465 /* Finally write to the Tx channel control register */
1466 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
1468 /* Populate the tail pointer and bring the Rx Axi DMA engine out of
1469 * halted state. This will make the Rx side ready for reception.
1471 axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
1472 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1473 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
1474 cr | XAXIDMA_CR_RUNSTOP_MASK);
1475 axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
1476 (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
1478 /* Write to the RS (Run-stop) bit in the Tx channel control register.
1479 * Tx channel is now ready to run. But only after we write to the
1480 * tail pointer register that the Tx channel will start transmitting
1482 axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
1483 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1484 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
1485 cr | XAXIDMA_CR_RUNSTOP_MASK);
1487 axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);
1488 axienet_status &= ~XAE_RCW1_RX_MASK;
1489 axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
1491 axienet_status = axienet_ior(lp, XAE_IP_OFFSET);
1492 if (axienet_status & XAE_INT_RXRJECT_MASK)
1493 axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
1494 axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
1496 /* Sync default options with HW but leave receiver and
1497 * transmitter disabled.
1499 axienet_setoptions(ndev, lp->options &
1500 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1501 axienet_set_mac_address(ndev, NULL);
1502 axienet_set_multicast_list(ndev);
1503 axienet_setoptions(ndev, lp->options);
1507 * axienet_probe - Axi Ethernet probe function.
1508 * @pdev: Pointer to platform device structure.
1510 * Return: 0, on success
1511 * Non-zero error value on failure.
1513 * This is the probe routine for Axi Ethernet driver. This is called before
1514 * any other driver routines are invoked. It allocates and sets up the Ethernet
1515 * device. Parses through device tree and populates fields of
1516 * axienet_local. It registers the Ethernet device.
1518 static int axienet_probe(struct platform_device *pdev)
1521 struct device_node *np;
1522 struct axienet_local *lp;
1523 struct net_device *ndev;
1525 struct resource *ethres, dmares;
1528 ndev = alloc_etherdev(sizeof(*lp));
1532 platform_set_drvdata(pdev, ndev);
1534 SET_NETDEV_DEV(ndev, &pdev->dev);
1535 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
1536 ndev->features = NETIF_F_SG;
1537 ndev->netdev_ops = &axienet_netdev_ops;
1538 ndev->ethtool_ops = &axienet_ethtool_ops;
1540 lp = netdev_priv(ndev);
1542 lp->dev = &pdev->dev;
1543 lp->options = XAE_OPTION_DEFAULTS;
1544 /* Map device registers */
1545 ethres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1546 lp->regs = devm_ioremap_resource(&pdev->dev, ethres);
1547 if (IS_ERR(lp->regs)) {
1548 dev_err(&pdev->dev, "could not map Axi Ethernet regs.\n");
1549 ret = PTR_ERR(lp->regs);
1553 /* Setup checksum offload, but default to off if not specified */
1556 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,txcsum", &value);
1560 lp->csum_offload_on_tx_path =
1561 XAE_FEATURE_PARTIAL_TX_CSUM;
1562 lp->features |= XAE_FEATURE_PARTIAL_TX_CSUM;
1563 /* Can checksum TCP/UDP over IPv4. */
1564 ndev->features |= NETIF_F_IP_CSUM;
1567 lp->csum_offload_on_tx_path =
1568 XAE_FEATURE_FULL_TX_CSUM;
1569 lp->features |= XAE_FEATURE_FULL_TX_CSUM;
1570 /* Can checksum TCP/UDP over IPv4. */
1571 ndev->features |= NETIF_F_IP_CSUM;
1574 lp->csum_offload_on_tx_path = XAE_NO_CSUM_OFFLOAD;
1577 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,rxcsum", &value);
1581 lp->csum_offload_on_rx_path =
1582 XAE_FEATURE_PARTIAL_RX_CSUM;
1583 lp->features |= XAE_FEATURE_PARTIAL_RX_CSUM;
1586 lp->csum_offload_on_rx_path =
1587 XAE_FEATURE_FULL_RX_CSUM;
1588 lp->features |= XAE_FEATURE_FULL_RX_CSUM;
1591 lp->csum_offload_on_rx_path = XAE_NO_CSUM_OFFLOAD;
1594 /* For supporting jumbo frames, the Axi Ethernet hardware must have
1595 * a larger Rx/Tx Memory. Typically, the size must be large so that
1596 * we can enable jumbo option and start supporting jumbo frames.
1597 * Here we check for memory allocated for Rx/Tx in the hardware from
1598 * the device-tree and accordingly set flags.
1600 of_property_read_u32(pdev->dev.of_node, "xlnx,rxmem", &lp->rxmem);
1601 of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &lp->phy_type);
1603 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
1604 np = of_parse_phandle(pdev->dev.of_node, "axistream-connected", 0);
1606 dev_err(&pdev->dev, "could not find DMA node\n");
1610 ret = of_address_to_resource(np, 0, &dmares);
1612 dev_err(&pdev->dev, "unable to get DMA resource\n");
1616 lp->dma_regs = devm_ioremap_resource(&pdev->dev, &dmares);
1617 if (IS_ERR(lp->dma_regs)) {
1618 dev_err(&pdev->dev, "could not map DMA regs\n");
1619 ret = PTR_ERR(lp->dma_regs);
1623 lp->rx_irq = irq_of_parse_and_map(np, 1);
1624 lp->tx_irq = irq_of_parse_and_map(np, 0);
1626 if ((lp->rx_irq <= 0) || (lp->tx_irq <= 0)) {
1627 dev_err(&pdev->dev, "could not determine irqs\n");
1632 /* Retrieve the MAC address */
1633 ret = of_property_read_u8_array(pdev->dev.of_node,
1634 "local-mac-address", mac_addr, 6);
1636 dev_err(&pdev->dev, "could not find MAC address\n");
1639 axienet_set_mac_address(ndev, (void *)mac_addr);
1641 lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
1642 lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
1644 lp->phy_node = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1646 ret = axienet_mdio_setup(lp, pdev->dev.of_node);
1648 dev_warn(&pdev->dev, "error registering MDIO bus\n");
1651 ret = register_netdev(lp->ndev);
1653 dev_err(lp->dev, "register_netdev() error (%i)\n", ret);
1665 static int axienet_remove(struct platform_device *pdev)
1667 struct net_device *ndev = platform_get_drvdata(pdev);
1668 struct axienet_local *lp = netdev_priv(ndev);
1670 axienet_mdio_teardown(lp);
1671 unregister_netdev(ndev);
1673 of_node_put(lp->phy_node);
1674 lp->phy_node = NULL;
1681 static struct platform_driver axienet_driver = {
1682 .probe = axienet_probe,
1683 .remove = axienet_remove,
1685 .name = "xilinx_axienet",
1686 .of_match_table = axienet_of_match,
1690 module_platform_driver(axienet_driver);
1692 MODULE_DESCRIPTION("Xilinx Axi Ethernet driver");
1693 MODULE_AUTHOR("Xilinx");
1694 MODULE_LICENSE("GPL");