2 * Xilinx Axi Ethernet device driver
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
7 * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
8 * Copyright (c) 2010 - 2011 PetaLogix
9 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
11 * This is a driver for the Xilinx Axi Ethernet which is used in the Virtex6
15 * - Add Axi Fifo support.
16 * - Factor out Axi DMA code into separate driver.
17 * - Test and fix basic multicast filtering.
18 * - Add support for extended multicast filtering.
19 * - Test basic VLAN support.
20 * - Add support for extended VLAN support.
23 #include <linux/delay.h>
24 #include <linux/etherdevice.h>
25 #include <linux/module.h>
26 #include <linux/netdevice.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/of_platform.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_address.h>
32 #include <linux/skbuff.h>
33 #include <linux/spinlock.h>
34 #include <linux/phy.h>
35 #include <linux/mii.h>
36 #include <linux/ethtool.h>
38 #include "xilinx_axienet.h"
40 /* Descriptors defines for Tx and Rx DMA - 2^n for the best performance */
44 /* Must be shorter than length of ethtool_drvinfo.driver field to fit */
45 #define DRIVER_NAME "xaxienet"
46 #define DRIVER_DESCRIPTION "Xilinx Axi Ethernet driver"
47 #define DRIVER_VERSION "1.00a"
49 #define AXIENET_REGS_N 32
51 /* Match table for of_platform binding */
52 static const struct of_device_id axienet_of_match[] = {
53 { .compatible = "xlnx,axi-ethernet-1.00.a", },
54 { .compatible = "xlnx,axi-ethernet-1.01.a", },
55 { .compatible = "xlnx,axi-ethernet-2.01.a", },
59 MODULE_DEVICE_TABLE(of, axienet_of_match);
61 /* Option table for setting up Axi Ethernet hardware options */
62 static struct axienet_option axienet_options[] = {
63 /* Turn on jumbo packet support for both Rx and Tx */
65 .opt = XAE_OPTION_JUMBO,
67 .m_or = XAE_TC_JUM_MASK,
69 .opt = XAE_OPTION_JUMBO,
70 .reg = XAE_RCW1_OFFSET,
71 .m_or = XAE_RCW1_JUM_MASK,
72 }, { /* Turn on VLAN packet support for both Rx and Tx */
73 .opt = XAE_OPTION_VLAN,
75 .m_or = XAE_TC_VLAN_MASK,
77 .opt = XAE_OPTION_VLAN,
78 .reg = XAE_RCW1_OFFSET,
79 .m_or = XAE_RCW1_VLAN_MASK,
80 }, { /* Turn on FCS stripping on receive packets */
81 .opt = XAE_OPTION_FCS_STRIP,
82 .reg = XAE_RCW1_OFFSET,
83 .m_or = XAE_RCW1_FCS_MASK,
84 }, { /* Turn on FCS insertion on transmit packets */
85 .opt = XAE_OPTION_FCS_INSERT,
87 .m_or = XAE_TC_FCS_MASK,
88 }, { /* Turn off length/type field checking on receive packets */
89 .opt = XAE_OPTION_LENTYPE_ERR,
90 .reg = XAE_RCW1_OFFSET,
91 .m_or = XAE_RCW1_LT_DIS_MASK,
92 }, { /* Turn on Rx flow control */
93 .opt = XAE_OPTION_FLOW_CONTROL,
94 .reg = XAE_FCC_OFFSET,
95 .m_or = XAE_FCC_FCRX_MASK,
96 }, { /* Turn on Tx flow control */
97 .opt = XAE_OPTION_FLOW_CONTROL,
98 .reg = XAE_FCC_OFFSET,
99 .m_or = XAE_FCC_FCTX_MASK,
100 }, { /* Turn on promiscuous frame filtering */
101 .opt = XAE_OPTION_PROMISC,
102 .reg = XAE_FMI_OFFSET,
103 .m_or = XAE_FMI_PM_MASK,
104 }, { /* Enable transmitter */
105 .opt = XAE_OPTION_TXEN,
106 .reg = XAE_TC_OFFSET,
107 .m_or = XAE_TC_TX_MASK,
108 }, { /* Enable receiver */
109 .opt = XAE_OPTION_RXEN,
110 .reg = XAE_RCW1_OFFSET,
111 .m_or = XAE_RCW1_RX_MASK,
117 * axienet_dma_in32 - Memory mapped Axi DMA register read
118 * @lp: Pointer to axienet local structure
119 * @reg: Address offset from the base address of the Axi DMA core
121 * Return: The contents of the Axi DMA register
123 * This function returns the contents of the corresponding Axi DMA register.
125 static inline u32 axienet_dma_in32(struct axienet_local *lp, off_t reg)
127 return in_be32(lp->dma_regs + reg);
131 * axienet_dma_out32 - Memory mapped Axi DMA register write.
132 * @lp: Pointer to axienet local structure
133 * @reg: Address offset from the base address of the Axi DMA core
134 * @value: Value to be written into the Axi DMA register
136 * This function writes the desired value into the corresponding Axi DMA
139 static inline void axienet_dma_out32(struct axienet_local *lp,
140 off_t reg, u32 value)
142 out_be32((lp->dma_regs + reg), value);
146 * axienet_dma_bd_release - Release buffer descriptor rings
147 * @ndev: Pointer to the net_device structure
149 * This function is used to release the descriptors allocated in
150 * axienet_dma_bd_init. axienet_dma_bd_release is called when Axi Ethernet
151 * driver stop api is called.
153 static void axienet_dma_bd_release(struct net_device *ndev)
156 struct axienet_local *lp = netdev_priv(ndev);
158 for (i = 0; i < RX_BD_NUM; i++) {
159 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
160 lp->max_frm_size, DMA_FROM_DEVICE);
161 dev_kfree_skb((struct sk_buff *)
162 (lp->rx_bd_v[i].sw_id_offset));
166 dma_free_coherent(ndev->dev.parent,
167 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
172 dma_free_coherent(ndev->dev.parent,
173 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
180 * axienet_dma_bd_init - Setup buffer descriptor rings for Axi DMA
181 * @ndev: Pointer to the net_device structure
183 * Return: 0, on success -ENOMEM, on failure
185 * This function is called to initialize the Rx and Tx DMA descriptor
186 * rings. This initializes the descriptors with required default values
187 * and is called when Axi Ethernet driver reset is called.
189 static int axienet_dma_bd_init(struct net_device *ndev)
194 struct axienet_local *lp = netdev_priv(ndev);
196 /* Reset the indexes which are used for accessing the BDs */
201 /* Allocate the Tx and Rx buffer descriptors. */
202 lp->tx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
203 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
204 &lp->tx_bd_p, GFP_KERNEL);
208 lp->rx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
209 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
210 &lp->rx_bd_p, GFP_KERNEL);
214 for (i = 0; i < TX_BD_NUM; i++) {
215 lp->tx_bd_v[i].next = lp->tx_bd_p +
216 sizeof(*lp->tx_bd_v) *
217 ((i + 1) % TX_BD_NUM);
220 for (i = 0; i < RX_BD_NUM; i++) {
221 lp->rx_bd_v[i].next = lp->rx_bd_p +
222 sizeof(*lp->rx_bd_v) *
223 ((i + 1) % RX_BD_NUM);
225 skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size);
229 lp->rx_bd_v[i].sw_id_offset = (u32) skb;
230 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
234 lp->rx_bd_v[i].cntrl = lp->max_frm_size;
237 /* Start updating the Rx channel control register */
238 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
239 /* Update the interrupt coalesce count */
240 cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
241 ((lp->coalesce_count_rx) << XAXIDMA_COALESCE_SHIFT));
242 /* Update the delay timer count */
243 cr = ((cr & ~XAXIDMA_DELAY_MASK) |
244 (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
245 /* Enable coalesce, delay timer and error interrupts */
246 cr |= XAXIDMA_IRQ_ALL_MASK;
247 /* Write to the Rx channel control register */
248 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
250 /* Start updating the Tx channel control register */
251 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
252 /* Update the interrupt coalesce count */
253 cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
254 ((lp->coalesce_count_tx) << XAXIDMA_COALESCE_SHIFT));
255 /* Update the delay timer count */
256 cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
257 (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
258 /* Enable coalesce, delay timer and error interrupts */
259 cr |= XAXIDMA_IRQ_ALL_MASK;
260 /* Write to the Tx channel control register */
261 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
263 /* Populate the tail pointer and bring the Rx Axi DMA engine out of
264 * halted state. This will make the Rx side ready for reception.
266 axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
267 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
268 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
269 cr | XAXIDMA_CR_RUNSTOP_MASK);
270 axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
271 (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
273 /* Write to the RS (Run-stop) bit in the Tx channel control register.
274 * Tx channel is now ready to run. But only after we write to the
275 * tail pointer register that the Tx channel will start transmitting.
277 axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
278 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
279 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
280 cr | XAXIDMA_CR_RUNSTOP_MASK);
284 axienet_dma_bd_release(ndev);
289 * axienet_set_mac_address - Write the MAC address
290 * @ndev: Pointer to the net_device structure
291 * @address: 6 byte Address to be written as MAC address
293 * This function is called to initialize the MAC address of the Axi Ethernet
294 * core. It writes to the UAW0 and UAW1 registers of the core.
296 static void axienet_set_mac_address(struct net_device *ndev,
299 struct axienet_local *lp = netdev_priv(ndev);
302 memcpy(ndev->dev_addr, address, ETH_ALEN);
303 if (!is_valid_ether_addr(ndev->dev_addr))
304 eth_hw_addr_random(ndev);
306 /* Set up unicast MAC address filter set its mac address */
307 axienet_iow(lp, XAE_UAW0_OFFSET,
308 (ndev->dev_addr[0]) |
309 (ndev->dev_addr[1] << 8) |
310 (ndev->dev_addr[2] << 16) |
311 (ndev->dev_addr[3] << 24));
312 axienet_iow(lp, XAE_UAW1_OFFSET,
313 (((axienet_ior(lp, XAE_UAW1_OFFSET)) &
314 ~XAE_UAW1_UNICASTADDR_MASK) |
316 (ndev->dev_addr[5] << 8))));
320 * netdev_set_mac_address - Write the MAC address (from outside the driver)
321 * @ndev: Pointer to the net_device structure
322 * @p: 6 byte Address to be written as MAC address
324 * Return: 0 for all conditions. Presently, there is no failure case.
326 * This function is called to initialize the MAC address of the Axi Ethernet
327 * core. It calls the core specific axienet_set_mac_address. This is the
328 * function that goes into net_device_ops structure entry ndo_set_mac_address.
330 static int netdev_set_mac_address(struct net_device *ndev, void *p)
332 struct sockaddr *addr = p;
333 axienet_set_mac_address(ndev, addr->sa_data);
338 * axienet_set_multicast_list - Prepare the multicast table
339 * @ndev: Pointer to the net_device structure
341 * This function is called to initialize the multicast table during
342 * initialization. The Axi Ethernet basic multicast support has a four-entry
343 * multicast table which is initialized here. Additionally this function
344 * goes into the net_device_ops structure entry ndo_set_multicast_list. This
345 * means whenever the multicast table entries need to be updated this
346 * function gets called.
348 static void axienet_set_multicast_list(struct net_device *ndev)
351 u32 reg, af0reg, af1reg;
352 struct axienet_local *lp = netdev_priv(ndev);
354 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
355 netdev_mc_count(ndev) > XAE_MULTICAST_CAM_TABLE_NUM) {
356 /* We must make the kernel realize we had to move into
357 * promiscuous mode. If it was a promiscuous mode request
358 * the flag is already set. If not we set it.
360 ndev->flags |= IFF_PROMISC;
361 reg = axienet_ior(lp, XAE_FMI_OFFSET);
362 reg |= XAE_FMI_PM_MASK;
363 axienet_iow(lp, XAE_FMI_OFFSET, reg);
364 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
365 } else if (!netdev_mc_empty(ndev)) {
366 struct netdev_hw_addr *ha;
369 netdev_for_each_mc_addr(ha, ndev) {
370 if (i >= XAE_MULTICAST_CAM_TABLE_NUM)
373 af0reg = (ha->addr[0]);
374 af0reg |= (ha->addr[1] << 8);
375 af0reg |= (ha->addr[2] << 16);
376 af0reg |= (ha->addr[3] << 24);
378 af1reg = (ha->addr[4]);
379 af1reg |= (ha->addr[5] << 8);
381 reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
384 axienet_iow(lp, XAE_FMI_OFFSET, reg);
385 axienet_iow(lp, XAE_AF0_OFFSET, af0reg);
386 axienet_iow(lp, XAE_AF1_OFFSET, af1reg);
390 reg = axienet_ior(lp, XAE_FMI_OFFSET);
391 reg &= ~XAE_FMI_PM_MASK;
393 axienet_iow(lp, XAE_FMI_OFFSET, reg);
395 for (i = 0; i < XAE_MULTICAST_CAM_TABLE_NUM; i++) {
396 reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
399 axienet_iow(lp, XAE_FMI_OFFSET, reg);
400 axienet_iow(lp, XAE_AF0_OFFSET, 0);
401 axienet_iow(lp, XAE_AF1_OFFSET, 0);
404 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
409 * axienet_setoptions - Set an Axi Ethernet option
410 * @ndev: Pointer to the net_device structure
411 * @options: Option to be enabled/disabled
413 * The Axi Ethernet core has multiple features which can be selectively turned
414 * on or off. The typical options could be jumbo frame option, basic VLAN
415 * option, promiscuous mode option etc. This function is used to set or clear
416 * these options in the Axi Ethernet hardware. This is done through
417 * axienet_option structure .
419 static void axienet_setoptions(struct net_device *ndev, u32 options)
422 struct axienet_local *lp = netdev_priv(ndev);
423 struct axienet_option *tp = &axienet_options[0];
426 reg = ((axienet_ior(lp, tp->reg)) & ~(tp->m_or));
427 if (options & tp->opt)
429 axienet_iow(lp, tp->reg, reg);
433 lp->options |= options;
436 static void __axienet_device_reset(struct axienet_local *lp, off_t offset)
439 /* Reset Axi DMA. This would reset Axi Ethernet core as well. The reset
440 * process of Axi DMA takes a while to complete as all pending
441 * commands/transfers will be flushed or completed during this
444 axienet_dma_out32(lp, offset, XAXIDMA_CR_RESET_MASK);
445 timeout = DELAY_OF_ONE_MILLISEC;
446 while (axienet_dma_in32(lp, offset) & XAXIDMA_CR_RESET_MASK) {
448 if (--timeout == 0) {
449 netdev_err(lp->ndev, "%s: DMA reset timeout!\n",
457 * axienet_device_reset - Reset and initialize the Axi Ethernet hardware.
458 * @ndev: Pointer to the net_device structure
460 * This function is called to reset and initialize the Axi Ethernet core. This
461 * is typically called during initialization. It does a reset of the Axi DMA
462 * Rx/Tx channels and initializes the Axi DMA BDs. Since Axi DMA reset lines
463 * areconnected to Axi Ethernet reset lines, this in turn resets the Axi
464 * Ethernet core. No separate hardware reset is done for the Axi Ethernet
467 static void axienet_device_reset(struct net_device *ndev)
470 struct axienet_local *lp = netdev_priv(ndev);
472 __axienet_device_reset(lp, XAXIDMA_TX_CR_OFFSET);
473 __axienet_device_reset(lp, XAXIDMA_RX_CR_OFFSET);
475 lp->max_frm_size = XAE_MAX_VLAN_FRAME_SIZE;
476 lp->options |= XAE_OPTION_VLAN;
477 lp->options &= (~XAE_OPTION_JUMBO);
479 if ((ndev->mtu > XAE_MTU) &&
480 (ndev->mtu <= XAE_JUMBO_MTU)) {
481 lp->max_frm_size = ndev->mtu + VLAN_ETH_HLEN +
484 if (lp->max_frm_size <= lp->rxmem)
485 lp->options |= XAE_OPTION_JUMBO;
488 if (axienet_dma_bd_init(ndev)) {
489 netdev_err(ndev, "%s: descriptor allocation failed\n",
493 axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);
494 axienet_status &= ~XAE_RCW1_RX_MASK;
495 axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
497 axienet_status = axienet_ior(lp, XAE_IP_OFFSET);
498 if (axienet_status & XAE_INT_RXRJECT_MASK)
499 axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
501 axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
503 /* Sync default options with HW but leave receiver and
504 * transmitter disabled.
506 axienet_setoptions(ndev, lp->options &
507 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
508 axienet_set_mac_address(ndev, NULL);
509 axienet_set_multicast_list(ndev);
510 axienet_setoptions(ndev, lp->options);
512 netif_trans_update(ndev);
516 * axienet_adjust_link - Adjust the PHY link speed/duplex.
517 * @ndev: Pointer to the net_device structure
519 * This function is called to change the speed and duplex setting after
520 * auto negotiation is done by the PHY. This is the function that gets
521 * registered with the PHY interface through the "of_phy_connect" call.
523 static void axienet_adjust_link(struct net_device *ndev)
528 struct axienet_local *lp = netdev_priv(ndev);
529 struct phy_device *phy = ndev->phydev;
531 link_state = phy->speed | (phy->duplex << 1) | phy->link;
532 if (lp->last_link != link_state) {
533 if ((phy->speed == SPEED_10) || (phy->speed == SPEED_100)) {
534 if (lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX)
537 if ((phy->speed == SPEED_1000) &&
538 (lp->phy_mode == PHY_INTERFACE_MODE_MII))
543 emmc_reg = axienet_ior(lp, XAE_EMMC_OFFSET);
544 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
546 switch (phy->speed) {
548 emmc_reg |= XAE_EMMC_LINKSPD_1000;
551 emmc_reg |= XAE_EMMC_LINKSPD_100;
554 emmc_reg |= XAE_EMMC_LINKSPD_10;
557 dev_err(&ndev->dev, "Speed other than 10, 100 "
558 "or 1Gbps is not supported\n");
562 axienet_iow(lp, XAE_EMMC_OFFSET, emmc_reg);
563 lp->last_link = link_state;
564 phy_print_status(phy);
567 "Error setting Axi Ethernet mac speed\n");
573 * axienet_start_xmit_done - Invoked once a transmit is completed by the
574 * Axi DMA Tx channel.
575 * @ndev: Pointer to the net_device structure
577 * This function is invoked from the Axi DMA Tx isr to notify the completion
578 * of transmit operation. It clears fields in the corresponding Tx BDs and
579 * unmaps the corresponding buffer so that CPU can regain ownership of the
580 * buffer. It finally invokes "netif_wake_queue" to restart transmission if
583 static void axienet_start_xmit_done(struct net_device *ndev)
587 struct axienet_local *lp = netdev_priv(ndev);
588 struct axidma_bd *cur_p;
589 unsigned int status = 0;
591 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
592 status = cur_p->status;
593 while (status & XAXIDMA_BD_STS_COMPLETE_MASK) {
594 dma_unmap_single(ndev->dev.parent, cur_p->phys,
595 (cur_p->cntrl & XAXIDMA_BD_CTRL_LENGTH_MASK),
598 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
606 size += status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
610 lp->tx_bd_ci %= TX_BD_NUM;
611 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
612 status = cur_p->status;
615 ndev->stats.tx_packets += packets;
616 ndev->stats.tx_bytes += size;
618 /* Matches barrier in axienet_start_xmit */
621 netif_wake_queue(ndev);
625 * axienet_check_tx_bd_space - Checks if a BD/group of BDs are currently busy
626 * @lp: Pointer to the axienet_local structure
627 * @num_frag: The number of BDs to check for
629 * Return: 0, on success
630 * NETDEV_TX_BUSY, if any of the descriptors are not free
632 * This function is invoked before BDs are allocated and transmission starts.
633 * This function returns 0 if a BD or group of BDs can be allocated for
634 * transmission. If the BD or any of the BDs are not free the function
635 * returns a busy status. This is invoked from axienet_start_xmit.
637 static inline int axienet_check_tx_bd_space(struct axienet_local *lp,
640 struct axidma_bd *cur_p;
641 cur_p = &lp->tx_bd_v[(lp->tx_bd_tail + num_frag) % TX_BD_NUM];
642 if (cur_p->status & XAXIDMA_BD_STS_ALL_MASK)
643 return NETDEV_TX_BUSY;
648 * axienet_start_xmit - Starts the transmission.
649 * @skb: sk_buff pointer that contains data to be Txed.
650 * @ndev: Pointer to net_device structure.
652 * Return: NETDEV_TX_OK, on success
653 * NETDEV_TX_BUSY, if any of the descriptors are not free
655 * This function is invoked from upper layers to initiate transmission. The
656 * function uses the next available free BDs and populates their fields to
657 * start the transmission. Additionally if checksum offloading is supported,
658 * it populates AXI Stream Control fields with appropriate values.
661 axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
669 struct axienet_local *lp = netdev_priv(ndev);
670 struct axidma_bd *cur_p;
672 num_frag = skb_shinfo(skb)->nr_frags;
673 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
675 if (axienet_check_tx_bd_space(lp, num_frag)) {
676 if (netif_queue_stopped(ndev))
677 return NETDEV_TX_BUSY;
679 netif_stop_queue(ndev);
681 /* Matches barrier in axienet_start_xmit_done */
684 /* Space might have just been freed - check again */
685 if (axienet_check_tx_bd_space(lp, num_frag))
686 return NETDEV_TX_BUSY;
688 netif_wake_queue(ndev);
691 if (skb->ip_summed == CHECKSUM_PARTIAL) {
692 if (lp->features & XAE_FEATURE_FULL_TX_CSUM) {
693 /* Tx Full Checksum Offload Enabled */
695 } else if (lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) {
696 csum_start_off = skb_transport_offset(skb);
697 csum_index_off = csum_start_off + skb->csum_offset;
698 /* Tx Partial Checksum Offload Enabled */
700 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
702 } else if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
703 cur_p->app0 |= 2; /* Tx Full Checksum Offload Enabled */
706 cur_p->cntrl = skb_headlen(skb) | XAXIDMA_BD_CTRL_TXSOF_MASK;
707 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data,
708 skb_headlen(skb), DMA_TO_DEVICE);
710 for (ii = 0; ii < num_frag; ii++) {
712 lp->tx_bd_tail %= TX_BD_NUM;
713 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
714 frag = &skb_shinfo(skb)->frags[ii];
715 cur_p->phys = dma_map_single(ndev->dev.parent,
716 skb_frag_address(frag),
719 cur_p->cntrl = skb_frag_size(frag);
722 cur_p->cntrl |= XAXIDMA_BD_CTRL_TXEOF_MASK;
723 cur_p->app4 = (unsigned long)skb;
725 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
726 /* Start the transfer */
727 axienet_dma_out32(lp, XAXIDMA_TX_TDESC_OFFSET, tail_p);
729 lp->tx_bd_tail %= TX_BD_NUM;
735 * axienet_recv - Is called from Axi DMA Rx Isr to complete the received
737 * @ndev: Pointer to net_device structure.
739 * This function is invoked from the Axi DMA Rx isr to process the Rx BDs. It
740 * does minimal processing and invokes "netif_rx" to complete further
743 static void axienet_recv(struct net_device *ndev)
749 dma_addr_t tail_p = 0;
750 struct axienet_local *lp = netdev_priv(ndev);
751 struct sk_buff *skb, *new_skb;
752 struct axidma_bd *cur_p;
754 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
756 while ((cur_p->status & XAXIDMA_BD_STS_COMPLETE_MASK)) {
757 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
758 skb = (struct sk_buff *) (cur_p->sw_id_offset);
759 length = cur_p->app4 & 0x0000FFFF;
761 dma_unmap_single(ndev->dev.parent, cur_p->phys,
765 skb_put(skb, length);
766 skb->protocol = eth_type_trans(skb, ndev);
767 /*skb_checksum_none_assert(skb);*/
768 skb->ip_summed = CHECKSUM_NONE;
770 /* if we're doing Rx csum offload, set it up */
771 if (lp->features & XAE_FEATURE_FULL_RX_CSUM) {
772 csumstatus = (cur_p->app2 &
773 XAE_FULL_CSUM_STATUS_MASK) >> 3;
774 if ((csumstatus == XAE_IP_TCP_CSUM_VALIDATED) ||
775 (csumstatus == XAE_IP_UDP_CSUM_VALIDATED)) {
776 skb->ip_summed = CHECKSUM_UNNECESSARY;
778 } else if ((lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) != 0 &&
779 skb->protocol == htons(ETH_P_IP) &&
781 skb->csum = be32_to_cpu(cur_p->app3 & 0xFFFF);
782 skb->ip_summed = CHECKSUM_COMPLETE;
790 new_skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size);
794 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
797 cur_p->cntrl = lp->max_frm_size;
799 cur_p->sw_id_offset = (u32) new_skb;
802 lp->rx_bd_ci %= RX_BD_NUM;
803 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
806 ndev->stats.rx_packets += packets;
807 ndev->stats.rx_bytes += size;
810 axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, tail_p);
814 * axienet_tx_irq - Tx Done Isr.
816 * @_ndev: net_device pointer
818 * Return: IRQ_HANDLED for all cases.
820 * This is the Axi DMA Tx done Isr. It invokes "axienet_start_xmit_done"
821 * to complete the BD processing.
823 static irqreturn_t axienet_tx_irq(int irq, void *_ndev)
827 struct net_device *ndev = _ndev;
828 struct axienet_local *lp = netdev_priv(ndev);
830 status = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);
831 if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
832 axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status);
833 axienet_start_xmit_done(lp->ndev);
836 if (!(status & XAXIDMA_IRQ_ALL_MASK))
837 dev_err(&ndev->dev, "No interrupts asserted in Tx path\n");
838 if (status & XAXIDMA_IRQ_ERROR_MASK) {
839 dev_err(&ndev->dev, "DMA Tx error 0x%x\n", status);
840 dev_err(&ndev->dev, "Current BD is at: 0x%x\n",
841 (lp->tx_bd_v[lp->tx_bd_ci]).phys);
843 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
844 /* Disable coalesce, delay timer and error interrupts */
845 cr &= (~XAXIDMA_IRQ_ALL_MASK);
846 /* Write to the Tx channel control register */
847 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
849 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
850 /* Disable coalesce, delay timer and error interrupts */
851 cr &= (~XAXIDMA_IRQ_ALL_MASK);
852 /* Write to the Rx channel control register */
853 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
855 tasklet_schedule(&lp->dma_err_tasklet);
856 axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status);
863 * axienet_rx_irq - Rx Isr.
865 * @_ndev: net_device pointer
867 * Return: IRQ_HANDLED for all cases.
869 * This is the Axi DMA Rx Isr. It invokes "axienet_recv" to complete the BD
872 static irqreturn_t axienet_rx_irq(int irq, void *_ndev)
876 struct net_device *ndev = _ndev;
877 struct axienet_local *lp = netdev_priv(ndev);
879 status = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);
880 if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
881 axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status);
882 axienet_recv(lp->ndev);
885 if (!(status & XAXIDMA_IRQ_ALL_MASK))
886 dev_err(&ndev->dev, "No interrupts asserted in Rx path\n");
887 if (status & XAXIDMA_IRQ_ERROR_MASK) {
888 dev_err(&ndev->dev, "DMA Rx error 0x%x\n", status);
889 dev_err(&ndev->dev, "Current BD is at: 0x%x\n",
890 (lp->rx_bd_v[lp->rx_bd_ci]).phys);
892 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
893 /* Disable coalesce, delay timer and error interrupts */
894 cr &= (~XAXIDMA_IRQ_ALL_MASK);
895 /* Finally write to the Tx channel control register */
896 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
898 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
899 /* Disable coalesce, delay timer and error interrupts */
900 cr &= (~XAXIDMA_IRQ_ALL_MASK);
901 /* write to the Rx channel control register */
902 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
904 tasklet_schedule(&lp->dma_err_tasklet);
905 axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status);
911 static void axienet_dma_err_handler(unsigned long data);
914 * axienet_open - Driver open routine.
915 * @ndev: Pointer to net_device structure
917 * Return: 0, on success.
918 * -ENODEV, if PHY cannot be connected to
919 * non-zero error value on failure
921 * This is the driver open routine. It calls phy_start to start the PHY device.
922 * It also allocates interrupt service routines, enables the interrupt lines
923 * and ISR handling. Axi Ethernet core is reset through Axi DMA core. Buffer
924 * descriptors are initialized.
926 static int axienet_open(struct net_device *ndev)
929 struct axienet_local *lp = netdev_priv(ndev);
930 struct phy_device *phydev = NULL;
932 dev_dbg(&ndev->dev, "axienet_open()\n");
934 mdio_mcreg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
935 ret = axienet_mdio_wait_until_ready(lp);
938 /* Disable the MDIO interface till Axi Ethernet Reset is completed.
939 * When we do an Axi Ethernet reset, it resets the complete core
940 * including the MDIO. If MDIO is not disabled when the reset
941 * process is started, MDIO will be broken afterwards.
943 axienet_iow(lp, XAE_MDIO_MC_OFFSET,
944 (mdio_mcreg & (~XAE_MDIO_MC_MDIOEN_MASK)));
945 axienet_device_reset(ndev);
946 /* Enable the MDIO */
947 axienet_iow(lp, XAE_MDIO_MC_OFFSET, mdio_mcreg);
948 ret = axienet_mdio_wait_until_ready(lp);
953 phydev = of_phy_connect(lp->ndev, lp->phy_node,
954 axienet_adjust_link, 0, lp->phy_mode);
957 dev_err(lp->dev, "of_phy_connect() failed\n");
962 /* Enable tasklets for Axi DMA error handling */
963 tasklet_init(&lp->dma_err_tasklet, axienet_dma_err_handler,
966 /* Enable interrupts for Axi DMA Tx */
967 ret = request_irq(lp->tx_irq, axienet_tx_irq, 0, ndev->name, ndev);
970 /* Enable interrupts for Axi DMA Rx */
971 ret = request_irq(lp->rx_irq, axienet_rx_irq, 0, ndev->name, ndev);
978 free_irq(lp->tx_irq, ndev);
981 phy_disconnect(phydev);
982 tasklet_kill(&lp->dma_err_tasklet);
983 dev_err(lp->dev, "request_irq() failed\n");
988 * axienet_stop - Driver stop routine.
989 * @ndev: Pointer to net_device structure
991 * Return: 0, on success.
993 * This is the driver stop routine. It calls phy_disconnect to stop the PHY
994 * device. It also removes the interrupt handlers and disables the interrupts.
995 * The Axi DMA Tx/Rx BDs are released.
997 static int axienet_stop(struct net_device *ndev)
1000 struct axienet_local *lp = netdev_priv(ndev);
1002 dev_dbg(&ndev->dev, "axienet_close()\n");
1004 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1005 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
1006 cr & (~XAXIDMA_CR_RUNSTOP_MASK));
1007 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1008 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
1009 cr & (~XAXIDMA_CR_RUNSTOP_MASK));
1010 axienet_setoptions(ndev, lp->options &
1011 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1013 tasklet_kill(&lp->dma_err_tasklet);
1015 free_irq(lp->tx_irq, ndev);
1016 free_irq(lp->rx_irq, ndev);
1019 phy_disconnect(ndev->phydev);
1021 axienet_dma_bd_release(ndev);
1026 * axienet_change_mtu - Driver change mtu routine.
1027 * @ndev: Pointer to net_device structure
1028 * @new_mtu: New mtu value to be applied
1030 * Return: Always returns 0 (success).
1032 * This is the change mtu driver routine. It checks if the Axi Ethernet
1033 * hardware supports jumbo frames before changing the mtu. This can be
1034 * called only when the device is not up.
1036 static int axienet_change_mtu(struct net_device *ndev, int new_mtu)
1038 struct axienet_local *lp = netdev_priv(ndev);
1040 if (netif_running(ndev))
1043 if ((new_mtu + VLAN_ETH_HLEN +
1044 XAE_TRL_SIZE) > lp->rxmem)
1047 ndev->mtu = new_mtu;
1052 #ifdef CONFIG_NET_POLL_CONTROLLER
1054 * axienet_poll_controller - Axi Ethernet poll mechanism.
1055 * @ndev: Pointer to net_device structure
1057 * This implements Rx/Tx ISR poll mechanisms. The interrupts are disabled prior
1058 * to polling the ISRs and are enabled back after the polling is done.
1060 static void axienet_poll_controller(struct net_device *ndev)
1062 struct axienet_local *lp = netdev_priv(ndev);
1063 disable_irq(lp->tx_irq);
1064 disable_irq(lp->rx_irq);
1065 axienet_rx_irq(lp->tx_irq, ndev);
1066 axienet_tx_irq(lp->rx_irq, ndev);
1067 enable_irq(lp->tx_irq);
1068 enable_irq(lp->rx_irq);
1072 static const struct net_device_ops axienet_netdev_ops = {
1073 .ndo_open = axienet_open,
1074 .ndo_stop = axienet_stop,
1075 .ndo_start_xmit = axienet_start_xmit,
1076 .ndo_change_mtu = axienet_change_mtu,
1077 .ndo_set_mac_address = netdev_set_mac_address,
1078 .ndo_validate_addr = eth_validate_addr,
1079 .ndo_set_rx_mode = axienet_set_multicast_list,
1080 #ifdef CONFIG_NET_POLL_CONTROLLER
1081 .ndo_poll_controller = axienet_poll_controller,
1086 * axienet_ethtools_get_drvinfo - Get various Axi Ethernet driver information.
1087 * @ndev: Pointer to net_device structure
1088 * @ed: Pointer to ethtool_drvinfo structure
1090 * This implements ethtool command for getting the driver information.
1091 * Issue "ethtool -i ethX" under linux prompt to execute this function.
1093 static void axienet_ethtools_get_drvinfo(struct net_device *ndev,
1094 struct ethtool_drvinfo *ed)
1096 strlcpy(ed->driver, DRIVER_NAME, sizeof(ed->driver));
1097 strlcpy(ed->version, DRIVER_VERSION, sizeof(ed->version));
1101 * axienet_ethtools_get_regs_len - Get the total regs length present in the
1103 * @ndev: Pointer to net_device structure
1105 * This implements ethtool command for getting the total register length
1108 * Return: the total regs length
1110 static int axienet_ethtools_get_regs_len(struct net_device *ndev)
1112 return sizeof(u32) * AXIENET_REGS_N;
1116 * axienet_ethtools_get_regs - Dump the contents of all registers present
1117 * in AxiEthernet core.
1118 * @ndev: Pointer to net_device structure
1119 * @regs: Pointer to ethtool_regs structure
1120 * @ret: Void pointer used to return the contents of the registers.
1122 * This implements ethtool command for getting the Axi Ethernet register dump.
1123 * Issue "ethtool -d ethX" to execute this function.
1125 static void axienet_ethtools_get_regs(struct net_device *ndev,
1126 struct ethtool_regs *regs, void *ret)
1128 u32 *data = (u32 *) ret;
1129 size_t len = sizeof(u32) * AXIENET_REGS_N;
1130 struct axienet_local *lp = netdev_priv(ndev);
1135 memset(data, 0, len);
1136 data[0] = axienet_ior(lp, XAE_RAF_OFFSET);
1137 data[1] = axienet_ior(lp, XAE_TPF_OFFSET);
1138 data[2] = axienet_ior(lp, XAE_IFGP_OFFSET);
1139 data[3] = axienet_ior(lp, XAE_IS_OFFSET);
1140 data[4] = axienet_ior(lp, XAE_IP_OFFSET);
1141 data[5] = axienet_ior(lp, XAE_IE_OFFSET);
1142 data[6] = axienet_ior(lp, XAE_TTAG_OFFSET);
1143 data[7] = axienet_ior(lp, XAE_RTAG_OFFSET);
1144 data[8] = axienet_ior(lp, XAE_UAWL_OFFSET);
1145 data[9] = axienet_ior(lp, XAE_UAWU_OFFSET);
1146 data[10] = axienet_ior(lp, XAE_TPID0_OFFSET);
1147 data[11] = axienet_ior(lp, XAE_TPID1_OFFSET);
1148 data[12] = axienet_ior(lp, XAE_PPST_OFFSET);
1149 data[13] = axienet_ior(lp, XAE_RCW0_OFFSET);
1150 data[14] = axienet_ior(lp, XAE_RCW1_OFFSET);
1151 data[15] = axienet_ior(lp, XAE_TC_OFFSET);
1152 data[16] = axienet_ior(lp, XAE_FCC_OFFSET);
1153 data[17] = axienet_ior(lp, XAE_EMMC_OFFSET);
1154 data[18] = axienet_ior(lp, XAE_PHYC_OFFSET);
1155 data[19] = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
1156 data[20] = axienet_ior(lp, XAE_MDIO_MCR_OFFSET);
1157 data[21] = axienet_ior(lp, XAE_MDIO_MWD_OFFSET);
1158 data[22] = axienet_ior(lp, XAE_MDIO_MRD_OFFSET);
1159 data[23] = axienet_ior(lp, XAE_MDIO_MIS_OFFSET);
1160 data[24] = axienet_ior(lp, XAE_MDIO_MIP_OFFSET);
1161 data[25] = axienet_ior(lp, XAE_MDIO_MIE_OFFSET);
1162 data[26] = axienet_ior(lp, XAE_MDIO_MIC_OFFSET);
1163 data[27] = axienet_ior(lp, XAE_UAW0_OFFSET);
1164 data[28] = axienet_ior(lp, XAE_UAW1_OFFSET);
1165 data[29] = axienet_ior(lp, XAE_FMI_OFFSET);
1166 data[30] = axienet_ior(lp, XAE_AF0_OFFSET);
1167 data[31] = axienet_ior(lp, XAE_AF1_OFFSET);
1171 * axienet_ethtools_get_pauseparam - Get the pause parameter setting for
1173 * @ndev: Pointer to net_device structure
1174 * @epauseparm: Pointer to ethtool_pauseparam structure.
1176 * This implements ethtool command for getting axi ethernet pause frame
1177 * setting. Issue "ethtool -a ethX" to execute this function.
1180 axienet_ethtools_get_pauseparam(struct net_device *ndev,
1181 struct ethtool_pauseparam *epauseparm)
1184 struct axienet_local *lp = netdev_priv(ndev);
1185 epauseparm->autoneg = 0;
1186 regval = axienet_ior(lp, XAE_FCC_OFFSET);
1187 epauseparm->tx_pause = regval & XAE_FCC_FCTX_MASK;
1188 epauseparm->rx_pause = regval & XAE_FCC_FCRX_MASK;
1192 * axienet_ethtools_set_pauseparam - Set device pause parameter(flow control)
1194 * @ndev: Pointer to net_device structure
1195 * @epauseparm:Pointer to ethtool_pauseparam structure
1197 * This implements ethtool command for enabling flow control on Rx and Tx
1198 * paths. Issue "ethtool -A ethX tx on|off" under linux prompt to execute this
1201 * Return: 0 on success, -EFAULT if device is running
1204 axienet_ethtools_set_pauseparam(struct net_device *ndev,
1205 struct ethtool_pauseparam *epauseparm)
1208 struct axienet_local *lp = netdev_priv(ndev);
1210 if (netif_running(ndev)) {
1212 "Please stop netif before applying configuration\n");
1216 regval = axienet_ior(lp, XAE_FCC_OFFSET);
1217 if (epauseparm->tx_pause)
1218 regval |= XAE_FCC_FCTX_MASK;
1220 regval &= ~XAE_FCC_FCTX_MASK;
1221 if (epauseparm->rx_pause)
1222 regval |= XAE_FCC_FCRX_MASK;
1224 regval &= ~XAE_FCC_FCRX_MASK;
1225 axienet_iow(lp, XAE_FCC_OFFSET, regval);
1231 * axienet_ethtools_get_coalesce - Get DMA interrupt coalescing count.
1232 * @ndev: Pointer to net_device structure
1233 * @ecoalesce: Pointer to ethtool_coalesce structure
1235 * This implements ethtool command for getting the DMA interrupt coalescing
1236 * count on Tx and Rx paths. Issue "ethtool -c ethX" under linux prompt to
1237 * execute this function.
1241 static int axienet_ethtools_get_coalesce(struct net_device *ndev,
1242 struct ethtool_coalesce *ecoalesce)
1245 struct axienet_local *lp = netdev_priv(ndev);
1246 regval = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1247 ecoalesce->rx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1248 >> XAXIDMA_COALESCE_SHIFT;
1249 regval = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1250 ecoalesce->tx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1251 >> XAXIDMA_COALESCE_SHIFT;
1256 * axienet_ethtools_set_coalesce - Set DMA interrupt coalescing count.
1257 * @ndev: Pointer to net_device structure
1258 * @ecoalesce: Pointer to ethtool_coalesce structure
1260 * This implements ethtool command for setting the DMA interrupt coalescing
1261 * count on Tx and Rx paths. Issue "ethtool -C ethX rx-frames 5" under linux
1262 * prompt to execute this function.
1264 * Return: 0, on success, Non-zero error value on failure.
1266 static int axienet_ethtools_set_coalesce(struct net_device *ndev,
1267 struct ethtool_coalesce *ecoalesce)
1269 struct axienet_local *lp = netdev_priv(ndev);
1271 if (netif_running(ndev)) {
1273 "Please stop netif before applying configuration\n");
1277 if ((ecoalesce->rx_coalesce_usecs) ||
1278 (ecoalesce->rx_coalesce_usecs_irq) ||
1279 (ecoalesce->rx_max_coalesced_frames_irq) ||
1280 (ecoalesce->tx_coalesce_usecs) ||
1281 (ecoalesce->tx_coalesce_usecs_irq) ||
1282 (ecoalesce->tx_max_coalesced_frames_irq) ||
1283 (ecoalesce->stats_block_coalesce_usecs) ||
1284 (ecoalesce->use_adaptive_rx_coalesce) ||
1285 (ecoalesce->use_adaptive_tx_coalesce) ||
1286 (ecoalesce->pkt_rate_low) ||
1287 (ecoalesce->rx_coalesce_usecs_low) ||
1288 (ecoalesce->rx_max_coalesced_frames_low) ||
1289 (ecoalesce->tx_coalesce_usecs_low) ||
1290 (ecoalesce->tx_max_coalesced_frames_low) ||
1291 (ecoalesce->pkt_rate_high) ||
1292 (ecoalesce->rx_coalesce_usecs_high) ||
1293 (ecoalesce->rx_max_coalesced_frames_high) ||
1294 (ecoalesce->tx_coalesce_usecs_high) ||
1295 (ecoalesce->tx_max_coalesced_frames_high) ||
1296 (ecoalesce->rate_sample_interval))
1298 if (ecoalesce->rx_max_coalesced_frames)
1299 lp->coalesce_count_rx = ecoalesce->rx_max_coalesced_frames;
1300 if (ecoalesce->tx_max_coalesced_frames)
1301 lp->coalesce_count_tx = ecoalesce->tx_max_coalesced_frames;
1306 static const struct ethtool_ops axienet_ethtool_ops = {
1307 .get_drvinfo = axienet_ethtools_get_drvinfo,
1308 .get_regs_len = axienet_ethtools_get_regs_len,
1309 .get_regs = axienet_ethtools_get_regs,
1310 .get_link = ethtool_op_get_link,
1311 .get_pauseparam = axienet_ethtools_get_pauseparam,
1312 .set_pauseparam = axienet_ethtools_set_pauseparam,
1313 .get_coalesce = axienet_ethtools_get_coalesce,
1314 .set_coalesce = axienet_ethtools_set_coalesce,
1315 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1316 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1320 * axienet_dma_err_handler - Tasklet handler for Axi DMA Error
1321 * @data: Data passed
1323 * Resets the Axi DMA and Axi Ethernet devices, and reconfigures the
1326 static void axienet_dma_err_handler(unsigned long data)
1331 struct axienet_local *lp = (struct axienet_local *) data;
1332 struct net_device *ndev = lp->ndev;
1333 struct axidma_bd *cur_p;
1335 axienet_setoptions(ndev, lp->options &
1336 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1337 mdio_mcreg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
1338 axienet_mdio_wait_until_ready(lp);
1339 /* Disable the MDIO interface till Axi Ethernet Reset is completed.
1340 * When we do an Axi Ethernet reset, it resets the complete core
1341 * including the MDIO. So if MDIO is not disabled when the reset
1342 * process is started, MDIO will be broken afterwards.
1344 axienet_iow(lp, XAE_MDIO_MC_OFFSET, (mdio_mcreg &
1345 ~XAE_MDIO_MC_MDIOEN_MASK));
1347 __axienet_device_reset(lp, XAXIDMA_TX_CR_OFFSET);
1348 __axienet_device_reset(lp, XAXIDMA_RX_CR_OFFSET);
1350 axienet_iow(lp, XAE_MDIO_MC_OFFSET, mdio_mcreg);
1351 axienet_mdio_wait_until_ready(lp);
1353 for (i = 0; i < TX_BD_NUM; i++) {
1354 cur_p = &lp->tx_bd_v[i];
1356 dma_unmap_single(ndev->dev.parent, cur_p->phys,
1358 XAXIDMA_BD_CTRL_LENGTH_MASK),
1361 dev_kfree_skb_irq((struct sk_buff *) cur_p->app4);
1370 cur_p->sw_id_offset = 0;
1373 for (i = 0; i < RX_BD_NUM; i++) {
1374 cur_p = &lp->rx_bd_v[i];
1387 /* Start updating the Rx channel control register */
1388 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1389 /* Update the interrupt coalesce count */
1390 cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
1391 (XAXIDMA_DFT_RX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
1392 /* Update the delay timer count */
1393 cr = ((cr & ~XAXIDMA_DELAY_MASK) |
1394 (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
1395 /* Enable coalesce, delay timer and error interrupts */
1396 cr |= XAXIDMA_IRQ_ALL_MASK;
1397 /* Finally write to the Rx channel control register */
1398 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
1400 /* Start updating the Tx channel control register */
1401 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1402 /* Update the interrupt coalesce count */
1403 cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
1404 (XAXIDMA_DFT_TX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
1405 /* Update the delay timer count */
1406 cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
1407 (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
1408 /* Enable coalesce, delay timer and error interrupts */
1409 cr |= XAXIDMA_IRQ_ALL_MASK;
1410 /* Finally write to the Tx channel control register */
1411 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
1413 /* Populate the tail pointer and bring the Rx Axi DMA engine out of
1414 * halted state. This will make the Rx side ready for reception.
1416 axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
1417 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1418 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
1419 cr | XAXIDMA_CR_RUNSTOP_MASK);
1420 axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
1421 (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
1423 /* Write to the RS (Run-stop) bit in the Tx channel control register.
1424 * Tx channel is now ready to run. But only after we write to the
1425 * tail pointer register that the Tx channel will start transmitting
1427 axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
1428 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1429 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
1430 cr | XAXIDMA_CR_RUNSTOP_MASK);
1432 axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);
1433 axienet_status &= ~XAE_RCW1_RX_MASK;
1434 axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
1436 axienet_status = axienet_ior(lp, XAE_IP_OFFSET);
1437 if (axienet_status & XAE_INT_RXRJECT_MASK)
1438 axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
1439 axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
1441 /* Sync default options with HW but leave receiver and
1442 * transmitter disabled.
1444 axienet_setoptions(ndev, lp->options &
1445 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1446 axienet_set_mac_address(ndev, NULL);
1447 axienet_set_multicast_list(ndev);
1448 axienet_setoptions(ndev, lp->options);
1452 * axienet_probe - Axi Ethernet probe function.
1453 * @pdev: Pointer to platform device structure.
1455 * Return: 0, on success
1456 * Non-zero error value on failure.
1458 * This is the probe routine for Axi Ethernet driver. This is called before
1459 * any other driver routines are invoked. It allocates and sets up the Ethernet
1460 * device. Parses through device tree and populates fields of
1461 * axienet_local. It registers the Ethernet device.
1463 static int axienet_probe(struct platform_device *pdev)
1466 struct device_node *np;
1467 struct axienet_local *lp;
1468 struct net_device *ndev;
1469 const void *mac_addr;
1470 struct resource *ethres, dmares;
1473 ndev = alloc_etherdev(sizeof(*lp));
1477 platform_set_drvdata(pdev, ndev);
1479 SET_NETDEV_DEV(ndev, &pdev->dev);
1480 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
1481 ndev->features = NETIF_F_SG;
1482 ndev->netdev_ops = &axienet_netdev_ops;
1483 ndev->ethtool_ops = &axienet_ethtool_ops;
1485 /* MTU range: 64 - 9000 */
1487 ndev->max_mtu = XAE_JUMBO_MTU;
1489 lp = netdev_priv(ndev);
1491 lp->dev = &pdev->dev;
1492 lp->options = XAE_OPTION_DEFAULTS;
1493 /* Map device registers */
1494 ethres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1495 lp->regs = devm_ioremap_resource(&pdev->dev, ethres);
1496 if (IS_ERR(lp->regs)) {
1497 dev_err(&pdev->dev, "could not map Axi Ethernet regs.\n");
1498 ret = PTR_ERR(lp->regs);
1502 /* Setup checksum offload, but default to off if not specified */
1505 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,txcsum", &value);
1509 lp->csum_offload_on_tx_path =
1510 XAE_FEATURE_PARTIAL_TX_CSUM;
1511 lp->features |= XAE_FEATURE_PARTIAL_TX_CSUM;
1512 /* Can checksum TCP/UDP over IPv4. */
1513 ndev->features |= NETIF_F_IP_CSUM;
1516 lp->csum_offload_on_tx_path =
1517 XAE_FEATURE_FULL_TX_CSUM;
1518 lp->features |= XAE_FEATURE_FULL_TX_CSUM;
1519 /* Can checksum TCP/UDP over IPv4. */
1520 ndev->features |= NETIF_F_IP_CSUM;
1523 lp->csum_offload_on_tx_path = XAE_NO_CSUM_OFFLOAD;
1526 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,rxcsum", &value);
1530 lp->csum_offload_on_rx_path =
1531 XAE_FEATURE_PARTIAL_RX_CSUM;
1532 lp->features |= XAE_FEATURE_PARTIAL_RX_CSUM;
1535 lp->csum_offload_on_rx_path =
1536 XAE_FEATURE_FULL_RX_CSUM;
1537 lp->features |= XAE_FEATURE_FULL_RX_CSUM;
1540 lp->csum_offload_on_rx_path = XAE_NO_CSUM_OFFLOAD;
1543 /* For supporting jumbo frames, the Axi Ethernet hardware must have
1544 * a larger Rx/Tx Memory. Typically, the size must be large so that
1545 * we can enable jumbo option and start supporting jumbo frames.
1546 * Here we check for memory allocated for Rx/Tx in the hardware from
1547 * the device-tree and accordingly set flags.
1549 of_property_read_u32(pdev->dev.of_node, "xlnx,rxmem", &lp->rxmem);
1551 /* Start with the proprietary, and broken phy_type */
1552 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &value);
1554 netdev_warn(ndev, "Please upgrade your device tree binary blob to use phy-mode");
1556 case XAE_PHY_TYPE_MII:
1557 lp->phy_mode = PHY_INTERFACE_MODE_MII;
1559 case XAE_PHY_TYPE_GMII:
1560 lp->phy_mode = PHY_INTERFACE_MODE_GMII;
1562 case XAE_PHY_TYPE_RGMII_2_0:
1563 lp->phy_mode = PHY_INTERFACE_MODE_RGMII_ID;
1565 case XAE_PHY_TYPE_SGMII:
1566 lp->phy_mode = PHY_INTERFACE_MODE_SGMII;
1568 case XAE_PHY_TYPE_1000BASE_X:
1569 lp->phy_mode = PHY_INTERFACE_MODE_1000BASEX;
1576 lp->phy_mode = of_get_phy_mode(pdev->dev.of_node);
1577 if ((int)lp->phy_mode < 0) {
1583 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
1584 np = of_parse_phandle(pdev->dev.of_node, "axistream-connected", 0);
1586 dev_err(&pdev->dev, "could not find DMA node\n");
1590 ret = of_address_to_resource(np, 0, &dmares);
1592 dev_err(&pdev->dev, "unable to get DMA resource\n");
1596 lp->dma_regs = devm_ioremap_resource(&pdev->dev, &dmares);
1597 if (IS_ERR(lp->dma_regs)) {
1598 dev_err(&pdev->dev, "could not map DMA regs\n");
1599 ret = PTR_ERR(lp->dma_regs);
1603 lp->rx_irq = irq_of_parse_and_map(np, 1);
1604 lp->tx_irq = irq_of_parse_and_map(np, 0);
1606 if ((lp->rx_irq <= 0) || (lp->tx_irq <= 0)) {
1607 dev_err(&pdev->dev, "could not determine irqs\n");
1612 /* Retrieve the MAC address */
1613 mac_addr = of_get_mac_address(pdev->dev.of_node);
1615 dev_err(&pdev->dev, "could not find MAC address\n");
1618 axienet_set_mac_address(ndev, mac_addr);
1620 lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
1621 lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
1623 lp->phy_node = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1625 ret = axienet_mdio_setup(lp, pdev->dev.of_node);
1627 dev_warn(&pdev->dev, "error registering MDIO bus\n");
1630 ret = register_netdev(lp->ndev);
1632 dev_err(lp->dev, "register_netdev() error (%i)\n", ret);
1644 static int axienet_remove(struct platform_device *pdev)
1646 struct net_device *ndev = platform_get_drvdata(pdev);
1647 struct axienet_local *lp = netdev_priv(ndev);
1649 axienet_mdio_teardown(lp);
1650 unregister_netdev(ndev);
1652 of_node_put(lp->phy_node);
1653 lp->phy_node = NULL;
1660 static struct platform_driver axienet_driver = {
1661 .probe = axienet_probe,
1662 .remove = axienet_remove,
1664 .name = "xilinx_axienet",
1665 .of_match_table = axienet_of_match,
1669 module_platform_driver(axienet_driver);
1671 MODULE_DESCRIPTION("Xilinx Axi Ethernet driver");
1672 MODULE_AUTHOR("Xilinx");
1673 MODULE_LICENSE("GPL");