1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2015 - 2023 Beijing WangXun Technology Co., Ltd. */
4 #include <linux/gpio/machine.h>
5 #include <linux/gpio/driver.h>
6 #include <linux/gpio/property.h>
7 #include <linux/clk-provider.h>
8 #include <linux/clkdev.h>
10 #include <linux/pci.h>
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
13 #include <linux/pcs/pcs-xpcs.h>
14 #include <linux/phylink.h>
16 #include "../libwx/wx_type.h"
17 #include "../libwx/wx_lib.h"
18 #include "../libwx/wx_hw.h"
19 #include "txgbe_type.h"
20 #include "txgbe_phy.h"
23 #define TXGBE_I2C_CLK_DEV_NAME "i2c_dw"
25 static int txgbe_swnodes_register(struct txgbe *txgbe)
27 struct txgbe_nodes *nodes = &txgbe->nodes;
28 struct pci_dev *pdev = txgbe->wx->pdev;
29 struct software_node *swnodes;
32 id = pci_dev_id(pdev);
34 snprintf(nodes->gpio_name, sizeof(nodes->gpio_name), "txgbe_gpio-%x", id);
35 snprintf(nodes->i2c_name, sizeof(nodes->i2c_name), "txgbe_i2c-%x", id);
36 snprintf(nodes->sfp_name, sizeof(nodes->sfp_name), "txgbe_sfp-%x", id);
37 snprintf(nodes->phylink_name, sizeof(nodes->phylink_name), "txgbe_phylink-%x", id);
39 swnodes = nodes->swnodes;
43 * GPIO 2: sfp module absent
44 * GPIO 3: rx signal lost
45 * GPIO 4: rate select, 1G(0) 10G(1)
46 * GPIO 5: rate select, 1G(0) 10G(1)
48 nodes->gpio_props[0] = PROPERTY_ENTRY_STRING("pinctrl-names", "default");
49 swnodes[SWNODE_GPIO] = NODE_PROP(nodes->gpio_name, nodes->gpio_props);
50 nodes->gpio0_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 0, GPIO_ACTIVE_HIGH);
51 nodes->gpio1_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 1, GPIO_ACTIVE_HIGH);
52 nodes->gpio2_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 2, GPIO_ACTIVE_LOW);
53 nodes->gpio3_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 3, GPIO_ACTIVE_HIGH);
54 nodes->gpio4_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 4, GPIO_ACTIVE_HIGH);
55 nodes->gpio5_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 5, GPIO_ACTIVE_HIGH);
57 nodes->i2c_props[0] = PROPERTY_ENTRY_STRING("compatible", "snps,designware-i2c");
58 nodes->i2c_props[1] = PROPERTY_ENTRY_BOOL("wx,i2c-snps-model");
59 nodes->i2c_props[2] = PROPERTY_ENTRY_U32("clock-frequency", I2C_MAX_STANDARD_MODE_FREQ);
60 swnodes[SWNODE_I2C] = NODE_PROP(nodes->i2c_name, nodes->i2c_props);
61 nodes->i2c_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_I2C]);
63 nodes->sfp_props[0] = PROPERTY_ENTRY_STRING("compatible", "sff,sfp");
64 nodes->sfp_props[1] = PROPERTY_ENTRY_REF_ARRAY("i2c-bus", nodes->i2c_ref);
65 nodes->sfp_props[2] = PROPERTY_ENTRY_REF_ARRAY("tx-fault-gpios", nodes->gpio0_ref);
66 nodes->sfp_props[3] = PROPERTY_ENTRY_REF_ARRAY("tx-disable-gpios", nodes->gpio1_ref);
67 nodes->sfp_props[4] = PROPERTY_ENTRY_REF_ARRAY("mod-def0-gpios", nodes->gpio2_ref);
68 nodes->sfp_props[5] = PROPERTY_ENTRY_REF_ARRAY("los-gpios", nodes->gpio3_ref);
69 nodes->sfp_props[6] = PROPERTY_ENTRY_REF_ARRAY("rate-select1-gpios", nodes->gpio4_ref);
70 nodes->sfp_props[7] = PROPERTY_ENTRY_REF_ARRAY("rate-select0-gpios", nodes->gpio5_ref);
71 swnodes[SWNODE_SFP] = NODE_PROP(nodes->sfp_name, nodes->sfp_props);
72 nodes->sfp_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_SFP]);
74 nodes->phylink_props[0] = PROPERTY_ENTRY_STRING("managed", "in-band-status");
75 nodes->phylink_props[1] = PROPERTY_ENTRY_REF_ARRAY("sfp", nodes->sfp_ref);
76 swnodes[SWNODE_PHYLINK] = NODE_PROP(nodes->phylink_name, nodes->phylink_props);
78 nodes->group[SWNODE_GPIO] = &swnodes[SWNODE_GPIO];
79 nodes->group[SWNODE_I2C] = &swnodes[SWNODE_I2C];
80 nodes->group[SWNODE_SFP] = &swnodes[SWNODE_SFP];
81 nodes->group[SWNODE_PHYLINK] = &swnodes[SWNODE_PHYLINK];
83 return software_node_register_node_group(nodes->group);
86 static int txgbe_pcs_read(struct mii_bus *bus, int addr, int devnum, int regnum)
88 struct wx *wx = bus->priv;
94 offset = devnum << 16 | regnum;
96 /* Set the LAN port indicator to IDA_ADDR */
97 wr32(wx, TXGBE_XPCS_IDA_ADDR, offset);
99 /* Read the data from IDA_DATA register */
100 val = rd32(wx, TXGBE_XPCS_IDA_DATA);
105 static int txgbe_pcs_write(struct mii_bus *bus, int addr, int devnum, int regnum, u16 val)
107 struct wx *wx = bus->priv;
113 offset = devnum << 16 | regnum;
115 /* Set the LAN port indicator to IDA_ADDR */
116 wr32(wx, TXGBE_XPCS_IDA_ADDR, offset);
118 /* Write the data to IDA_DATA register */
119 wr32(wx, TXGBE_XPCS_IDA_DATA, val);
124 static int txgbe_mdio_pcs_init(struct txgbe *txgbe)
126 struct mii_bus *mii_bus;
127 struct dw_xpcs *xpcs;
128 struct pci_dev *pdev;
135 mii_bus = devm_mdiobus_alloc(&pdev->dev);
139 mii_bus->name = "txgbe_pcs_mdio_bus";
140 mii_bus->read_c45 = &txgbe_pcs_read;
141 mii_bus->write_c45 = &txgbe_pcs_write;
142 mii_bus->parent = &pdev->dev;
143 mii_bus->phy_mask = ~0;
145 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe_pcs-%x",
148 ret = devm_mdiobus_register(&pdev->dev, mii_bus);
152 xpcs = xpcs_create_mdiodev(mii_bus, 0, PHY_INTERFACE_MODE_10GBASER);
154 return PTR_ERR(xpcs);
161 static struct phylink_pcs *txgbe_phylink_mac_select(struct phylink_config *config,
162 phy_interface_t interface)
164 struct wx *wx = phylink_to_wx(config);
165 struct txgbe *txgbe = wx->priv;
167 if (interface == PHY_INTERFACE_MODE_10GBASER)
168 return &txgbe->xpcs->pcs;
173 static void txgbe_mac_config(struct phylink_config *config, unsigned int mode,
174 const struct phylink_link_state *state)
178 static void txgbe_mac_link_down(struct phylink_config *config,
179 unsigned int mode, phy_interface_t interface)
181 struct wx *wx = phylink_to_wx(config);
183 wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0);
186 static void txgbe_mac_link_up(struct phylink_config *config,
187 struct phy_device *phy,
188 unsigned int mode, phy_interface_t interface,
189 int speed, int duplex,
190 bool tx_pause, bool rx_pause)
192 struct wx *wx = phylink_to_wx(config);
195 wx_fc_enable(wx, tx_pause, rx_pause);
197 txcfg = rd32(wx, WX_MAC_TX_CFG);
198 txcfg &= ~WX_MAC_TX_CFG_SPEED_MASK;
202 txcfg |= WX_MAC_TX_CFG_SPEED_10G;
207 txcfg |= WX_MAC_TX_CFG_SPEED_1G;
213 wr32(wx, WX_MAC_TX_CFG, txcfg | WX_MAC_TX_CFG_TE);
215 /* Re configure MAC Rx */
216 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE);
217 wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR);
218 wdg = rd32(wx, WX_MAC_WDG_TIMEOUT);
219 wr32(wx, WX_MAC_WDG_TIMEOUT, wdg);
222 static int txgbe_mac_prepare(struct phylink_config *config, unsigned int mode,
223 phy_interface_t interface)
225 struct wx *wx = phylink_to_wx(config);
227 wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0);
228 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, 0);
230 return txgbe_disable_sec_tx_path(wx);
233 static int txgbe_mac_finish(struct phylink_config *config, unsigned int mode,
234 phy_interface_t interface)
236 struct wx *wx = phylink_to_wx(config);
238 txgbe_enable_sec_tx_path(wx);
239 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE);
244 static const struct phylink_mac_ops txgbe_mac_ops = {
245 .mac_select_pcs = txgbe_phylink_mac_select,
246 .mac_prepare = txgbe_mac_prepare,
247 .mac_finish = txgbe_mac_finish,
248 .mac_config = txgbe_mac_config,
249 .mac_link_down = txgbe_mac_link_down,
250 .mac_link_up = txgbe_mac_link_up,
253 static int txgbe_phylink_init(struct txgbe *txgbe)
255 struct fwnode_handle *fwnode = NULL;
256 struct phylink_config *config;
257 struct wx *wx = txgbe->wx;
258 phy_interface_t phy_mode;
259 struct phylink *phylink;
261 config = &wx->phylink_config;
262 config->dev = &wx->netdev->dev;
263 config->type = PHYLINK_NETDEV;
264 config->mac_capabilities = MAC_10000FD | MAC_1000FD | MAC_100FD |
265 MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
267 if (wx->media_type == sp_media_copper) {
268 phy_mode = PHY_INTERFACE_MODE_XAUI;
269 __set_bit(PHY_INTERFACE_MODE_XAUI, config->supported_interfaces);
271 phy_mode = PHY_INTERFACE_MODE_10GBASER;
272 fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_PHYLINK]);
273 __set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces);
274 __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces);
275 __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces);
278 phylink = phylink_create(config, fwnode, phy_mode, &txgbe_mac_ops);
280 return PTR_ERR(phylink);
285 ret = phylink_connect_phy(phylink, wx->phydev);
287 phylink_destroy(phylink);
292 wx->phylink = phylink;
297 static int txgbe_gpio_get(struct gpio_chip *chip, unsigned int offset)
299 struct wx *wx = gpiochip_get_data(chip);
302 val = rd32m(wx, WX_GPIO_EXT, BIT(offset));
304 return !!(val & BIT(offset));
307 static int txgbe_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
309 struct wx *wx = gpiochip_get_data(chip);
312 val = rd32(wx, WX_GPIO_DDR);
313 if (BIT(offset) & val)
314 return GPIO_LINE_DIRECTION_OUT;
316 return GPIO_LINE_DIRECTION_IN;
319 static int txgbe_gpio_direction_in(struct gpio_chip *chip, unsigned int offset)
321 struct wx *wx = gpiochip_get_data(chip);
324 raw_spin_lock_irqsave(&wx->gpio_lock, flags);
325 wr32m(wx, WX_GPIO_DDR, BIT(offset), 0);
326 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
331 static int txgbe_gpio_direction_out(struct gpio_chip *chip, unsigned int offset,
334 struct wx *wx = gpiochip_get_data(chip);
338 set = val ? BIT(offset) : 0;
340 raw_spin_lock_irqsave(&wx->gpio_lock, flags);
341 wr32m(wx, WX_GPIO_DR, BIT(offset), set);
342 wr32m(wx, WX_GPIO_DDR, BIT(offset), BIT(offset));
343 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
348 static void txgbe_gpio_irq_ack(struct irq_data *d)
350 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
351 irq_hw_number_t hwirq = irqd_to_hwirq(d);
352 struct wx *wx = gpiochip_get_data(gc);
355 raw_spin_lock_irqsave(&wx->gpio_lock, flags);
356 wr32(wx, WX_GPIO_EOI, BIT(hwirq));
357 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
360 static void txgbe_gpio_irq_mask(struct irq_data *d)
362 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
363 irq_hw_number_t hwirq = irqd_to_hwirq(d);
364 struct wx *wx = gpiochip_get_data(gc);
367 gpiochip_disable_irq(gc, hwirq);
369 raw_spin_lock_irqsave(&wx->gpio_lock, flags);
370 wr32m(wx, WX_GPIO_INTMASK, BIT(hwirq), BIT(hwirq));
371 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
374 static void txgbe_gpio_irq_unmask(struct irq_data *d)
376 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
377 irq_hw_number_t hwirq = irqd_to_hwirq(d);
378 struct wx *wx = gpiochip_get_data(gc);
381 gpiochip_enable_irq(gc, hwirq);
383 raw_spin_lock_irqsave(&wx->gpio_lock, flags);
384 wr32m(wx, WX_GPIO_INTMASK, BIT(hwirq), 0);
385 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
388 static void txgbe_toggle_trigger(struct gpio_chip *gc, unsigned int offset)
390 struct wx *wx = gpiochip_get_data(gc);
393 pol = rd32(wx, WX_GPIO_POLARITY);
394 val = rd32(wx, WX_GPIO_EXT);
396 if (val & BIT(offset))
401 wr32(wx, WX_GPIO_POLARITY, pol);
404 static int txgbe_gpio_set_type(struct irq_data *d, unsigned int type)
406 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
407 irq_hw_number_t hwirq = irqd_to_hwirq(d);
408 struct wx *wx = gpiochip_get_data(gc);
409 u32 level, polarity, mask;
414 if (type & IRQ_TYPE_LEVEL_MASK) {
416 irq_set_handler_locked(d, handle_level_irq);
419 irq_set_handler_locked(d, handle_edge_irq);
422 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
427 raw_spin_lock_irqsave(&wx->gpio_lock, flags);
429 wr32m(wx, WX_GPIO_INTEN, mask, mask);
430 wr32m(wx, WX_GPIO_INTTYPE_LEVEL, mask, level);
431 if (type == IRQ_TYPE_EDGE_BOTH)
432 txgbe_toggle_trigger(gc, hwirq);
434 wr32m(wx, WX_GPIO_POLARITY, mask, polarity);
436 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
441 static const struct irq_chip txgbe_gpio_irq_chip = {
442 .name = "txgbe_gpio_irq",
443 .irq_ack = txgbe_gpio_irq_ack,
444 .irq_mask = txgbe_gpio_irq_mask,
445 .irq_unmask = txgbe_gpio_irq_unmask,
446 .irq_set_type = txgbe_gpio_set_type,
447 .flags = IRQCHIP_IMMUTABLE,
448 GPIOCHIP_IRQ_RESOURCE_HELPERS,
451 static void txgbe_irq_handler(struct irq_desc *desc)
453 struct irq_chip *chip = irq_desc_get_chip(desc);
454 struct wx *wx = irq_desc_get_handler_data(desc);
455 struct txgbe *txgbe = wx->priv;
456 irq_hw_number_t hwirq;
457 unsigned long gpioirq;
458 struct gpio_chip *gc;
462 eicr = wx_misc_isb(wx, WX_ISB_MISC);
464 chained_irq_enter(chip, desc);
466 gpioirq = rd32(wx, WX_GPIO_INTSTATUS);
469 for_each_set_bit(hwirq, &gpioirq, gc->ngpio) {
470 int gpio = irq_find_mapping(gc->irq.domain, hwirq);
471 u32 irq_type = irq_get_trigger_type(gpio);
473 generic_handle_domain_irq(gc->irq.domain, hwirq);
475 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
476 raw_spin_lock_irqsave(&wx->gpio_lock, flags);
477 txgbe_toggle_trigger(gc, hwirq);
478 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
482 chained_irq_exit(chip, desc);
484 if (eicr & (TXGBE_PX_MISC_ETH_LK | TXGBE_PX_MISC_ETH_LKDN |
485 TXGBE_PX_MISC_ETH_AN)) {
486 u32 reg = rd32(wx, TXGBE_CFG_PORT_ST);
488 phylink_mac_change(wx->phylink, !!(reg & TXGBE_CFG_PORT_ST_LINK_UP));
491 /* unmask interrupt */
492 wx_intr_enable(wx, TXGBE_INTR_MISC);
495 static int txgbe_gpio_init(struct txgbe *txgbe)
497 struct gpio_irq_chip *girq;
498 struct gpio_chip *gc;
504 dev = &wx->pdev->dev;
506 raw_spin_lock_init(&wx->gpio_lock);
508 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
512 gc->label = devm_kasprintf(dev, GFP_KERNEL, "txgbe_gpio-%x",
513 pci_dev_id(wx->pdev));
519 gc->owner = THIS_MODULE;
521 gc->fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_GPIO]);
522 gc->get = txgbe_gpio_get;
523 gc->get_direction = txgbe_gpio_get_direction;
524 gc->direction_input = txgbe_gpio_direction_in;
525 gc->direction_output = txgbe_gpio_direction_out;
528 gpio_irq_chip_set_chip(girq, &txgbe_gpio_irq_chip);
529 girq->parent_handler = txgbe_irq_handler;
530 girq->parent_handler_data = wx;
531 girq->num_parents = 1;
532 girq->parents = devm_kcalloc(dev, girq->num_parents,
533 sizeof(*girq->parents), GFP_KERNEL);
537 /* now only suuported on MSI-X interrupt */
541 girq->parents[0] = wx->msix_entry->vector;
542 girq->default_type = IRQ_TYPE_NONE;
543 girq->handler = handle_bad_irq;
545 ret = devm_gpiochip_add_data(dev, gc, wx);
554 static int txgbe_clock_register(struct txgbe *txgbe)
556 struct pci_dev *pdev = txgbe->wx->pdev;
557 struct clk_lookup *clock;
561 snprintf(clk_name, sizeof(clk_name), "%s.%d",
562 TXGBE_I2C_CLK_DEV_NAME, pci_dev_id(pdev));
564 clk = clk_register_fixed_rate(NULL, clk_name, NULL, 0, 156250000);
568 clock = clkdev_create(clk, NULL, clk_name);
575 txgbe->clock = clock;
580 static int txgbe_i2c_read(void *context, unsigned int reg, unsigned int *val)
582 struct wx *wx = context;
584 *val = rd32(wx, reg + TXGBE_I2C_BASE);
589 static int txgbe_i2c_write(void *context, unsigned int reg, unsigned int val)
591 struct wx *wx = context;
593 wr32(wx, reg + TXGBE_I2C_BASE, val);
598 static const struct regmap_config i2c_regmap_config = {
601 .reg_read = txgbe_i2c_read,
602 .reg_write = txgbe_i2c_write,
606 static int txgbe_i2c_register(struct txgbe *txgbe)
608 struct platform_device_info info = {};
609 struct platform_device *i2c_dev;
610 struct regmap *i2c_regmap;
611 struct pci_dev *pdev;
616 i2c_regmap = devm_regmap_init(&pdev->dev, NULL, wx, &i2c_regmap_config);
617 if (IS_ERR(i2c_regmap)) {
618 wx_err(wx, "failed to init I2C regmap\n");
619 return PTR_ERR(i2c_regmap);
622 info.parent = &pdev->dev;
623 info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_I2C]);
624 info.name = TXGBE_I2C_CLK_DEV_NAME;
625 info.id = pci_dev_id(pdev);
627 info.res = &DEFINE_RES_IRQ(pdev->irq);
629 i2c_dev = platform_device_register_full(&info);
631 return PTR_ERR(i2c_dev);
633 txgbe->i2c_dev = i2c_dev;
638 static int txgbe_sfp_register(struct txgbe *txgbe)
640 struct pci_dev *pdev = txgbe->wx->pdev;
641 struct platform_device_info info = {};
642 struct platform_device *sfp_dev;
644 info.parent = &pdev->dev;
645 info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_SFP]);
647 info.id = pci_dev_id(pdev);
648 sfp_dev = platform_device_register_full(&info);
650 return PTR_ERR(sfp_dev);
652 txgbe->sfp_dev = sfp_dev;
657 static int txgbe_ext_phy_init(struct txgbe *txgbe)
659 struct phy_device *phydev;
660 struct mii_bus *mii_bus;
661 struct pci_dev *pdev;
668 mii_bus = devm_mdiobus_alloc(&pdev->dev);
672 mii_bus->name = "txgbe_mii_bus";
673 mii_bus->read_c45 = &wx_phy_read_reg_mdi_c45;
674 mii_bus->write_c45 = &wx_phy_write_reg_mdi_c45;
675 mii_bus->parent = &pdev->dev;
676 mii_bus->phy_mask = GENMASK(31, 1);
678 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe-%x",
679 (pdev->bus->number << 8) | pdev->devfn);
681 ret = devm_mdiobus_register(&pdev->dev, mii_bus);
683 wx_err(wx, "failed to register MDIO bus: %d\n", ret);
687 phydev = phy_find_first(mii_bus);
689 wx_err(wx, "no PHY found\n");
693 phy_attached_info(phydev);
700 ret = txgbe_phylink_init(txgbe);
702 wx_err(wx, "failed to init phylink: %d\n", ret);
709 int txgbe_init_phy(struct txgbe *txgbe)
711 struct wx *wx = txgbe->wx;
714 if (txgbe->wx->media_type == sp_media_copper)
715 return txgbe_ext_phy_init(txgbe);
717 ret = txgbe_swnodes_register(txgbe);
719 wx_err(wx, "failed to register software nodes\n");
723 ret = txgbe_mdio_pcs_init(txgbe);
725 wx_err(wx, "failed to init mdio pcs: %d\n", ret);
726 goto err_unregister_swnode;
729 ret = txgbe_phylink_init(txgbe);
731 wx_err(wx, "failed to init phylink\n");
732 goto err_destroy_xpcs;
735 ret = txgbe_gpio_init(txgbe);
737 wx_err(wx, "failed to init gpio\n");
738 goto err_destroy_phylink;
741 ret = txgbe_clock_register(txgbe);
743 wx_err(wx, "failed to register clock: %d\n", ret);
744 goto err_destroy_phylink;
747 ret = txgbe_i2c_register(txgbe);
749 wx_err(wx, "failed to init i2c interface: %d\n", ret);
750 goto err_unregister_clk;
753 ret = txgbe_sfp_register(txgbe);
755 wx_err(wx, "failed to register sfp\n");
756 goto err_unregister_i2c;
759 wx->msix_in_use = true;
764 platform_device_unregister(txgbe->i2c_dev);
766 clkdev_drop(txgbe->clock);
767 clk_unregister(txgbe->clk);
769 phylink_destroy(wx->phylink);
771 xpcs_destroy(txgbe->xpcs);
772 err_unregister_swnode:
773 software_node_unregister_node_group(txgbe->nodes.group);
778 void txgbe_remove_phy(struct txgbe *txgbe)
780 if (txgbe->wx->media_type == sp_media_copper) {
781 phylink_disconnect_phy(txgbe->wx->phylink);
782 phylink_destroy(txgbe->wx->phylink);
786 platform_device_unregister(txgbe->sfp_dev);
787 platform_device_unregister(txgbe->i2c_dev);
788 clkdev_drop(txgbe->clock);
789 clk_unregister(txgbe->clk);
790 phylink_destroy(txgbe->wx->phylink);
791 xpcs_destroy(txgbe->xpcs);
792 software_node_unregister_node_group(txgbe->nodes.group);
793 txgbe->wx->msix_in_use = false;