1 /* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
3 Written 1998-2001 by Donald Becker.
5 Current Maintainer: Kevin Brace <kevinbrace@bracecomputerlab.com>
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
14 This driver is designed for the VIA VT86C100A Rhine-I.
15 It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
16 and management NIC 6105M).
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
24 This driver contains some changes from the original Donald Becker
25 version. He may or may not be interested in bug reports on this
26 code. You can find his versions at:
27 http://www.scyld.com/network/via-rhine.html
28 [link no longer provides useful info -jgarzik]
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34 #define DRV_NAME "via-rhine"
36 #include <linux/types.h>
38 /* A few user-configurable values.
39 These may be modified when a driver module is loaded. */
41 #define RHINE_MSG_DEFAULT \
44 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
45 Setting to > 1518 effectively disables this feature. */
46 #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \
47 defined(CONFIG_SPARC) || defined(__ia64__) || \
48 defined(__sh__) || defined(__mips__)
49 static int rx_copybreak = 1518;
51 static int rx_copybreak;
54 /* Work-around for broken BIOSes: they are unable to get the chip back out of
55 power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */
59 * In case you are looking for 'options[]' or 'full_duplex[]', they
60 * are gone. Use ethtool(8) instead.
63 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
64 The Rhine has a 64 element 8390-like hash table. */
65 static const int multicast_filter_limit = 32;
68 /* Operational parameters that are set at compile time. */
70 /* Keep the ring sizes a power of two for compile efficiency.
71 * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
72 * Making the Tx ring too large decreases the effectiveness of channel
73 * bonding and packet priority.
74 * With BQL support, we can increase TX ring safely.
75 * There are no ill effects from too-large receive rings.
77 #define TX_RING_SIZE 64
78 #define TX_QUEUE_LEN (TX_RING_SIZE - 6) /* Limit ring entries actually used. */
79 #define RX_RING_SIZE 64
81 /* Operational parameters that usually are not changed. */
83 /* Time in jiffies before concluding the transmitter is hung. */
84 #define TX_TIMEOUT (2*HZ)
86 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
88 #include <linux/module.h>
89 #include <linux/moduleparam.h>
90 #include <linux/kernel.h>
91 #include <linux/string.h>
92 #include <linux/timer.h>
93 #include <linux/errno.h>
94 #include <linux/ioport.h>
95 #include <linux/interrupt.h>
96 #include <linux/pci.h>
97 #include <linux/of_device.h>
98 #include <linux/of_irq.h>
99 #include <linux/platform_device.h>
100 #include <linux/dma-mapping.h>
101 #include <linux/netdevice.h>
102 #include <linux/etherdevice.h>
103 #include <linux/skbuff.h>
104 #include <linux/init.h>
105 #include <linux/delay.h>
106 #include <linux/mii.h>
107 #include <linux/ethtool.h>
108 #include <linux/crc32.h>
109 #include <linux/if_vlan.h>
110 #include <linux/bitops.h>
111 #include <linux/workqueue.h>
112 #include <asm/processor.h> /* Processor type for cache alignment. */
115 #include <linux/uaccess.h>
116 #include <linux/dmi.h>
118 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
119 MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
120 MODULE_LICENSE("GPL");
122 module_param(debug, int, 0);
123 module_param(rx_copybreak, int, 0);
124 module_param(avoid_D3, bool, 0);
125 MODULE_PARM_DESC(debug, "VIA Rhine debug message flags");
126 MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
127 MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");
135 I. Board Compatibility
137 This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
140 II. Board-specific settings
142 Boards with this chip are functional only in a bus-master PCI slot.
144 Many operational settings are loaded from the EEPROM to the Config word at
145 offset 0x78. For most of these settings, this driver assumes that they are
147 If this driver is compiled to use PCI memory space operations the EEPROM
148 must be configured to enable memory ops.
150 III. Driver operation
154 This driver uses two statically allocated fixed-size descriptor lists
155 formed into rings by a branch from the final descriptor to the beginning of
156 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
158 IIIb/c. Transmit/Receive Structure
160 This driver attempts to use a zero-copy receive and transmit scheme.
162 Alas, all data buffers are required to start on a 32 bit boundary, so
163 the driver must often copy transmit packets into bounce buffers.
165 The driver allocates full frame size skbuffs for the Rx ring buffers at
166 open() time and passes the skb->data field to the chip as receive data
167 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
168 a fresh skbuff is allocated and the frame is copied to the new skbuff.
169 When the incoming frame is larger, the skbuff is passed directly up the
170 protocol stack. Buffers consumed this way are replaced by newly allocated
171 skbuffs in the last phase of rhine_rx().
173 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
174 using a full-sized skbuff for small frames vs. the copying costs of larger
175 frames. New boards are typically used in generously configured machines
176 and the underfilled buffers have negligible impact compared to the benefit of
177 a single allocation size, so the default value of zero results in never
178 copying packets. When copying is done, the cost is usually mitigated by using
179 a combined copy/checksum routine. Copying also preloads the cache, which is
180 most useful with small frames.
182 Since the VIA chips are only able to transfer data to buffers on 32 bit
183 boundaries, the IP header at offset 14 in an ethernet frame isn't
184 longword aligned for further processing. Copying these unaligned buffers
185 has the beneficial effect of 16-byte aligning the IP header.
187 IIId. Synchronization
189 The driver runs as two independent, single-threaded flows of control. One
190 is the send-packet routine, which enforces single-threaded use by the
191 netdev_priv(dev)->lock spinlock. The other thread is the interrupt handler,
192 which is single threaded by the hardware and interrupt handling software.
194 The send packet thread has partial control over the Tx ring. It locks the
195 netdev_priv(dev)->lock whenever it's queuing a Tx packet. If the next slot in
196 the ring is not available it stops the transmit queue by
197 calling netif_stop_queue.
199 The interrupt handler has exclusive control over the Rx ring and records stats
200 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
201 empty by incrementing the dirty_tx mark. If at least half of the entries in
202 the Rx ring are available the transmit queue is woken up if it was stopped.
208 Preliminary VT86C100A manual from http://www.via.com.tw/
209 http://www.scyld.com/expert/100mbps.html
210 http://www.scyld.com/expert/NWay.html
211 ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
212 ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
217 The VT86C100A manual is not reliable information.
218 The 3043 chip does not handle unaligned transmit or receive buffers, resulting
219 in significant performance degradation for bounce buffer copies on transmit
220 and unaligned IP headers on receive.
221 The chip does not pad to minimum transmit length.
226 /* This table drives the PCI probe routines. It's mostly boilerplate in all
227 of the drivers, and will likely be provided by some future kernel.
228 Note the matching code -- the first table entry matchs all 56** cards but
229 second only the 1234 card.
236 VT8231 = 0x50, /* Integrated MAC */
237 VT8233 = 0x60, /* Integrated MAC */
238 VT8235 = 0x74, /* Integrated MAC */
239 VT8237 = 0x78, /* Integrated MAC */
240 VT8251 = 0x7C, /* Integrated MAC */
246 VT6105M = 0x90, /* Management adapter */
250 rqWOL = 0x0001, /* Wake-On-LAN support */
251 rqForceReset = 0x0002,
252 rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */
253 rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */
254 rqRhineI = 0x0100, /* See comment below */
255 rqIntPHY = 0x0200, /* Integrated PHY */
256 rqMgmt = 0x0400, /* Management adapter */
257 rqNeedEnMMIO = 0x0800, /* Whether the core needs to be
258 * switched from PIO mode to MMIO
259 * (only applies to PCI)
263 * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
264 * MMIO as well as for the collision counter and the Tx FIFO underflow
265 * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
268 /* Beware of PCI posted writes */
269 #define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
271 static const struct pci_device_id rhine_pci_tbl[] = {
272 { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */
273 { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */
274 { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */
275 { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */
276 { } /* terminate list */
278 MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
280 /* OpenFirmware identifiers for platform-bus devices
281 * The .data field is currently only used to store quirks
283 static u32 vt8500_quirks = rqWOL | rqForceReset | rq6patterns;
284 static const struct of_device_id rhine_of_tbl[] = {
285 { .compatible = "via,vt8500-rhine", .data = &vt8500_quirks },
286 { } /* terminate list */
288 MODULE_DEVICE_TABLE(of, rhine_of_tbl);
290 /* Offsets to the device registers. */
291 enum register_offsets {
292 StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
293 ChipCmd1=0x09, TQWake=0x0A,
294 IntrStatus=0x0C, IntrEnable=0x0E,
295 MulticastFilter0=0x10, MulticastFilter1=0x14,
296 RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
297 MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E, PCIBusConfig1=0x6F,
298 MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
299 ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
300 RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
301 StickyHW=0x83, IntrStatus2=0x84,
302 CamMask=0x88, CamCon=0x92, CamAddr=0x93,
303 WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
304 WOLcrClr1=0xA6, WOLcgClr=0xA7,
305 PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
308 /* Bits in ConfigD */
310 BackOptional=0x01, BackModify=0x02,
311 BackCaptureEffect=0x04, BackRandom=0x08
314 /* Bits in the TxConfig (TCR) register */
317 TCR_LB0=0x02, /* loopback[0] */
318 TCR_LB1=0x04, /* loopback[1] */
326 /* Bits in the CamCon (CAMC) register */
334 /* Bits in the PCIBusConfig1 (BCR1) register */
342 BCR1_TXQNOBK=0x40, /* for VT6105 */
343 BCR1_VIDFR=0x80, /* for VT6105 */
344 BCR1_MED0=0x40, /* for VT6102 */
345 BCR1_MED1=0x80, /* for VT6102 */
348 /* Registers we check that mmio and reg are the same. */
349 static const int mmio_verify_registers[] = {
350 RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
354 /* Bits in the interrupt status/mask registers. */
355 enum intr_status_bits {
359 IntrTxError = 0x0008,
360 IntrRxEmpty = 0x0020,
362 IntrStatsMax = 0x0080,
363 IntrRxEarly = 0x0100,
364 IntrTxUnderrun = 0x0210,
365 IntrRxOverflow = 0x0400,
366 IntrRxDropped = 0x0800,
367 IntrRxNoBuf = 0x1000,
368 IntrTxAborted = 0x2000,
369 IntrLinkChange = 0x4000,
370 IntrRxWakeUp = 0x8000,
371 IntrTxDescRace = 0x080000, /* mapped from IntrStatus2 */
372 IntrNormalSummary = IntrRxDone | IntrTxDone,
373 IntrTxErrSummary = IntrTxDescRace | IntrTxAborted | IntrTxError |
377 /* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
386 /* The Rx and Tx buffer descriptors. */
389 __le32 desc_length; /* Chain flag, Buffer/frame length */
395 __le32 desc_length; /* Chain flag, Tx Config, Frame length */
400 /* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
401 #define TXDESC 0x00e08000
403 enum rx_status_bits {
404 RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
407 /* Bits in *_desc.*_status */
408 enum desc_status_bits {
412 /* Bits in *_desc.*_length */
413 enum desc_length_bits {
417 /* Bits in ChipCmd. */
419 CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
420 CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
421 Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
422 Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
428 struct u64_stats_sync syncp;
431 struct rhine_private {
432 /* Bit mask for configured VLAN ids */
433 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
435 /* Descriptor rings */
436 struct rx_desc *rx_ring;
437 struct tx_desc *tx_ring;
438 dma_addr_t rx_ring_dma;
439 dma_addr_t tx_ring_dma;
441 /* The addresses of receive-in-place skbuffs. */
442 struct sk_buff *rx_skbuff[RX_RING_SIZE];
443 dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
445 /* The saved address of a sent-in-place packet/buffer, for later free(). */
446 struct sk_buff *tx_skbuff[TX_RING_SIZE];
447 dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
449 /* Tx bounce buffers (Rhine-I only) */
450 unsigned char *tx_buf[TX_RING_SIZE];
451 unsigned char *tx_bufs;
452 dma_addr_t tx_bufs_dma;
456 struct net_device *dev;
457 struct napi_struct napi;
459 struct mutex task_lock;
461 struct work_struct slow_event_task;
462 struct work_struct reset_task;
466 /* Frequently used values: keep some adjacent for cache effect. */
469 unsigned int cur_tx, dirty_tx;
470 unsigned int rx_buf_sz; /* Based on MTU+slack. */
471 struct rhine_stats rx_stats;
472 struct rhine_stats tx_stats;
475 u8 tx_thresh, rx_thresh;
477 struct mii_if_info mii_if;
481 #define BYTE_REG_BITS_ON(x, p) do { iowrite8((ioread8((p))|(x)), (p)); } while (0)
482 #define WORD_REG_BITS_ON(x, p) do { iowrite16((ioread16((p))|(x)), (p)); } while (0)
483 #define DWORD_REG_BITS_ON(x, p) do { iowrite32((ioread32((p))|(x)), (p)); } while (0)
485 #define BYTE_REG_BITS_IS_ON(x, p) (ioread8((p)) & (x))
486 #define WORD_REG_BITS_IS_ON(x, p) (ioread16((p)) & (x))
487 #define DWORD_REG_BITS_IS_ON(x, p) (ioread32((p)) & (x))
489 #define BYTE_REG_BITS_OFF(x, p) do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0)
490 #define WORD_REG_BITS_OFF(x, p) do { iowrite16(ioread16((p)) & (~(x)), (p)); } while (0)
491 #define DWORD_REG_BITS_OFF(x, p) do { iowrite32(ioread32((p)) & (~(x)), (p)); } while (0)
493 #define BYTE_REG_BITS_SET(x, m, p) do { iowrite8((ioread8((p)) & (~(m)))|(x), (p)); } while (0)
494 #define WORD_REG_BITS_SET(x, m, p) do { iowrite16((ioread16((p)) & (~(m)))|(x), (p)); } while (0)
495 #define DWORD_REG_BITS_SET(x, m, p) do { iowrite32((ioread32((p)) & (~(m)))|(x), (p)); } while (0)
498 static int mdio_read(struct net_device *dev, int phy_id, int location);
499 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
500 static int rhine_open(struct net_device *dev);
501 static void rhine_reset_task(struct work_struct *work);
502 static void rhine_slow_event_task(struct work_struct *work);
503 static void rhine_tx_timeout(struct net_device *dev, unsigned int txqueue);
504 static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
505 struct net_device *dev);
506 static irqreturn_t rhine_interrupt(int irq, void *dev_instance);
507 static void rhine_tx(struct net_device *dev);
508 static int rhine_rx(struct net_device *dev, int limit);
509 static void rhine_set_rx_mode(struct net_device *dev);
510 static void rhine_get_stats64(struct net_device *dev,
511 struct rtnl_link_stats64 *stats);
512 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
513 static const struct ethtool_ops netdev_ethtool_ops;
514 static int rhine_close(struct net_device *dev);
515 static int rhine_vlan_rx_add_vid(struct net_device *dev,
516 __be16 proto, u16 vid);
517 static int rhine_vlan_rx_kill_vid(struct net_device *dev,
518 __be16 proto, u16 vid);
519 static void rhine_restart_tx(struct net_device *dev);
521 static void rhine_wait_bit(struct rhine_private *rp, u8 reg, u8 mask, bool low)
523 void __iomem *ioaddr = rp->base;
526 for (i = 0; i < 1024; i++) {
527 bool has_mask_bits = !!(ioread8(ioaddr + reg) & mask);
529 if (low ^ has_mask_bits)
534 netif_dbg(rp, hw, rp->dev, "%s bit wait (%02x/%02x) cycle "
535 "count: %04d\n", low ? "low" : "high", reg, mask, i);
539 static void rhine_wait_bit_high(struct rhine_private *rp, u8 reg, u8 mask)
541 rhine_wait_bit(rp, reg, mask, false);
544 static void rhine_wait_bit_low(struct rhine_private *rp, u8 reg, u8 mask)
546 rhine_wait_bit(rp, reg, mask, true);
549 static u32 rhine_get_events(struct rhine_private *rp)
551 void __iomem *ioaddr = rp->base;
554 intr_status = ioread16(ioaddr + IntrStatus);
555 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
556 if (rp->quirks & rqStatusWBRace)
557 intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
561 static void rhine_ack_events(struct rhine_private *rp, u32 mask)
563 void __iomem *ioaddr = rp->base;
565 if (rp->quirks & rqStatusWBRace)
566 iowrite8(mask >> 16, ioaddr + IntrStatus2);
567 iowrite16(mask, ioaddr + IntrStatus);
571 * Get power related registers into sane state.
572 * Notify user about past WOL event.
574 static void rhine_power_init(struct net_device *dev)
576 struct rhine_private *rp = netdev_priv(dev);
577 void __iomem *ioaddr = rp->base;
580 if (rp->quirks & rqWOL) {
581 /* Make sure chip is in power state D0 */
582 iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
584 /* Disable "force PME-enable" */
585 iowrite8(0x80, ioaddr + WOLcgClr);
587 /* Clear power-event config bits (WOL) */
588 iowrite8(0xFF, ioaddr + WOLcrClr);
589 /* More recent cards can manage two additional patterns */
590 if (rp->quirks & rq6patterns)
591 iowrite8(0x03, ioaddr + WOLcrClr1);
593 /* Save power-event status bits */
594 wolstat = ioread8(ioaddr + PwrcsrSet);
595 if (rp->quirks & rq6patterns)
596 wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
598 /* Clear power-event status bits */
599 iowrite8(0xFF, ioaddr + PwrcsrClr);
600 if (rp->quirks & rq6patterns)
601 iowrite8(0x03, ioaddr + PwrcsrClr1);
607 reason = "Magic packet";
610 reason = "Link went up";
613 reason = "Link went down";
616 reason = "Unicast packet";
619 reason = "Multicast/broadcast packet";
624 netdev_info(dev, "Woke system up. Reason: %s\n",
630 static void rhine_chip_reset(struct net_device *dev)
632 struct rhine_private *rp = netdev_priv(dev);
633 void __iomem *ioaddr = rp->base;
636 iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
639 if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
640 netdev_info(dev, "Reset not complete yet. Trying harder.\n");
643 if (rp->quirks & rqForceReset)
644 iowrite8(0x40, ioaddr + MiscCmd);
646 /* Reset can take somewhat longer (rare) */
647 rhine_wait_bit_low(rp, ChipCmd1, Cmd1Reset);
650 cmd1 = ioread8(ioaddr + ChipCmd1);
651 netif_info(rp, hw, dev, "Reset %s\n", (cmd1 & Cmd1Reset) ?
652 "failed" : "succeeded");
655 static void enable_mmio(long pioaddr, u32 quirks)
659 if (quirks & rqNeedEnMMIO) {
660 if (quirks & rqRhineI) {
661 /* More recent docs say that this bit is reserved */
662 n = inb(pioaddr + ConfigA) | 0x20;
663 outb(n, pioaddr + ConfigA);
665 n = inb(pioaddr + ConfigD) | 0x80;
666 outb(n, pioaddr + ConfigD);
671 static inline int verify_mmio(struct device *hwdev,
673 void __iomem *ioaddr,
676 if (quirks & rqNeedEnMMIO) {
679 /* Check that selected MMIO registers match the PIO ones */
680 while (mmio_verify_registers[i]) {
681 int reg = mmio_verify_registers[i++];
682 unsigned char a = inb(pioaddr+reg);
683 unsigned char b = readb(ioaddr+reg);
687 "MMIO do not match PIO [%02x] (%02x != %02x)\n",
697 * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
698 * (plus 0x6C for Rhine-I/II)
700 static void rhine_reload_eeprom(long pioaddr, struct net_device *dev)
702 struct rhine_private *rp = netdev_priv(dev);
703 void __iomem *ioaddr = rp->base;
706 outb(0x20, pioaddr + MACRegEEcsr);
707 for (i = 0; i < 1024; i++) {
708 if (!(inb(pioaddr + MACRegEEcsr) & 0x20))
712 pr_info("%4d cycles used @ %s:%d\n", i, __func__, __LINE__);
715 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
716 * MMIO. If reloading EEPROM was done first this could be avoided, but
717 * it is not known if that still works with the "win98-reboot" problem.
719 enable_mmio(pioaddr, rp->quirks);
721 /* Turn off EEPROM-controlled wake-up (magic packet) */
722 if (rp->quirks & rqWOL)
723 iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
727 #ifdef CONFIG_NET_POLL_CONTROLLER
728 static void rhine_poll(struct net_device *dev)
730 struct rhine_private *rp = netdev_priv(dev);
731 const int irq = rp->irq;
734 rhine_interrupt(irq, dev);
739 static void rhine_kick_tx_threshold(struct rhine_private *rp)
741 if (rp->tx_thresh < 0xe0) {
742 void __iomem *ioaddr = rp->base;
744 rp->tx_thresh += 0x20;
745 BYTE_REG_BITS_SET(rp->tx_thresh, 0x80, ioaddr + TxConfig);
749 static void rhine_tx_err(struct rhine_private *rp, u32 status)
751 struct net_device *dev = rp->dev;
753 if (status & IntrTxAborted) {
754 netif_info(rp, tx_err, dev,
755 "Abort %08x, frame dropped\n", status);
758 if (status & IntrTxUnderrun) {
759 rhine_kick_tx_threshold(rp);
760 netif_info(rp, tx_err ,dev, "Transmitter underrun, "
761 "Tx threshold now %02x\n", rp->tx_thresh);
764 if (status & IntrTxDescRace)
765 netif_info(rp, tx_err, dev, "Tx descriptor write-back race\n");
767 if ((status & IntrTxError) &&
768 (status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace)) == 0) {
769 rhine_kick_tx_threshold(rp);
770 netif_info(rp, tx_err, dev, "Unspecified error. "
771 "Tx threshold now %02x\n", rp->tx_thresh);
774 rhine_restart_tx(dev);
777 static void rhine_update_rx_crc_and_missed_errord(struct rhine_private *rp)
779 void __iomem *ioaddr = rp->base;
780 struct net_device_stats *stats = &rp->dev->stats;
782 stats->rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
783 stats->rx_missed_errors += ioread16(ioaddr + RxMissed);
786 * Clears the "tally counters" for CRC errors and missed frames(?).
787 * It has been reported that some chips need a write of 0 to clear
788 * these, for others the counters are set to 1 when written to and
789 * instead cleared when read. So we clear them both ways ...
791 iowrite32(0, ioaddr + RxMissed);
792 ioread16(ioaddr + RxCRCErrs);
793 ioread16(ioaddr + RxMissed);
796 #define RHINE_EVENT_NAPI_RX (IntrRxDone | \
804 #define RHINE_EVENT_NAPI_TX_ERR (IntrTxError | \
808 #define RHINE_EVENT_NAPI_TX (IntrTxDone | RHINE_EVENT_NAPI_TX_ERR)
810 #define RHINE_EVENT_NAPI (RHINE_EVENT_NAPI_RX | \
811 RHINE_EVENT_NAPI_TX | \
813 #define RHINE_EVENT_SLOW (IntrPCIErr | IntrLinkChange)
814 #define RHINE_EVENT (RHINE_EVENT_NAPI | RHINE_EVENT_SLOW)
816 static int rhine_napipoll(struct napi_struct *napi, int budget)
818 struct rhine_private *rp = container_of(napi, struct rhine_private, napi);
819 struct net_device *dev = rp->dev;
820 void __iomem *ioaddr = rp->base;
821 u16 enable_mask = RHINE_EVENT & 0xffff;
825 status = rhine_get_events(rp);
826 rhine_ack_events(rp, status & ~RHINE_EVENT_SLOW);
828 if (status & RHINE_EVENT_NAPI_RX)
829 work_done += rhine_rx(dev, budget);
831 if (status & RHINE_EVENT_NAPI_TX) {
832 if (status & RHINE_EVENT_NAPI_TX_ERR) {
833 /* Avoid scavenging before Tx engine turned off */
834 rhine_wait_bit_low(rp, ChipCmd, CmdTxOn);
835 if (ioread8(ioaddr + ChipCmd) & CmdTxOn)
836 netif_warn(rp, tx_err, dev, "Tx still on\n");
841 if (status & RHINE_EVENT_NAPI_TX_ERR)
842 rhine_tx_err(rp, status);
845 if (status & IntrStatsMax) {
846 spin_lock(&rp->lock);
847 rhine_update_rx_crc_and_missed_errord(rp);
848 spin_unlock(&rp->lock);
851 if (status & RHINE_EVENT_SLOW) {
852 enable_mask &= ~RHINE_EVENT_SLOW;
853 schedule_work(&rp->slow_event_task);
856 if (work_done < budget) {
857 napi_complete_done(napi, work_done);
858 iowrite16(enable_mask, ioaddr + IntrEnable);
863 static void rhine_hw_init(struct net_device *dev, long pioaddr)
865 struct rhine_private *rp = netdev_priv(dev);
867 /* Reset the chip to erase previous misconfiguration. */
868 rhine_chip_reset(dev);
870 /* Rhine-I needs extra time to recuperate before EEPROM reload */
871 if (rp->quirks & rqRhineI)
874 /* Reload EEPROM controlled bytes cleared by soft reset */
875 if (dev_is_pci(dev->dev.parent))
876 rhine_reload_eeprom(pioaddr, dev);
879 static const struct net_device_ops rhine_netdev_ops = {
880 .ndo_open = rhine_open,
881 .ndo_stop = rhine_close,
882 .ndo_start_xmit = rhine_start_tx,
883 .ndo_get_stats64 = rhine_get_stats64,
884 .ndo_set_rx_mode = rhine_set_rx_mode,
885 .ndo_validate_addr = eth_validate_addr,
886 .ndo_set_mac_address = eth_mac_addr,
887 .ndo_do_ioctl = netdev_ioctl,
888 .ndo_tx_timeout = rhine_tx_timeout,
889 .ndo_vlan_rx_add_vid = rhine_vlan_rx_add_vid,
890 .ndo_vlan_rx_kill_vid = rhine_vlan_rx_kill_vid,
891 #ifdef CONFIG_NET_POLL_CONTROLLER
892 .ndo_poll_controller = rhine_poll,
896 static int rhine_init_one_common(struct device *hwdev, u32 quirks,
897 long pioaddr, void __iomem *ioaddr, int irq)
899 struct net_device *dev;
900 struct rhine_private *rp;
904 /* this should always be supported */
905 rc = dma_set_mask(hwdev, DMA_BIT_MASK(32));
907 dev_err(hwdev, "32-bit DMA addresses not supported by the card!?\n");
911 dev = alloc_etherdev(sizeof(struct rhine_private));
916 SET_NETDEV_DEV(dev, hwdev);
918 rp = netdev_priv(dev);
921 rp->pioaddr = pioaddr;
924 rp->msg_enable = netif_msg_init(debug, RHINE_MSG_DEFAULT);
926 phy_id = rp->quirks & rqIntPHY ? 1 : 0;
928 u64_stats_init(&rp->tx_stats.syncp);
929 u64_stats_init(&rp->rx_stats.syncp);
931 /* Get chip registers into a sane state */
932 rhine_power_init(dev);
933 rhine_hw_init(dev, pioaddr);
935 for (i = 0; i < 6; i++)
936 dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
938 if (!is_valid_ether_addr(dev->dev_addr)) {
939 /* Report it and use a random ethernet address instead */
940 netdev_err(dev, "Invalid MAC address: %pM\n", dev->dev_addr);
941 eth_hw_addr_random(dev);
942 netdev_info(dev, "Using random MAC address: %pM\n",
946 /* For Rhine-I/II, phy_id is loaded from EEPROM */
948 phy_id = ioread8(ioaddr + 0x6C);
950 spin_lock_init(&rp->lock);
951 mutex_init(&rp->task_lock);
952 INIT_WORK(&rp->reset_task, rhine_reset_task);
953 INIT_WORK(&rp->slow_event_task, rhine_slow_event_task);
955 rp->mii_if.dev = dev;
956 rp->mii_if.mdio_read = mdio_read;
957 rp->mii_if.mdio_write = mdio_write;
958 rp->mii_if.phy_id_mask = 0x1f;
959 rp->mii_if.reg_num_mask = 0x1f;
961 /* The chip-specific entries in the device structure. */
962 dev->netdev_ops = &rhine_netdev_ops;
963 dev->ethtool_ops = &netdev_ethtool_ops;
964 dev->watchdog_timeo = TX_TIMEOUT;
966 netif_napi_add(dev, &rp->napi, rhine_napipoll, 64);
968 if (rp->quirks & rqRhineI)
969 dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
971 if (rp->quirks & rqMgmt)
972 dev->features |= NETIF_F_HW_VLAN_CTAG_TX |
973 NETIF_F_HW_VLAN_CTAG_RX |
974 NETIF_F_HW_VLAN_CTAG_FILTER;
976 /* dev->name not defined before register_netdev()! */
977 rc = register_netdev(dev);
979 goto err_out_free_netdev;
981 if (rp->quirks & rqRhineI)
983 else if (rp->quirks & rqStatusWBRace)
985 else if (rp->quirks & rqMgmt)
986 name = "Rhine III (Management Adapter)";
990 netdev_info(dev, "VIA %s at %p, %pM, IRQ %d\n",
991 name, ioaddr, dev->dev_addr, rp->irq);
993 dev_set_drvdata(hwdev, dev);
997 int mii_status = mdio_read(dev, phy_id, 1);
998 mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
999 mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
1000 if (mii_status != 0xffff && mii_status != 0x0000) {
1001 rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
1003 "MII PHY found at address %d, status 0x%04x advertising %04x Link %04x\n",
1005 mii_status, rp->mii_if.advertising,
1006 mdio_read(dev, phy_id, 5));
1008 /* set IFF_RUNNING */
1009 if (mii_status & BMSR_LSTATUS)
1010 netif_carrier_on(dev);
1012 netif_carrier_off(dev);
1016 rp->mii_if.phy_id = phy_id;
1018 netif_info(rp, probe, dev, "No D3 power state at shutdown\n");
1022 err_out_free_netdev:
1028 static int rhine_init_one_pci(struct pci_dev *pdev,
1029 const struct pci_device_id *ent)
1031 struct device *hwdev = &pdev->dev;
1033 long pioaddr, memaddr;
1034 void __iomem *ioaddr;
1035 int io_size = pdev->revision < VTunknown0 ? 128 : 256;
1037 /* This driver was written to use PCI memory space. Some early versions
1038 * of the Rhine may only work correctly with I/O space accesses.
1039 * TODO: determine for which revisions this is true and assign the flag
1040 * in code as opposed to this Kconfig option (???)
1042 #ifdef CONFIG_VIA_RHINE_MMIO
1043 u32 quirks = rqNeedEnMMIO;
1048 rc = pci_enable_device(pdev);
1052 if (pdev->revision < VTunknown0) {
1054 } else if (pdev->revision >= VT6102) {
1055 quirks |= rqWOL | rqForceReset;
1056 if (pdev->revision < VT6105) {
1057 quirks |= rqStatusWBRace;
1060 if (pdev->revision >= VT6105_B0)
1061 quirks |= rq6patterns;
1062 if (pdev->revision >= VT6105M)
1068 if ((pci_resource_len(pdev, 0) < io_size) ||
1069 (pci_resource_len(pdev, 1) < io_size)) {
1071 dev_err(hwdev, "Insufficient PCI resources, aborting\n");
1072 goto err_out_pci_disable;
1075 pioaddr = pci_resource_start(pdev, 0);
1076 memaddr = pci_resource_start(pdev, 1);
1078 pci_set_master(pdev);
1080 rc = pci_request_regions(pdev, DRV_NAME);
1082 goto err_out_pci_disable;
1084 ioaddr = pci_iomap(pdev, (quirks & rqNeedEnMMIO ? 1 : 0), io_size);
1088 "ioremap failed for device %s, region 0x%X @ 0x%lX\n",
1089 dev_name(hwdev), io_size, memaddr);
1090 goto err_out_free_res;
1093 enable_mmio(pioaddr, quirks);
1095 rc = verify_mmio(hwdev, pioaddr, ioaddr, quirks);
1099 rc = rhine_init_one_common(&pdev->dev, quirks,
1100 pioaddr, ioaddr, pdev->irq);
1105 pci_iounmap(pdev, ioaddr);
1107 pci_release_regions(pdev);
1108 err_out_pci_disable:
1109 pci_disable_device(pdev);
1114 static int rhine_init_one_platform(struct platform_device *pdev)
1116 const struct of_device_id *match;
1119 void __iomem *ioaddr;
1121 match = of_match_device(rhine_of_tbl, &pdev->dev);
1125 ioaddr = devm_platform_ioremap_resource(pdev, 0);
1127 return PTR_ERR(ioaddr);
1129 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1133 quirks = match->data;
1137 return rhine_init_one_common(&pdev->dev, *quirks,
1138 (long)ioaddr, ioaddr, irq);
1141 static int alloc_ring(struct net_device* dev)
1143 struct rhine_private *rp = netdev_priv(dev);
1144 struct device *hwdev = dev->dev.parent;
1146 dma_addr_t ring_dma;
1148 ring = dma_alloc_coherent(hwdev,
1149 RX_RING_SIZE * sizeof(struct rx_desc) +
1150 TX_RING_SIZE * sizeof(struct tx_desc),
1154 netdev_err(dev, "Could not allocate DMA memory\n");
1157 if (rp->quirks & rqRhineI) {
1158 rp->tx_bufs = dma_alloc_coherent(hwdev,
1159 PKT_BUF_SZ * TX_RING_SIZE,
1162 if (rp->tx_bufs == NULL) {
1163 dma_free_coherent(hwdev,
1164 RX_RING_SIZE * sizeof(struct rx_desc) +
1165 TX_RING_SIZE * sizeof(struct tx_desc),
1172 rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
1173 rp->rx_ring_dma = ring_dma;
1174 rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
1179 static void free_ring(struct net_device* dev)
1181 struct rhine_private *rp = netdev_priv(dev);
1182 struct device *hwdev = dev->dev.parent;
1184 dma_free_coherent(hwdev,
1185 RX_RING_SIZE * sizeof(struct rx_desc) +
1186 TX_RING_SIZE * sizeof(struct tx_desc),
1187 rp->rx_ring, rp->rx_ring_dma);
1191 dma_free_coherent(hwdev, PKT_BUF_SZ * TX_RING_SIZE,
1192 rp->tx_bufs, rp->tx_bufs_dma);
1198 struct rhine_skb_dma {
1199 struct sk_buff *skb;
1203 static inline int rhine_skb_dma_init(struct net_device *dev,
1204 struct rhine_skb_dma *sd)
1206 struct rhine_private *rp = netdev_priv(dev);
1207 struct device *hwdev = dev->dev.parent;
1208 const int size = rp->rx_buf_sz;
1210 sd->skb = netdev_alloc_skb(dev, size);
1214 sd->dma = dma_map_single(hwdev, sd->skb->data, size, DMA_FROM_DEVICE);
1215 if (unlikely(dma_mapping_error(hwdev, sd->dma))) {
1216 netif_err(rp, drv, dev, "Rx DMA mapping failure\n");
1217 dev_kfree_skb_any(sd->skb);
1224 static void rhine_reset_rbufs(struct rhine_private *rp)
1230 for (i = 0; i < RX_RING_SIZE; i++)
1231 rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
1234 static inline void rhine_skb_dma_nic_store(struct rhine_private *rp,
1235 struct rhine_skb_dma *sd, int entry)
1237 rp->rx_skbuff_dma[entry] = sd->dma;
1238 rp->rx_skbuff[entry] = sd->skb;
1240 rp->rx_ring[entry].addr = cpu_to_le32(sd->dma);
1244 static void free_rbufs(struct net_device* dev);
1246 static int alloc_rbufs(struct net_device *dev)
1248 struct rhine_private *rp = netdev_priv(dev);
1252 rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1253 next = rp->rx_ring_dma;
1255 /* Init the ring entries */
1256 for (i = 0; i < RX_RING_SIZE; i++) {
1257 rp->rx_ring[i].rx_status = 0;
1258 rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
1259 next += sizeof(struct rx_desc);
1260 rp->rx_ring[i].next_desc = cpu_to_le32(next);
1261 rp->rx_skbuff[i] = NULL;
1263 /* Mark the last entry as wrapping the ring. */
1264 rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
1266 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1267 for (i = 0; i < RX_RING_SIZE; i++) {
1268 struct rhine_skb_dma sd;
1270 rc = rhine_skb_dma_init(dev, &sd);
1276 rhine_skb_dma_nic_store(rp, &sd, i);
1279 rhine_reset_rbufs(rp);
1284 static void free_rbufs(struct net_device* dev)
1286 struct rhine_private *rp = netdev_priv(dev);
1287 struct device *hwdev = dev->dev.parent;
1290 /* Free all the skbuffs in the Rx queue. */
1291 for (i = 0; i < RX_RING_SIZE; i++) {
1292 rp->rx_ring[i].rx_status = 0;
1293 rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1294 if (rp->rx_skbuff[i]) {
1295 dma_unmap_single(hwdev,
1296 rp->rx_skbuff_dma[i],
1297 rp->rx_buf_sz, DMA_FROM_DEVICE);
1298 dev_kfree_skb(rp->rx_skbuff[i]);
1300 rp->rx_skbuff[i] = NULL;
1304 static void alloc_tbufs(struct net_device* dev)
1306 struct rhine_private *rp = netdev_priv(dev);
1310 rp->dirty_tx = rp->cur_tx = 0;
1311 next = rp->tx_ring_dma;
1312 for (i = 0; i < TX_RING_SIZE; i++) {
1313 rp->tx_skbuff[i] = NULL;
1314 rp->tx_ring[i].tx_status = 0;
1315 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
1316 next += sizeof(struct tx_desc);
1317 rp->tx_ring[i].next_desc = cpu_to_le32(next);
1318 if (rp->quirks & rqRhineI)
1319 rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
1321 rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
1323 netdev_reset_queue(dev);
1326 static void free_tbufs(struct net_device* dev)
1328 struct rhine_private *rp = netdev_priv(dev);
1329 struct device *hwdev = dev->dev.parent;
1332 for (i = 0; i < TX_RING_SIZE; i++) {
1333 rp->tx_ring[i].tx_status = 0;
1334 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
1335 rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1336 if (rp->tx_skbuff[i]) {
1337 if (rp->tx_skbuff_dma[i]) {
1338 dma_unmap_single(hwdev,
1339 rp->tx_skbuff_dma[i],
1340 rp->tx_skbuff[i]->len,
1343 dev_kfree_skb(rp->tx_skbuff[i]);
1345 rp->tx_skbuff[i] = NULL;
1346 rp->tx_buf[i] = NULL;
1350 static void rhine_check_media(struct net_device *dev, unsigned int init_media)
1352 struct rhine_private *rp = netdev_priv(dev);
1353 void __iomem *ioaddr = rp->base;
1355 if (!rp->mii_if.force_media)
1356 mii_check_media(&rp->mii_if, netif_msg_link(rp), init_media);
1358 if (rp->mii_if.full_duplex)
1359 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
1362 iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
1365 netif_info(rp, link, dev, "force_media %d, carrier %d\n",
1366 rp->mii_if.force_media, netif_carrier_ok(dev));
1369 /* Called after status of force_media possibly changed */
1370 static void rhine_set_carrier(struct mii_if_info *mii)
1372 struct net_device *dev = mii->dev;
1373 struct rhine_private *rp = netdev_priv(dev);
1375 if (mii->force_media) {
1376 /* autoneg is off: Link is always assumed to be up */
1377 if (!netif_carrier_ok(dev))
1378 netif_carrier_on(dev);
1381 rhine_check_media(dev, 0);
1383 netif_info(rp, link, dev, "force_media %d, carrier %d\n",
1384 mii->force_media, netif_carrier_ok(dev));
1388 * rhine_set_cam - set CAM multicast filters
1389 * @ioaddr: register block of this Rhine
1390 * @idx: multicast CAM index [0..MCAM_SIZE-1]
1391 * @addr: multicast address (6 bytes)
1393 * Load addresses into multicast filters.
1395 static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr)
1399 iowrite8(CAMC_CAMEN, ioaddr + CamCon);
1402 /* Paranoid -- idx out of range should never happen */
1403 idx &= (MCAM_SIZE - 1);
1405 iowrite8((u8) idx, ioaddr + CamAddr);
1407 for (i = 0; i < 6; i++, addr++)
1408 iowrite8(*addr, ioaddr + MulticastFilter0 + i);
1412 iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
1415 iowrite8(0, ioaddr + CamCon);
1419 * rhine_set_vlan_cam - set CAM VLAN filters
1420 * @ioaddr: register block of this Rhine
1421 * @idx: VLAN CAM index [0..VCAM_SIZE-1]
1422 * @addr: VLAN ID (2 bytes)
1424 * Load addresses into VLAN filters.
1426 static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr)
1428 iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
1431 /* Paranoid -- idx out of range should never happen */
1432 idx &= (VCAM_SIZE - 1);
1434 iowrite8((u8) idx, ioaddr + CamAddr);
1436 iowrite16(*((u16 *) addr), ioaddr + MulticastFilter0 + 6);
1440 iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
1443 iowrite8(0, ioaddr + CamCon);
1447 * rhine_set_cam_mask - set multicast CAM mask
1448 * @ioaddr: register block of this Rhine
1449 * @mask: multicast CAM mask
1451 * Mask sets multicast filters active/inactive.
1453 static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask)
1455 iowrite8(CAMC_CAMEN, ioaddr + CamCon);
1459 iowrite32(mask, ioaddr + CamMask);
1462 iowrite8(0, ioaddr + CamCon);
1466 * rhine_set_vlan_cam_mask - set VLAN CAM mask
1467 * @ioaddr: register block of this Rhine
1468 * @mask: VLAN CAM mask
1470 * Mask sets VLAN filters active/inactive.
1472 static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask)
1474 iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
1478 iowrite32(mask, ioaddr + CamMask);
1481 iowrite8(0, ioaddr + CamCon);
1485 * rhine_init_cam_filter - initialize CAM filters
1486 * @dev: network device
1488 * Initialize (disable) hardware VLAN and multicast support on this
1491 static void rhine_init_cam_filter(struct net_device *dev)
1493 struct rhine_private *rp = netdev_priv(dev);
1494 void __iomem *ioaddr = rp->base;
1496 /* Disable all CAMs */
1497 rhine_set_vlan_cam_mask(ioaddr, 0);
1498 rhine_set_cam_mask(ioaddr, 0);
1500 /* disable hardware VLAN support */
1501 BYTE_REG_BITS_ON(TCR_PQEN, ioaddr + TxConfig);
1502 BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
1506 * rhine_update_vcam - update VLAN CAM filters
1507 * @dev: rhine_private data of this Rhine
1509 * Update VLAN CAM filters to match configuration change.
1511 static void rhine_update_vcam(struct net_device *dev)
1513 struct rhine_private *rp = netdev_priv(dev);
1514 void __iomem *ioaddr = rp->base;
1516 u32 vCAMmask = 0; /* 32 vCAMs (6105M and better) */
1519 for_each_set_bit(vid, rp->active_vlans, VLAN_N_VID) {
1520 rhine_set_vlan_cam(ioaddr, i, (u8 *)&vid);
1522 if (++i >= VCAM_SIZE)
1525 rhine_set_vlan_cam_mask(ioaddr, vCAMmask);
1528 static int rhine_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
1530 struct rhine_private *rp = netdev_priv(dev);
1532 spin_lock_bh(&rp->lock);
1533 set_bit(vid, rp->active_vlans);
1534 rhine_update_vcam(dev);
1535 spin_unlock_bh(&rp->lock);
1539 static int rhine_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
1541 struct rhine_private *rp = netdev_priv(dev);
1543 spin_lock_bh(&rp->lock);
1544 clear_bit(vid, rp->active_vlans);
1545 rhine_update_vcam(dev);
1546 spin_unlock_bh(&rp->lock);
1550 static void init_registers(struct net_device *dev)
1552 struct rhine_private *rp = netdev_priv(dev);
1553 void __iomem *ioaddr = rp->base;
1556 for (i = 0; i < 6; i++)
1557 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
1559 /* Initialize other registers. */
1560 iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */
1561 /* Configure initial FIFO thresholds. */
1562 iowrite8(0x20, ioaddr + TxConfig);
1563 rp->tx_thresh = 0x20;
1564 rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */
1566 iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
1567 iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
1569 rhine_set_rx_mode(dev);
1571 if (rp->quirks & rqMgmt)
1572 rhine_init_cam_filter(dev);
1574 napi_enable(&rp->napi);
1576 iowrite16(RHINE_EVENT & 0xffff, ioaddr + IntrEnable);
1578 iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
1580 rhine_check_media(dev, 1);
1583 /* Enable MII link status auto-polling (required for IntrLinkChange) */
1584 static void rhine_enable_linkmon(struct rhine_private *rp)
1586 void __iomem *ioaddr = rp->base;
1588 iowrite8(0, ioaddr + MIICmd);
1589 iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
1590 iowrite8(0x80, ioaddr + MIICmd);
1592 rhine_wait_bit_high(rp, MIIRegAddr, 0x20);
1594 iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
1597 /* Disable MII link status auto-polling (required for MDIO access) */
1598 static void rhine_disable_linkmon(struct rhine_private *rp)
1600 void __iomem *ioaddr = rp->base;
1602 iowrite8(0, ioaddr + MIICmd);
1604 if (rp->quirks & rqRhineI) {
1605 iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR
1607 /* Can be called from ISR. Evil. */
1610 /* 0x80 must be set immediately before turning it off */
1611 iowrite8(0x80, ioaddr + MIICmd);
1613 rhine_wait_bit_high(rp, MIIRegAddr, 0x20);
1615 /* Heh. Now clear 0x80 again. */
1616 iowrite8(0, ioaddr + MIICmd);
1619 rhine_wait_bit_high(rp, MIIRegAddr, 0x80);
1622 /* Read and write over the MII Management Data I/O (MDIO) interface. */
1624 static int mdio_read(struct net_device *dev, int phy_id, int regnum)
1626 struct rhine_private *rp = netdev_priv(dev);
1627 void __iomem *ioaddr = rp->base;
1630 rhine_disable_linkmon(rp);
1632 /* rhine_disable_linkmon already cleared MIICmd */
1633 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1634 iowrite8(regnum, ioaddr + MIIRegAddr);
1635 iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */
1636 rhine_wait_bit_low(rp, MIICmd, 0x40);
1637 result = ioread16(ioaddr + MIIData);
1639 rhine_enable_linkmon(rp);
1643 static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
1645 struct rhine_private *rp = netdev_priv(dev);
1646 void __iomem *ioaddr = rp->base;
1648 rhine_disable_linkmon(rp);
1650 /* rhine_disable_linkmon already cleared MIICmd */
1651 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1652 iowrite8(regnum, ioaddr + MIIRegAddr);
1653 iowrite16(value, ioaddr + MIIData);
1654 iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */
1655 rhine_wait_bit_low(rp, MIICmd, 0x20);
1657 rhine_enable_linkmon(rp);
1660 static void rhine_task_disable(struct rhine_private *rp)
1662 mutex_lock(&rp->task_lock);
1663 rp->task_enable = false;
1664 mutex_unlock(&rp->task_lock);
1666 cancel_work_sync(&rp->slow_event_task);
1667 cancel_work_sync(&rp->reset_task);
1670 static void rhine_task_enable(struct rhine_private *rp)
1672 mutex_lock(&rp->task_lock);
1673 rp->task_enable = true;
1674 mutex_unlock(&rp->task_lock);
1677 static int rhine_open(struct net_device *dev)
1679 struct rhine_private *rp = netdev_priv(dev);
1680 void __iomem *ioaddr = rp->base;
1683 rc = request_irq(rp->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev);
1687 netif_dbg(rp, ifup, dev, "%s() irq %d\n", __func__, rp->irq);
1689 rc = alloc_ring(dev);
1693 rc = alloc_rbufs(dev);
1698 enable_mmio(rp->pioaddr, rp->quirks);
1699 rhine_power_init(dev);
1700 rhine_chip_reset(dev);
1701 rhine_task_enable(rp);
1702 init_registers(dev);
1704 netif_dbg(rp, ifup, dev, "%s() Done - status %04x MII status: %04x\n",
1705 __func__, ioread16(ioaddr + ChipCmd),
1706 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1708 netif_start_queue(dev);
1716 free_irq(rp->irq, dev);
1720 static void rhine_reset_task(struct work_struct *work)
1722 struct rhine_private *rp = container_of(work, struct rhine_private,
1724 struct net_device *dev = rp->dev;
1726 mutex_lock(&rp->task_lock);
1728 if (!rp->task_enable)
1731 napi_disable(&rp->napi);
1732 netif_tx_disable(dev);
1733 spin_lock_bh(&rp->lock);
1735 /* clear all descriptors */
1739 rhine_reset_rbufs(rp);
1741 /* Reinitialize the hardware. */
1742 rhine_chip_reset(dev);
1743 init_registers(dev);
1745 spin_unlock_bh(&rp->lock);
1747 netif_trans_update(dev); /* prevent tx timeout */
1748 dev->stats.tx_errors++;
1749 netif_wake_queue(dev);
1752 mutex_unlock(&rp->task_lock);
1755 static void rhine_tx_timeout(struct net_device *dev, unsigned int txqueue)
1757 struct rhine_private *rp = netdev_priv(dev);
1758 void __iomem *ioaddr = rp->base;
1760 netdev_warn(dev, "Transmit timed out, status %04x, PHY status %04x, resetting...\n",
1761 ioread16(ioaddr + IntrStatus),
1762 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1764 schedule_work(&rp->reset_task);
1767 static inline bool rhine_tx_queue_full(struct rhine_private *rp)
1769 return (rp->cur_tx - rp->dirty_tx) >= TX_QUEUE_LEN;
1772 static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
1773 struct net_device *dev)
1775 struct rhine_private *rp = netdev_priv(dev);
1776 struct device *hwdev = dev->dev.parent;
1777 void __iomem *ioaddr = rp->base;
1780 /* Caution: the write order is important here, set the field
1781 with the "ownership" bits last. */
1783 /* Calculate the next Tx descriptor entry. */
1784 entry = rp->cur_tx % TX_RING_SIZE;
1786 if (skb_padto(skb, ETH_ZLEN))
1787 return NETDEV_TX_OK;
1789 rp->tx_skbuff[entry] = skb;
1791 if ((rp->quirks & rqRhineI) &&
1792 (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) {
1793 /* Must use alignment buffer. */
1794 if (skb->len > PKT_BUF_SZ) {
1795 /* packet too long, drop it */
1796 dev_kfree_skb_any(skb);
1797 rp->tx_skbuff[entry] = NULL;
1798 dev->stats.tx_dropped++;
1799 return NETDEV_TX_OK;
1802 /* Padding is not copied and so must be redone. */
1803 skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
1804 if (skb->len < ETH_ZLEN)
1805 memset(rp->tx_buf[entry] + skb->len, 0,
1806 ETH_ZLEN - skb->len);
1807 rp->tx_skbuff_dma[entry] = 0;
1808 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
1809 (rp->tx_buf[entry] -
1812 rp->tx_skbuff_dma[entry] =
1813 dma_map_single(hwdev, skb->data, skb->len,
1815 if (dma_mapping_error(hwdev, rp->tx_skbuff_dma[entry])) {
1816 dev_kfree_skb_any(skb);
1817 rp->tx_skbuff_dma[entry] = 0;
1818 dev->stats.tx_dropped++;
1819 return NETDEV_TX_OK;
1821 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
1824 rp->tx_ring[entry].desc_length =
1825 cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1827 if (unlikely(skb_vlan_tag_present(skb))) {
1828 u16 vid_pcp = skb_vlan_tag_get(skb);
1830 /* drop CFI/DEI bit, register needs VID and PCP */
1831 vid_pcp = (vid_pcp & VLAN_VID_MASK) |
1832 ((vid_pcp & VLAN_PRIO_MASK) >> 1);
1833 rp->tx_ring[entry].tx_status = cpu_to_le32((vid_pcp) << 16);
1834 /* request tagging */
1835 rp->tx_ring[entry].desc_length |= cpu_to_le32(0x020000);
1838 rp->tx_ring[entry].tx_status = 0;
1840 netdev_sent_queue(dev, skb->len);
1843 rp->tx_ring[entry].tx_status |= cpu_to_le32(DescOwn);
1848 * Nobody wants cur_tx write to rot for ages after the NIC will have
1849 * seen the transmit request, especially as the transmit completion
1850 * handler could miss it.
1854 /* Non-x86 Todo: explicitly flush cache lines here. */
1856 if (skb_vlan_tag_present(skb))
1857 /* Tx queues are bits 7-0 (first Tx queue: bit 7) */
1858 BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
1860 /* Wake the potentially-idle transmit channel */
1861 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1865 /* dirty_tx may be pessimistically out-of-sync. See rhine_tx. */
1866 if (rhine_tx_queue_full(rp)) {
1867 netif_stop_queue(dev);
1870 if (!rhine_tx_queue_full(rp))
1871 netif_wake_queue(dev);
1874 netif_dbg(rp, tx_queued, dev, "Transmit frame #%d queued in slot %d\n",
1875 rp->cur_tx - 1, entry);
1877 return NETDEV_TX_OK;
1880 static void rhine_irq_disable(struct rhine_private *rp)
1882 iowrite16(0x0000, rp->base + IntrEnable);
1885 /* The interrupt handler does all of the Rx thread work and cleans up
1886 after the Tx thread. */
1887 static irqreturn_t rhine_interrupt(int irq, void *dev_instance)
1889 struct net_device *dev = dev_instance;
1890 struct rhine_private *rp = netdev_priv(dev);
1894 status = rhine_get_events(rp);
1896 netif_dbg(rp, intr, dev, "Interrupt, status %08x\n", status);
1898 if (status & RHINE_EVENT) {
1901 rhine_irq_disable(rp);
1902 napi_schedule(&rp->napi);
1905 if (status & ~(IntrLinkChange | IntrStatsMax | RHINE_EVENT_NAPI)) {
1906 netif_err(rp, intr, dev, "Something Wicked happened! %08x\n",
1910 return IRQ_RETVAL(handled);
1913 /* This routine is logically part of the interrupt handler, but isolated
1915 static void rhine_tx(struct net_device *dev)
1917 struct rhine_private *rp = netdev_priv(dev);
1918 struct device *hwdev = dev->dev.parent;
1919 unsigned int pkts_compl = 0, bytes_compl = 0;
1920 unsigned int dirty_tx = rp->dirty_tx;
1921 unsigned int cur_tx;
1922 struct sk_buff *skb;
1925 * The race with rhine_start_tx does not matter here as long as the
1926 * driver enforces a value of cur_tx that was relevant when the
1927 * packet was scheduled to the network chipset.
1928 * Executive summary: smp_rmb() balances smp_wmb() in rhine_start_tx.
1931 cur_tx = rp->cur_tx;
1932 /* find and cleanup dirty tx descriptors */
1933 while (dirty_tx != cur_tx) {
1934 unsigned int entry = dirty_tx % TX_RING_SIZE;
1935 u32 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
1937 netif_dbg(rp, tx_done, dev, "Tx scavenge %d status %08x\n",
1939 if (txstatus & DescOwn)
1941 skb = rp->tx_skbuff[entry];
1942 if (txstatus & 0x8000) {
1943 netif_dbg(rp, tx_done, dev,
1944 "Transmit error, Tx status %08x\n", txstatus);
1945 dev->stats.tx_errors++;
1946 if (txstatus & 0x0400)
1947 dev->stats.tx_carrier_errors++;
1948 if (txstatus & 0x0200)
1949 dev->stats.tx_window_errors++;
1950 if (txstatus & 0x0100)
1951 dev->stats.tx_aborted_errors++;
1952 if (txstatus & 0x0080)
1953 dev->stats.tx_heartbeat_errors++;
1954 if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
1955 (txstatus & 0x0800) || (txstatus & 0x1000)) {
1956 dev->stats.tx_fifo_errors++;
1957 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1958 break; /* Keep the skb - we try again */
1960 /* Transmitter restarted in 'abnormal' handler. */
1962 if (rp->quirks & rqRhineI)
1963 dev->stats.collisions += (txstatus >> 3) & 0x0F;
1965 dev->stats.collisions += txstatus & 0x0F;
1966 netif_dbg(rp, tx_done, dev, "collisions: %1.1x:%1.1x\n",
1967 (txstatus >> 3) & 0xF, txstatus & 0xF);
1969 u64_stats_update_begin(&rp->tx_stats.syncp);
1970 rp->tx_stats.bytes += skb->len;
1971 rp->tx_stats.packets++;
1972 u64_stats_update_end(&rp->tx_stats.syncp);
1974 /* Free the original skb. */
1975 if (rp->tx_skbuff_dma[entry]) {
1976 dma_unmap_single(hwdev,
1977 rp->tx_skbuff_dma[entry],
1981 bytes_compl += skb->len;
1983 dev_consume_skb_any(skb);
1984 rp->tx_skbuff[entry] = NULL;
1988 rp->dirty_tx = dirty_tx;
1989 /* Pity we can't rely on the nearby BQL completion implicit barrier. */
1992 netdev_completed_queue(dev, pkts_compl, bytes_compl);
1994 /* cur_tx may be optimistically out-of-sync. See rhine_start_tx. */
1995 if (!rhine_tx_queue_full(rp) && netif_queue_stopped(dev)) {
1996 netif_wake_queue(dev);
1999 if (rhine_tx_queue_full(rp))
2000 netif_stop_queue(dev);
2005 * rhine_get_vlan_tci - extract TCI from Rx data buffer
2006 * @skb: pointer to sk_buff
2007 * @data_size: used data area of the buffer including CRC
2009 * If hardware VLAN tag extraction is enabled and the chip indicates a 802.1Q
2010 * packet, the extracted 802.1Q header (2 bytes TPID + 2 bytes TCI) is 4-byte
2011 * aligned following the CRC.
2013 static inline u16 rhine_get_vlan_tci(struct sk_buff *skb, int data_size)
2015 u8 *trailer = (u8 *)skb->data + ((data_size + 3) & ~3) + 2;
2016 return be16_to_cpup((__be16 *)trailer);
2019 static inline void rhine_rx_vlan_tag(struct sk_buff *skb, struct rx_desc *desc,
2023 if (unlikely(desc->desc_length & cpu_to_le32(DescTag))) {
2026 vlan_tci = rhine_get_vlan_tci(skb, data_size);
2027 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci);
2031 /* Process up to limit frames from receive ring */
2032 static int rhine_rx(struct net_device *dev, int limit)
2034 struct rhine_private *rp = netdev_priv(dev);
2035 struct device *hwdev = dev->dev.parent;
2036 int entry = rp->cur_rx % RX_RING_SIZE;
2039 netif_dbg(rp, rx_status, dev, "%s(), entry %d status %08x\n", __func__,
2040 entry, le32_to_cpu(rp->rx_ring[entry].rx_status));
2042 /* If EOP is set on the next entry, it's a new packet. Send it up. */
2043 for (count = 0; count < limit; ++count) {
2044 struct rx_desc *desc = rp->rx_ring + entry;
2045 u32 desc_status = le32_to_cpu(desc->rx_status);
2046 int data_size = desc_status >> 16;
2048 if (desc_status & DescOwn)
2051 netif_dbg(rp, rx_status, dev, "%s() status %08x\n", __func__,
2054 if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
2055 if ((desc_status & RxWholePkt) != RxWholePkt) {
2057 "Oversized Ethernet frame spanned multiple buffers, "
2058 "entry %#x length %d status %08x!\n",
2061 dev->stats.rx_length_errors++;
2062 } else if (desc_status & RxErr) {
2063 /* There was a error. */
2064 netif_dbg(rp, rx_err, dev,
2065 "%s() Rx error %08x\n", __func__,
2067 dev->stats.rx_errors++;
2068 if (desc_status & 0x0030)
2069 dev->stats.rx_length_errors++;
2070 if (desc_status & 0x0048)
2071 dev->stats.rx_fifo_errors++;
2072 if (desc_status & 0x0004)
2073 dev->stats.rx_frame_errors++;
2074 if (desc_status & 0x0002) {
2075 /* this can also be updated outside the interrupt handler */
2076 spin_lock(&rp->lock);
2077 dev->stats.rx_crc_errors++;
2078 spin_unlock(&rp->lock);
2082 /* Length should omit the CRC */
2083 int pkt_len = data_size - 4;
2084 struct sk_buff *skb;
2086 /* Check if the packet is long enough to accept without
2087 copying to a minimally-sized skbuff. */
2088 if (pkt_len < rx_copybreak) {
2089 skb = netdev_alloc_skb_ip_align(dev, pkt_len);
2093 dma_sync_single_for_cpu(hwdev,
2094 rp->rx_skbuff_dma[entry],
2098 skb_copy_to_linear_data(skb,
2099 rp->rx_skbuff[entry]->data,
2102 dma_sync_single_for_device(hwdev,
2103 rp->rx_skbuff_dma[entry],
2107 struct rhine_skb_dma sd;
2109 if (unlikely(rhine_skb_dma_init(dev, &sd) < 0))
2112 skb = rp->rx_skbuff[entry];
2114 dma_unmap_single(hwdev,
2115 rp->rx_skbuff_dma[entry],
2118 rhine_skb_dma_nic_store(rp, &sd, entry);
2121 skb_put(skb, pkt_len);
2123 rhine_rx_vlan_tag(skb, desc, data_size);
2125 skb->protocol = eth_type_trans(skb, dev);
2127 netif_receive_skb(skb);
2129 u64_stats_update_begin(&rp->rx_stats.syncp);
2130 rp->rx_stats.bytes += pkt_len;
2131 rp->rx_stats.packets++;
2132 u64_stats_update_end(&rp->rx_stats.syncp);
2134 give_descriptor_to_nic:
2135 desc->rx_status = cpu_to_le32(DescOwn);
2136 entry = (++rp->cur_rx) % RX_RING_SIZE;
2142 dev->stats.rx_dropped++;
2143 goto give_descriptor_to_nic;
2146 static void rhine_restart_tx(struct net_device *dev) {
2147 struct rhine_private *rp = netdev_priv(dev);
2148 void __iomem *ioaddr = rp->base;
2149 int entry = rp->dirty_tx % TX_RING_SIZE;
2153 * If new errors occurred, we need to sort them out before doing Tx.
2154 * In that case the ISR will be back here RSN anyway.
2156 intr_status = rhine_get_events(rp);
2158 if ((intr_status & IntrTxErrSummary) == 0) {
2160 /* We know better than the chip where it should continue. */
2161 iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
2162 ioaddr + TxRingPtr);
2164 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
2167 if (rp->tx_ring[entry].desc_length & cpu_to_le32(0x020000))
2168 /* Tx queues are bits 7-0 (first Tx queue: bit 7) */
2169 BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
2171 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
2176 /* This should never happen */
2177 netif_warn(rp, tx_err, dev, "another error occurred %08x\n",
2183 static void rhine_slow_event_task(struct work_struct *work)
2185 struct rhine_private *rp =
2186 container_of(work, struct rhine_private, slow_event_task);
2187 struct net_device *dev = rp->dev;
2190 mutex_lock(&rp->task_lock);
2192 if (!rp->task_enable)
2195 intr_status = rhine_get_events(rp);
2196 rhine_ack_events(rp, intr_status & RHINE_EVENT_SLOW);
2198 if (intr_status & IntrLinkChange)
2199 rhine_check_media(dev, 0);
2201 if (intr_status & IntrPCIErr)
2202 netif_warn(rp, hw, dev, "PCI error\n");
2204 iowrite16(RHINE_EVENT & 0xffff, rp->base + IntrEnable);
2207 mutex_unlock(&rp->task_lock);
2211 rhine_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
2213 struct rhine_private *rp = netdev_priv(dev);
2216 spin_lock_bh(&rp->lock);
2217 rhine_update_rx_crc_and_missed_errord(rp);
2218 spin_unlock_bh(&rp->lock);
2220 netdev_stats_to_stats64(stats, &dev->stats);
2223 start = u64_stats_fetch_begin_irq(&rp->rx_stats.syncp);
2224 stats->rx_packets = rp->rx_stats.packets;
2225 stats->rx_bytes = rp->rx_stats.bytes;
2226 } while (u64_stats_fetch_retry_irq(&rp->rx_stats.syncp, start));
2229 start = u64_stats_fetch_begin_irq(&rp->tx_stats.syncp);
2230 stats->tx_packets = rp->tx_stats.packets;
2231 stats->tx_bytes = rp->tx_stats.bytes;
2232 } while (u64_stats_fetch_retry_irq(&rp->tx_stats.syncp, start));
2235 static void rhine_set_rx_mode(struct net_device *dev)
2237 struct rhine_private *rp = netdev_priv(dev);
2238 void __iomem *ioaddr = rp->base;
2239 u32 mc_filter[2]; /* Multicast hash filter */
2240 u8 rx_mode = 0x0C; /* Note: 0x02=accept runt, 0x01=accept errs */
2241 struct netdev_hw_addr *ha;
2243 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
2245 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
2246 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
2247 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
2248 (dev->flags & IFF_ALLMULTI)) {
2249 /* Too many to match, or accept all multicasts. */
2250 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
2251 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
2252 } else if (rp->quirks & rqMgmt) {
2254 u32 mCAMmask = 0; /* 32 mCAMs (6105M and better) */
2255 netdev_for_each_mc_addr(ha, dev) {
2258 rhine_set_cam(ioaddr, i, ha->addr);
2262 rhine_set_cam_mask(ioaddr, mCAMmask);
2264 memset(mc_filter, 0, sizeof(mc_filter));
2265 netdev_for_each_mc_addr(ha, dev) {
2266 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2268 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2270 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
2271 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
2273 /* enable/disable VLAN receive filtering */
2274 if (rp->quirks & rqMgmt) {
2275 if (dev->flags & IFF_PROMISC)
2276 BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
2278 BYTE_REG_BITS_ON(BCR1_VIDFR, ioaddr + PCIBusConfig1);
2280 BYTE_REG_BITS_ON(rx_mode, ioaddr + RxConfig);
2283 static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2285 struct device *hwdev = dev->dev.parent;
2287 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2288 strlcpy(info->bus_info, dev_name(hwdev), sizeof(info->bus_info));
2291 static int netdev_get_link_ksettings(struct net_device *dev,
2292 struct ethtool_link_ksettings *cmd)
2294 struct rhine_private *rp = netdev_priv(dev);
2296 mutex_lock(&rp->task_lock);
2297 mii_ethtool_get_link_ksettings(&rp->mii_if, cmd);
2298 mutex_unlock(&rp->task_lock);
2303 static int netdev_set_link_ksettings(struct net_device *dev,
2304 const struct ethtool_link_ksettings *cmd)
2306 struct rhine_private *rp = netdev_priv(dev);
2309 mutex_lock(&rp->task_lock);
2310 rc = mii_ethtool_set_link_ksettings(&rp->mii_if, cmd);
2311 rhine_set_carrier(&rp->mii_if);
2312 mutex_unlock(&rp->task_lock);
2317 static int netdev_nway_reset(struct net_device *dev)
2319 struct rhine_private *rp = netdev_priv(dev);
2321 return mii_nway_restart(&rp->mii_if);
2324 static u32 netdev_get_link(struct net_device *dev)
2326 struct rhine_private *rp = netdev_priv(dev);
2328 return mii_link_ok(&rp->mii_if);
2331 static u32 netdev_get_msglevel(struct net_device *dev)
2333 struct rhine_private *rp = netdev_priv(dev);
2335 return rp->msg_enable;
2338 static void netdev_set_msglevel(struct net_device *dev, u32 value)
2340 struct rhine_private *rp = netdev_priv(dev);
2342 rp->msg_enable = value;
2345 static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2347 struct rhine_private *rp = netdev_priv(dev);
2349 if (!(rp->quirks & rqWOL))
2352 spin_lock_irq(&rp->lock);
2353 wol->supported = WAKE_PHY | WAKE_MAGIC |
2354 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
2355 wol->wolopts = rp->wolopts;
2356 spin_unlock_irq(&rp->lock);
2359 static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2361 struct rhine_private *rp = netdev_priv(dev);
2362 u32 support = WAKE_PHY | WAKE_MAGIC |
2363 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
2365 if (!(rp->quirks & rqWOL))
2368 if (wol->wolopts & ~support)
2371 spin_lock_irq(&rp->lock);
2372 rp->wolopts = wol->wolopts;
2373 spin_unlock_irq(&rp->lock);
2378 static const struct ethtool_ops netdev_ethtool_ops = {
2379 .get_drvinfo = netdev_get_drvinfo,
2380 .nway_reset = netdev_nway_reset,
2381 .get_link = netdev_get_link,
2382 .get_msglevel = netdev_get_msglevel,
2383 .set_msglevel = netdev_set_msglevel,
2384 .get_wol = rhine_get_wol,
2385 .set_wol = rhine_set_wol,
2386 .get_link_ksettings = netdev_get_link_ksettings,
2387 .set_link_ksettings = netdev_set_link_ksettings,
2390 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2392 struct rhine_private *rp = netdev_priv(dev);
2395 if (!netif_running(dev))
2398 mutex_lock(&rp->task_lock);
2399 rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
2400 rhine_set_carrier(&rp->mii_if);
2401 mutex_unlock(&rp->task_lock);
2406 static int rhine_close(struct net_device *dev)
2408 struct rhine_private *rp = netdev_priv(dev);
2409 void __iomem *ioaddr = rp->base;
2411 rhine_task_disable(rp);
2412 napi_disable(&rp->napi);
2413 netif_stop_queue(dev);
2415 netif_dbg(rp, ifdown, dev, "Shutting down ethercard, status was %04x\n",
2416 ioread16(ioaddr + ChipCmd));
2418 /* Switch to loopback mode to avoid hardware races. */
2419 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
2421 rhine_irq_disable(rp);
2423 /* Stop the chip's Tx and Rx processes. */
2424 iowrite16(CmdStop, ioaddr + ChipCmd);
2426 free_irq(rp->irq, dev);
2435 static void rhine_remove_one_pci(struct pci_dev *pdev)
2437 struct net_device *dev = pci_get_drvdata(pdev);
2438 struct rhine_private *rp = netdev_priv(dev);
2440 unregister_netdev(dev);
2442 pci_iounmap(pdev, rp->base);
2443 pci_release_regions(pdev);
2446 pci_disable_device(pdev);
2449 static int rhine_remove_one_platform(struct platform_device *pdev)
2451 struct net_device *dev = platform_get_drvdata(pdev);
2452 struct rhine_private *rp = netdev_priv(dev);
2454 unregister_netdev(dev);
2463 static void rhine_shutdown_pci(struct pci_dev *pdev)
2465 struct net_device *dev = pci_get_drvdata(pdev);
2466 struct rhine_private *rp = netdev_priv(dev);
2467 void __iomem *ioaddr = rp->base;
2469 if (!(rp->quirks & rqWOL))
2470 return; /* Nothing to do for non-WOL adapters */
2472 rhine_power_init(dev);
2474 /* Make sure we use pattern 0, 1 and not 4, 5 */
2475 if (rp->quirks & rq6patterns)
2476 iowrite8(0x04, ioaddr + WOLcgClr);
2478 spin_lock(&rp->lock);
2480 if (rp->wolopts & WAKE_MAGIC) {
2481 iowrite8(WOLmagic, ioaddr + WOLcrSet);
2483 * Turn EEPROM-controlled wake-up back on -- some hardware may
2484 * not cooperate otherwise.
2486 iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
2489 if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
2490 iowrite8(WOLbmcast, ioaddr + WOLcgSet);
2492 if (rp->wolopts & WAKE_PHY)
2493 iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
2495 if (rp->wolopts & WAKE_UCAST)
2496 iowrite8(WOLucast, ioaddr + WOLcrSet);
2499 /* Enable legacy WOL (for old motherboards) */
2500 iowrite8(0x01, ioaddr + PwcfgSet);
2501 iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
2504 spin_unlock(&rp->lock);
2506 if (system_state == SYSTEM_POWER_OFF && !avoid_D3) {
2507 iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
2509 pci_wake_from_d3(pdev, true);
2510 pci_set_power_state(pdev, PCI_D3hot);
2514 #ifdef CONFIG_PM_SLEEP
2515 static int rhine_suspend(struct device *device)
2517 struct net_device *dev = dev_get_drvdata(device);
2518 struct rhine_private *rp = netdev_priv(dev);
2520 if (!netif_running(dev))
2523 rhine_task_disable(rp);
2524 rhine_irq_disable(rp);
2525 napi_disable(&rp->napi);
2527 netif_device_detach(dev);
2529 if (dev_is_pci(device))
2530 rhine_shutdown_pci(to_pci_dev(device));
2535 static int rhine_resume(struct device *device)
2537 struct net_device *dev = dev_get_drvdata(device);
2538 struct rhine_private *rp = netdev_priv(dev);
2540 if (!netif_running(dev))
2543 enable_mmio(rp->pioaddr, rp->quirks);
2544 rhine_power_init(dev);
2547 rhine_reset_rbufs(rp);
2548 rhine_task_enable(rp);
2549 spin_lock_bh(&rp->lock);
2550 init_registers(dev);
2551 spin_unlock_bh(&rp->lock);
2553 netif_device_attach(dev);
2558 static SIMPLE_DEV_PM_OPS(rhine_pm_ops, rhine_suspend, rhine_resume);
2559 #define RHINE_PM_OPS (&rhine_pm_ops)
2563 #define RHINE_PM_OPS NULL
2565 #endif /* !CONFIG_PM_SLEEP */
2567 static struct pci_driver rhine_driver_pci = {
2569 .id_table = rhine_pci_tbl,
2570 .probe = rhine_init_one_pci,
2571 .remove = rhine_remove_one_pci,
2572 .shutdown = rhine_shutdown_pci,
2573 .driver.pm = RHINE_PM_OPS,
2576 static struct platform_driver rhine_driver_platform = {
2577 .probe = rhine_init_one_platform,
2578 .remove = rhine_remove_one_platform,
2581 .of_match_table = rhine_of_tbl,
2586 static const struct dmi_system_id rhine_dmi_table[] __initconst = {
2590 DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."),
2591 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
2597 DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
2598 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
2604 static int __init rhine_init(void)
2606 int ret_pci, ret_platform;
2608 /* when a module, this is printed whether or not devices are found in probe */
2609 if (dmi_check_system(rhine_dmi_table)) {
2610 /* these BIOSes fail at PXE boot if chip is in D3 */
2612 pr_warn("Broken BIOS detected, avoid_D3 enabled\n");
2615 pr_info("avoid_D3 set\n");
2617 ret_pci = pci_register_driver(&rhine_driver_pci);
2618 ret_platform = platform_driver_register(&rhine_driver_platform);
2619 if ((ret_pci < 0) && (ret_platform < 0))
2626 static void __exit rhine_cleanup(void)
2628 platform_driver_unregister(&rhine_driver_platform);
2629 pci_unregister_driver(&rhine_driver_pci);
2633 module_init(rhine_init);
2634 module_exit(rhine_cleanup);