1 // SPDX-License-Identifier: GPL-2.0+
3 * DaVinci MDIO Module driver
5 * Copyright (C) 2010 Texas Instruments.
7 * Shamelessly ripped out of davinci_emac.c, original copyrights follow:
9 * Copyright (C) 2009 Texas Instruments.
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/platform_device.h>
15 #include <linux/delay.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/phy.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
22 #include <linux/iopoll.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/davinci_emac.h>
26 #include <linux/of_mdio.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/mdio-bitbang.h>
29 #include <linux/sys_soc.h>
32 * This timeout definition is a worst-case ultra defensive measure against
33 * unexpected controller lock ups. Ideally, we should never ever hit this
34 * scenario in practice.
36 #define MDIO_TIMEOUT 100 /* msecs */
38 #define PHY_REG_MASK 0x1f
39 #define PHY_ID_MASK 0x1f
41 #define DEF_OUT_FREQ 2200000 /* 2.2 MHz */
43 struct davinci_mdio_of_param {
44 int autosuspend_delay_ms;
48 struct davinci_mdio_regs {
51 #define CONTROL_IDLE BIT(31)
52 #define CONTROL_ENABLE BIT(30)
53 #define CONTROL_MAX_DIV (0xffff)
54 #define CONTROL_CLKDIV GENMASK(15, 0)
56 #define MDIO_MAN_MDCLK_O BIT(2)
57 #define MDIO_MAN_OE BIT(1)
58 #define MDIO_MAN_PIN BIT(0)
59 #define MDIO_MANUALMODE BIT(31)
79 #define USERACCESS_GO BIT(31)
80 #define USERACCESS_WRITE BIT(30)
81 #define USERACCESS_ACK BIT(29)
82 #define USERACCESS_READ (0)
83 #define USERACCESS_DATA (0xffff)
89 static const struct mdio_platform_data default_pdata = {
90 .bus_freq = DEF_OUT_FREQ,
93 struct davinci_mdio_data {
94 struct mdio_platform_data pdata;
95 struct mdiobb_ctrl bb_ctrl;
96 struct davinci_mdio_regs __iomem *regs;
100 bool active_in_suspend;
101 unsigned long access_time; /* jiffies */
102 /* Indicates that driver shouldn't modify phy_mask in case
103 * if MDIO bus is registered from DT.
110 static void davinci_mdio_init_clk(struct davinci_mdio_data *data)
112 u32 mdio_in, div, mdio_out_khz, access_time;
114 mdio_in = clk_get_rate(data->clk);
115 div = (mdio_in / data->pdata.bus_freq) - 1;
116 if (div > CONTROL_MAX_DIV)
117 div = CONTROL_MAX_DIV;
121 * One mdio transaction consists of:
122 * 32 bits of preamble
123 * 32 bits of transferred data
124 * 24 bits of bus yield (not needed unless shared?)
126 mdio_out_khz = mdio_in / (1000 * (div + 1));
127 access_time = (88 * 1000) / mdio_out_khz;
130 * In the worst case, we could be kicking off a user-access immediately
131 * after the mdio bus scan state-machine triggered its own read. If
132 * so, our request could get deferred by one access cycle. We
133 * defensively allow for 4 access cycles.
135 data->access_time = usecs_to_jiffies(access_time * 4);
136 if (!data->access_time)
137 data->access_time = 1;
140 static void davinci_mdio_enable(struct davinci_mdio_data *data)
142 /* set enable and clock divider */
143 writel(data->clk_div | CONTROL_ENABLE, &data->regs->control);
146 static void davinci_mdio_disable(struct davinci_mdio_data *data)
150 /* Disable MDIO state machine */
151 reg = readl(&data->regs->control);
153 reg &= ~CONTROL_CLKDIV;
154 reg |= data->clk_div;
156 reg &= ~CONTROL_ENABLE;
157 writel(reg, &data->regs->control);
160 static void davinci_mdio_enable_manual_mode(struct davinci_mdio_data *data)
163 /* set manual mode */
164 reg = readl(&data->regs->poll);
165 reg |= MDIO_MANUALMODE;
166 writel(reg, &data->regs->poll);
169 static void davinci_set_mdc(struct mdiobb_ctrl *ctrl, int level)
171 struct davinci_mdio_data *data;
174 data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
175 reg = readl(&data->regs->manualif);
178 reg |= MDIO_MAN_MDCLK_O;
180 reg &= ~MDIO_MAN_MDCLK_O;
182 writel(reg, &data->regs->manualif);
185 static void davinci_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
187 struct davinci_mdio_data *data;
190 data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
191 reg = readl(&data->regs->manualif);
198 writel(reg, &data->regs->manualif);
201 static void davinci_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
203 struct davinci_mdio_data *data;
206 data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
207 reg = readl(&data->regs->manualif);
212 reg &= ~MDIO_MAN_PIN;
214 writel(reg, &data->regs->manualif);
217 static int davinci_get_mdio_data(struct mdiobb_ctrl *ctrl)
219 struct davinci_mdio_data *data;
222 data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
223 reg = readl(&data->regs->manualif);
224 return test_bit(MDIO_PIN, ®);
227 static int davinci_mdiobb_read_c22(struct mii_bus *bus, int phy, int reg)
231 ret = pm_runtime_resume_and_get(bus->parent);
235 ret = mdiobb_read_c22(bus, phy, reg);
237 pm_runtime_mark_last_busy(bus->parent);
238 pm_runtime_put_autosuspend(bus->parent);
243 static int davinci_mdiobb_write_c22(struct mii_bus *bus, int phy, int reg,
248 ret = pm_runtime_resume_and_get(bus->parent);
252 ret = mdiobb_write_c22(bus, phy, reg, val);
254 pm_runtime_mark_last_busy(bus->parent);
255 pm_runtime_put_autosuspend(bus->parent);
260 static int davinci_mdiobb_read_c45(struct mii_bus *bus, int phy, int devad,
265 ret = pm_runtime_resume_and_get(bus->parent);
269 ret = mdiobb_read_c45(bus, phy, devad, reg);
271 pm_runtime_mark_last_busy(bus->parent);
272 pm_runtime_put_autosuspend(bus->parent);
277 static int davinci_mdiobb_write_c45(struct mii_bus *bus, int phy, int devad,
282 ret = pm_runtime_resume_and_get(bus->parent);
286 ret = mdiobb_write_c45(bus, phy, devad, reg, val);
288 pm_runtime_mark_last_busy(bus->parent);
289 pm_runtime_put_autosuspend(bus->parent);
294 static int davinci_mdio_common_reset(struct davinci_mdio_data *data)
299 ret = pm_runtime_resume_and_get(data->dev);
303 if (data->manual_mode) {
304 davinci_mdio_disable(data);
305 davinci_mdio_enable_manual_mode(data);
308 /* wait for scan logic to settle */
309 msleep(PHY_MAX_ADDR * data->access_time);
311 /* dump hardware version info */
312 ver = readl(&data->regs->version);
314 "davinci mdio revision %d.%d, bus freq %ld\n",
315 (ver >> 8) & 0xff, ver & 0xff,
316 data->pdata.bus_freq);
321 /* get phy mask from the alive register */
322 phy_mask = readl(&data->regs->alive);
324 /* restrict mdio bus to live phys only */
325 dev_info(data->dev, "detected phy mask %x\n", ~phy_mask);
326 phy_mask = ~phy_mask;
328 /* desperately scan all phys */
329 dev_warn(data->dev, "no live phy, scanning all\n");
332 data->bus->phy_mask = phy_mask;
335 pm_runtime_mark_last_busy(data->dev);
336 pm_runtime_put_autosuspend(data->dev);
341 static int davinci_mdio_reset(struct mii_bus *bus)
343 struct davinci_mdio_data *data = bus->priv;
345 return davinci_mdio_common_reset(data);
348 static int davinci_mdiobb_reset(struct mii_bus *bus)
350 struct mdiobb_ctrl *ctrl = bus->priv;
351 struct davinci_mdio_data *data;
353 data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
355 return davinci_mdio_common_reset(data);
358 /* wait until hardware is ready for another user access */
359 static inline int wait_for_user_access(struct davinci_mdio_data *data)
361 struct davinci_mdio_regs __iomem *regs = data->regs;
362 unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
365 while (time_after(timeout, jiffies)) {
366 reg = readl(®s->user[0].access);
367 if ((reg & USERACCESS_GO) == 0)
370 reg = readl(®s->control);
371 if ((reg & CONTROL_IDLE) == 0) {
372 usleep_range(100, 200);
377 * An emac soft_reset may have clobbered the mdio controller's
378 * state machine. We need to reset and retry the current
381 dev_warn(data->dev, "resetting idled controller\n");
382 davinci_mdio_enable(data);
386 reg = readl(®s->user[0].access);
387 if ((reg & USERACCESS_GO) == 0)
390 dev_err(data->dev, "timed out waiting for user access\n");
394 /* wait until hardware state machine is idle */
395 static inline int wait_for_idle(struct davinci_mdio_data *data)
397 struct davinci_mdio_regs __iomem *regs = data->regs;
400 ret = readl_poll_timeout(®s->control, val, val & CONTROL_IDLE,
401 0, MDIO_TIMEOUT * 1000);
403 dev_err(data->dev, "timed out waiting for idle\n");
408 static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
410 struct davinci_mdio_data *data = bus->priv;
414 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
417 ret = pm_runtime_resume_and_get(data->dev);
421 reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
425 ret = wait_for_user_access(data);
431 writel(reg, &data->regs->user[0].access);
433 ret = wait_for_user_access(data);
439 reg = readl(&data->regs->user[0].access);
440 ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO;
444 pm_runtime_mark_last_busy(data->dev);
445 pm_runtime_put_autosuspend(data->dev);
449 static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
450 int phy_reg, u16 phy_data)
452 struct davinci_mdio_data *data = bus->priv;
456 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
459 ret = pm_runtime_resume_and_get(data->dev);
463 reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
464 (phy_id << 16) | (phy_data & USERACCESS_DATA));
467 ret = wait_for_user_access(data);
473 writel(reg, &data->regs->user[0].access);
475 ret = wait_for_user_access(data);
481 pm_runtime_mark_last_busy(data->dev);
482 pm_runtime_put_autosuspend(data->dev);
487 static int davinci_mdio_probe_dt(struct mdio_platform_data *data,
488 struct platform_device *pdev)
490 struct device_node *node = pdev->dev.of_node;
496 if (of_property_read_u32(node, "bus_freq", &prop)) {
497 dev_err(&pdev->dev, "Missing bus_freq property in the DT.\n");
500 data->bus_freq = prop;
505 struct k3_mdio_soc_data {
509 static const struct k3_mdio_soc_data am65_mdio_soc_data = {
513 static const struct soc_device_attribute k3_mdio_socinfo[] = {
514 { .family = "AM62X", .data = &am65_mdio_soc_data },
515 { .family = "AM64X", .data = &am65_mdio_soc_data },
516 { .family = "AM65X", .data = &am65_mdio_soc_data },
517 { .family = "J7200", .data = &am65_mdio_soc_data },
518 { .family = "J721E", .data = &am65_mdio_soc_data },
519 { .family = "J721S2", .data = &am65_mdio_soc_data },
523 #if IS_ENABLED(CONFIG_OF)
524 static const struct davinci_mdio_of_param of_cpsw_mdio_data = {
525 .autosuspend_delay_ms = 100,
528 static const struct of_device_id davinci_mdio_of_mtable[] = {
529 { .compatible = "ti,davinci_mdio", },
530 { .compatible = "ti,cpsw-mdio", .data = &of_cpsw_mdio_data},
533 MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable);
536 static const struct mdiobb_ops davinci_mdiobb_ops = {
537 .owner = THIS_MODULE,
538 .set_mdc = davinci_set_mdc,
539 .set_mdio_dir = davinci_set_mdio_dir,
540 .set_mdio_data = davinci_set_mdio_data,
541 .get_mdio_data = davinci_get_mdio_data,
544 static int davinci_mdio_probe(struct platform_device *pdev)
546 struct mdio_platform_data *pdata = dev_get_platdata(&pdev->dev);
547 struct device *dev = &pdev->dev;
548 struct davinci_mdio_data *data;
549 struct resource *res;
550 struct phy_device *phy;
552 int autosuspend_delay_ms = -1;
554 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
558 data->manual_mode = false;
559 data->bb_ctrl.ops = &davinci_mdiobb_ops;
561 if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
562 const struct soc_device_attribute *soc_match_data;
564 soc_match_data = soc_device_match(k3_mdio_socinfo);
565 if (soc_match_data && soc_match_data->data) {
566 const struct k3_mdio_soc_data *socdata =
567 soc_match_data->data;
569 data->manual_mode = socdata->manual_mode;
573 if (data->manual_mode)
574 data->bus = alloc_mdio_bitbang(&data->bb_ctrl);
576 data->bus = devm_mdiobus_alloc(dev);
579 dev_err(dev, "failed to alloc mii bus\n");
583 if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
584 const struct davinci_mdio_of_param *of_mdio_data;
586 ret = davinci_mdio_probe_dt(&data->pdata, pdev);
589 snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
591 of_mdio_data = of_device_get_match_data(&pdev->dev);
593 autosuspend_delay_ms =
594 of_mdio_data->autosuspend_delay_ms;
597 data->pdata = pdata ? (*pdata) : default_pdata;
598 snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
599 pdev->name, pdev->id);
602 data->bus->name = dev_name(dev);
604 if (data->manual_mode) {
605 data->bus->read = davinci_mdiobb_read_c22;
606 data->bus->write = davinci_mdiobb_write_c22;
607 data->bus->read_c45 = davinci_mdiobb_read_c45;
608 data->bus->write_c45 = davinci_mdiobb_write_c45;
609 data->bus->reset = davinci_mdiobb_reset;
611 dev_info(dev, "Configuring MDIO in manual mode\n");
613 data->bus->read = davinci_mdio_read;
614 data->bus->write = davinci_mdio_write;
615 data->bus->reset = davinci_mdio_reset;
616 data->bus->priv = data;
618 data->bus->parent = dev;
620 data->clk = devm_clk_get(dev, "fck");
621 if (IS_ERR(data->clk)) {
622 dev_err(dev, "failed to get device clock\n");
623 return PTR_ERR(data->clk);
626 dev_set_drvdata(dev, data);
629 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
632 data->regs = devm_ioremap(dev, res->start, resource_size(res));
636 davinci_mdio_init_clk(data);
638 pm_runtime_set_autosuspend_delay(&pdev->dev, autosuspend_delay_ms);
639 pm_runtime_use_autosuspend(&pdev->dev);
640 pm_runtime_enable(&pdev->dev);
642 /* register the mii bus
643 * Create PHYs from DT only in case if PHY child nodes are explicitly
644 * defined to support backward compatibility with DTs which assume that
645 * Davinci MDIO will always scan the bus for PHYs detection.
647 if (dev->of_node && of_get_child_count(dev->of_node))
648 data->skip_scan = true;
650 ret = of_mdiobus_register(data->bus, dev->of_node);
654 /* scan and dump the bus */
655 for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
656 phy = mdiobus_get_phy(data->bus, addr);
658 dev_info(dev, "phy[%d]: device %s, driver %s\n",
659 phy->mdio.addr, phydev_name(phy),
660 phy->drv ? phy->drv->name : "unknown");
667 pm_runtime_dont_use_autosuspend(&pdev->dev);
668 pm_runtime_disable(&pdev->dev);
672 static void davinci_mdio_remove(struct platform_device *pdev)
674 struct davinci_mdio_data *data = platform_get_drvdata(pdev);
677 mdiobus_unregister(data->bus);
679 if (data->manual_mode)
680 free_mdio_bitbang(data->bus);
683 pm_runtime_dont_use_autosuspend(&pdev->dev);
684 pm_runtime_disable(&pdev->dev);
688 static int davinci_mdio_runtime_suspend(struct device *dev)
690 struct davinci_mdio_data *data = dev_get_drvdata(dev);
693 /* shutdown the scan state machine */
694 ctrl = readl(&data->regs->control);
695 ctrl &= ~CONTROL_ENABLE;
696 writel(ctrl, &data->regs->control);
698 if (!data->manual_mode)
704 static int davinci_mdio_runtime_resume(struct device *dev)
706 struct davinci_mdio_data *data = dev_get_drvdata(dev);
708 if (data->manual_mode) {
709 davinci_mdio_disable(data);
710 davinci_mdio_enable_manual_mode(data);
712 davinci_mdio_enable(data);
718 #ifdef CONFIG_PM_SLEEP
719 static int davinci_mdio_suspend(struct device *dev)
721 struct davinci_mdio_data *data = dev_get_drvdata(dev);
724 data->active_in_suspend = !pm_runtime_status_suspended(dev);
725 if (data->active_in_suspend)
726 ret = pm_runtime_force_suspend(dev);
730 /* Select sleep pin state */
731 pinctrl_pm_select_sleep_state(dev);
736 static int davinci_mdio_resume(struct device *dev)
738 struct davinci_mdio_data *data = dev_get_drvdata(dev);
740 /* Select default pin state */
741 pinctrl_pm_select_default_state(dev);
743 if (data->active_in_suspend)
744 pm_runtime_force_resume(dev);
750 static const struct dev_pm_ops davinci_mdio_pm_ops = {
751 SET_RUNTIME_PM_OPS(davinci_mdio_runtime_suspend,
752 davinci_mdio_runtime_resume, NULL)
753 SET_LATE_SYSTEM_SLEEP_PM_OPS(davinci_mdio_suspend, davinci_mdio_resume)
756 static struct platform_driver davinci_mdio_driver = {
758 .name = "davinci_mdio",
759 .pm = &davinci_mdio_pm_ops,
760 .of_match_table = of_match_ptr(davinci_mdio_of_mtable),
762 .probe = davinci_mdio_probe,
763 .remove_new = davinci_mdio_remove,
766 static int __init davinci_mdio_init(void)
768 return platform_driver_register(&davinci_mdio_driver);
770 device_initcall(davinci_mdio_init);
772 static void __exit davinci_mdio_exit(void)
774 platform_driver_unregister(&davinci_mdio_driver);
776 module_exit(davinci_mdio_exit);
778 MODULE_LICENSE("GPL");
779 MODULE_DESCRIPTION("DaVinci MDIO driver");