2 * DaVinci Ethernet Medium Access Controller
4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
6 * Copyright (C) 2009 Texas Instruments.
8 * ---------------------------------------------------------------------------
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole
27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/sched.h>
35 #include <linux/string.h>
36 #include <linux/timer.h>
37 #include <linux/errno.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
42 #include <linux/interrupt.h>
43 #include <linux/init.h>
44 #include <linux/netdevice.h>
45 #include <linux/etherdevice.h>
46 #include <linux/skbuff.h>
47 #include <linux/ethtool.h>
48 #include <linux/highmem.h>
49 #include <linux/proc_fs.h>
50 #include <linux/ctype.h>
51 #include <linux/spinlock.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/clk.h>
54 #include <linux/platform_device.h>
55 #include <linux/regmap.h>
56 #include <linux/semaphore.h>
57 #include <linux/phy.h>
58 #include <linux/bitops.h>
60 #include <linux/uaccess.h>
61 #include <linux/pm_runtime.h>
62 #include <linux/davinci_emac.h>
64 #include <linux/of_address.h>
65 #include <linux/of_device.h>
66 #include <linux/of_mdio.h>
67 #include <linux/of_irq.h>
68 #include <linux/of_net.h>
69 #include <linux/mfd/syscon.h>
75 #include "davinci_cpdma.h"
77 static int debug_level;
78 module_param(debug_level, int, 0);
79 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
81 /* Netif debug messages possible */
82 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
90 NETIF_MSG_TX_QUEUED | \
93 NETIF_MSG_RX_STATUS | \
99 #define EMAC_MAJOR_VERSION 6
100 #define EMAC_MINOR_VERSION 1
101 #define EMAC_MODULE_VERSION "6.1"
102 MODULE_VERSION(EMAC_MODULE_VERSION);
103 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
105 /* Configuration items */
106 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */
107 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
108 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
109 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
110 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
111 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
112 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */
113 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */
114 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
115 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
116 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
117 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
119 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
120 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
122 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
123 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
124 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
125 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
126 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
127 #define EMAC_DEF_RX_NUM_DESC (128)
128 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
129 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
130 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
132 /* Buffer descriptor parameters */
133 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
134 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
136 /* EMAC register related defines */
137 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
138 #define EMAC_NUM_MULTICAST_BITS (64)
139 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
140 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
141 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
142 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
143 #define EMAC_INT_MASK_CLEAR (0xFF)
145 /* RX MBP register bit positions */
146 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
147 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
148 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
149 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
150 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
151 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
152 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
153 #define EMAC_RXMBP_PROMCH_SHIFT (16)
154 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
155 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
156 #define EMAC_RXMBP_BROADCH_SHIFT (8)
157 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
158 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
159 #define EMAC_RXMBP_MULTICH_SHIFT (0)
160 #define EMAC_RXMBP_MULTICH_MASK (0x7)
161 #define EMAC_RXMBP_CHMASK (0x7)
163 /* EMAC register definitions/bit maps used */
164 # define EMAC_MBP_RXPROMISC (0x00200000)
165 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
166 # define EMAC_MBP_RXBCAST (0x00002000)
167 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
168 # define EMAC_MBP_RXMCAST (0x00000020)
169 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
171 /* EMAC mac_control register */
172 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
173 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
174 #define EMAC_MACCONTROL_GMIIEN BIT(5)
175 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
176 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
177 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
179 /* GIGABIT MODE related bits */
180 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
181 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
183 /* EMAC mac_status register */
184 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
185 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
186 #define EMAC_MACSTATUS_TXERRCH_MASK (0x70000)
187 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
188 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
189 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
190 #define EMAC_MACSTATUS_RXERRCH_MASK (0x700)
191 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
193 /* EMAC RX register masks */
194 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
195 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
197 /* MAC_IN_VECTOR (0x180) register bit fields */
198 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
199 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
200 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
201 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
203 /** NOTE:: For DM646x the IN_VECTOR has changed */
204 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
205 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
206 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
207 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
209 /* CPPI bit positions */
210 #define EMAC_CPPI_SOP_BIT BIT(31)
211 #define EMAC_CPPI_EOP_BIT BIT(30)
212 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
213 #define EMAC_CPPI_EOQ_BIT BIT(28)
214 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
215 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
216 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
217 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
218 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
220 /* Max hardware defines */
221 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
222 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
224 /* EMAC Peripheral Device Register Memory Layout structure */
225 #define EMAC_MACINVECTOR 0x90
227 #define EMAC_DM646X_MACEOIVECTOR 0x94
229 #define EMAC_MACINTSTATRAW 0xB0
230 #define EMAC_MACINTSTATMASKED 0xB4
231 #define EMAC_MACINTMASKSET 0xB8
232 #define EMAC_MACINTMASKCLEAR 0xBC
234 #define EMAC_RXMBPENABLE 0x100
235 #define EMAC_RXUNICASTSET 0x104
236 #define EMAC_RXUNICASTCLEAR 0x108
237 #define EMAC_RXMAXLEN 0x10C
238 #define EMAC_RXBUFFEROFFSET 0x110
239 #define EMAC_RXFILTERLOWTHRESH 0x114
241 #define EMAC_MACCONTROL 0x160
242 #define EMAC_MACSTATUS 0x164
243 #define EMAC_EMCONTROL 0x168
244 #define EMAC_FIFOCONTROL 0x16C
245 #define EMAC_MACCONFIG 0x170
246 #define EMAC_SOFTRESET 0x174
247 #define EMAC_MACSRCADDRLO 0x1D0
248 #define EMAC_MACSRCADDRHI 0x1D4
249 #define EMAC_MACHASH1 0x1D8
250 #define EMAC_MACHASH2 0x1DC
251 #define EMAC_MACADDRLO 0x500
252 #define EMAC_MACADDRHI 0x504
253 #define EMAC_MACINDEX 0x508
255 /* EMAC statistics registers */
256 #define EMAC_RXGOODFRAMES 0x200
257 #define EMAC_RXBCASTFRAMES 0x204
258 #define EMAC_RXMCASTFRAMES 0x208
259 #define EMAC_RXPAUSEFRAMES 0x20C
260 #define EMAC_RXCRCERRORS 0x210
261 #define EMAC_RXALIGNCODEERRORS 0x214
262 #define EMAC_RXOVERSIZED 0x218
263 #define EMAC_RXJABBER 0x21C
264 #define EMAC_RXUNDERSIZED 0x220
265 #define EMAC_RXFRAGMENTS 0x224
266 #define EMAC_RXFILTERED 0x228
267 #define EMAC_RXQOSFILTERED 0x22C
268 #define EMAC_RXOCTETS 0x230
269 #define EMAC_TXGOODFRAMES 0x234
270 #define EMAC_TXBCASTFRAMES 0x238
271 #define EMAC_TXMCASTFRAMES 0x23C
272 #define EMAC_TXPAUSEFRAMES 0x240
273 #define EMAC_TXDEFERRED 0x244
274 #define EMAC_TXCOLLISION 0x248
275 #define EMAC_TXSINGLECOLL 0x24C
276 #define EMAC_TXMULTICOLL 0x250
277 #define EMAC_TXEXCESSIVECOLL 0x254
278 #define EMAC_TXLATECOLL 0x258
279 #define EMAC_TXUNDERRUN 0x25C
280 #define EMAC_TXCARRIERSENSE 0x260
281 #define EMAC_TXOCTETS 0x264
282 #define EMAC_NETOCTETS 0x280
283 #define EMAC_RXSOFOVERRUNS 0x284
284 #define EMAC_RXMOFOVERRUNS 0x288
285 #define EMAC_RXDMAOVERRUNS 0x28C
287 /* EMAC DM644x control registers */
288 #define EMAC_CTRL_EWCTL (0x4)
289 #define EMAC_CTRL_EWINTTCNT (0x8)
291 /* EMAC DM644x control module masks */
292 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
293 #define EMAC_DM644X_INTMIN_INTVL 0x1
294 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
296 /* EMAC DM646X control module registers */
297 #define EMAC_DM646X_CMINTCTRL 0x0C
298 #define EMAC_DM646X_CMRXINTEN 0x14
299 #define EMAC_DM646X_CMTXINTEN 0x18
300 #define EMAC_DM646X_CMRXINTMAX 0x70
301 #define EMAC_DM646X_CMTXINTMAX 0x74
303 /* EMAC DM646X control module masks */
304 #define EMAC_DM646X_INTPACEEN (0x3 << 16)
305 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
306 #define EMAC_DM646X_CMINTMAX_CNT 63
307 #define EMAC_DM646X_CMINTMIN_CNT 2
308 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
309 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
312 /* EMAC EOI codes for C0 */
313 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
314 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
316 /* EMAC Stats Clear Mask */
317 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
319 /* emac_priv: EMAC private data structure
321 * EMAC adapter private data structure
325 struct net_device *ndev;
326 struct platform_device *pdev;
327 struct napi_struct napi;
329 void __iomem *remap_addr;
331 void __iomem *emac_base;
332 void __iomem *ctrl_base;
333 struct cpdma_ctlr *dma;
334 struct cpdma_chan *txchan;
335 struct cpdma_chan *rxchan;
336 u32 link; /* 1=link on, 0=link off */
337 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
338 u32 duplex; /* Link duplex: 0=Half, 1=Full */
347 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
350 struct device_node *phy_node;
352 /*platform specific members*/
353 void (*int_enable) (void);
354 void (*int_disable) (void);
357 /* EMAC TX Host Error description strings */
358 static char *emac_txhost_errcodes[16] = {
359 "No error", "SOP error", "Ownership bit not set in SOP buffer",
360 "Zero Next Buffer Descriptor Pointer Without EOP",
361 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
362 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
363 "Reserved", "Reserved", "Reserved", "Reserved"
366 /* EMAC RX Host Error description strings */
367 static char *emac_rxhost_errcodes[16] = {
368 "No error", "Reserved", "Ownership bit not set in input buffer",
369 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
370 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
371 "Reserved", "Reserved", "Reserved", "Reserved"
375 #define emac_read(reg) ioread32(priv->emac_base + (reg))
376 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
378 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
379 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
382 * emac_get_drvinfo - Get EMAC driver information
383 * @ndev: The DaVinci EMAC network adapter
384 * @info: ethtool info structure containing name and version
386 * Returns EMAC driver information (name and version)
389 static void emac_get_drvinfo(struct net_device *ndev,
390 struct ethtool_drvinfo *info)
392 strlcpy(info->driver, emac_version_string, sizeof(info->driver));
393 strlcpy(info->version, EMAC_MODULE_VERSION, sizeof(info->version));
397 * emac_get_coalesce - Get interrupt coalesce settings for this device
398 * @ndev : The DaVinci EMAC network adapter
399 * @coal : ethtool coalesce settings structure
401 * Fetch the current interrupt coalesce settings
404 static int emac_get_coalesce(struct net_device *ndev,
405 struct ethtool_coalesce *coal)
407 struct emac_priv *priv = netdev_priv(ndev);
409 coal->rx_coalesce_usecs = priv->coal_intvl;
415 * emac_set_coalesce - Set interrupt coalesce settings for this device
416 * @ndev : The DaVinci EMAC network adapter
417 * @coal : ethtool coalesce settings structure
419 * Set interrupt coalesce parameters
422 static int emac_set_coalesce(struct net_device *ndev,
423 struct ethtool_coalesce *coal)
425 struct emac_priv *priv = netdev_priv(ndev);
426 u32 int_ctrl, num_interrupts = 0;
427 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
429 if (!coal->rx_coalesce_usecs) {
430 priv->coal_intvl = 0;
432 switch (priv->version) {
434 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, 0);
437 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, 0);
444 coal_intvl = coal->rx_coalesce_usecs;
446 switch (priv->version) {
448 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
449 prescale = priv->bus_freq_mhz * 4;
451 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
452 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
454 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
456 * Interrupt pacer works with 4us Pulse, we can
457 * throttle further by dilating the 4us pulse.
459 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
461 if (addnl_dvdr > 1) {
462 prescale *= addnl_dvdr;
463 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
465 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
469 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
473 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
475 int_ctrl |= EMAC_DM646X_INTPACEEN;
476 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
477 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
478 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
480 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
481 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
485 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
486 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
487 prescale = coal_intvl * priv->bus_freq_mhz;
488 if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
489 prescale = EMAC_DM644X_EWINTCNT_MASK;
490 coal_intvl = prescale / priv->bus_freq_mhz;
492 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
497 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
498 priv->coal_intvl = coal_intvl;
505 /* ethtool_ops: DaVinci EMAC Ethtool structure
507 * Ethtool support for EMAC adapter
509 static const struct ethtool_ops ethtool_ops = {
510 .get_drvinfo = emac_get_drvinfo,
511 .get_link = ethtool_op_get_link,
512 .get_coalesce = emac_get_coalesce,
513 .set_coalesce = emac_set_coalesce,
514 .get_ts_info = ethtool_op_get_ts_info,
515 .get_link_ksettings = phy_ethtool_get_link_ksettings,
516 .set_link_ksettings = phy_ethtool_set_link_ksettings,
520 * emac_update_phystatus - Update Phy status
521 * @priv: The DaVinci EMAC private adapter structure
523 * Updates phy status and takes action for network queue if required
524 * based upon link status
527 static void emac_update_phystatus(struct emac_priv *priv)
532 struct net_device *ndev = priv->ndev;
534 mac_control = emac_read(EMAC_MACCONTROL);
535 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
536 DUPLEX_FULL : DUPLEX_HALF;
538 new_duplex = ndev->phydev->duplex;
540 new_duplex = DUPLEX_FULL;
542 /* We get called only if link has changed (speed/duplex/status) */
543 if ((priv->link) && (new_duplex != cur_duplex)) {
544 priv->duplex = new_duplex;
545 if (DUPLEX_FULL == priv->duplex)
546 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
548 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
551 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
552 mac_control = emac_read(EMAC_MACCONTROL);
553 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
554 EMAC_DM646X_MACCONTORL_GIGFORCE);
556 /* Clear the GIG bit and GIGFORCE bit */
557 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
558 EMAC_DM646X_MACCONTORL_GIG);
560 if (priv->rmii_en && (priv->speed == SPEED_100))
561 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
563 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
566 /* Update mac_control if changed */
567 emac_write(EMAC_MACCONTROL, mac_control);
571 if (!netif_carrier_ok(ndev))
572 netif_carrier_on(ndev);
573 /* reactivate the transmit queue if it is stopped */
574 if (netif_running(ndev) && netif_queue_stopped(ndev))
575 netif_wake_queue(ndev);
578 if (netif_carrier_ok(ndev))
579 netif_carrier_off(ndev);
580 if (!netif_queue_stopped(ndev))
581 netif_stop_queue(ndev);
586 * hash_get - Calculate hash value from mac address
587 * @addr: mac address to delete from hash table
589 * Calculates hash value from mac address
592 static u32 hash_get(u8 *addr)
599 for (cnt = 0; cnt < 2; cnt++) {
601 hash ^= (tmpval >> 2) ^ (tmpval << 4);
603 hash ^= (tmpval >> 4) ^ (tmpval << 2);
605 hash ^= (tmpval >> 6) ^ (tmpval);
612 * emac_hash_add - Hash function to add mac addr from hash table
613 * @priv: The DaVinci EMAC private adapter structure
614 * @mac_addr: mac address to delete from hash table
616 * Adds mac address to the internal hash table
619 static int emac_hash_add(struct emac_priv *priv, u8 *mac_addr)
621 struct device *emac_dev = &priv->ndev->dev;
624 u32 hash_value = hash_get(mac_addr);
626 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
627 if (netif_msg_drv(priv)) {
628 dev_err(emac_dev, "DaVinci EMAC: emac_hash_add(): Invalid "\
629 "Hash %08x, should not be greater than %08x",
630 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
635 /* set the hash bit only if not previously set */
636 if (priv->multicast_hash_cnt[hash_value] == 0) {
637 rc = 1; /* hash value changed */
638 if (hash_value < 32) {
639 hash_bit = BIT(hash_value);
640 priv->mac_hash1 |= hash_bit;
642 hash_bit = BIT((hash_value - 32));
643 priv->mac_hash2 |= hash_bit;
647 /* incr counter for num of mcast addr's mapped to "this" hash bit */
648 ++priv->multicast_hash_cnt[hash_value];
654 * emac_hash_del - Hash function to delete mac addr from hash table
655 * @priv: The DaVinci EMAC private adapter structure
656 * @mac_addr: mac address to delete from hash table
658 * Removes mac address from the internal hash table
661 static int emac_hash_del(struct emac_priv *priv, u8 *mac_addr)
666 hash_value = hash_get(mac_addr);
667 if (priv->multicast_hash_cnt[hash_value] > 0) {
668 /* dec cntr for num of mcast addr's mapped to this hash bit */
669 --priv->multicast_hash_cnt[hash_value];
672 /* if counter still > 0, at least one multicast address refers
673 * to this hash bit. so return 0 */
674 if (priv->multicast_hash_cnt[hash_value] > 0)
677 if (hash_value < 32) {
678 hash_bit = BIT(hash_value);
679 priv->mac_hash1 &= ~hash_bit;
681 hash_bit = BIT((hash_value - 32));
682 priv->mac_hash2 &= ~hash_bit;
685 /* return 1 to indicate change in mac_hash registers reqd */
689 /* EMAC multicast operation */
690 #define EMAC_MULTICAST_ADD 0
691 #define EMAC_MULTICAST_DEL 1
692 #define EMAC_ALL_MULTI_SET 2
693 #define EMAC_ALL_MULTI_CLR 3
696 * emac_add_mcast - Set multicast address in the EMAC adapter (Internal)
697 * @priv: The DaVinci EMAC private adapter structure
698 * @action: multicast operation to perform
699 * mac_addr: mac address to set
701 * Set multicast addresses in EMAC adapter - internal function
704 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
706 struct device *emac_dev = &priv->ndev->dev;
710 case EMAC_MULTICAST_ADD:
711 update = emac_hash_add(priv, mac_addr);
713 case EMAC_MULTICAST_DEL:
714 update = emac_hash_del(priv, mac_addr);
716 case EMAC_ALL_MULTI_SET:
718 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
719 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
721 case EMAC_ALL_MULTI_CLR:
725 memset(&(priv->multicast_hash_cnt[0]), 0,
726 sizeof(priv->multicast_hash_cnt[0]) *
727 EMAC_NUM_MULTICAST_BITS);
730 if (netif_msg_drv(priv))
731 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
732 ": bad operation %d", action);
736 /* write to the hardware only if the register status chances */
738 emac_write(EMAC_MACHASH1, priv->mac_hash1);
739 emac_write(EMAC_MACHASH2, priv->mac_hash2);
744 * emac_dev_mcast_set - Set multicast address in the EMAC adapter
745 * @ndev: The DaVinci EMAC network adapter
747 * Set multicast addresses in EMAC adapter
750 static void emac_dev_mcast_set(struct net_device *ndev)
753 struct emac_priv *priv = netdev_priv(ndev);
755 mbp_enable = emac_read(EMAC_RXMBPENABLE);
756 if (ndev->flags & IFF_PROMISC) {
757 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
758 mbp_enable |= (EMAC_MBP_RXPROMISC);
760 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
761 if ((ndev->flags & IFF_ALLMULTI) ||
762 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
763 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
764 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
765 } else if (!netdev_mc_empty(ndev)) {
766 struct netdev_hw_addr *ha;
768 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
769 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
770 /* program multicast address list into EMAC hardware */
771 netdev_for_each_mc_addr(ha, ndev) {
772 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
776 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
777 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
780 /* Set mbp config register */
781 emac_write(EMAC_RXMBPENABLE, mbp_enable);
784 /*************************************************************************
785 * EMAC Hardware manipulation
786 *************************************************************************/
789 * emac_int_disable - Disable EMAC module interrupt (from adapter)
790 * @priv: The DaVinci EMAC private adapter structure
792 * Disable EMAC interrupt on the adapter
795 static void emac_int_disable(struct emac_priv *priv)
797 if (priv->version == EMAC_VERSION_2) {
800 local_irq_save(flags);
802 /* Program C0_Int_En to zero to turn off
803 * interrupts to the CPU */
804 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
805 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
806 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
807 if (priv->int_disable)
810 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
812 /* ack rxen only then a new pulse will be generated */
813 emac_write(EMAC_DM646X_MACEOIVECTOR,
814 EMAC_DM646X_MAC_EOI_C0_RXEN);
816 /* ack txen- only then a new pulse will be generated */
817 emac_write(EMAC_DM646X_MACEOIVECTOR,
818 EMAC_DM646X_MAC_EOI_C0_TXEN);
820 local_irq_restore(flags);
823 /* Set DM644x control registers for interrupt control */
824 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
829 * emac_int_enable - Enable EMAC module interrupt (from adapter)
830 * @priv: The DaVinci EMAC private adapter structure
832 * Enable EMAC interrupt on the adapter
835 static void emac_int_enable(struct emac_priv *priv)
837 if (priv->version == EMAC_VERSION_2) {
838 if (priv->int_enable)
841 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
842 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
844 /* In addition to turning on interrupt Enable, we need
845 * ack by writing appropriate values to the EOI
848 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
850 /* Set DM644x control registers for interrupt control */
851 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
856 * emac_irq - EMAC interrupt handler
857 * @irq: interrupt number
858 * @dev_id: EMAC network adapter data structure ptr
860 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
861 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
863 * Returns interrupt handled condition
865 static irqreturn_t emac_irq(int irq, void *dev_id)
867 struct net_device *ndev = (struct net_device *)dev_id;
868 struct emac_priv *priv = netdev_priv(ndev);
871 if (likely(netif_running(priv->ndev))) {
872 emac_int_disable(priv);
873 napi_schedule(&priv->napi);
875 /* we are closing down, so dont process anything */
880 static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
882 struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size);
885 skb_reserve(skb, NET_IP_ALIGN);
889 static void emac_rx_handler(void *token, int len, int status)
891 struct sk_buff *skb = token;
892 struct net_device *ndev = skb->dev;
893 struct emac_priv *priv = netdev_priv(ndev);
894 struct device *emac_dev = &ndev->dev;
897 /* free and bail if we are shutting down */
898 if (unlikely(!netif_running(ndev))) {
899 dev_kfree_skb_any(skb);
903 /* recycle on receive error */
905 ndev->stats.rx_errors++;
909 /* feed received packet up the stack */
911 skb->protocol = eth_type_trans(skb, ndev);
912 netif_receive_skb(skb);
913 ndev->stats.rx_bytes += len;
914 ndev->stats.rx_packets++;
916 /* alloc a new packet for receive */
917 skb = emac_rx_alloc(priv);
919 if (netif_msg_rx_err(priv) && net_ratelimit())
920 dev_err(emac_dev, "failed rx buffer alloc\n");
925 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
926 skb_tailroom(skb), 0);
928 WARN_ON(ret == -ENOMEM);
929 if (unlikely(ret < 0))
930 dev_kfree_skb_any(skb);
933 static void emac_tx_handler(void *token, int len, int status)
935 struct sk_buff *skb = token;
936 struct net_device *ndev = skb->dev;
938 /* Check whether the queue is stopped due to stalled tx dma, if the
939 * queue is stopped then start the queue as we have free desc for tx
941 if (unlikely(netif_queue_stopped(ndev)))
942 netif_wake_queue(ndev);
943 ndev->stats.tx_packets++;
944 ndev->stats.tx_bytes += len;
945 dev_kfree_skb_any(skb);
949 * emac_dev_xmit - EMAC Transmit function
951 * @ndev: The DaVinci EMAC network adapter
953 * Called by the system to transmit a packet - we queue the packet in
954 * EMAC hardware transmit queue
956 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
958 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
960 struct device *emac_dev = &ndev->dev;
962 struct emac_priv *priv = netdev_priv(ndev);
964 /* If no link, return */
965 if (unlikely(!priv->link)) {
966 if (netif_msg_tx_err(priv) && net_ratelimit())
967 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
971 ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
972 if (unlikely(ret_code < 0)) {
973 if (netif_msg_tx_err(priv) && net_ratelimit())
974 dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
978 skb_tx_timestamp(skb);
980 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
982 if (unlikely(ret_code != 0)) {
983 if (netif_msg_tx_err(priv) && net_ratelimit())
984 dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
988 /* If there is no more tx desc left free then we need to
989 * tell the kernel to stop sending us tx frames.
991 if (unlikely(!cpdma_check_free_tx_desc(priv->txchan)))
992 netif_stop_queue(ndev);
997 ndev->stats.tx_dropped++;
998 netif_stop_queue(ndev);
999 return NETDEV_TX_BUSY;
1003 * emac_dev_tx_timeout - EMAC Transmit timeout function
1004 * @ndev: The DaVinci EMAC network adapter
1006 * Called when system detects that a skb timeout period has expired
1007 * potentially due to a fault in the adapter in not being able to send
1008 * it out on the wire. We teardown the TX channel assuming a hardware
1009 * error and re-initialize the TX channel for hardware operation
1012 static void emac_dev_tx_timeout(struct net_device *ndev)
1014 struct emac_priv *priv = netdev_priv(ndev);
1015 struct device *emac_dev = &ndev->dev;
1017 if (netif_msg_tx_err(priv))
1018 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1020 ndev->stats.tx_errors++;
1021 emac_int_disable(priv);
1022 cpdma_chan_stop(priv->txchan);
1023 cpdma_chan_start(priv->txchan);
1024 emac_int_enable(priv);
1028 * emac_set_type0addr - Set EMAC Type0 mac address
1029 * @priv: The DaVinci EMAC private adapter structure
1030 * @ch: RX channel number
1031 * @mac_addr: MAC address to set in device
1033 * Called internally to set Type0 mac address of the adapter (Device)
1035 * Returns success (0) or appropriate error code (none as of now)
1037 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1040 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1041 emac_write(EMAC_MACSRCADDRLO, val);
1043 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1044 (mac_addr[1] << 8) | (mac_addr[0]));
1045 emac_write(EMAC_MACSRCADDRHI, val);
1046 val = emac_read(EMAC_RXUNICASTSET);
1048 emac_write(EMAC_RXUNICASTSET, val);
1049 val = emac_read(EMAC_RXUNICASTCLEAR);
1051 emac_write(EMAC_RXUNICASTCLEAR, val);
1055 * emac_set_type1addr - Set EMAC Type1 mac address
1056 * @priv: The DaVinci EMAC private adapter structure
1057 * @ch: RX channel number
1058 * @mac_addr: MAC address to set in device
1060 * Called internally to set Type1 mac address of the adapter (Device)
1062 * Returns success (0) or appropriate error code (none as of now)
1064 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1067 emac_write(EMAC_MACINDEX, ch);
1068 val = ((mac_addr[5] << 8) | mac_addr[4]);
1069 emac_write(EMAC_MACADDRLO, val);
1070 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1071 (mac_addr[1] << 8) | (mac_addr[0]));
1072 emac_write(EMAC_MACADDRHI, val);
1073 emac_set_type0addr(priv, ch, mac_addr);
1077 * emac_set_type2addr - Set EMAC Type2 mac address
1078 * @priv: The DaVinci EMAC private adapter structure
1079 * @ch: RX channel number
1080 * @mac_addr: MAC address to set in device
1081 * @index: index into RX address entries
1082 * @match: match parameter for RX address matching logic
1084 * Called internally to set Type2 mac address of the adapter (Device)
1086 * Returns success (0) or appropriate error code (none as of now)
1088 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1089 char *mac_addr, int index, int match)
1092 emac_write(EMAC_MACINDEX, index);
1093 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1094 (mac_addr[1] << 8) | (mac_addr[0]));
1095 emac_write(EMAC_MACADDRHI, val);
1096 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1097 (match << 19) | BIT(20));
1098 emac_write(EMAC_MACADDRLO, val);
1099 emac_set_type0addr(priv, ch, mac_addr);
1103 * emac_setmac - Set mac address in the adapter (internal function)
1104 * @priv: The DaVinci EMAC private adapter structure
1105 * @ch: RX channel number
1106 * @mac_addr: MAC address to set in device
1108 * Called internally to set the mac address of the adapter (Device)
1110 * Returns success (0) or appropriate error code (none as of now)
1112 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1114 struct device *emac_dev = &priv->ndev->dev;
1116 if (priv->rx_addr_type == 0) {
1117 emac_set_type0addr(priv, ch, mac_addr);
1118 } else if (priv->rx_addr_type == 1) {
1120 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1121 emac_set_type1addr(priv, ch, mac_addr);
1122 } else if (priv->rx_addr_type == 2) {
1123 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1124 emac_set_type0addr(priv, ch, mac_addr);
1126 if (netif_msg_drv(priv))
1127 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1132 * emac_dev_setmac_addr - Set mac address in the adapter
1133 * @ndev: The DaVinci EMAC network adapter
1134 * @addr: MAC address to set in device
1136 * Called by the system to set the mac address of the adapter (Device)
1138 * Returns success (0) or appropriate error code (none as of now)
1140 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1142 struct emac_priv *priv = netdev_priv(ndev);
1143 struct device *emac_dev = &priv->ndev->dev;
1144 struct sockaddr *sa = addr;
1146 if (!is_valid_ether_addr(sa->sa_data))
1147 return -EADDRNOTAVAIL;
1149 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1150 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1151 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1153 /* MAC address is configured only after the interface is enabled. */
1154 if (netif_running(ndev)) {
1155 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1158 if (netif_msg_drv(priv))
1159 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1166 * emac_hw_enable - Enable EMAC hardware for packet transmission/reception
1167 * @priv: The DaVinci EMAC private adapter structure
1169 * Enables EMAC hardware for packet processing - enables PHY, enables RX
1170 * for packet reception and enables device interrupts and then NAPI
1172 * Returns success (0) or appropriate error code (none right now)
1174 static int emac_hw_enable(struct emac_priv *priv)
1176 u32 val, mbp_enable, mac_control;
1179 emac_write(EMAC_SOFTRESET, 1);
1180 while (emac_read(EMAC_SOFTRESET))
1183 /* Disable interrupt & Set pacing for more interrupts initially */
1184 emac_int_disable(priv);
1186 /* Full duplex enable bit set when auto negotiation happens */
1188 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
1189 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
1190 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
1191 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
1192 emac_write(EMAC_MACCONTROL, mac_control);
1195 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
1196 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
1197 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
1198 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
1199 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
1200 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
1201 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
1202 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
1203 EMAC_RXMBP_PROMCH_SHIFT) |
1204 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
1205 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
1206 EMAC_RXMBP_BROADCH_SHIFT) |
1207 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
1208 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
1209 EMAC_RXMBP_MULTICH_SHIFT));
1210 emac_write(EMAC_RXMBPENABLE, mbp_enable);
1211 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
1212 EMAC_RX_MAX_LEN_MASK));
1213 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
1214 EMAC_RX_BUFFER_OFFSET_MASK));
1215 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
1216 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
1217 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
1219 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
1221 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1224 val = emac_read(EMAC_MACCONTROL);
1225 val |= (EMAC_MACCONTROL_GMIIEN);
1226 emac_write(EMAC_MACCONTROL, val);
1228 /* Enable NAPI and interrupts */
1229 napi_enable(&priv->napi);
1230 emac_int_enable(priv);
1236 * emac_poll - EMAC NAPI Poll function
1237 * @ndev: The DaVinci EMAC network adapter
1238 * @budget: Number of receive packets to process (as told by NAPI layer)
1240 * NAPI Poll function implemented to process packets as per budget. We check
1241 * the type of interrupt on the device and accordingly call the TX or RX
1242 * packet processing functions. We follow the budget for RX processing and
1243 * also put a cap on number of TX pkts processed through config param. The
1244 * NAPI schedule function is called if more packets pending.
1246 * Returns number of packets received (in most cases; else TX pkts - rarely)
1248 static int emac_poll(struct napi_struct *napi, int budget)
1251 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
1252 struct net_device *ndev = priv->ndev;
1253 struct device *emac_dev = &ndev->dev;
1255 u32 num_tx_pkts = 0, num_rx_pkts = 0;
1257 /* Check interrupt vectors and call packet processing */
1258 status = emac_read(EMAC_MACINVECTOR);
1260 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
1262 if (priv->version == EMAC_VERSION_2)
1263 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
1265 if (status & mask) {
1266 num_tx_pkts = cpdma_chan_process(priv->txchan,
1267 EMAC_DEF_TX_MAX_SERVICE);
1268 } /* TX processing */
1270 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
1272 if (priv->version == EMAC_VERSION_2)
1273 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
1275 if (status & mask) {
1276 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
1277 } /* RX processing */
1279 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
1280 if (priv->version == EMAC_VERSION_2)
1281 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
1283 if (unlikely(status & mask)) {
1285 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
1286 netif_stop_queue(ndev);
1287 napi_disable(&priv->napi);
1289 status = emac_read(EMAC_MACSTATUS);
1290 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
1291 EMAC_MACSTATUS_TXERRCODE_SHIFT);
1293 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
1294 EMAC_MACSTATUS_TXERRCH_SHIFT);
1295 if (net_ratelimit()) {
1296 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
1297 &emac_txhost_errcodes[cause][0], ch);
1300 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
1301 EMAC_MACSTATUS_RXERRCODE_SHIFT);
1303 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
1304 EMAC_MACSTATUS_RXERRCH_SHIFT);
1305 if (netif_msg_hw(priv) && net_ratelimit())
1306 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
1307 &emac_rxhost_errcodes[cause][0], ch);
1309 } else if (num_rx_pkts < budget) {
1310 napi_complete(napi);
1311 emac_int_enable(priv);
1317 #ifdef CONFIG_NET_POLL_CONTROLLER
1319 * emac_poll_controller - EMAC Poll controller function
1320 * @ndev: The DaVinci EMAC network adapter
1322 * Polled functionality used by netconsole and others in non interrupt mode
1325 static void emac_poll_controller(struct net_device *ndev)
1327 struct emac_priv *priv = netdev_priv(ndev);
1329 emac_int_disable(priv);
1330 emac_irq(ndev->irq, ndev);
1331 emac_int_enable(priv);
1335 static void emac_adjust_link(struct net_device *ndev)
1337 struct emac_priv *priv = netdev_priv(ndev);
1338 struct phy_device *phydev = ndev->phydev;
1339 unsigned long flags;
1342 spin_lock_irqsave(&priv->lock, flags);
1345 /* check the mode of operation - full/half duplex */
1346 if (phydev->duplex != priv->duplex) {
1348 priv->duplex = phydev->duplex;
1350 if (phydev->speed != priv->speed) {
1352 priv->speed = phydev->speed;
1359 } else if (priv->link) {
1366 emac_update_phystatus(priv);
1367 phy_print_status(ndev->phydev);
1370 spin_unlock_irqrestore(&priv->lock, flags);
1373 /*************************************************************************
1374 * Linux Driver Model
1375 *************************************************************************/
1378 * emac_devioctl - EMAC adapter ioctl
1379 * @ndev: The DaVinci EMAC network adapter
1380 * @ifrq: request parameter
1381 * @cmd: command parameter
1383 * EMAC driver ioctl function
1385 * Returns success(0) or appropriate error code
1387 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
1389 if (!(netif_running(ndev)))
1392 /* TODO: Add phy read and write and private statistics get feature */
1395 return phy_mii_ioctl(ndev->phydev, ifrq, cmd);
1400 static int match_first_device(struct device *dev, void *data)
1402 if (dev->parent && dev->parent->of_node)
1403 return of_device_is_compatible(dev->parent->of_node,
1406 return !strncmp(dev_name(dev), "davinci_mdio", 12);
1410 * emac_dev_open - EMAC device open
1411 * @ndev: The DaVinci EMAC network adapter
1413 * Called when system wants to start the interface. We init TX/RX channels
1414 * and enable the hardware for packet reception/transmission and start the
1417 * Returns 0 for a successful open, or appropriate error code
1419 static int emac_dev_open(struct net_device *ndev)
1421 struct device *emac_dev = &ndev->dev;
1423 struct resource *res;
1425 int res_num = 0, irq_num = 0;
1427 struct emac_priv *priv = netdev_priv(ndev);
1428 struct phy_device *phydev = NULL;
1429 struct device *phy = NULL;
1431 ret = pm_runtime_get_sync(&priv->pdev->dev);
1433 pm_runtime_put_noidle(&priv->pdev->dev);
1434 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
1439 netif_carrier_off(ndev);
1440 for (cnt = 0; cnt < ETH_ALEN; cnt++)
1441 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
1443 /* Configuration items */
1444 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
1446 priv->mac_hash1 = 0;
1447 priv->mac_hash2 = 0;
1448 emac_write(EMAC_MACHASH1, 0);
1449 emac_write(EMAC_MACHASH2, 0);
1451 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
1452 struct sk_buff *skb = emac_rx_alloc(priv);
1457 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1458 skb_tailroom(skb), 0);
1459 if (WARN_ON(ret < 0))
1464 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ,
1466 for (irq_num = res->start; irq_num <= res->end; irq_num++) {
1467 if (request_irq(irq_num, emac_irq, 0, ndev->name,
1470 "DaVinci EMAC: request_irq() failed\n");
1478 /* prepare counters for rollback in case of an error */
1482 /* Start/Enable EMAC hardware */
1483 emac_hw_enable(priv);
1485 /* Enable Interrupt pacing if configured */
1486 if (priv->coal_intvl != 0) {
1487 struct ethtool_coalesce coal;
1489 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1490 emac_set_coalesce(ndev, &coal);
1493 cpdma_ctlr_start(priv->dma);
1495 if (priv->phy_node) {
1496 phydev = of_phy_connect(ndev, priv->phy_node,
1497 &emac_adjust_link, 0, 0);
1499 dev_err(emac_dev, "could not connect to phy %s\n",
1500 priv->phy_node->full_name);
1506 /* use the first phy on the bus if pdata did not give us a phy id */
1507 if (!phydev && !priv->phy_id) {
1508 phy = bus_find_device(&mdio_bus_type, NULL, NULL,
1509 match_first_device);
1511 priv->phy_id = dev_name(phy);
1512 if (!priv->phy_id || !*priv->phy_id)
1517 if (!phydev && priv->phy_id && *priv->phy_id) {
1518 phydev = phy_connect(ndev, priv->phy_id,
1520 PHY_INTERFACE_MODE_MII);
1521 put_device(phy); /* reference taken by bus_find_device */
1522 if (IS_ERR(phydev)) {
1523 dev_err(emac_dev, "could not connect to phy %s\n",
1525 ret = PTR_ERR(phydev);
1533 phy_attached_info(phydev);
1537 /* No PHY , fix the link, speed and duplex settings */
1538 dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
1540 priv->speed = SPEED_100;
1541 priv->duplex = DUPLEX_FULL;
1542 emac_update_phystatus(priv);
1545 if (netif_msg_drv(priv))
1546 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
1554 emac_int_disable(priv);
1555 napi_disable(&priv->napi);
1558 for (q = res_num; q >= 0; q--) {
1559 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, q);
1560 /* at the first iteration, irq_num is already set to the
1566 for (m = irq_num; m >= res->start; m--)
1569 cpdma_ctlr_stop(priv->dma);
1570 pm_runtime_put(&priv->pdev->dev);
1575 * emac_dev_stop - EMAC device stop
1576 * @ndev: The DaVinci EMAC network adapter
1578 * Called when system wants to stop or down the interface. We stop the network
1579 * queue, disable interrupts and cleanup TX/RX channels.
1581 * We return the statistics in net_device_stats structure pulled from emac
1583 static int emac_dev_stop(struct net_device *ndev)
1585 struct resource *res;
1588 struct emac_priv *priv = netdev_priv(ndev);
1589 struct device *emac_dev = &ndev->dev;
1591 /* inform the upper layers. */
1592 netif_stop_queue(ndev);
1593 napi_disable(&priv->napi);
1595 netif_carrier_off(ndev);
1596 emac_int_disable(priv);
1597 cpdma_ctlr_stop(priv->dma);
1598 emac_write(EMAC_SOFTRESET, 1);
1601 phy_disconnect(ndev->phydev);
1604 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
1605 for (irq_num = res->start; irq_num <= res->end; irq_num++)
1606 free_irq(irq_num, priv->ndev);
1610 if (netif_msg_drv(priv))
1611 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
1613 pm_runtime_put(&priv->pdev->dev);
1618 * emac_dev_getnetstats - EMAC get statistics function
1619 * @ndev: The DaVinci EMAC network adapter
1621 * Called when system wants to get statistics from the device.
1623 * We return the statistics in net_device_stats structure pulled from emac
1625 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
1627 struct emac_priv *priv = netdev_priv(ndev);
1629 u32 stats_clear_mask;
1632 err = pm_runtime_get_sync(&priv->pdev->dev);
1634 pm_runtime_put_noidle(&priv->pdev->dev);
1635 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
1637 return &ndev->stats;
1640 /* update emac hardware stats and reset the registers*/
1642 mac_control = emac_read(EMAC_MACCONTROL);
1644 if (mac_control & EMAC_MACCONTROL_GMIIEN)
1645 stats_clear_mask = EMAC_STATS_CLR_MASK;
1647 stats_clear_mask = 0;
1649 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
1650 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
1652 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
1653 emac_read(EMAC_TXSINGLECOLL) +
1654 emac_read(EMAC_TXMULTICOLL));
1655 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
1656 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
1657 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
1659 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
1660 emac_read(EMAC_RXJABBER) +
1661 emac_read(EMAC_RXUNDERSIZED));
1662 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
1663 emac_write(EMAC_RXJABBER, stats_clear_mask);
1664 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
1666 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
1667 emac_read(EMAC_RXMOFOVERRUNS));
1668 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
1669 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
1671 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
1672 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
1674 ndev->stats.tx_carrier_errors +=
1675 emac_read(EMAC_TXCARRIERSENSE);
1676 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
1678 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN);
1679 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
1681 pm_runtime_put(&priv->pdev->dev);
1683 return &ndev->stats;
1686 static const struct net_device_ops emac_netdev_ops = {
1687 .ndo_open = emac_dev_open,
1688 .ndo_stop = emac_dev_stop,
1689 .ndo_start_xmit = emac_dev_xmit,
1690 .ndo_set_rx_mode = emac_dev_mcast_set,
1691 .ndo_set_mac_address = emac_dev_setmac_addr,
1692 .ndo_do_ioctl = emac_devioctl,
1693 .ndo_tx_timeout = emac_dev_tx_timeout,
1694 .ndo_get_stats = emac_dev_getnetstats,
1695 #ifdef CONFIG_NET_POLL_CONTROLLER
1696 .ndo_poll_controller = emac_poll_controller,
1700 static const struct of_device_id davinci_emac_of_match[];
1702 static struct emac_platform_data *
1703 davinci_emac_of_get_pdata(struct platform_device *pdev, struct emac_priv *priv)
1705 struct device_node *np;
1706 const struct of_device_id *match;
1707 const struct emac_platform_data *auxdata;
1708 struct emac_platform_data *pdata = NULL;
1711 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
1712 return dev_get_platdata(&pdev->dev);
1714 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1718 np = pdev->dev.of_node;
1719 pdata->version = EMAC_VERSION_2;
1721 if (!is_valid_ether_addr(pdata->mac_addr)) {
1722 mac_addr = of_get_mac_address(np);
1724 ether_addr_copy(pdata->mac_addr, mac_addr);
1727 of_property_read_u32(np, "ti,davinci-ctrl-reg-offset",
1728 &pdata->ctrl_reg_offset);
1730 of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset",
1731 &pdata->ctrl_mod_reg_offset);
1733 of_property_read_u32(np, "ti,davinci-ctrl-ram-offset",
1734 &pdata->ctrl_ram_offset);
1736 of_property_read_u32(np, "ti,davinci-ctrl-ram-size",
1737 &pdata->ctrl_ram_size);
1739 of_property_read_u8(np, "ti,davinci-rmii-en", &pdata->rmii_en);
1741 pdata->no_bd_ram = of_property_read_bool(np, "ti,davinci-no-bd-ram");
1743 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
1744 if (!priv->phy_node) {
1745 if (!of_phy_is_fixed_link(np))
1746 pdata->phy_id = NULL;
1747 else if (of_phy_register_fixed_link(np) >= 0)
1748 priv->phy_node = of_node_get(np);
1751 auxdata = pdev->dev.platform_data;
1753 pdata->interrupt_enable = auxdata->interrupt_enable;
1754 pdata->interrupt_disable = auxdata->interrupt_disable;
1757 match = of_match_device(davinci_emac_of_match, &pdev->dev);
1758 if (match && match->data) {
1759 auxdata = match->data;
1760 pdata->version = auxdata->version;
1761 pdata->hw_ram_addr = auxdata->hw_ram_addr;
1767 static int davinci_emac_try_get_mac(struct platform_device *pdev,
1768 int instance, u8 *mac_addr)
1770 if (!pdev->dev.of_node)
1773 return ti_cm_get_macid(&pdev->dev, instance, mac_addr);
1777 * davinci_emac_probe - EMAC device probe
1778 * @pdev: The DaVinci EMAC device that we are removing
1780 * Called when probing for emac devicesr. We get details of instances and
1781 * resource information from platform init and register a network device
1782 * and allocate resources necessary for driver to perform
1784 static int davinci_emac_probe(struct platform_device *pdev)
1786 struct device_node *np = pdev->dev.of_node;
1788 struct resource *res, *res_ctrl;
1789 struct net_device *ndev;
1790 struct emac_priv *priv;
1791 unsigned long hw_ram_addr;
1792 struct emac_platform_data *pdata;
1793 struct cpdma_params dma_params;
1794 struct clk *emac_clk;
1795 unsigned long emac_bus_frequency;
1798 /* obtain emac clock from kernel */
1799 emac_clk = devm_clk_get(&pdev->dev, NULL);
1800 if (IS_ERR(emac_clk)) {
1801 dev_err(&pdev->dev, "failed to get EMAC clock\n");
1804 emac_bus_frequency = clk_get_rate(emac_clk);
1805 devm_clk_put(&pdev->dev, emac_clk);
1807 /* TODO: Probe PHY here if possible */
1809 ndev = alloc_etherdev(sizeof(struct emac_priv));
1813 platform_set_drvdata(pdev, ndev);
1814 priv = netdev_priv(ndev);
1817 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
1819 spin_lock_init(&priv->lock);
1821 pdata = davinci_emac_of_get_pdata(pdev, priv);
1823 dev_err(&pdev->dev, "no platform data\n");
1825 goto err_free_netdev;
1828 /* MAC addr and PHY mask , RMII enable info from platform_data */
1829 memcpy(priv->mac_addr, pdata->mac_addr, ETH_ALEN);
1830 priv->phy_id = pdata->phy_id;
1831 priv->rmii_en = pdata->rmii_en;
1832 priv->version = pdata->version;
1833 priv->int_enable = pdata->interrupt_enable;
1834 priv->int_disable = pdata->interrupt_disable;
1836 priv->coal_intvl = 0;
1837 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
1839 /* Get EMAC platform data */
1840 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1841 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
1842 priv->remap_addr = devm_ioremap_resource(&pdev->dev, res);
1843 if (IS_ERR(priv->remap_addr)) {
1844 rc = PTR_ERR(priv->remap_addr);
1848 res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1851 devm_ioremap_resource(&pdev->dev, res_ctrl);
1852 if (IS_ERR(priv->ctrl_base)) {
1853 rc = PTR_ERR(priv->ctrl_base);
1857 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
1860 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
1861 ndev->base_addr = (unsigned long)priv->remap_addr;
1863 hw_ram_addr = pdata->hw_ram_addr;
1865 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
1867 memset(&dma_params, 0, sizeof(dma_params));
1868 dma_params.dev = &pdev->dev;
1869 dma_params.dmaregs = priv->emac_base;
1870 dma_params.rxthresh = priv->emac_base + 0x120;
1871 dma_params.rxfree = priv->emac_base + 0x140;
1872 dma_params.txhdp = priv->emac_base + 0x600;
1873 dma_params.rxhdp = priv->emac_base + 0x620;
1874 dma_params.txcp = priv->emac_base + 0x640;
1875 dma_params.rxcp = priv->emac_base + 0x660;
1876 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS;
1877 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE;
1878 dma_params.desc_hw_addr = hw_ram_addr;
1879 dma_params.desc_mem_size = pdata->ctrl_ram_size;
1880 dma_params.desc_align = 16;
1882 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :
1883 (u32 __force)res->start + pdata->ctrl_ram_offset;
1885 priv->dma = cpdma_ctlr_create(&dma_params);
1887 dev_err(&pdev->dev, "error initializing DMA\n");
1892 priv->txchan = cpdma_chan_create(priv->dma, EMAC_DEF_TX_CH,
1893 emac_tx_handler, 0);
1894 priv->rxchan = cpdma_chan_create(priv->dma, EMAC_DEF_RX_CH,
1895 emac_rx_handler, 1);
1896 if (WARN_ON(!priv->txchan || !priv->rxchan)) {
1901 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1903 dev_err(&pdev->dev, "error getting irq res\n");
1907 ndev->irq = res->start;
1909 rc = davinci_emac_try_get_mac(pdev, res_ctrl ? 0 : 1, priv->mac_addr);
1911 ether_addr_copy(ndev->dev_addr, priv->mac_addr);
1913 if (!is_valid_ether_addr(priv->mac_addr)) {
1914 /* Use random MAC if none passed */
1915 eth_hw_addr_random(ndev);
1916 memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len);
1917 dev_warn(&pdev->dev, "using random MAC addr: %pM\n",
1921 ndev->netdev_ops = &emac_netdev_ops;
1922 ndev->ethtool_ops = ðtool_ops;
1923 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
1925 pm_runtime_enable(&pdev->dev);
1926 rc = pm_runtime_get_sync(&pdev->dev);
1928 pm_runtime_put_noidle(&pdev->dev);
1929 dev_err(&pdev->dev, "%s: failed to get_sync(%d)\n",
1934 /* register the network device */
1935 SET_NETDEV_DEV(ndev, &pdev->dev);
1936 rc = register_netdev(ndev);
1938 dev_err(&pdev->dev, "error in register_netdev\n");
1940 pm_runtime_put(&pdev->dev);
1945 if (netif_msg_probe(priv)) {
1946 dev_notice(&pdev->dev, "DaVinci EMAC Probe found device "
1947 "(regs: %p, irq: %d)\n",
1948 (void *)priv->emac_base_phys, ndev->irq);
1950 pm_runtime_put(&pdev->dev);
1956 cpdma_chan_destroy(priv->txchan);
1958 cpdma_chan_destroy(priv->rxchan);
1959 cpdma_ctlr_destroy(priv->dma);
1961 if (of_phy_is_fixed_link(np))
1962 of_phy_deregister_fixed_link(np);
1963 of_node_put(priv->phy_node);
1970 * davinci_emac_remove - EMAC device remove
1971 * @pdev: The DaVinci EMAC device that we are removing
1973 * Called when removing the device driver. We disable clock usage and release
1974 * the resources taken up by the driver and unregister network device
1976 static int davinci_emac_remove(struct platform_device *pdev)
1978 struct net_device *ndev = platform_get_drvdata(pdev);
1979 struct emac_priv *priv = netdev_priv(ndev);
1980 struct device_node *np = pdev->dev.of_node;
1982 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
1985 cpdma_chan_destroy(priv->txchan);
1987 cpdma_chan_destroy(priv->rxchan);
1988 cpdma_ctlr_destroy(priv->dma);
1990 unregister_netdev(ndev);
1991 of_node_put(priv->phy_node);
1992 pm_runtime_disable(&pdev->dev);
1993 if (of_phy_is_fixed_link(np))
1994 of_phy_deregister_fixed_link(np);
2000 static int davinci_emac_suspend(struct device *dev)
2002 struct platform_device *pdev = to_platform_device(dev);
2003 struct net_device *ndev = platform_get_drvdata(pdev);
2005 if (netif_running(ndev))
2006 emac_dev_stop(ndev);
2011 static int davinci_emac_resume(struct device *dev)
2013 struct platform_device *pdev = to_platform_device(dev);
2014 struct net_device *ndev = platform_get_drvdata(pdev);
2016 if (netif_running(ndev))
2017 emac_dev_open(ndev);
2022 static const struct dev_pm_ops davinci_emac_pm_ops = {
2023 .suspend = davinci_emac_suspend,
2024 .resume = davinci_emac_resume,
2027 #if IS_ENABLED(CONFIG_OF)
2028 static const struct emac_platform_data am3517_emac_data = {
2029 .version = EMAC_VERSION_2,
2030 .hw_ram_addr = 0x01e20000,
2033 static const struct emac_platform_data dm816_emac_data = {
2034 .version = EMAC_VERSION_2,
2037 static const struct of_device_id davinci_emac_of_match[] = {
2038 {.compatible = "ti,davinci-dm6467-emac", },
2039 {.compatible = "ti,am3517-emac", .data = &am3517_emac_data, },
2040 {.compatible = "ti,dm816-emac", .data = &dm816_emac_data, },
2043 MODULE_DEVICE_TABLE(of, davinci_emac_of_match);
2046 /* davinci_emac_driver: EMAC platform driver structure */
2047 static struct platform_driver davinci_emac_driver = {
2049 .name = "davinci_emac",
2050 .pm = &davinci_emac_pm_ops,
2051 .of_match_table = of_match_ptr(davinci_emac_of_match),
2053 .probe = davinci_emac_probe,
2054 .remove = davinci_emac_remove,
2058 * davinci_emac_init - EMAC driver module init
2060 * Called when initializing the driver. We register the driver with
2063 static int __init davinci_emac_init(void)
2065 return platform_driver_register(&davinci_emac_driver);
2067 late_initcall(davinci_emac_init);
2070 * davinci_emac_exit - EMAC driver module exit
2072 * Called when exiting the driver completely. We unregister the driver with
2073 * the platform and exit
2075 static void __exit davinci_emac_exit(void)
2077 platform_driver_unregister(&davinci_emac_driver);
2079 module_exit(davinci_emac_exit);
2081 MODULE_LICENSE("GPL");
2082 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2083 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2084 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");