drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/gpio.h>
  33 #include <linux/of.h>
  34 #include <linux/of_mdio.h>
  35 #include <linux/of_net.h>
  36 #include <linux/of_device.h>
  37 #include <linux/if_vlan.h>
  38
  39 #include <linux/pinctrl/consumer.h>
  40
  41 #include "cpsw.h"
  42 #include "cpsw_ale.h"
  43 #include "cpts.h"
  44 #include "davinci_cpdma.h"
  45
  46 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  47                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  48                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  49                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  50                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  51                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  52                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  53                          NETIF_MSG_RX_STATUS)
  54
  55 #define cpsw_info(priv, type, format, ...)              \
  56 do {                                                            \
  57         if (netif_msg_##type(priv) && net_ratelimit())          \
  58                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  59 } while (0)
  60
  61 #define cpsw_err(priv, type, format, ...)               \
  62 do {                                                            \
  63         if (netif_msg_##type(priv) && net_ratelimit())          \
  64                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  65 } while (0)
  66
  67 #define cpsw_dbg(priv, type, format, ...)               \
  68 do {                                                            \
  69         if (netif_msg_##type(priv) && net_ratelimit())          \
  70                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  71 } while (0)
  72
  73 #define cpsw_notice(priv, type, format, ...)            \
  74 do {                                                            \
  75         if (netif_msg_##type(priv) && net_ratelimit())          \
  76                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  77 } while (0)
  78
  79 #define ALE_ALL_PORTS           0x7
  80
  81 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  82 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  83 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  84
  85 #define CPSW_VERSION_1          0x19010a
  86 #define CPSW_VERSION_2          0x19010c
  87 #define CPSW_VERSION_3          0x19010f
  88 #define CPSW_VERSION_4          0x190112
  89
  90 #define HOST_PORT_NUM           0
  91 #define SLIVER_SIZE             0x40
  92
  93 #define CPSW1_HOST_PORT_OFFSET  0x028
  94 #define CPSW1_SLAVE_OFFSET      0x050
  95 #define CPSW1_SLAVE_SIZE        0x040
  96 #define CPSW1_CPDMA_OFFSET      0x100
  97 #define CPSW1_STATERAM_OFFSET   0x200
  98 #define CPSW1_HW_STATS          0x400
  99 #define CPSW1_CPTS_OFFSET       0x500
 100 #define CPSW1_ALE_OFFSET        0x600
 101 #define CPSW1_SLIVER_OFFSET     0x700
 102
 103 #define CPSW2_HOST_PORT_OFFSET  0x108
 104 #define CPSW2_SLAVE_OFFSET      0x200
 105 #define CPSW2_SLAVE_SIZE        0x100
 106 #define CPSW2_CPDMA_OFFSET      0x800
 107 #define CPSW2_HW_STATS          0x900
 108 #define CPSW2_STATERAM_OFFSET   0xa00
 109 #define CPSW2_CPTS_OFFSET       0xc00
 110 #define CPSW2_ALE_OFFSET        0xd00
 111 #define CPSW2_SLIVER_OFFSET     0xd80
 112 #define CPSW2_BD_OFFSET         0x2000
 113
 114 #define CPDMA_RXTHRESH          0x0c0
 115 #define CPDMA_RXFREE            0x0e0
 116 #define CPDMA_TXHDP             0x00
 117 #define CPDMA_RXHDP             0x20
 118 #define CPDMA_TXCP              0x40
 119 #define CPDMA_RXCP              0x60
 120
 121 #define CPSW_POLL_WEIGHT        64
 122 #define CPSW_MIN_PACKET_SIZE    60
 123 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 124
 125 #define RX_PRIORITY_MAPPING     0x76543210
 126 #define TX_PRIORITY_MAPPING     0x33221100
 127 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 128
 129 #define CPSW_VLAN_AWARE         BIT(1)
 130 #define CPSW_ALE_VLAN_AWARE     1
 131
 132 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 133 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 134 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 135
 136 #define CPSW_INTPACEEN          (0x3f << 16)
 137 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 138 #define CPSW_CMINTMAX_CNT       63
 139 #define CPSW_CMINTMIN_CNT       2
 140 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 141 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 142
 143 #define cpsw_slave_index(cpsw, priv)                            \
 144                 ((cpsw->data.dual_emac) ? priv->emac_port :     \
 145                 cpsw->data.active_slave)
 146 #define IRQ_NUM                 2
 147 #define CPSW_MAX_QUEUES         8
 148 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
 149
 150 static int debug_level;
 151 module_param(debug_level, int, 0);
 152 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 153
 154 static int ale_ageout = 10;
 155 module_param(ale_ageout, int, 0);
 156 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 157
 158 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 159 module_param(rx_packet_max, int, 0);
 160 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 161
 162 static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT;
 163 module_param(descs_pool_size, int, 0444);
 164 MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool");
 165
 166 struct cpsw_wr_regs {
 167         u32     id_ver;
 168         u32     soft_reset;
 169         u32     control;
 170         u32     int_control;
 171         u32     rx_thresh_en;
 172         u32     rx_en;
 173         u32     tx_en;
 174         u32     misc_en;
 175         u32     mem_allign1[8];
 176         u32     rx_thresh_stat;
 177         u32     rx_stat;
 178         u32     tx_stat;
 179         u32     misc_stat;
 180         u32     mem_allign2[8];
 181         u32     rx_imax;
 182         u32     tx_imax;
 183
 184 };
 185
 186 struct cpsw_ss_regs {
 187         u32     id_ver;
 188         u32     control;
 189         u32     soft_reset;
 190         u32     stat_port_en;
 191         u32     ptype;
 192         u32     soft_idle;
 193         u32     thru_rate;
 194         u32     gap_thresh;
 195         u32     tx_start_wds;
 196         u32     flow_control;
 197         u32     vlan_ltype;
 198         u32     ts_ltype;
 199         u32     dlr_ltype;
 200 };
 201
 202 /* CPSW_PORT_V1 */
 203 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 204 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 205 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 206 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 207 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 208 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 209 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 210 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 211
 212 /* CPSW_PORT_V2 */
 213 #define CPSW2_CONTROL       0x00 /* Control Register */
 214 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 215 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 216 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 217 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 218 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 219 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 220
 221 /* CPSW_PORT_V1 and V2 */
 222 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 223 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 224 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 225
 226 /* CPSW_PORT_V2 only */
 227 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 228 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 229 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 230 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 231 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 232 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 233 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 234 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 235
 236 /* Bit definitions for the CPSW2_CONTROL register */
 237 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 238 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 239 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 240 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 241 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 242 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 243 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 244 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 245 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 246 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 247 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 248 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 249 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 250 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 251 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 252 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 253 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 254
 255 #define CTRL_V2_TS_BITS \
 256         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 257          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 258
 259 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 260 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 261 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 262
 263
 264 #define CTRL_V3_TS_BITS \
 265         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 266          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 267          TS_LTYPE1_EN)
 268
 269 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 270 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 271 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 272
 273 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 274 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 275 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 276 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 277 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 278
 279 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 280 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 281
 282 /* Bit definitions for the CPSW1_TS_CTL register */
 283 #define CPSW_V1_TS_RX_EN                BIT(0)
 284 #define CPSW_V1_TS_TX_EN                BIT(4)
 285 #define CPSW_V1_MSG_TYPE_OFS            16
 286
 287 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 288 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 289
 290 #define CPSW_MAX_BLKS_TX                15
 291 #define CPSW_MAX_BLKS_TX_SHIFT          4
 292 #define CPSW_MAX_BLKS_RX                5
 293
 294 struct cpsw_host_regs {
 295         u32     max_blks;
 296         u32     blk_cnt;
 297         u32     tx_in_ctl;
 298         u32     port_vlan;
 299         u32     tx_pri_map;
 300         u32     cpdma_tx_pri_map;
 301         u32     cpdma_rx_chan_map;
 302 };
 303
 304 struct cpsw_sliver_regs {
 305         u32     id_ver;
 306         u32     mac_control;
 307         u32     mac_status;
 308         u32     soft_reset;
 309         u32     rx_maxlen;
 310         u32     __reserved_0;
 311         u32     rx_pause;
 312         u32     tx_pause;
 313         u32     __reserved_1;
 314         u32     rx_pri_map;
 315 };
 316
 317 struct cpsw_hw_stats {
 318         u32     rxgoodframes;
 319         u32     rxbroadcastframes;
 320         u32     rxmulticastframes;
 321         u32     rxpauseframes;
 322         u32     rxcrcerrors;
 323         u32     rxaligncodeerrors;
 324         u32     rxoversizedframes;
 325         u32     rxjabberframes;
 326         u32     rxundersizedframes;
 327         u32     rxfragments;
 328         u32     __pad_0[2];
 329         u32     rxoctets;
 330         u32     txgoodframes;
 331         u32     txbroadcastframes;
 332         u32     txmulticastframes;
 333         u32     txpauseframes;
 334         u32     txdeferredframes;
 335         u32     txcollisionframes;
 336         u32     txsinglecollframes;
 337         u32     txmultcollframes;
 338         u32     txexcessivecollisions;
 339         u32     txlatecollisions;
 340         u32     txunderrun;
 341         u32     txcarriersenseerrors;
 342         u32     txoctets;
 343         u32     octetframes64;
 344         u32     octetframes65t127;
 345         u32     octetframes128t255;
 346         u32     octetframes256t511;
 347         u32     octetframes512t1023;
 348         u32     octetframes1024tup;
 349         u32     netoctets;
 350         u32     rxsofoverruns;
 351         u32     rxmofoverruns;
 352         u32     rxdmaoverruns;
 353 };
 354
 355 struct cpsw_slave {
 356         void __iomem                    *regs;
 357         struct cpsw_sliver_regs __iomem *sliver;
 358         int                             slave_num;
 359         u32                             mac_control;
 360         struct cpsw_slave_data          *data;
 361         struct phy_device               *phy;
 362         struct net_device               *ndev;
 363         u32                             port_vlan;
 364 };
 365
 366 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 367 {
 368         return __raw_readl(slave->regs + offset);
 369 }
 370
 371 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 372 {
 373         __raw_writel(val, slave->regs + offset);
 374 }
 375
 376 struct cpsw_vector {
 377         struct cpdma_chan *ch;
 378         int budget;
 379 };
 380
 381 struct cpsw_common {
 382         struct device                   *dev;
 383         struct cpsw_platform_data       data;
 384         struct napi_struct              napi_rx;
 385         struct napi_struct              napi_tx;
 386         struct cpsw_ss_regs __iomem     *regs;
 387         struct cpsw_wr_regs __iomem     *wr_regs;
 388         u8 __iomem                      *hw_stats;
 389         struct cpsw_host_regs __iomem   *host_port_regs;
 390         u32                             version;
 391         u32                             coal_intvl;
 392         u32                             bus_freq_mhz;
 393         int                             rx_packet_max;
 394         struct cpsw_slave               *slaves;
 395         struct cpdma_ctlr               *dma;
 396         struct cpsw_vector              txv[CPSW_MAX_QUEUES];
 397         struct cpsw_vector              rxv[CPSW_MAX_QUEUES];
 398         struct cpsw_ale                 *ale;
 399         bool                            quirk_irq;
 400         bool                            rx_irq_disabled;
 401         bool                            tx_irq_disabled;
 402         u32 irqs_table[IRQ_NUM];
 403         struct cpts                     *cpts;
 404         int                             rx_ch_num, tx_ch_num;
 405         int                             speed;
 406         int                             usage_count;
 407 };
 408
 409 struct cpsw_priv {
 410         struct net_device               *ndev;
 411         struct device                   *dev;
 412         u32                             msg_enable;
 413         u8                              mac_addr[ETH_ALEN];
 414         bool                            rx_pause;
 415         bool                            tx_pause;
 416         u32 emac_port;
 417         struct cpsw_common *cpsw;
 418 };
 419
 420 struct cpsw_stats {
 421         char stat_string[ETH_GSTRING_LEN];
 422         int type;
 423         int sizeof_stat;
 424         int stat_offset;
 425 };
 426
 427 enum {
 428         CPSW_STATS,
 429         CPDMA_RX_STATS,
 430         CPDMA_TX_STATS,
 431 };
 432
 433 #define CPSW_STAT(m)            CPSW_STATS,                             \
 434                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 435                                 offsetof(struct cpsw_hw_stats, m)
 436 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 437                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 438                                 offsetof(struct cpdma_chan_stats, m)
 439 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 440                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 441                                 offsetof(struct cpdma_chan_stats, m)
 442
 443 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 444         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 445         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 446         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 447         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 448         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 449         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 450         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 451         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 452         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 453         { "Rx Fragments", CPSW_STAT(rxfragments) },
 454         { "Rx Octets", CPSW_STAT(rxoctets) },
 455         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 456         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 457         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 458         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 459         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 460         { "Collisions", CPSW_STAT(txcollisionframes) },
 461         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 462         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 463         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 464         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 465         { "Tx Underrun", CPSW_STAT(txunderrun) },
 466         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 467         { "Tx Octets", CPSW_STAT(txoctets) },
 468         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 469         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 470         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 471         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 472         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 473         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 474         { "Net Octets", CPSW_STAT(netoctets) },
 475         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 476         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 477         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 478 };
 479
 480 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
 481         { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 482         { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 483         { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 484         { "misqueued", CPDMA_RX_STAT(misqueued) },
 485         { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 486         { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 487         { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 488         { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 489         { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 490         { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 491         { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 492         { "requeue", CPDMA_RX_STAT(requeue) },
 493         { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 494 };
 495
 496 #define CPSW_STATS_COMMON_LEN   ARRAY_SIZE(cpsw_gstrings_stats)
 497 #define CPSW_STATS_CH_LEN       ARRAY_SIZE(cpsw_gstrings_ch_stats)
 498
 499 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
 500 #define napi_to_cpsw(napi)      container_of(napi, struct cpsw_common, napi)
 501 #define for_each_slave(priv, func, arg...)                              \
 502         do {                                                            \
 503                 struct cpsw_slave *slave;                               \
 504                 struct cpsw_common *cpsw = (priv)->cpsw;                \
 505                 int n;                                                  \
 506                 if (cpsw->data.dual_emac)                               \
 507                         (func)((cpsw)->slaves + priv->emac_port, ##arg);\
 508                 else                                                    \
 509                         for (n = cpsw->data.slaves,                     \
 510                                         slave = cpsw->slaves;           \
 511                                         n; n--)                         \
 512                                 (func)(slave++, ##arg);                 \
 513         } while (0)
 514
 515 #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb)         \
 516         do {                                                            \
 517                 if (!cpsw->data.dual_emac)                              \
 518                         break;                                          \
 519                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 520                         ndev = cpsw->slaves[0].ndev;                    \
 521                         skb->dev = ndev;                                \
 522                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 523                         ndev = cpsw->slaves[1].ndev;                    \
 524                         skb->dev = ndev;                                \
 525                 }                                                       \
 526         } while (0)
 527 #define cpsw_add_mcast(cpsw, priv, addr)                                \
 528         do {                                                            \
 529                 if (cpsw->data.dual_emac) {                             \
 530                         struct cpsw_slave *slave = cpsw->slaves +       \
 531                                                 priv->emac_port;        \
 532                         int slave_port = cpsw_get_slave_port(           \
 533                                                 slave->slave_num);      \
 534                         cpsw_ale_add_mcast(cpsw->ale, addr,             \
 535                                 1 << slave_port | ALE_PORT_HOST,        \
 536                                 ALE_VLAN, slave->port_vlan, 0);         \
 537                 } else {                                                \
 538                         cpsw_ale_add_mcast(cpsw->ale, addr,             \
 539                                 ALE_ALL_PORTS,                          \
 540                                 0, 0, 0);                               \
 541                 }                                                       \
 542         } while (0)
 543
 544 static inline int cpsw_get_slave_port(u32 slave_num)
 545 {
 546         return slave_num + 1;
 547 }
 548
 549 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 550 {
 551         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
 552         struct cpsw_ale *ale = cpsw->ale;
 553         int i;
 554
 555         if (cpsw->data.dual_emac) {
 556                 bool flag = false;
 557
 558                 /* Enabling promiscuous mode for one interface will be
 559                  * common for both the interface as the interface shares
 560                  * the same hardware resource.
 561                  */
 562                 for (i = 0; i < cpsw->data.slaves; i++)
 563                         if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
 564                                 flag = true;
 565
 566                 if (!enable && flag) {
 567                         enable = true;
 568                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 569                 }
 570
 571                 if (enable) {
 572                         /* Enable Bypass */
 573                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 574
 575                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 576                 } else {
 577                         /* Disable Bypass */
 578                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 579                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 580                 }
 581         } else {
 582                 if (enable) {
 583                         unsigned long timeout = jiffies + HZ;
 584
 585                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 586                         for (i = 0; i <= cpsw->data.slaves; i++) {
 587                                 cpsw_ale_control_set(ale, i,
 588                                                      ALE_PORT_NOLEARN, 1);
 589                                 cpsw_ale_control_set(ale, i,
 590                                                      ALE_PORT_NO_SA_UPDATE, 1);
 591                         }
 592
 593                         /* Clear All Untouched entries */
 594                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 595                         do {
 596                                 cpu_relax();
 597                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 598                                         break;
 599                         } while (time_after(timeout, jiffies));
 600                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 601
 602                         /* Clear all mcast from ALE */
 603                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
 604                         __dev_mc_unsync(ndev, NULL);
 605
 606                         /* Flood All Unicast Packets to Host port */
 607                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 608                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 609                 } else {
 610                         /* Don't Flood All Unicast Packets to Host port */
 611                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 612
 613                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 614                         for (i = 0; i <= cpsw->data.slaves; i++) {
 615                                 cpsw_ale_control_set(ale, i,
 616                                                      ALE_PORT_NOLEARN, 0);
 617                                 cpsw_ale_control_set(ale, i,
 618                                                      ALE_PORT_NO_SA_UPDATE, 0);
 619                         }
 620                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 621                 }
 622         }
 623 }
 624
 625 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 626 {
 627         struct cpsw_priv *priv = netdev_priv(ndev);
 628         struct cpsw_common *cpsw = priv->cpsw;
 629         int vid;
 630
 631         if (cpsw->data.dual_emac)
 632                 vid = cpsw->slaves[priv->emac_port].port_vlan;
 633         else
 634                 vid = cpsw->data.default_vlan;
 635
 636         if (ndev->flags & IFF_PROMISC) {
 637                 /* Enable promiscuous mode */
 638                 cpsw_set_promiscious(ndev, true);
 639                 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
 640                 return;
 641         } else {
 642                 /* Disable promiscuous mode */
 643                 cpsw_set_promiscious(ndev, false);
 644         }
 645
 646         /* Restore allmulti on vlans if necessary */
 647         cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
 648
 649         /* Clear all mcast from ALE */
 650         cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
 651
 652         if (!netdev_mc_empty(ndev)) {
 653                 struct netdev_hw_addr *ha;
 654
 655                 /* program multicast address list into ALE register */
 656                 netdev_for_each_mc_addr(ha, ndev) {
 657                         cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr);
 658                 }
 659         }
 660 }
 661
 662 static void cpsw_intr_enable(struct cpsw_common *cpsw)
 663 {
 664         __raw_writel(0xFF, &cpsw->wr_regs->tx_en);
 665         __raw_writel(0xFF, &cpsw->wr_regs->rx_en);
 666
 667         cpdma_ctlr_int_ctrl(cpsw->dma, true);
 668         return;
 669 }
 670
 671 static void cpsw_intr_disable(struct cpsw_common *cpsw)
 672 {
 673         __raw_writel(0, &cpsw->wr_regs->tx_en);
 674         __raw_writel(0, &cpsw->wr_regs->rx_en);
 675
 676         cpdma_ctlr_int_ctrl(cpsw->dma, false);
 677         return;
 678 }
 679
 680 static void cpsw_tx_handler(void *token, int len, int status)
 681 {
 682         struct netdev_queue     *txq;
 683         struct sk_buff          *skb = token;
 684         struct net_device       *ndev = skb->dev;
 685         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 686
 687         /* Check whether the queue is stopped due to stalled tx dma, if the
 688          * queue is stopped then start the queue as we have free desc for tx
 689          */
 690         txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
 691         if (unlikely(netif_tx_queue_stopped(txq)))
 692                 netif_tx_wake_queue(txq);
 693
 694         cpts_tx_timestamp(cpsw->cpts, skb);
 695         ndev->stats.tx_packets++;
 696         ndev->stats.tx_bytes += len;
 697         dev_kfree_skb_any(skb);
 698 }
 699
 700 static void cpsw_rx_handler(void *token, int len, int status)
 701 {
 702         struct cpdma_chan       *ch;
 703         struct sk_buff          *skb = token;
 704         struct sk_buff          *new_skb;
 705         struct net_device       *ndev = skb->dev;
 706         int                     ret = 0;
 707         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 708
 709         cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb);
 710
 711         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 712                 /* In dual emac mode check for all interfaces */
 713                 if (cpsw->data.dual_emac && cpsw->usage_count &&
 714                     (status >= 0)) {
 715                         /* The packet received is for the interface which
 716                          * is already down and the other interface is up
 717                          * and running, instead of freeing which results
 718                          * in reducing of the number of rx descriptor in
 719                          * DMA engine, requeue skb back to cpdma.
 720                          */
 721                         new_skb = skb;
 722                         goto requeue;
 723                 }
 724
 725                 /* the interface is going down, skbs are purged */
 726                 dev_kfree_skb_any(skb);
 727                 return;
 728         }
 729
 730         new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
 731         if (new_skb) {
 732                 skb_copy_queue_mapping(new_skb, skb);
 733                 skb_put(skb, len);
 734                 cpts_rx_timestamp(cpsw->cpts, skb);
 735                 skb->protocol = eth_type_trans(skb, ndev);
 736                 netif_receive_skb(skb);
 737                 ndev->stats.rx_bytes += len;
 738                 ndev->stats.rx_packets++;
 739                 kmemleak_not_leak(new_skb);
 740         } else {
 741                 ndev->stats.rx_dropped++;
 742                 new_skb = skb;
 743         }
 744
 745 requeue:
 746         if (netif_dormant(ndev)) {
 747                 dev_kfree_skb_any(new_skb);
 748                 return;
 749         }
 750
 751         ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch;
 752         ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
 753                                 skb_tailroom(new_skb), 0);
 754         if (WARN_ON(ret < 0))
 755                 dev_kfree_skb_any(new_skb);
 756 }
 757
 758 static void cpsw_split_res(struct net_device *ndev)
 759 {
 760         struct cpsw_priv *priv = netdev_priv(ndev);
 761         u32 consumed_rate = 0, bigest_rate = 0;
 762         struct cpsw_common *cpsw = priv->cpsw;
 763         struct cpsw_vector *txv = cpsw->txv;
 764         int i, ch_weight, rlim_ch_num = 0;
 765         int budget, bigest_rate_ch = 0;
 766         u32 ch_rate, max_rate;
 767         int ch_budget = 0;
 768
 769         for (i = 0; i < cpsw->tx_ch_num; i++) {
 770                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
 771                 if (!ch_rate)
 772                         continue;
 773
 774                 rlim_ch_num++;
 775                 consumed_rate += ch_rate;
 776         }
 777
 778         if (cpsw->tx_ch_num == rlim_ch_num) {
 779                 max_rate = consumed_rate;
 780         } else if (!rlim_ch_num) {
 781                 ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
 782                 bigest_rate = 0;
 783                 max_rate = consumed_rate;
 784         } else {
 785                 max_rate = cpsw->speed * 1000;
 786
 787                 /* if max_rate is less then expected due to reduced link speed,
 788                  * split proportionally according next potential max speed
 789                  */
 790                 if (max_rate < consumed_rate)
 791                         max_rate *= 10;
 792
 793                 if (max_rate < consumed_rate)
 794                         max_rate *= 10;
 795
 796                 ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
 797                 ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
 798                             (cpsw->tx_ch_num - rlim_ch_num);
 799                 bigest_rate = (max_rate - consumed_rate) /
 800                               (cpsw->tx_ch_num - rlim_ch_num);
 801         }
 802
 803         /* split tx weight/budget */
 804         budget = CPSW_POLL_WEIGHT;
 805         for (i = 0; i < cpsw->tx_ch_num; i++) {
 806                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
 807                 if (ch_rate) {
 808                         txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
 809                         if (!txv[i].budget)
 810                                 txv[i].budget++;
 811                         if (ch_rate > bigest_rate) {
 812                                 bigest_rate_ch = i;
 813                                 bigest_rate = ch_rate;
 814                         }
 815
 816                         ch_weight = (ch_rate * 100) / max_rate;
 817                         if (!ch_weight)
 818                                 ch_weight++;
 819                         cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
 820                 } else {
 821                         txv[i].budget = ch_budget;
 822                         if (!bigest_rate_ch)
 823                                 bigest_rate_ch = i;
 824                         cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
 825                 }
 826
 827                 budget -= txv[i].budget;
 828         }
 829
 830         if (budget)
 831                 txv[bigest_rate_ch].budget += budget;
 832
 833         /* split rx budget */
 834         budget = CPSW_POLL_WEIGHT;
 835         ch_budget = budget / cpsw->rx_ch_num;
 836         for (i = 0; i < cpsw->rx_ch_num; i++) {
 837                 cpsw->rxv[i].budget = ch_budget;
 838                 budget -= ch_budget;
 839         }
 840
 841         if (budget)
 842                 cpsw->rxv[0].budget += budget;
 843 }
 844
 845 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
 846 {
 847         struct cpsw_common *cpsw = dev_id;
 848
 849         writel(0, &cpsw->wr_regs->tx_en);
 850         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
 851
 852         if (cpsw->quirk_irq) {
 853                 disable_irq_nosync(cpsw->irqs_table[1]);
 854                 cpsw->tx_irq_disabled = true;
 855         }
 856
 857         napi_schedule(&cpsw->napi_tx);
 858         return IRQ_HANDLED;
 859 }
 860
 861 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
 862 {
 863         struct cpsw_common *cpsw = dev_id;
 864
 865         writel(0, &cpsw->wr_regs->rx_en);
 866         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
 867
 868         if (cpsw->quirk_irq) {
 869                 disable_irq_nosync(cpsw->irqs_table[0]);
 870                 cpsw->rx_irq_disabled = true;
 871         }
 872
 873         napi_schedule(&cpsw->napi_rx);
 874         return IRQ_HANDLED;
 875 }
 876
 877 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
 878 {
 879         u32                     ch_map;
 880         int                     num_tx, cur_budget, ch;
 881         struct cpsw_common      *cpsw = napi_to_cpsw(napi_tx);
 882         struct cpsw_vector      *txv;
 883
 884         /* process every unprocessed channel */
 885         ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
 886         for (ch = 0, num_tx = 0; ch_map; ch_map >>= 1, ch++) {
 887                 if (!(ch_map & 0x01))
 888                         continue;
 889
 890                 txv = &cpsw->txv[ch];
 891                 if (unlikely(txv->budget > budget - num_tx))
 892                         cur_budget = budget - num_tx;
 893                 else
 894                         cur_budget = txv->budget;
 895
 896                 num_tx += cpdma_chan_process(txv->ch, cur_budget);
 897                 if (num_tx >= budget)
 898                         break;
 899         }
 900
 901         if (num_tx < budget) {
 902                 napi_complete(napi_tx);
 903                 writel(0xff, &cpsw->wr_regs->tx_en);
 904                 if (cpsw->quirk_irq && cpsw->tx_irq_disabled) {
 905                         cpsw->tx_irq_disabled = false;
 906                         enable_irq(cpsw->irqs_table[1]);
 907                 }
 908         }
 909
 910         return num_tx;
 911 }
 912
 913 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
 914 {
 915         u32                     ch_map;
 916         int                     num_rx, cur_budget, ch;
 917         struct cpsw_common      *cpsw = napi_to_cpsw(napi_rx);
 918         struct cpsw_vector      *rxv;
 919
 920         /* process every unprocessed channel */
 921         ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
 922         for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
 923                 if (!(ch_map & 0x01))
 924                         continue;
 925
 926                 rxv = &cpsw->rxv[ch];
 927                 if (unlikely(rxv->budget > budget - num_rx))
 928                         cur_budget = budget - num_rx;
 929                 else
 930                         cur_budget = rxv->budget;
 931
 932                 num_rx += cpdma_chan_process(rxv->ch, cur_budget);
 933                 if (num_rx >= budget)
 934                         break;
 935         }
 936
 937         if (num_rx < budget) {
 938                 napi_complete_done(napi_rx, num_rx);
 939                 writel(0xff, &cpsw->wr_regs->rx_en);
 940                 if (cpsw->quirk_irq && cpsw->rx_irq_disabled) {
 941                         cpsw->rx_irq_disabled = false;
 942                         enable_irq(cpsw->irqs_table[0]);
 943                 }
 944         }
 945
 946         return num_rx;
 947 }
 948
 949 static inline void soft_reset(const char *module, void __iomem *reg)
 950 {
 951         unsigned long timeout = jiffies + HZ;
 952
 953         __raw_writel(1, reg);
 954         do {
 955                 cpu_relax();
 956         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 957
 958         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 959 }
 960
 961 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 962                          ((mac)[2] << 16) | ((mac)[3] << 24))
 963 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 964
 965 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 966                                struct cpsw_priv *priv)
 967 {
 968         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 969         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 970 }
 971
 972 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 973                               struct cpsw_priv *priv, bool *link)
 974 {
 975         struct phy_device       *phy = slave->phy;
 976         u32                     mac_control = 0;
 977         u32                     slave_port;
 978         struct cpsw_common *cpsw = priv->cpsw;
 979
 980         if (!phy)
 981                 return;
 982
 983         slave_port = cpsw_get_slave_port(slave->slave_num);
 984
 985         if (phy->link) {
 986                 mac_control = cpsw->data.mac_control;
 987
 988                 /* enable forwarding */
 989                 cpsw_ale_control_set(cpsw->ale, slave_port,
 990                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 991
 992                 if (phy->speed == 1000)
 993                         mac_control |= BIT(7);  /* GIGABITEN    */
 994                 if (phy->duplex)
 995                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 996
 997                 /* set speed_in input in case RMII mode is used in 100Mbps */
 998                 if (phy->speed == 100)
 999                         mac_control |= BIT(15);
1000                 /* in band mode only works in 10Mbps RGMII mode */
1001                 else if ((phy->speed == 10) && phy_interface_is_rgmii(phy))
1002                         mac_control |= BIT(18); /* In Band mode */
1003
1004                 if (priv->rx_pause)
1005                         mac_control |= BIT(3);
1006
1007                 if (priv->tx_pause)
1008                         mac_control |= BIT(4);
1009
1010                 *link = true;
1011         } else {
1012                 mac_control = 0;
1013                 /* disable forwarding */
1014                 cpsw_ale_control_set(cpsw->ale, slave_port,
1015                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1016         }
1017
1018         if (mac_control != slave->mac_control) {
1019                 phy_print_status(phy);
1020                 __raw_writel(mac_control, &slave->sliver->mac_control);
1021         }
1022
1023         slave->mac_control = mac_control;
1024 }
1025
1026 static int cpsw_get_common_speed(struct cpsw_common *cpsw)
1027 {
1028         int i, speed;
1029
1030         for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
1031                 if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
1032                         speed += cpsw->slaves[i].phy->speed;
1033
1034         return speed;
1035 }
1036
1037 static int cpsw_need_resplit(struct cpsw_common *cpsw)
1038 {
1039         int i, rlim_ch_num;
1040         int speed, ch_rate;
1041
1042         /* re-split resources only in case speed was changed */
1043         speed = cpsw_get_common_speed(cpsw);
1044         if (speed == cpsw->speed || !speed)
1045                 return 0;
1046
1047         cpsw->speed = speed;
1048
1049         for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
1050                 ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
1051                 if (!ch_rate)
1052                         break;
1053
1054                 rlim_ch_num++;
1055         }
1056
1057         /* cases not dependent on speed */
1058         if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
1059                 return 0;
1060
1061         return 1;
1062 }
1063
1064 static void cpsw_adjust_link(struct net_device *ndev)
1065 {
1066         struct cpsw_priv        *priv = netdev_priv(ndev);
1067         struct cpsw_common      *cpsw = priv->cpsw;
1068         bool                    link = false;
1069
1070         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1071
1072         if (link) {
1073                 if (cpsw_need_resplit(cpsw))
1074                         cpsw_split_res(ndev);
1075
1076                 netif_carrier_on(ndev);
1077                 if (netif_running(ndev))
1078                         netif_tx_wake_all_queues(ndev);
1079         } else {
1080                 netif_carrier_off(ndev);
1081                 netif_tx_stop_all_queues(ndev);
1082         }
1083 }
1084
1085 static int cpsw_get_coalesce(struct net_device *ndev,
1086                                 struct ethtool_coalesce *coal)
1087 {
1088         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1089
1090         coal->rx_coalesce_usecs = cpsw->coal_intvl;
1091         return 0;
1092 }
1093
1094 static int cpsw_set_coalesce(struct net_device *ndev,
1095                                 struct ethtool_coalesce *coal)
1096 {
1097         struct cpsw_priv *priv = netdev_priv(ndev);
1098         u32 int_ctrl;
1099         u32 num_interrupts = 0;
1100         u32 prescale = 0;
1101         u32 addnl_dvdr = 1;
1102         u32 coal_intvl = 0;
1103         struct cpsw_common *cpsw = priv->cpsw;
1104
1105         coal_intvl = coal->rx_coalesce_usecs;
1106
1107         int_ctrl =  readl(&cpsw->wr_regs->int_control);
1108         prescale = cpsw->bus_freq_mhz * 4;
1109
1110         if (!coal->rx_coalesce_usecs) {
1111                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1112                 goto update_return;
1113         }
1114
1115         if (coal_intvl < CPSW_CMINTMIN_INTVL)
1116                 coal_intvl = CPSW_CMINTMIN_INTVL;
1117
1118         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1119                 /* Interrupt pacer works with 4us Pulse, we can
1120                  * throttle further by dilating the 4us pulse.
1121                  */
1122                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1123
1124                 if (addnl_dvdr > 1) {
1125                         prescale *= addnl_dvdr;
1126                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1127                                 coal_intvl = (CPSW_CMINTMAX_INTVL
1128                                                 * addnl_dvdr);
1129                 } else {
1130                         addnl_dvdr = 1;
1131                         coal_intvl = CPSW_CMINTMAX_INTVL;
1132                 }
1133         }
1134
1135         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
1136         writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1137         writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1138
1139         int_ctrl |= CPSW_INTPACEEN;
1140         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1141         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1142
1143 update_return:
1144         writel(int_ctrl, &cpsw->wr_regs->int_control);
1145
1146         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1147         cpsw->coal_intvl = coal_intvl;
1148
1149         return 0;
1150 }
1151
1152 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1153 {
1154         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1155
1156         switch (sset) {
1157         case ETH_SS_STATS:
1158                 return (CPSW_STATS_COMMON_LEN +
1159                        (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1160                        CPSW_STATS_CH_LEN);
1161         default:
1162                 return -EOPNOTSUPP;
1163         }
1164 }
1165
1166 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1167 {
1168         int ch_stats_len;
1169         int line;
1170         int i;
1171
1172         ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1173         for (i = 0; i < ch_stats_len; i++) {
1174                 line = i % CPSW_STATS_CH_LEN;
1175                 snprintf(*p, ETH_GSTRING_LEN,
1176                          "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx",
1177                          i / CPSW_STATS_CH_LEN,
1178                          cpsw_gstrings_ch_stats[line].stat_string);
1179                 *p += ETH_GSTRING_LEN;
1180         }
1181 }
1182
1183 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1184 {
1185         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1186         u8 *p = data;
1187         int i;
1188
1189         switch (stringset) {
1190         case ETH_SS_STATS:
1191                 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1192                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1193                                ETH_GSTRING_LEN);
1194                         p += ETH_GSTRING_LEN;
1195                 }
1196
1197                 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1198                 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1199                 break;
1200         }
1201 }
1202
1203 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1204                                     struct ethtool_stats *stats, u64 *data)
1205 {
1206         u8 *p;
1207         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1208         struct cpdma_chan_stats ch_stats;
1209         int i, l, ch;
1210
1211         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1212         for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1213                 data[l] = readl(cpsw->hw_stats +
1214                                 cpsw_gstrings_stats[l].stat_offset);
1215
1216         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1217                 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
1218                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1219                         p = (u8 *)&ch_stats +
1220                                 cpsw_gstrings_ch_stats[i].stat_offset;
1221                         data[l] = *(u32 *)p;
1222                 }
1223         }
1224
1225         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1226                 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
1227                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1228                         p = (u8 *)&ch_stats +
1229                                 cpsw_gstrings_ch_stats[i].stat_offset;
1230                         data[l] = *(u32 *)p;
1231                 }
1232         }
1233 }
1234
1235 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1236                                         struct sk_buff *skb,
1237                                         struct cpdma_chan *txch)
1238 {
1239         struct cpsw_common *cpsw = priv->cpsw;
1240
1241         skb_tx_timestamp(skb);
1242         return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1243                                  priv->emac_port + cpsw->data.dual_emac);
1244 }
1245
1246 static inline void cpsw_add_dual_emac_def_ale_entries(
1247                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1248                 u32 slave_port)
1249 {
1250         struct cpsw_common *cpsw = priv->cpsw;
1251         u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1252
1253         if (cpsw->version == CPSW_VERSION_1)
1254                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1255         else
1256                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1257         cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1258                           port_mask, port_mask, 0);
1259         cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1260                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1261         cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1262                            HOST_PORT_NUM, ALE_VLAN |
1263                            ALE_SECURE, slave->port_vlan);
1264         cpsw_ale_control_set(cpsw->ale, slave_port,
1265                              ALE_PORT_DROP_UNKNOWN_VLAN, 1);
1266 }
1267
1268 static void soft_reset_slave(struct cpsw_slave *slave)
1269 {
1270         char name[32];
1271
1272         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1273         soft_reset(name, &slave->sliver->soft_reset);
1274 }
1275
1276 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1277 {
1278         u32 slave_port;
1279         struct phy_device *phy;
1280         struct cpsw_common *cpsw = priv->cpsw;
1281
1282         soft_reset_slave(slave);
1283
1284         /* setup priority mapping */
1285         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1286
1287         switch (cpsw->version) {
1288         case CPSW_VERSION_1:
1289                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1290                 /* Increase RX FIFO size to 5 for supporting fullduplex
1291                  * flow control mode
1292                  */
1293                 slave_write(slave,
1294                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1295                             CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS);
1296                 break;
1297         case CPSW_VERSION_2:
1298         case CPSW_VERSION_3:
1299         case CPSW_VERSION_4:
1300                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1301                 /* Increase RX FIFO size to 5 for supporting fullduplex
1302                  * flow control mode
1303                  */
1304                 slave_write(slave,
1305                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1306                             CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS);
1307                 break;
1308         }
1309
1310         /* setup max packet size, and mac address */
1311         __raw_writel(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1312         cpsw_set_slave_mac(slave, priv);
1313
1314         slave->mac_control = 0; /* no link yet */
1315
1316         slave_port = cpsw_get_slave_port(slave->slave_num);
1317
1318         if (cpsw->data.dual_emac)
1319                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1320         else
1321                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1322                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1323
1324         if (slave->data->phy_node) {
1325                 phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1326                                  &cpsw_adjust_link, 0, slave->data->phy_if);
1327                 if (!phy) {
1328                         dev_err(priv->dev, "phy \"%pOF\" not found on slave %d\n",
1329                                 slave->data->phy_node,
1330                                 slave->slave_num);
1331                         return;
1332                 }
1333         } else {
1334                 phy = phy_connect(priv->ndev, slave->data->phy_id,
1335                                  &cpsw_adjust_link, slave->data->phy_if);
1336                 if (IS_ERR(phy)) {
1337                         dev_err(priv->dev,
1338                                 "phy \"%s\" not found on slave %d, err %ld\n",
1339                                 slave->data->phy_id, slave->slave_num,
1340                                 PTR_ERR(phy));
1341                         return;
1342                 }
1343         }
1344
1345         slave->phy = phy;
1346
1347         phy_attached_info(slave->phy);
1348
1349         phy_start(slave->phy);
1350
1351         /* Configure GMII_SEL register */
1352         cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
1353 }
1354
1355 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1356 {
1357         struct cpsw_common *cpsw = priv->cpsw;
1358         const int vlan = cpsw->data.default_vlan;
1359         u32 reg;
1360         int i;
1361         int unreg_mcast_mask;
1362
1363         reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1364                CPSW2_PORT_VLAN;
1365
1366         writel(vlan, &cpsw->host_port_regs->port_vlan);
1367
1368         for (i = 0; i < cpsw->data.slaves; i++)
1369                 slave_write(cpsw->slaves + i, vlan, reg);
1370
1371         if (priv->ndev->flags & IFF_ALLMULTI)
1372                 unreg_mcast_mask = ALE_ALL_PORTS;
1373         else
1374                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1375
1376         cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1377                           ALE_ALL_PORTS, ALE_ALL_PORTS,
1378                           unreg_mcast_mask);
1379 }
1380
1381 static void cpsw_init_host_port(struct cpsw_priv *priv)
1382 {
1383         u32 fifo_mode;
1384         u32 control_reg;
1385         struct cpsw_common *cpsw = priv->cpsw;
1386
1387         /* soft reset the controller and initialize ale */
1388         soft_reset("cpsw", &cpsw->regs->soft_reset);
1389         cpsw_ale_start(cpsw->ale);
1390
1391         /* switch to vlan unaware mode */
1392         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1393                              CPSW_ALE_VLAN_AWARE);
1394         control_reg = readl(&cpsw->regs->control);
1395         control_reg |= CPSW_VLAN_AWARE;
1396         writel(control_reg, &cpsw->regs->control);
1397         fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1398                      CPSW_FIFO_NORMAL_MODE;
1399         writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1400
1401         /* setup host port priority mapping */
1402         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1403                      &cpsw->host_port_regs->cpdma_tx_pri_map);
1404         __raw_writel(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1405
1406         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1407                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1408
1409         if (!cpsw->data.dual_emac) {
1410                 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1411                                    0, 0);
1412                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1413                                    ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1414         }
1415 }
1416
1417 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1418 {
1419         struct cpsw_common *cpsw = priv->cpsw;
1420         struct sk_buff *skb;
1421         int ch_buf_num;
1422         int ch, i, ret;
1423
1424         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1425                 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
1426                 for (i = 0; i < ch_buf_num; i++) {
1427                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1428                                                           cpsw->rx_packet_max,
1429                                                           GFP_KERNEL);
1430                         if (!skb) {
1431                                 cpsw_err(priv, ifup, "cannot allocate skb\n");
1432                                 return -ENOMEM;
1433                         }
1434
1435                         skb_set_queue_mapping(skb, ch);
1436                         ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb,
1437                                                 skb->data, skb_tailroom(skb),
1438                                                 0);
1439                         if (ret < 0) {
1440                                 cpsw_err(priv, ifup,
1441                                          "cannot submit skb to channel %d rx, error %d\n",
1442                                          ch, ret);
1443                                 kfree_skb(skb);
1444                                 return ret;
1445                         }
1446                         kmemleak_not_leak(skb);
1447                 }
1448
1449                 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1450                           ch, ch_buf_num);
1451         }
1452
1453         return 0;
1454 }
1455
1456 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1457 {
1458         u32 slave_port;
1459
1460         slave_port = cpsw_get_slave_port(slave->slave_num);
1461
1462         if (!slave->phy)
1463                 return;
1464         phy_stop(slave->phy);
1465         phy_disconnect(slave->phy);
1466         slave->phy = NULL;
1467         cpsw_ale_control_set(cpsw->ale, slave_port,
1468                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1469         soft_reset_slave(slave);
1470 }
1471
1472 static int cpsw_ndo_open(struct net_device *ndev)
1473 {
1474         struct cpsw_priv *priv = netdev_priv(ndev);
1475         struct cpsw_common *cpsw = priv->cpsw;
1476         int ret;
1477         u32 reg;
1478
1479         ret = pm_runtime_get_sync(cpsw->dev);
1480         if (ret < 0) {
1481                 pm_runtime_put_noidle(cpsw->dev);
1482                 return ret;
1483         }
1484
1485         netif_carrier_off(ndev);
1486
1487         /* Notify the stack of the actual queue counts. */
1488         ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1489         if (ret) {
1490                 dev_err(priv->dev, "cannot set real number of tx queues\n");
1491                 goto err_cleanup;
1492         }
1493
1494         ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1495         if (ret) {
1496                 dev_err(priv->dev, "cannot set real number of rx queues\n");
1497                 goto err_cleanup;
1498         }
1499
1500         reg = cpsw->version;
1501
1502         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1503                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1504                  CPSW_RTL_VERSION(reg));
1505
1506         /* Initialize host and slave ports */
1507         if (!cpsw->usage_count)
1508                 cpsw_init_host_port(priv);
1509         for_each_slave(priv, cpsw_slave_open, priv);
1510
1511         /* Add default VLAN */
1512         if (!cpsw->data.dual_emac)
1513                 cpsw_add_default_vlan(priv);
1514         else
1515                 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
1516                                   ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1517
1518         /* initialize shared resources for every ndev */
1519         if (!cpsw->usage_count) {
1520                 /* disable priority elevation */
1521                 __raw_writel(0, &cpsw->regs->ptype);
1522
1523                 /* enable statistics collection only on all ports */
1524                 __raw_writel(0x7, &cpsw->regs->stat_port_en);
1525
1526                 /* Enable internal fifo flow control */
1527                 writel(0x7, &cpsw->regs->flow_control);
1528
1529                 napi_enable(&cpsw->napi_rx);
1530                 napi_enable(&cpsw->napi_tx);
1531
1532                 if (cpsw->tx_irq_disabled) {
1533                         cpsw->tx_irq_disabled = false;
1534                         enable_irq(cpsw->irqs_table[1]);
1535                 }
1536
1537                 if (cpsw->rx_irq_disabled) {
1538                         cpsw->rx_irq_disabled = false;
1539                         enable_irq(cpsw->irqs_table[0]);
1540                 }
1541
1542                 ret = cpsw_fill_rx_channels(priv);
1543                 if (ret < 0)
1544                         goto err_cleanup;
1545
1546                 if (cpts_register(cpsw->cpts))
1547                         dev_err(priv->dev, "error registering cpts device\n");
1548
1549         }
1550
1551         /* Enable Interrupt pacing if configured */
1552         if (cpsw->coal_intvl != 0) {
1553                 struct ethtool_coalesce coal;
1554
1555                 coal.rx_coalesce_usecs = cpsw->coal_intvl;
1556                 cpsw_set_coalesce(ndev, &coal);
1557         }
1558
1559         cpdma_ctlr_start(cpsw->dma);
1560         cpsw_intr_enable(cpsw);
1561         cpsw->usage_count++;
1562
1563         return 0;
1564
1565 err_cleanup:
1566         cpdma_ctlr_stop(cpsw->dma);
1567         for_each_slave(priv, cpsw_slave_stop, cpsw);
1568         pm_runtime_put_sync(cpsw->dev);
1569         netif_carrier_off(priv->ndev);
1570         return ret;
1571 }
1572
1573 static int cpsw_ndo_stop(struct net_device *ndev)
1574 {
1575         struct cpsw_priv *priv = netdev_priv(ndev);
1576         struct cpsw_common *cpsw = priv->cpsw;
1577
1578         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1579         netif_tx_stop_all_queues(priv->ndev);
1580         netif_carrier_off(priv->ndev);
1581
1582         if (cpsw->usage_count <= 1) {
1583                 napi_disable(&cpsw->napi_rx);
1584                 napi_disable(&cpsw->napi_tx);
1585                 cpts_unregister(cpsw->cpts);
1586                 cpsw_intr_disable(cpsw);
1587                 cpdma_ctlr_stop(cpsw->dma);
1588                 cpsw_ale_stop(cpsw->ale);
1589         }
1590         for_each_slave(priv, cpsw_slave_stop, cpsw);
1591
1592         if (cpsw_need_resplit(cpsw))
1593                 cpsw_split_res(ndev);
1594
1595         cpsw->usage_count--;
1596         pm_runtime_put_sync(cpsw->dev);
1597         return 0;
1598 }
1599
1600 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1601                                        struct net_device *ndev)
1602 {
1603         struct cpsw_priv *priv = netdev_priv(ndev);
1604         struct cpsw_common *cpsw = priv->cpsw;
1605         struct cpts *cpts = cpsw->cpts;
1606         struct netdev_queue *txq;
1607         struct cpdma_chan *txch;
1608         int ret, q_idx;
1609
1610         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1611                 cpsw_err(priv, tx_err, "packet pad failed\n");
1612                 ndev->stats.tx_dropped++;
1613                 return NET_XMIT_DROP;
1614         }
1615
1616         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1617             cpts_is_tx_enabled(cpts) && cpts_can_timestamp(cpts, skb))
1618                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1619
1620         q_idx = skb_get_queue_mapping(skb);
1621         if (q_idx >= cpsw->tx_ch_num)
1622                 q_idx = q_idx % cpsw->tx_ch_num;
1623
1624         txch = cpsw->txv[q_idx].ch;
1625         txq = netdev_get_tx_queue(ndev, q_idx);
1626         ret = cpsw_tx_packet_submit(priv, skb, txch);
1627         if (unlikely(ret != 0)) {
1628                 cpsw_err(priv, tx_err, "desc submit failed\n");
1629                 goto fail;
1630         }
1631
1632         /* If there is no more tx desc left free then we need to
1633          * tell the kernel to stop sending us tx frames.
1634          */
1635         if (unlikely(!cpdma_check_free_tx_desc(txch))) {
1636                 netif_tx_stop_queue(txq);
1637
1638                 /* Barrier, so that stop_queue visible to other cpus */
1639                 smp_mb__after_atomic();
1640
1641                 if (cpdma_check_free_tx_desc(txch))
1642                         netif_tx_wake_queue(txq);
1643         }
1644
1645         return NETDEV_TX_OK;
1646 fail:
1647         ndev->stats.tx_dropped++;
1648         netif_tx_stop_queue(txq);
1649
1650         /* Barrier, so that stop_queue visible to other cpus */
1651         smp_mb__after_atomic();
1652
1653         if (cpdma_check_free_tx_desc(txch))
1654                 netif_tx_wake_queue(txq);
1655
1656         return NETDEV_TX_BUSY;
1657 }
1658
1659 #if IS_ENABLED(CONFIG_TI_CPTS)
1660
1661 static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
1662 {
1663         struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
1664         u32 ts_en, seq_id;
1665
1666         if (!cpts_is_tx_enabled(cpsw->cpts) &&
1667             !cpts_is_rx_enabled(cpsw->cpts)) {
1668                 slave_write(slave, 0, CPSW1_TS_CTL);
1669                 return;
1670         }
1671
1672         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1673         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1674
1675         if (cpts_is_tx_enabled(cpsw->cpts))
1676                 ts_en |= CPSW_V1_TS_TX_EN;
1677
1678         if (cpts_is_rx_enabled(cpsw->cpts))
1679                 ts_en |= CPSW_V1_TS_RX_EN;
1680
1681         slave_write(slave, ts_en, CPSW1_TS_CTL);
1682         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1683 }
1684
1685 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1686 {
1687         struct cpsw_slave *slave;
1688         struct cpsw_common *cpsw = priv->cpsw;
1689         u32 ctrl, mtype;
1690
1691         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1692
1693         ctrl = slave_read(slave, CPSW2_CONTROL);
1694         switch (cpsw->version) {
1695         case CPSW_VERSION_2:
1696                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1697
1698                 if (cpts_is_tx_enabled(cpsw->cpts))
1699                         ctrl |= CTRL_V2_TX_TS_BITS;
1700
1701                 if (cpts_is_rx_enabled(cpsw->cpts))
1702                         ctrl |= CTRL_V2_RX_TS_BITS;
1703                 break;
1704         case CPSW_VERSION_3:
1705         default:
1706                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1707
1708                 if (cpts_is_tx_enabled(cpsw->cpts))
1709                         ctrl |= CTRL_V3_TX_TS_BITS;
1710
1711                 if (cpts_is_rx_enabled(cpsw->cpts))
1712                         ctrl |= CTRL_V3_RX_TS_BITS;
1713                 break;
1714         }
1715
1716         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1717
1718         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1719         slave_write(slave, ctrl, CPSW2_CONTROL);
1720         __raw_writel(ETH_P_1588, &cpsw->regs->ts_ltype);
1721 }
1722
1723 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1724 {
1725         struct cpsw_priv *priv = netdev_priv(dev);
1726         struct hwtstamp_config cfg;
1727         struct cpsw_common *cpsw = priv->cpsw;
1728         struct cpts *cpts = cpsw->cpts;
1729
1730         if (cpsw->version != CPSW_VERSION_1 &&
1731             cpsw->version != CPSW_VERSION_2 &&
1732             cpsw->version != CPSW_VERSION_3)
1733                 return -EOPNOTSUPP;
1734
1735         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1736                 return -EFAULT;
1737
1738         /* reserved for future extensions */
1739         if (cfg.flags)
1740                 return -EINVAL;
1741
1742         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1743                 return -ERANGE;
1744
1745         switch (cfg.rx_filter) {
1746         case HWTSTAMP_FILTER_NONE:
1747                 cpts_rx_enable(cpts, 0);
1748                 break;
1749         case HWTSTAMP_FILTER_ALL:
1750         case HWTSTAMP_FILTER_NTP_ALL:
1751                 return -ERANGE;
1752         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1753         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1754         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1755                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V1_L4_EVENT);
1756                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
1757                 break;
1758         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1759         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1760         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1761         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1762         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1763         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1764         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1765         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1766         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1767                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V2_EVENT);
1768                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1769                 break;
1770         default:
1771                 return -ERANGE;
1772         }
1773
1774         cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON);
1775
1776         switch (cpsw->version) {
1777         case CPSW_VERSION_1:
1778                 cpsw_hwtstamp_v1(cpsw);
1779                 break;
1780         case CPSW_VERSION_2:
1781         case CPSW_VERSION_3:
1782                 cpsw_hwtstamp_v2(priv);
1783                 break;
1784         default:
1785                 WARN_ON(1);
1786         }
1787
1788         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1789 }
1790
1791 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1792 {
1793         struct cpsw_common *cpsw = ndev_to_cpsw(dev);
1794         struct cpts *cpts = cpsw->cpts;
1795         struct hwtstamp_config cfg;
1796
1797         if (cpsw->version != CPSW_VERSION_1 &&
1798             cpsw->version != CPSW_VERSION_2 &&
1799             cpsw->version != CPSW_VERSION_3)
1800                 return -EOPNOTSUPP;
1801
1802         cfg.flags = 0;
1803         cfg.tx_type = cpts_is_tx_enabled(cpts) ?
1804                       HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1805         cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
1806                          cpts->rx_enable : HWTSTAMP_FILTER_NONE);
1807
1808         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1809 }
1810 #else
1811 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1812 {
1813         return -EOPNOTSUPP;
1814 }
1815
1816 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1817 {
1818         return -EOPNOTSUPP;
1819 }
1820 #endif /*CONFIG_TI_CPTS*/
1821
1822 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1823 {
1824         struct cpsw_priv *priv = netdev_priv(dev);
1825         struct cpsw_common *cpsw = priv->cpsw;
1826         int slave_no = cpsw_slave_index(cpsw, priv);
1827
1828         if (!netif_running(dev))
1829                 return -EINVAL;
1830
1831         switch (cmd) {
1832         case SIOCSHWTSTAMP:
1833                 return cpsw_hwtstamp_set(dev, req);
1834         case SIOCGHWTSTAMP:
1835                 return cpsw_hwtstamp_get(dev, req);
1836         }
1837
1838         if (!cpsw->slaves[slave_no].phy)
1839                 return -EOPNOTSUPP;
1840         return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
1841 }
1842
1843 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1844 {
1845         struct cpsw_priv *priv = netdev_priv(ndev);
1846         struct cpsw_common *cpsw = priv->cpsw;
1847         int ch;
1848
1849         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1850         ndev->stats.tx_errors++;
1851         cpsw_intr_disable(cpsw);
1852         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1853                 cpdma_chan_stop(cpsw->txv[ch].ch);
1854                 cpdma_chan_start(cpsw->txv[ch].ch);
1855         }
1856
1857         cpsw_intr_enable(cpsw);
1858         netif_trans_update(ndev);
1859         netif_tx_wake_all_queues(ndev);
1860 }
1861
1862 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1863 {
1864         struct cpsw_priv *priv = netdev_priv(ndev);
1865         struct sockaddr *addr = (struct sockaddr *)p;
1866         struct cpsw_common *cpsw = priv->cpsw;
1867         int flags = 0;
1868         u16 vid = 0;
1869         int ret;
1870
1871         if (!is_valid_ether_addr(addr->sa_data))
1872                 return -EADDRNOTAVAIL;
1873
1874         ret = pm_runtime_get_sync(cpsw->dev);
1875         if (ret < 0) {
1876                 pm_runtime_put_noidle(cpsw->dev);
1877                 return ret;
1878         }
1879
1880         if (cpsw->data.dual_emac) {
1881                 vid = cpsw->slaves[priv->emac_port].port_vlan;
1882                 flags = ALE_VLAN;
1883         }
1884
1885         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1886                            flags, vid);
1887         cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
1888                            flags, vid);
1889
1890         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1891         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1892         for_each_slave(priv, cpsw_set_slave_mac, priv);
1893
1894         pm_runtime_put(cpsw->dev);
1895
1896         return 0;
1897 }
1898
1899 #ifdef CONFIG_NET_POLL_CONTROLLER
1900 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1901 {
1902         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1903
1904         cpsw_intr_disable(cpsw);
1905         cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
1906         cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
1907         cpsw_intr_enable(cpsw);
1908 }
1909 #endif
1910
1911 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1912                                 unsigned short vid)
1913 {
1914         int ret;
1915         int unreg_mcast_mask = 0;
1916         u32 port_mask;
1917         struct cpsw_common *cpsw = priv->cpsw;
1918
1919         if (cpsw->data.dual_emac) {
1920                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1921
1922                 if (priv->ndev->flags & IFF_ALLMULTI)
1923                         unreg_mcast_mask = port_mask;
1924         } else {
1925                 port_mask = ALE_ALL_PORTS;
1926
1927                 if (priv->ndev->flags & IFF_ALLMULTI)
1928                         unreg_mcast_mask = ALE_ALL_PORTS;
1929                 else
1930                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1931         }
1932
1933         ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
1934                                 unreg_mcast_mask);
1935         if (ret != 0)
1936                 return ret;
1937
1938         ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1939                                  HOST_PORT_NUM, ALE_VLAN, vid);
1940         if (ret != 0)
1941                 goto clean_vid;
1942
1943         ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1944                                  port_mask, ALE_VLAN, vid, 0);
1945         if (ret != 0)
1946                 goto clean_vlan_ucast;
1947         return 0;
1948
1949 clean_vlan_ucast:
1950         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
1951                            HOST_PORT_NUM, ALE_VLAN, vid);
1952 clean_vid:
1953         cpsw_ale_del_vlan(cpsw->ale, vid, 0);
1954         return ret;
1955 }
1956
1957 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1958                                     __be16 proto, u16 vid)
1959 {
1960         struct cpsw_priv *priv = netdev_priv(ndev);
1961         struct cpsw_common *cpsw = priv->cpsw;
1962         int ret;
1963
1964         if (vid == cpsw->data.default_vlan)
1965                 return 0;
1966
1967         ret = pm_runtime_get_sync(cpsw->dev);
1968         if (ret < 0) {
1969                 pm_runtime_put_noidle(cpsw->dev);
1970                 return ret;
1971         }
1972
1973         if (cpsw->data.dual_emac) {
1974                 /* In dual EMAC, reserved VLAN id should not be used for
1975                  * creating VLAN interfaces as this can break the dual
1976                  * EMAC port separation
1977                  */
1978                 int i;
1979
1980                 for (i = 0; i < cpsw->data.slaves; i++) {
1981                         if (vid == cpsw->slaves[i].port_vlan)
1982                                 return -EINVAL;
1983                 }
1984         }
1985
1986         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1987         ret = cpsw_add_vlan_ale_entry(priv, vid);
1988
1989         pm_runtime_put(cpsw->dev);
1990         return ret;
1991 }
1992
1993 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1994                                      __be16 proto, u16 vid)
1995 {
1996         struct cpsw_priv *priv = netdev_priv(ndev);
1997         struct cpsw_common *cpsw = priv->cpsw;
1998         int ret;
1999
2000         if (vid == cpsw->data.default_vlan)
2001                 return 0;
2002
2003         ret = pm_runtime_get_sync(cpsw->dev);
2004         if (ret < 0) {
2005                 pm_runtime_put_noidle(cpsw->dev);
2006                 return ret;
2007         }
2008
2009         if (cpsw->data.dual_emac) {
2010                 int i;
2011
2012                 for (i = 0; i < cpsw->data.slaves; i++) {
2013                         if (vid == cpsw->slaves[i].port_vlan)
2014                                 return -EINVAL;
2015                 }
2016         }
2017
2018         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
2019         ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2020         if (ret != 0)
2021                 return ret;
2022
2023         ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2024                                  HOST_PORT_NUM, ALE_VLAN, vid);
2025         if (ret != 0)
2026                 return ret;
2027
2028         ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
2029                                  0, ALE_VLAN, vid);
2030         pm_runtime_put(cpsw->dev);
2031         return ret;
2032 }
2033
2034 static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
2035 {
2036         struct cpsw_priv *priv = netdev_priv(ndev);
2037         struct cpsw_common *cpsw = priv->cpsw;
2038         struct cpsw_slave *slave;
2039         u32 min_rate;
2040         u32 ch_rate;
2041         int i, ret;
2042
2043         ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
2044         if (ch_rate == rate)
2045                 return 0;
2046
2047         ch_rate = rate * 1000;
2048         min_rate = cpdma_chan_get_min_rate(cpsw->dma);
2049         if ((ch_rate < min_rate && ch_rate)) {
2050                 dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
2051                         min_rate);
2052                 return -EINVAL;
2053         }
2054
2055         if (rate > cpsw->speed) {
2056                 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
2057                 return -EINVAL;
2058         }
2059
2060         ret = pm_runtime_get_sync(cpsw->dev);
2061         if (ret < 0) {
2062                 pm_runtime_put_noidle(cpsw->dev);
2063                 return ret;
2064         }
2065
2066         ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
2067         pm_runtime_put(cpsw->dev);
2068
2069         if (ret)
2070                 return ret;
2071
2072         /* update rates for slaves tx queues */
2073         for (i = 0; i < cpsw->data.slaves; i++) {
2074                 slave = &cpsw->slaves[i];
2075                 if (!slave->ndev)
2076                         continue;
2077
2078                 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
2079         }
2080
2081         cpsw_split_res(ndev);
2082         return ret;
2083 }
2084
2085 static const struct net_device_ops cpsw_netdev_ops = {
2086         .ndo_open               = cpsw_ndo_open,
2087         .ndo_stop               = cpsw_ndo_stop,
2088         .ndo_start_xmit         = cpsw_ndo_start_xmit,
2089         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
2090         .ndo_do_ioctl           = cpsw_ndo_ioctl,
2091         .ndo_validate_addr      = eth_validate_addr,
2092         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
2093         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
2094         .ndo_set_tx_maxrate     = cpsw_ndo_set_tx_maxrate,
2095 #ifdef CONFIG_NET_POLL_CONTROLLER
2096         .ndo_poll_controller    = cpsw_ndo_poll_controller,
2097 #endif
2098         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
2099         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
2100 };
2101
2102 static int cpsw_get_regs_len(struct net_device *ndev)
2103 {
2104         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2105
2106         return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
2107 }
2108
2109 static void cpsw_get_regs(struct net_device *ndev,
2110                           struct ethtool_regs *regs, void *p)
2111 {
2112         u32 *reg = p;
2113         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2114
2115         /* update CPSW IP version */
2116         regs->version = cpsw->version;
2117
2118         cpsw_ale_dump(cpsw->ale, reg);
2119 }
2120
2121 static void cpsw_get_drvinfo(struct net_device *ndev,
2122                              struct ethtool_drvinfo *info)
2123 {
2124         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2125         struct platform_device  *pdev = to_platform_device(cpsw->dev);
2126
2127         strlcpy(info->driver, "cpsw", sizeof(info->driver));
2128         strlcpy(info->version, "1.0", sizeof(info->version));
2129         strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
2130 }
2131
2132 static u32 cpsw_get_msglevel(struct net_device *ndev)
2133 {
2134         struct cpsw_priv *priv = netdev_priv(ndev);
2135         return priv->msg_enable;
2136 }
2137
2138 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2139 {
2140         struct cpsw_priv *priv = netdev_priv(ndev);
2141         priv->msg_enable = value;
2142 }
2143
2144 #if IS_ENABLED(CONFIG_TI_CPTS)
2145 static int cpsw_get_ts_info(struct net_device *ndev,
2146                             struct ethtool_ts_info *info)
2147 {
2148         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2149
2150         info->so_timestamping =
2151                 SOF_TIMESTAMPING_TX_HARDWARE |
2152                 SOF_TIMESTAMPING_TX_SOFTWARE |
2153                 SOF_TIMESTAMPING_RX_HARDWARE |
2154                 SOF_TIMESTAMPING_RX_SOFTWARE |
2155                 SOF_TIMESTAMPING_SOFTWARE |
2156                 SOF_TIMESTAMPING_RAW_HARDWARE;
2157         info->phc_index = cpsw->cpts->phc_index;
2158         info->tx_types =
2159                 (1 << HWTSTAMP_TX_OFF) |
2160                 (1 << HWTSTAMP_TX_ON);
2161         info->rx_filters =
2162                 (1 << HWTSTAMP_FILTER_NONE) |
2163                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2164                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2165         return 0;
2166 }
2167 #else
2168 static int cpsw_get_ts_info(struct net_device *ndev,
2169                             struct ethtool_ts_info *info)
2170 {
2171         info->so_timestamping =
2172                 SOF_TIMESTAMPING_TX_SOFTWARE |
2173                 SOF_TIMESTAMPING_RX_SOFTWARE |
2174                 SOF_TIMESTAMPING_SOFTWARE;
2175         info->phc_index = -1;
2176         info->tx_types = 0;
2177         info->rx_filters = 0;
2178         return 0;
2179 }
2180 #endif
2181
2182 static int cpsw_get_link_ksettings(struct net_device *ndev,
2183                                    struct ethtool_link_ksettings *ecmd)
2184 {
2185         struct cpsw_priv *priv = netdev_priv(ndev);
2186         struct cpsw_common *cpsw = priv->cpsw;
2187         int slave_no = cpsw_slave_index(cpsw, priv);
2188
2189         if (!cpsw->slaves[slave_no].phy)
2190                 return -EOPNOTSUPP;
2191
2192         phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd);
2193         return 0;
2194 }
2195
2196 static int cpsw_set_link_ksettings(struct net_device *ndev,
2197                                    const struct ethtool_link_ksettings *ecmd)
2198 {
2199         struct cpsw_priv *priv = netdev_priv(ndev);
2200         struct cpsw_common *cpsw = priv->cpsw;
2201         int slave_no = cpsw_slave_index(cpsw, priv);
2202
2203         if (cpsw->slaves[slave_no].phy)
2204                 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2205                                                  ecmd);
2206         else
2207                 return -EOPNOTSUPP;
2208 }
2209
2210 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2211 {
2212         struct cpsw_priv *priv = netdev_priv(ndev);
2213         struct cpsw_common *cpsw = priv->cpsw;
2214         int slave_no = cpsw_slave_index(cpsw, priv);
2215
2216         wol->supported = 0;
2217         wol->wolopts = 0;
2218
2219         if (cpsw->slaves[slave_no].phy)
2220                 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2221 }
2222
2223 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2224 {
2225         struct cpsw_priv *priv = netdev_priv(ndev);
2226         struct cpsw_common *cpsw = priv->cpsw;
2227         int slave_no = cpsw_slave_index(cpsw, priv);
2228
2229         if (cpsw->slaves[slave_no].phy)
2230                 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2231         else
2232                 return -EOPNOTSUPP;
2233 }
2234
2235 static void cpsw_get_pauseparam(struct net_device *ndev,
2236                                 struct ethtool_pauseparam *pause)
2237 {
2238         struct cpsw_priv *priv = netdev_priv(ndev);
2239
2240         pause->autoneg = AUTONEG_DISABLE;
2241         pause->rx_pause = priv->rx_pause ? true : false;
2242         pause->tx_pause = priv->tx_pause ? true : false;
2243 }
2244
2245 static int cpsw_set_pauseparam(struct net_device *ndev,
2246                                struct ethtool_pauseparam *pause)
2247 {
2248         struct cpsw_priv *priv = netdev_priv(ndev);
2249         bool link;
2250
2251         priv->rx_pause = pause->rx_pause ? true : false;
2252         priv->tx_pause = pause->tx_pause ? true : false;
2253
2254         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2255         return 0;
2256 }
2257
2258 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2259 {
2260         struct cpsw_priv *priv = netdev_priv(ndev);
2261         struct cpsw_common *cpsw = priv->cpsw;
2262         int ret;
2263
2264         ret = pm_runtime_get_sync(cpsw->dev);
2265         if (ret < 0) {
2266                 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2267                 pm_runtime_put_noidle(cpsw->dev);
2268         }
2269
2270         return ret;
2271 }
2272
2273 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2274 {
2275         struct cpsw_priv *priv = netdev_priv(ndev);
2276         int ret;
2277
2278         ret = pm_runtime_put(priv->cpsw->dev);
2279         if (ret < 0)
2280                 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2281 }
2282
2283 static void cpsw_get_channels(struct net_device *ndev,
2284                               struct ethtool_channels *ch)
2285 {
2286         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2287
2288         ch->max_combined = 0;
2289         ch->max_rx = CPSW_MAX_QUEUES;
2290         ch->max_tx = CPSW_MAX_QUEUES;
2291         ch->max_other = 0;
2292         ch->other_count = 0;
2293         ch->rx_count = cpsw->rx_ch_num;
2294         ch->tx_count = cpsw->tx_ch_num;
2295         ch->combined_count = 0;
2296 }
2297
2298 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2299                                   struct ethtool_channels *ch)
2300 {
2301         if (ch->combined_count)
2302                 return -EINVAL;
2303
2304         /* verify we have at least one channel in each direction */
2305         if (!ch->rx_count || !ch->tx_count)
2306                 return -EINVAL;
2307
2308         if (ch->rx_count > cpsw->data.channels ||
2309             ch->tx_count > cpsw->data.channels)
2310                 return -EINVAL;
2311
2312         return 0;
2313 }
2314
2315 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2316 {
2317         int (*poll)(struct napi_struct *, int);
2318         struct cpsw_common *cpsw = priv->cpsw;
2319         void (*handler)(void *, int, int);
2320         struct netdev_queue *queue;
2321         struct cpsw_vector *vec;
2322         int ret, *ch;
2323
2324         if (rx) {
2325                 ch = &cpsw->rx_ch_num;
2326                 vec = cpsw->rxv;
2327                 handler = cpsw_rx_handler;
2328                 poll = cpsw_rx_poll;
2329         } else {
2330                 ch = &cpsw->tx_ch_num;
2331                 vec = cpsw->txv;
2332                 handler = cpsw_tx_handler;
2333                 poll = cpsw_tx_poll;
2334         }
2335
2336         while (*ch < ch_num) {
2337                 vec[*ch].ch = cpdma_chan_create(cpsw->dma, *ch, handler, rx);
2338                 queue = netdev_get_tx_queue(priv->ndev, *ch);
2339                 queue->tx_maxrate = 0;
2340
2341                 if (IS_ERR(vec[*ch].ch))
2342                         return PTR_ERR(vec[*ch].ch);
2343
2344                 if (!vec[*ch].ch)
2345                         return -EINVAL;
2346
2347                 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2348                           (rx ? "rx" : "tx"));
2349                 (*ch)++;
2350         }
2351
2352         while (*ch > ch_num) {
2353                 (*ch)--;
2354
2355                 ret = cpdma_chan_destroy(vec[*ch].ch);
2356                 if (ret)
2357                         return ret;
2358
2359                 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2360                           (rx ? "rx" : "tx"));
2361         }
2362
2363         return 0;
2364 }
2365
2366 static int cpsw_update_channels(struct cpsw_priv *priv,
2367                                 struct ethtool_channels *ch)
2368 {
2369         int ret;
2370
2371         ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2372         if (ret)
2373                 return ret;
2374
2375         ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2376         if (ret)
2377                 return ret;
2378
2379         return 0;
2380 }
2381
2382 static void cpsw_suspend_data_pass(struct net_device *ndev)
2383 {
2384         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2385         struct cpsw_slave *slave;
2386         int i;
2387
2388         /* Disable NAPI scheduling */
2389         cpsw_intr_disable(cpsw);
2390
2391         /* Stop all transmit queues for every network device.
2392          * Disable re-using rx descriptors with dormant_on.
2393          */
2394         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2395                 if (!(slave->ndev && netif_running(slave->ndev)))
2396                         continue;
2397
2398                 netif_tx_stop_all_queues(slave->ndev);
2399                 netif_dormant_on(slave->ndev);
2400         }
2401
2402         /* Handle rest of tx packets and stop cpdma channels */
2403         cpdma_ctlr_stop(cpsw->dma);
2404 }
2405
2406 static int cpsw_resume_data_pass(struct net_device *ndev)
2407 {
2408         struct cpsw_priv *priv = netdev_priv(ndev);
2409         struct cpsw_common *cpsw = priv->cpsw;
2410         struct cpsw_slave *slave;
2411         int i, ret;
2412
2413         /* Allow rx packets handling */
2414         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2415                 if (slave->ndev && netif_running(slave->ndev))
2416                         netif_dormant_off(slave->ndev);
2417
2418         /* After this receive is started */
2419         if (cpsw->usage_count) {
2420                 ret = cpsw_fill_rx_channels(priv);
2421                 if (ret)
2422                         return ret;
2423
2424                 cpdma_ctlr_start(cpsw->dma);
2425                 cpsw_intr_enable(cpsw);
2426         }
2427
2428         /* Resume transmit for every affected interface */
2429         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2430                 if (slave->ndev && netif_running(slave->ndev))
2431                         netif_tx_start_all_queues(slave->ndev);
2432
2433         return 0;
2434 }
2435
2436 static int cpsw_set_channels(struct net_device *ndev,
2437                              struct ethtool_channels *chs)
2438 {
2439         struct cpsw_priv *priv = netdev_priv(ndev);
2440         struct cpsw_common *cpsw = priv->cpsw;
2441         struct cpsw_slave *slave;
2442         int i, ret;
2443
2444         ret = cpsw_check_ch_settings(cpsw, chs);
2445         if (ret < 0)
2446                 return ret;
2447
2448         cpsw_suspend_data_pass(ndev);
2449         ret = cpsw_update_channels(priv, chs);
2450         if (ret)
2451                 goto err;
2452
2453         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2454                 if (!(slave->ndev && netif_running(slave->ndev)))
2455                         continue;
2456
2457                 /* Inform stack about new count of queues */
2458                 ret = netif_set_real_num_tx_queues(slave->ndev,
2459                                                    cpsw->tx_ch_num);
2460                 if (ret) {
2461                         dev_err(priv->dev, "cannot set real number of tx queues\n");
2462                         goto err;
2463                 }
2464
2465                 ret = netif_set_real_num_rx_queues(slave->ndev,
2466                                                    cpsw->rx_ch_num);
2467                 if (ret) {
2468                         dev_err(priv->dev, "cannot set real number of rx queues\n");
2469                         goto err;
2470                 }
2471         }
2472
2473         if (cpsw->usage_count)
2474                 cpsw_split_res(ndev);
2475
2476         ret = cpsw_resume_data_pass(ndev);
2477         if (!ret)
2478                 return 0;
2479 err:
2480         dev_err(priv->dev, "cannot update channels number, closing device\n");
2481         dev_close(ndev);
2482         return ret;
2483 }
2484
2485 static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
2486 {
2487         struct cpsw_priv *priv = netdev_priv(ndev);
2488         struct cpsw_common *cpsw = priv->cpsw;
2489         int slave_no = cpsw_slave_index(cpsw, priv);
2490
2491         if (cpsw->slaves[slave_no].phy)
2492                 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
2493         else
2494                 return -EOPNOTSUPP;
2495 }
2496
2497 static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
2498 {
2499         struct cpsw_priv *priv = netdev_priv(ndev);
2500         struct cpsw_common *cpsw = priv->cpsw;
2501         int slave_no = cpsw_slave_index(cpsw, priv);
2502
2503         if (cpsw->slaves[slave_no].phy)
2504                 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
2505         else
2506                 return -EOPNOTSUPP;
2507 }
2508
2509 static int cpsw_nway_reset(struct net_device *ndev)
2510 {
2511         struct cpsw_priv *priv = netdev_priv(ndev);
2512         struct cpsw_common *cpsw = priv->cpsw;
2513         int slave_no = cpsw_slave_index(cpsw, priv);
2514
2515         if (cpsw->slaves[slave_no].phy)
2516                 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
2517         else
2518                 return -EOPNOTSUPP;
2519 }
2520
2521 static void cpsw_get_ringparam(struct net_device *ndev,
2522                                struct ethtool_ringparam *ering)
2523 {
2524         struct cpsw_priv *priv = netdev_priv(ndev);
2525         struct cpsw_common *cpsw = priv->cpsw;
2526
2527         /* not supported */
2528         ering->tx_max_pending = 0;
2529         ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
2530         ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES;
2531         ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
2532 }
2533
2534 static int cpsw_set_ringparam(struct net_device *ndev,
2535                               struct ethtool_ringparam *ering)
2536 {
2537         struct cpsw_priv *priv = netdev_priv(ndev);
2538         struct cpsw_common *cpsw = priv->cpsw;
2539         int ret;
2540
2541         /* ignore ering->tx_pending - only rx_pending adjustment is supported */
2542
2543         if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
2544             ering->rx_pending < CPSW_MAX_QUEUES ||
2545             ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES))
2546                 return -EINVAL;
2547
2548         if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma))
2549                 return 0;
2550
2551         cpsw_suspend_data_pass(ndev);
2552
2553         cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
2554
2555         if (cpsw->usage_count)
2556                 cpdma_chan_split_pool(cpsw->dma);
2557
2558         ret = cpsw_resume_data_pass(ndev);
2559         if (!ret)
2560                 return 0;
2561
2562         dev_err(&ndev->dev, "cannot set ring params, closing device\n");
2563         dev_close(ndev);
2564         return ret;
2565 }
2566
2567 static const struct ethtool_ops cpsw_ethtool_ops = {
2568         .get_drvinfo    = cpsw_get_drvinfo,
2569         .get_msglevel   = cpsw_get_msglevel,
2570         .set_msglevel   = cpsw_set_msglevel,
2571         .get_link       = ethtool_op_get_link,
2572         .get_ts_info    = cpsw_get_ts_info,
2573         .get_coalesce   = cpsw_get_coalesce,
2574         .set_coalesce   = cpsw_set_coalesce,
2575         .get_sset_count         = cpsw_get_sset_count,
2576         .get_strings            = cpsw_get_strings,
2577         .get_ethtool_stats      = cpsw_get_ethtool_stats,
2578         .get_pauseparam         = cpsw_get_pauseparam,
2579         .set_pauseparam         = cpsw_set_pauseparam,
2580         .get_wol        = cpsw_get_wol,
2581         .set_wol        = cpsw_set_wol,
2582         .get_regs_len   = cpsw_get_regs_len,
2583         .get_regs       = cpsw_get_regs,
2584         .begin          = cpsw_ethtool_op_begin,
2585         .complete       = cpsw_ethtool_op_complete,
2586         .get_channels   = cpsw_get_channels,
2587         .set_channels   = cpsw_set_channels,
2588         .get_link_ksettings     = cpsw_get_link_ksettings,
2589         .set_link_ksettings     = cpsw_set_link_ksettings,
2590         .get_eee        = cpsw_get_eee,
2591         .set_eee        = cpsw_set_eee,
2592         .nway_reset     = cpsw_nway_reset,
2593         .get_ringparam = cpsw_get_ringparam,
2594         .set_ringparam = cpsw_set_ringparam,
2595 };
2596
2597 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
2598                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
2599 {
2600         void __iomem            *regs = cpsw->regs;
2601         int                     slave_num = slave->slave_num;
2602         struct cpsw_slave_data  *data = cpsw->data.slave_data + slave_num;
2603
2604         slave->data     = data;
2605         slave->regs     = regs + slave_reg_ofs;
2606         slave->sliver   = regs + sliver_reg_ofs;
2607         slave->port_vlan = data->dual_emac_res_vlan;
2608 }
2609
2610 static int cpsw_probe_dt(struct cpsw_platform_data *data,
2611                          struct platform_device *pdev)
2612 {
2613         struct device_node *node = pdev->dev.of_node;
2614         struct device_node *slave_node;
2615         int i = 0, ret;
2616         u32 prop;
2617
2618         if (!node)
2619                 return -EINVAL;
2620
2621         if (of_property_read_u32(node, "slaves", &prop)) {
2622                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2623                 return -EINVAL;
2624         }
2625         data->slaves = prop;
2626
2627         if (of_property_read_u32(node, "active_slave", &prop)) {
2628                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
2629                 return -EINVAL;
2630         }
2631         data->active_slave = prop;
2632
2633         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2634                                         * sizeof(struct cpsw_slave_data),
2635                                         GFP_KERNEL);
2636         if (!data->slave_data)
2637                 return -ENOMEM;
2638
2639         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2640                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2641                 return -EINVAL;
2642         }
2643         data->channels = prop;
2644
2645         if (of_property_read_u32(node, "ale_entries", &prop)) {
2646                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2647                 return -EINVAL;
2648         }
2649         data->ale_entries = prop;
2650
2651         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2652                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2653                 return -EINVAL;
2654         }
2655         data->bd_ram_size = prop;
2656
2657         if (of_property_read_u32(node, "mac_control", &prop)) {
2658                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2659                 return -EINVAL;
2660         }
2661         data->mac_control = prop;
2662
2663         if (of_property_read_bool(node, "dual_emac"))
2664                 data->dual_emac = 1;
2665
2666         /*
2667          * Populate all the child nodes here...
2668          */
2669         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2670         /* We do not want to force this, as in some cases may not have child */
2671         if (ret)
2672                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2673
2674         for_each_available_child_of_node(node, slave_node) {
2675                 struct cpsw_slave_data *slave_data = data->slave_data + i;
2676                 const void *mac_addr = NULL;
2677                 int lenp;
2678                 const __be32 *parp;
2679
2680                 /* This is no slave child node, continue */
2681                 if (strcmp(slave_node->name, "slave"))
2682                         continue;
2683
2684                 slave_data->phy_node = of_parse_phandle(slave_node,
2685                                                         "phy-handle", 0);
2686                 parp = of_get_property(slave_node, "phy_id", &lenp);
2687                 if (slave_data->phy_node) {
2688                         dev_dbg(&pdev->dev,
2689                                 "slave[%d] using phy-handle=\"%pOF\"\n",
2690                                 i, slave_data->phy_node);
2691                 } else if (of_phy_is_fixed_link(slave_node)) {
2692                         /* In the case of a fixed PHY, the DT node associated
2693                          * to the PHY is the Ethernet MAC DT node.
2694                          */
2695                         ret = of_phy_register_fixed_link(slave_node);
2696                         if (ret) {
2697                                 if (ret != -EPROBE_DEFER)
2698                                         dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
2699                                 return ret;
2700                         }
2701                         slave_data->phy_node = of_node_get(slave_node);
2702                 } else if (parp) {
2703                         u32 phyid;
2704                         struct device_node *mdio_node;
2705                         struct platform_device *mdio;
2706
2707                         if (lenp != (sizeof(__be32) * 2)) {
2708                                 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2709                                 goto no_phy_slave;
2710                         }
2711                         mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2712                         phyid = be32_to_cpup(parp+1);
2713                         mdio = of_find_device_by_node(mdio_node);
2714                         of_node_put(mdio_node);
2715                         if (!mdio) {
2716                                 dev_err(&pdev->dev, "Missing mdio platform device\n");
2717                                 return -EINVAL;
2718                         }
2719                         snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2720                                  PHY_ID_FMT, mdio->name, phyid);
2721                         put_device(&mdio->dev);
2722                 } else {
2723                         dev_err(&pdev->dev,
2724                                 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2725                                 i);
2726                         goto no_phy_slave;
2727                 }
2728                 slave_data->phy_if = of_get_phy_mode(slave_node);
2729                 if (slave_data->phy_if < 0) {
2730                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2731                                 i);
2732                         return slave_data->phy_if;
2733                 }
2734
2735 no_phy_slave:
2736                 mac_addr = of_get_mac_address(slave_node);
2737                 if (mac_addr) {
2738                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2739                 } else {
2740                         ret = ti_cm_get_macid(&pdev->dev, i,
2741                                               slave_data->mac_addr);
2742                         if (ret)
2743                                 return ret;
2744                 }
2745                 if (data->dual_emac) {
2746                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2747                                                  &prop)) {
2748                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2749                                 slave_data->dual_emac_res_vlan = i+1;
2750                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2751                                         slave_data->dual_emac_res_vlan, i);
2752                         } else {
2753                                 slave_data->dual_emac_res_vlan = prop;
2754                         }
2755                 }
2756
2757                 i++;
2758                 if (i == data->slaves)
2759                         break;
2760         }
2761
2762         return 0;
2763 }
2764
2765 static void cpsw_remove_dt(struct platform_device *pdev)
2766 {
2767         struct net_device *ndev = platform_get_drvdata(pdev);
2768         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2769         struct cpsw_platform_data *data = &cpsw->data;
2770         struct device_node *node = pdev->dev.of_node;
2771         struct device_node *slave_node;
2772         int i = 0;
2773
2774         for_each_available_child_of_node(node, slave_node) {
2775                 struct cpsw_slave_data *slave_data = &data->slave_data[i];
2776
2777                 if (strcmp(slave_node->name, "slave"))
2778                         continue;
2779
2780                 if (of_phy_is_fixed_link(slave_node))
2781                         of_phy_deregister_fixed_link(slave_node);
2782
2783                 of_node_put(slave_data->phy_node);
2784
2785                 i++;
2786                 if (i == data->slaves)
2787                         break;
2788         }
2789
2790         of_platform_depopulate(&pdev->dev);
2791 }
2792
2793 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
2794 {
2795         struct cpsw_common              *cpsw = priv->cpsw;
2796         struct cpsw_platform_data       *data = &cpsw->data;
2797         struct net_device               *ndev;
2798         struct cpsw_priv                *priv_sl2;
2799         int ret = 0;
2800
2801         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2802         if (!ndev) {
2803                 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
2804                 return -ENOMEM;
2805         }
2806
2807         priv_sl2 = netdev_priv(ndev);
2808         priv_sl2->cpsw = cpsw;
2809         priv_sl2->ndev = ndev;
2810         priv_sl2->dev  = &ndev->dev;
2811         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2812
2813         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2814                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2815                         ETH_ALEN);
2816                 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
2817                          priv_sl2->mac_addr);
2818         } else {
2819                 random_ether_addr(priv_sl2->mac_addr);
2820                 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
2821                          priv_sl2->mac_addr);
2822         }
2823         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2824
2825         priv_sl2->emac_port = 1;
2826         cpsw->slaves[1].ndev = ndev;
2827         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2828
2829         ndev->netdev_ops = &cpsw_netdev_ops;
2830         ndev->ethtool_ops = &cpsw_ethtool_ops;
2831
2832         /* register the network device */
2833         SET_NETDEV_DEV(ndev, cpsw->dev);
2834         ret = register_netdev(ndev);
2835         if (ret) {
2836                 dev_err(cpsw->dev, "cpsw: error registering net device\n");
2837                 free_netdev(ndev);
2838                 ret = -ENODEV;
2839         }
2840
2841         return ret;
2842 }
2843
2844 #define CPSW_QUIRK_IRQ          BIT(0)
2845
2846 static const struct platform_device_id cpsw_devtype[] = {
2847         {
2848                 /* keep it for existing comaptibles */
2849                 .name = "cpsw",
2850                 .driver_data = CPSW_QUIRK_IRQ,
2851         }, {
2852                 .name = "am335x-cpsw",
2853                 .driver_data = CPSW_QUIRK_IRQ,
2854         }, {
2855                 .name = "am4372-cpsw",
2856                 .driver_data = 0,
2857         }, {
2858                 .name = "dra7-cpsw",
2859                 .driver_data = 0,
2860         }, {
2861                 /* sentinel */
2862         }
2863 };
2864 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2865
2866 enum ti_cpsw_type {
2867         CPSW = 0,
2868         AM335X_CPSW,
2869         AM4372_CPSW,
2870         DRA7_CPSW,
2871 };
2872
2873 static const struct of_device_id cpsw_of_mtable[] = {
2874         { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2875         { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2876         { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2877         { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2878         { /* sentinel */ },
2879 };
2880 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2881
2882 static int cpsw_probe(struct platform_device *pdev)
2883 {
2884         struct clk                      *clk;
2885         struct cpsw_platform_data       *data;
2886         struct net_device               *ndev;
2887         struct cpsw_priv                *priv;
2888         struct cpdma_params             dma_params;
2889         struct cpsw_ale_params          ale_params;
2890         void __iomem                    *ss_regs;
2891         void __iomem                    *cpts_regs;
2892         struct resource                 *res, *ss_res;
2893         const struct of_device_id       *of_id;
2894         struct gpio_descs               *mode;
2895         u32 slave_offset, sliver_offset, slave_size;
2896         struct cpsw_common              *cpsw;
2897         int ret = 0, i;
2898         int irq;
2899
2900         cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
2901         if (!cpsw)
2902                 return -ENOMEM;
2903
2904         cpsw->dev = &pdev->dev;
2905
2906         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2907         if (!ndev) {
2908                 dev_err(&pdev->dev, "error allocating net_device\n");
2909                 return -ENOMEM;
2910         }
2911
2912         platform_set_drvdata(pdev, ndev);
2913         priv = netdev_priv(ndev);
2914         priv->cpsw = cpsw;
2915         priv->ndev = ndev;
2916         priv->dev  = &ndev->dev;
2917         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2918         cpsw->rx_packet_max = max(rx_packet_max, 128);
2919
2920         mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2921         if (IS_ERR(mode)) {
2922                 ret = PTR_ERR(mode);
2923                 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2924                 goto clean_ndev_ret;
2925         }
2926
2927         /*
2928          * This may be required here for child devices.
2929          */
2930         pm_runtime_enable(&pdev->dev);
2931
2932         /* Select default pin state */
2933         pinctrl_pm_select_default_state(&pdev->dev);
2934
2935         /* Need to enable clocks with runtime PM api to access module
2936          * registers
2937          */
2938         ret = pm_runtime_get_sync(&pdev->dev);
2939         if (ret < 0) {
2940                 pm_runtime_put_noidle(&pdev->dev);
2941                 goto clean_runtime_disable_ret;
2942         }
2943
2944         ret = cpsw_probe_dt(&cpsw->data, pdev);
2945         if (ret)
2946                 goto clean_dt_ret;
2947
2948         data = &cpsw->data;
2949         cpsw->rx_ch_num = 1;
2950         cpsw->tx_ch_num = 1;
2951
2952         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2953                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2954                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2955         } else {
2956                 eth_random_addr(priv->mac_addr);
2957                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2958         }
2959
2960         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2961
2962         cpsw->slaves = devm_kzalloc(&pdev->dev,
2963                                     sizeof(struct cpsw_slave) * data->slaves,
2964                                     GFP_KERNEL);
2965         if (!cpsw->slaves) {
2966                 ret = -ENOMEM;
2967                 goto clean_dt_ret;
2968         }
2969         for (i = 0; i < data->slaves; i++)
2970                 cpsw->slaves[i].slave_num = i;
2971
2972         cpsw->slaves[0].ndev = ndev;
2973         priv->emac_port = 0;
2974
2975         clk = devm_clk_get(&pdev->dev, "fck");
2976         if (IS_ERR(clk)) {
2977                 dev_err(priv->dev, "fck is not found\n");
2978                 ret = -ENODEV;
2979                 goto clean_dt_ret;
2980         }
2981         cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
2982
2983         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2984         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2985         if (IS_ERR(ss_regs)) {
2986                 ret = PTR_ERR(ss_regs);
2987                 goto clean_dt_ret;
2988         }
2989         cpsw->regs = ss_regs;
2990
2991         cpsw->version = readl(&cpsw->regs->id_ver);
2992
2993         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2994         cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2995         if (IS_ERR(cpsw->wr_regs)) {
2996                 ret = PTR_ERR(cpsw->wr_regs);
2997                 goto clean_dt_ret;
2998         }
2999
3000         memset(&dma_params, 0, sizeof(dma_params));
3001         memset(&ale_params, 0, sizeof(ale_params));
3002
3003         switch (cpsw->version) {
3004         case CPSW_VERSION_1:
3005                 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
3006                 cpts_regs               = ss_regs + CPSW1_CPTS_OFFSET;
3007                 cpsw->hw_stats       = ss_regs + CPSW1_HW_STATS;
3008                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
3009                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
3010                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
3011                 slave_offset         = CPSW1_SLAVE_OFFSET;
3012                 slave_size           = CPSW1_SLAVE_SIZE;
3013                 sliver_offset        = CPSW1_SLIVER_OFFSET;
3014                 dma_params.desc_mem_phys = 0;
3015                 break;
3016         case CPSW_VERSION_2:
3017         case CPSW_VERSION_3:
3018         case CPSW_VERSION_4:
3019                 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
3020                 cpts_regs               = ss_regs + CPSW2_CPTS_OFFSET;
3021                 cpsw->hw_stats       = ss_regs + CPSW2_HW_STATS;
3022                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
3023                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
3024                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
3025                 slave_offset         = CPSW2_SLAVE_OFFSET;
3026                 slave_size           = CPSW2_SLAVE_SIZE;
3027                 sliver_offset        = CPSW2_SLIVER_OFFSET;
3028                 dma_params.desc_mem_phys =
3029                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
3030                 break;
3031         default:
3032                 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
3033                 ret = -ENODEV;
3034                 goto clean_dt_ret;
3035         }
3036         for (i = 0; i < cpsw->data.slaves; i++) {
3037                 struct cpsw_slave *slave = &cpsw->slaves[i];
3038
3039                 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
3040                 slave_offset  += slave_size;
3041                 sliver_offset += SLIVER_SIZE;
3042         }
3043
3044         dma_params.dev          = &pdev->dev;
3045         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
3046         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
3047         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
3048         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
3049         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
3050
3051         dma_params.num_chan             = data->channels;
3052         dma_params.has_soft_reset       = true;
3053         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
3054         dma_params.desc_mem_size        = data->bd_ram_size;
3055         dma_params.desc_align           = 16;
3056         dma_params.has_ext_regs         = true;
3057         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
3058         dma_params.bus_freq_mhz         = cpsw->bus_freq_mhz;
3059         dma_params.descs_pool_size      = descs_pool_size;
3060
3061         cpsw->dma = cpdma_ctlr_create(&dma_params);
3062         if (!cpsw->dma) {
3063                 dev_err(priv->dev, "error initializing dma\n");
3064                 ret = -ENOMEM;
3065                 goto clean_dt_ret;
3066         }
3067
3068         cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0);
3069         cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
3070         if (WARN_ON(!cpsw->rxv[0].ch || !cpsw->txv[0].ch)) {
3071                 dev_err(priv->dev, "error initializing dma channels\n");
3072                 ret = -ENOMEM;
3073                 goto clean_dma_ret;
3074         }
3075
3076         ale_params.dev                  = &pdev->dev;
3077         ale_params.ale_ageout           = ale_ageout;
3078         ale_params.ale_entries          = data->ale_entries;
3079         ale_params.ale_ports            = data->slaves;
3080
3081         cpsw->ale = cpsw_ale_create(&ale_params);
3082         if (!cpsw->ale) {
3083                 dev_err(priv->dev, "error initializing ale engine\n");
3084                 ret = -ENODEV;
3085                 goto clean_dma_ret;
3086         }
3087
3088         cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node);
3089         if (IS_ERR(cpsw->cpts)) {
3090                 ret = PTR_ERR(cpsw->cpts);
3091                 goto clean_ale_ret;
3092         }
3093
3094         ndev->irq = platform_get_irq(pdev, 1);
3095         if (ndev->irq < 0) {
3096                 dev_err(priv->dev, "error getting irq resource\n");
3097                 ret = ndev->irq;
3098                 goto clean_ale_ret;
3099         }
3100
3101         of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
3102         if (of_id) {
3103                 pdev->id_entry = of_id->data;
3104                 if (pdev->id_entry->driver_data)
3105                         cpsw->quirk_irq = true;
3106         }
3107
3108         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3109
3110         ndev->netdev_ops = &cpsw_netdev_ops;
3111         ndev->ethtool_ops = &cpsw_ethtool_ops;
3112         netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
3113         netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
3114         cpsw_split_res(ndev);
3115
3116         /* register the network device */
3117         SET_NETDEV_DEV(ndev, &pdev->dev);
3118         ret = register_netdev(ndev);
3119         if (ret) {
3120                 dev_err(priv->dev, "error registering net device\n");
3121                 ret = -ENODEV;
3122                 goto clean_ale_ret;
3123         }
3124
3125         if (cpsw->data.dual_emac) {
3126                 ret = cpsw_probe_dual_emac(priv);
3127                 if (ret) {
3128                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
3129                         goto clean_unregister_netdev_ret;
3130                 }
3131         }
3132
3133         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
3134          * MISC IRQs which are always kept disabled with this driver so
3135          * we will not request them.
3136          *
3137          * If anyone wants to implement support for those, make sure to
3138          * first request and append them to irqs_table array.
3139          */
3140
3141         /* RX IRQ */
3142         irq = platform_get_irq(pdev, 1);
3143         if (irq < 0) {
3144                 ret = irq;
3145                 goto clean_ale_ret;
3146         }
3147
3148         cpsw->irqs_table[0] = irq;
3149         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
3150                                0, dev_name(&pdev->dev), cpsw);
3151         if (ret < 0) {
3152                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3153                 goto clean_ale_ret;
3154         }
3155
3156         /* TX IRQ */
3157         irq = platform_get_irq(pdev, 2);
3158         if (irq < 0) {
3159                 ret = irq;
3160                 goto clean_ale_ret;
3161         }
3162
3163         cpsw->irqs_table[1] = irq;
3164         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
3165                                0, dev_name(&pdev->dev), cpsw);
3166         if (ret < 0) {
3167                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3168                 goto clean_ale_ret;
3169         }
3170
3171         cpsw_notice(priv, probe,
3172                     "initialized device (regs %pa, irq %d, pool size %d)\n",
3173                     &ss_res->start, ndev->irq, dma_params.descs_pool_size);
3174
3175         pm_runtime_put(&pdev->dev);
3176
3177         return 0;
3178
3179 clean_unregister_netdev_ret:
3180         unregister_netdev(ndev);
3181 clean_ale_ret:
3182         cpsw_ale_destroy(cpsw->ale);
3183 clean_dma_ret:
3184         cpdma_ctlr_destroy(cpsw->dma);
3185 clean_dt_ret:
3186         cpsw_remove_dt(pdev);
3187         pm_runtime_put_sync(&pdev->dev);
3188 clean_runtime_disable_ret:
3189         pm_runtime_disable(&pdev->dev);
3190 clean_ndev_ret:
3191         free_netdev(priv->ndev);
3192         return ret;
3193 }
3194
3195 static int cpsw_remove(struct platform_device *pdev)
3196 {
3197         struct net_device *ndev = platform_get_drvdata(pdev);
3198         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3199         int ret;
3200
3201         ret = pm_runtime_get_sync(&pdev->dev);
3202         if (ret < 0) {
3203                 pm_runtime_put_noidle(&pdev->dev);
3204                 return ret;
3205         }
3206
3207         if (cpsw->data.dual_emac)
3208                 unregister_netdev(cpsw->slaves[1].ndev);
3209         unregister_netdev(ndev);
3210
3211         cpts_release(cpsw->cpts);
3212         cpsw_ale_destroy(cpsw->ale);
3213         cpdma_ctlr_destroy(cpsw->dma);
3214         cpsw_remove_dt(pdev);
3215         pm_runtime_put_sync(&pdev->dev);
3216         pm_runtime_disable(&pdev->dev);
3217         if (cpsw->data.dual_emac)
3218                 free_netdev(cpsw->slaves[1].ndev);
3219         free_netdev(ndev);
3220         return 0;
3221 }
3222
3223 #ifdef CONFIG_PM_SLEEP
3224 static int cpsw_suspend(struct device *dev)
3225 {
3226         struct platform_device  *pdev = to_platform_device(dev);
3227         struct net_device       *ndev = platform_get_drvdata(pdev);
3228         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
3229
3230         if (cpsw->data.dual_emac) {
3231                 int i;
3232
3233                 for (i = 0; i < cpsw->data.slaves; i++) {
3234                         if (netif_running(cpsw->slaves[i].ndev))
3235                                 cpsw_ndo_stop(cpsw->slaves[i].ndev);
3236                 }
3237         } else {
3238                 if (netif_running(ndev))
3239                         cpsw_ndo_stop(ndev);
3240         }
3241
3242         /* Select sleep pin state */
3243         pinctrl_pm_select_sleep_state(dev);
3244
3245         return 0;
3246 }
3247
3248 static int cpsw_resume(struct device *dev)
3249 {
3250         struct platform_device  *pdev = to_platform_device(dev);
3251         struct net_device       *ndev = platform_get_drvdata(pdev);
3252         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
3253
3254         /* Select default pin state */
3255         pinctrl_pm_select_default_state(dev);
3256
3257         /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
3258         rtnl_lock();
3259         if (cpsw->data.dual_emac) {
3260                 int i;
3261
3262                 for (i = 0; i < cpsw->data.slaves; i++) {
3263                         if (netif_running(cpsw->slaves[i].ndev))
3264                                 cpsw_ndo_open(cpsw->slaves[i].ndev);
3265                 }
3266         } else {
3267                 if (netif_running(ndev))
3268                         cpsw_ndo_open(ndev);
3269         }
3270         rtnl_unlock();
3271
3272         return 0;
3273 }
3274 #endif
3275
3276 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
3277
3278 static struct platform_driver cpsw_driver = {
3279         .driver = {
3280                 .name    = "cpsw",
3281                 .pm      = &cpsw_pm_ops,
3282                 .of_match_table = cpsw_of_mtable,
3283         },
3284         .probe = cpsw_probe,
3285         .remove = cpsw_remove,
3286 };
3287
3288 module_platform_driver(cpsw_driver);
3289
3290 MODULE_LICENSE("GPL");
3291 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
3292 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
3293 MODULE_DESCRIPTION("TI CPSW Ethernet driver");