1 // SPDX-License-Identifier: GPL-2.0
2 /* Texas Instruments Ethernet Switch Driver
4 * Copyright (C) 2013 Texas Instruments
6 * Module Author: Mugunthan V N <mugunthanvnm@ti.com>
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/netdevice.h>
13 #include <linux/phy.h>
18 /* AM33xx SoC specific definitions for the CONTROL port */
19 #define AM33XX_GMII_SEL_MODE_MII 0
20 #define AM33XX_GMII_SEL_MODE_RMII 1
21 #define AM33XX_GMII_SEL_MODE_RGMII 2
23 #define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
24 #define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
25 #define AM33XX_GMII_SEL_RGMII2_IDMODE BIT(5)
26 #define AM33XX_GMII_SEL_RGMII1_IDMODE BIT(4)
28 #define GMII_SEL_MODE_MASK 0x3
30 struct cpsw_phy_sel_priv {
32 u32 __iomem *gmii_sel;
33 bool rmii_clock_external;
34 void (*cpsw_phy_sel)(struct cpsw_phy_sel_priv *priv,
35 phy_interface_t phy_mode, int slave);
39 static void cpsw_gmii_sel_am3352(struct cpsw_phy_sel_priv *priv,
40 phy_interface_t phy_mode, int slave)
45 bool rgmii_id = false;
47 reg = readl(priv->gmii_sel);
50 case PHY_INTERFACE_MODE_RMII:
51 mode = AM33XX_GMII_SEL_MODE_RMII;
54 case PHY_INTERFACE_MODE_RGMII:
55 mode = AM33XX_GMII_SEL_MODE_RGMII;
58 case PHY_INTERFACE_MODE_RGMII_ID:
59 case PHY_INTERFACE_MODE_RGMII_RXID:
60 case PHY_INTERFACE_MODE_RGMII_TXID:
61 mode = AM33XX_GMII_SEL_MODE_RGMII;
67 "Unsupported PHY mode: \"%s\". Defaulting to MII.\n",
70 case PHY_INTERFACE_MODE_MII:
71 mode = AM33XX_GMII_SEL_MODE_MII;
75 mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
76 mask |= BIT(slave + 4);
79 if (priv->rmii_clock_external) {
81 mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
83 mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
88 mode |= AM33XX_GMII_SEL_RGMII1_IDMODE;
90 mode |= AM33XX_GMII_SEL_RGMII2_IDMODE;
96 writel(reg, priv->gmii_sel);
99 static void cpsw_gmii_sel_dra7xx(struct cpsw_phy_sel_priv *priv,
100 phy_interface_t phy_mode, int slave)
106 reg = readl(priv->gmii_sel);
109 case PHY_INTERFACE_MODE_RMII:
110 mode = AM33XX_GMII_SEL_MODE_RMII;
113 case PHY_INTERFACE_MODE_RGMII:
114 case PHY_INTERFACE_MODE_RGMII_ID:
115 case PHY_INTERFACE_MODE_RGMII_RXID:
116 case PHY_INTERFACE_MODE_RGMII_TXID:
117 mode = AM33XX_GMII_SEL_MODE_RGMII;
122 "Unsupported PHY mode: \"%s\". Defaulting to MII.\n",
123 phy_modes(phy_mode));
125 case PHY_INTERFACE_MODE_MII:
126 mode = AM33XX_GMII_SEL_MODE_MII;
132 mask = GMII_SEL_MODE_MASK;
135 mask = GMII_SEL_MODE_MASK << 4;
139 dev_err(priv->dev, "invalid slave number...\n");
143 if (priv->rmii_clock_external)
144 dev_err(priv->dev, "RMII External clock is not supported\n");
149 writel(reg, priv->gmii_sel);
152 static struct platform_driver cpsw_phy_sel_driver;
153 static int match(struct device *dev, const void *data)
155 const struct device_node *node = (const struct device_node *)data;
156 return dev->of_node == node &&
157 dev->driver == &cpsw_phy_sel_driver.driver;
160 void cpsw_phy_sel(struct device *dev, phy_interface_t phy_mode, int slave)
162 struct device_node *node;
163 struct cpsw_phy_sel_priv *priv;
165 node = of_parse_phandle(dev->of_node, "cpsw-phy-sel", 0);
167 node = of_get_child_by_name(dev->of_node, "cpsw-phy-sel");
169 dev_err(dev, "Phy mode driver DT not found\n");
174 dev = bus_find_device(&platform_bus_type, NULL, node, match);
176 dev_err(dev, "unable to find platform device for %pOF\n", node);
180 priv = dev_get_drvdata(dev);
182 priv->cpsw_phy_sel(priv, phy_mode, slave);
188 EXPORT_SYMBOL_GPL(cpsw_phy_sel);
190 static const struct of_device_id cpsw_phy_sel_id_table[] = {
192 .compatible = "ti,am3352-cpsw-phy-sel",
193 .data = &cpsw_gmii_sel_am3352,
196 .compatible = "ti,dra7xx-cpsw-phy-sel",
197 .data = &cpsw_gmii_sel_dra7xx,
200 .compatible = "ti,am43xx-cpsw-phy-sel",
201 .data = &cpsw_gmii_sel_am3352,
206 static int cpsw_phy_sel_probe(struct platform_device *pdev)
208 const struct of_device_id *of_id;
209 struct cpsw_phy_sel_priv *priv;
211 of_id = of_match_node(cpsw_phy_sel_id_table, pdev->dev.of_node);
215 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
217 dev_err(&pdev->dev, "unable to alloc memory for cpsw phy sel\n");
221 priv->dev = &pdev->dev;
222 priv->cpsw_phy_sel = of_id->data;
224 priv->gmii_sel = devm_platform_ioremap_resource_byname(pdev, "gmii-sel");
225 if (IS_ERR(priv->gmii_sel))
226 return PTR_ERR(priv->gmii_sel);
228 priv->rmii_clock_external = of_property_read_bool(pdev->dev.of_node, "rmii-clock-ext");
230 dev_set_drvdata(&pdev->dev, priv);
235 static struct platform_driver cpsw_phy_sel_driver = {
236 .probe = cpsw_phy_sel_probe,
238 .name = "cpsw-phy-sel",
239 .of_match_table = cpsw_phy_sel_id_table,
242 builtin_platform_driver(cpsw_phy_sel_driver);