drivers/net/ethernet/ti/am65-cpsw-qos.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
   3  */
   4
   5 #ifndef AM65_CPSW_QOS_H_
   6 #define AM65_CPSW_QOS_H_
   7
   8 #include <linux/netdevice.h>
   9 #include <net/pkt_sched.h>
  10
  11 struct am65_cpsw_common;
  12 struct am65_cpsw_port;
  13
  14 struct am65_cpsw_est {
  15         int buf;
  16         /* has to be the last one */
  17         struct tc_taprio_qopt_offload taprio;
  18 };
  19
  20 struct am65_cpsw_mqprio {
  21         struct tc_mqprio_qopt_offload mqprio_hw;
  22         u64 max_rate_total;
  23         bool shaper_en;
  24 };
  25
  26 struct am65_cpsw_iet {
  27         u8 preemptible_tcs;
  28         u32 original_max_blks;
  29         int verify_time_ms;
  30 };
  31
  32 struct am65_cpsw_ale_ratelimit {
  33         unsigned long cookie;
  34         u64 rate_packet_ps;
  35 };
  36
  37 struct am65_cpsw_qos {
  38         struct am65_cpsw_est *est_admin;
  39         struct am65_cpsw_est *est_oper;
  40         ktime_t link_down_time;
  41         int link_speed;
  42         struct am65_cpsw_mqprio mqprio;
  43         struct am65_cpsw_iet iet;
  44
  45         struct am65_cpsw_ale_ratelimit ale_bc_ratelimit;
  46         struct am65_cpsw_ale_ratelimit ale_mc_ratelimit;
  47 };
  48
  49 #define AM65_CPSW_REG_CTL                       0x004
  50 #define AM65_CPSW_PN_REG_CTL                    0x004
  51 #define AM65_CPSW_PN_REG_FIFO_STATUS            0x050
  52 #define AM65_CPSW_PN_REG_EST_CTL                0x060
  53 #define AM65_CPSW_PN_REG_PRI_CIR(pri)           (0x140 + 4 * (pri))
  54 #define AM65_CPSW_P0_REG_PRI_EIR(pri)           (0x160 + 4 * (pri))
  55
  56 #define AM65_CPSW_PN_REG_CTL                    0x004
  57 #define AM65_CPSW_PN_REG_TX_PRI_MAP             0x018
  58 #define AM65_CPSW_PN_REG_RX_PRI_MAP             0x020
  59 #define AM65_CPSW_PN_REG_FIFO_STATUS            0x050
  60 #define AM65_CPSW_PN_REG_EST_CTL                0x060
  61 #define AM65_CPSW_PN_REG_PRI_CIR(pri)           (0x140 + 4 * (pri))
  62 #define AM65_CPSW_PN_REG_PRI_EIR(pri)           (0x160 + 4 * (pri))
  63
  64 /* AM65_CPSW_REG_CTL register fields */
  65 #define AM65_CPSW_CTL_EST_EN                    BIT(18)
  66
  67 /* AM65_CPSW_PN_REG_CTL register fields */
  68 #define AM65_CPSW_PN_CTL_EST_PORT_EN            BIT(17)
  69
  70 /* AM65_CPSW_PN_REG_EST_CTL register fields */
  71 #define AM65_CPSW_PN_EST_ONEBUF                 BIT(0)
  72 #define AM65_CPSW_PN_EST_BUFSEL                 BIT(1)
  73 #define AM65_CPSW_PN_EST_TS_EN                  BIT(2)
  74 #define AM65_CPSW_PN_EST_TS_FIRST               BIT(3)
  75 #define AM65_CPSW_PN_EST_ONEPRI                 BIT(4)
  76 #define AM65_CPSW_PN_EST_TS_PRI_MSK             GENMASK(7, 5)
  77
  78 /* AM65_CPSW_PN_REG_FIFO_STATUS register fields */
  79 #define AM65_CPSW_PN_FST_TX_PRI_ACTIVE_MSK      GENMASK(7, 0)
  80 #define AM65_CPSW_PN_FST_TX_E_MAC_ALLOW_MSK     GENMASK(15, 8)
  81 #define AM65_CPSW_PN_FST_EST_CNT_ERR            BIT(16)
  82 #define AM65_CPSW_PN_FST_EST_ADD_ERR            BIT(17)
  83 #define AM65_CPSW_PN_FST_EST_BUFACT             BIT(18)
  84
  85 /* EST FETCH COMMAND RAM */
  86 #define AM65_CPSW_FETCH_RAM_CMD_NUM             0x80
  87 #define AM65_CPSW_FETCH_CNT_MSK                 GENMASK(21, 8)
  88 #define AM65_CPSW_FETCH_CNT_MAX                 (AM65_CPSW_FETCH_CNT_MSK >> 8)
  89 #define AM65_CPSW_FETCH_CNT_OFFSET              8
  90 #define AM65_CPSW_FETCH_ALLOW_MSK               GENMASK(7, 0)
  91 #define AM65_CPSW_FETCH_ALLOW_MAX               AM65_CPSW_FETCH_ALLOW_MSK
  92
  93 /* number of priority queues per port FIFO */
  94 #define AM65_CPSW_PN_FIFO_PRIO_NUM              8
  95
  96 #if IS_ENABLED(CONFIG_TI_AM65_CPSW_QOS)
  97 int am65_cpsw_qos_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,
  98                                void *type_data);
  99 void am65_cpsw_qos_link_up(struct net_device *ndev, int link_speed);
 100 void am65_cpsw_qos_link_down(struct net_device *ndev);
 101 int am65_cpsw_qos_ndo_tx_p0_set_maxrate(struct net_device *ndev, int queue, u32 rate_mbps);
 102 void am65_cpsw_qos_tx_p0_rate_init(struct am65_cpsw_common *common);
 103 void am65_cpsw_iet_commit_preemptible_tcs(struct am65_cpsw_port *port);
 104 void am65_cpsw_iet_common_enable(struct am65_cpsw_common *common);
 105 #else
 106 static inline int am65_cpsw_qos_ndo_setup_tc(struct net_device *ndev,
 107                                              enum tc_setup_type type,
 108                                              void *type_data)
 109 {
 110         return -EOPNOTSUPP;
 111 }
 112
 113 static inline void am65_cpsw_qos_link_up(struct net_device *ndev,
 114                                          int link_speed)
 115 { }
 116
 117 static inline void am65_cpsw_qos_link_down(struct net_device *ndev)
 118 { }
 119
 120 static inline int am65_cpsw_qos_ndo_tx_p0_set_maxrate(struct net_device *ndev,
 121                                                       int queue,
 122                                                       u32 rate_mbps)
 123 {
 124         return 0;
 125 }
 126
 127 static inline void am65_cpsw_qos_tx_p0_rate_init(struct am65_cpsw_common *common)
 128 { }
 129 static inline void am65_cpsw_iet_commit_preemptible_tcs(struct am65_cpsw_port *port)
 130 { }
 131 static inline void am65_cpsw_iet_common_enable(struct am65_cpsw_common *common)
 132 { }
 133 #endif
 134
 135 #define AM65_CPSW_REG_CTL                       0x004
 136 #define AM65_CPSW_PN_REG_CTL                    0x004
 137 #define AM65_CPSW_PN_REG_MAX_BLKS               0x008
 138 #define AM65_CPSW_PN_REG_TX_PRI_MAP             0x018
 139 #define AM65_CPSW_PN_REG_RX_PRI_MAP             0x020
 140 #define AM65_CPSW_PN_REG_IET_CTRL               0x040
 141 #define AM65_CPSW_PN_REG_IET_STATUS             0x044
 142 #define AM65_CPSW_PN_REG_IET_VERIFY             0x048
 143 #define AM65_CPSW_PN_REG_FIFO_STATUS            0x050
 144 #define AM65_CPSW_PN_REG_EST_CTL                0x060
 145 #define AM65_CPSW_PN_REG_PRI_CIR(pri)           (0x140 + 4 * (pri))
 146 #define AM65_CPSW_PN_REG_PRI_EIR(pri)           (0x160 + 4 * (pri))
 147
 148 /* AM65_CPSW_REG_CTL register fields */
 149 #define AM65_CPSW_CTL_IET_EN                    BIT(17)
 150 #define AM65_CPSW_CTL_EST_EN                    BIT(18)
 151
 152 /* AM65_CPSW_PN_REG_CTL register fields */
 153 #define AM65_CPSW_PN_CTL_IET_PORT_EN            BIT(16)
 154 #define AM65_CPSW_PN_CTL_EST_PORT_EN            BIT(17)
 155
 156 /* AM65_CPSW_PN_REG_EST_CTL register fields */
 157 #define AM65_CPSW_PN_EST_ONEBUF                 BIT(0)
 158 #define AM65_CPSW_PN_EST_BUFSEL                 BIT(1)
 159 #define AM65_CPSW_PN_EST_TS_EN                  BIT(2)
 160 #define AM65_CPSW_PN_EST_TS_FIRST               BIT(3)
 161 #define AM65_CPSW_PN_EST_ONEPRI                 BIT(4)
 162 #define AM65_CPSW_PN_EST_TS_PRI_MSK             GENMASK(7, 5)
 163
 164 /* AM65_CPSW_PN_REG_IET_CTRL register fields */
 165 #define AM65_CPSW_PN_IET_MAC_PENABLE            BIT(0)
 166 #define AM65_CPSW_PN_IET_MAC_DISABLEVERIFY      BIT(2)
 167 #define AM65_CPSW_PN_IET_MAC_LINKFAIL           BIT(3)
 168 #define AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_MASK       GENMASK(10, 8)
 169 #define AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_OFFSET     8
 170 #define AM65_CPSW_PN_IET_MAC_PREMPT_MASK                GENMASK(23, 16)
 171 #define AM65_CPSW_PN_IET_MAC_PREMPT_OFFSET              16
 172
 173 #define AM65_CPSW_PN_IET_MAC_SET_ADDFRAGSIZE(n) (((n) << AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_OFFSET) & \
 174                                                   AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_MASK)
 175 #define AM65_CPSW_PN_IET_MAC_GET_ADDFRAGSIZE(n) (((n) & AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_MASK) >> \
 176                                                   AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_OFFSET)
 177 #define AM65_CPSW_PN_IET_MAC_SET_PREEMPT(n)     (((n) << AM65_CPSW_PN_IET_MAC_PREMPT_OFFSET) & \
 178                                                  AM65_CPSW_PN_IET_MAC_PREMPT_MASK)
 179 #define AM65_CPSW_PN_IET_MAC_GET_PREEMPT(n)     (((n) & AM65_CPSW_PN_IET_MAC_PREMPT_MASK) >> \
 180                                                  AM65_CPSW_PN_IET_MAC_PREMPT_OFFSET)
 181
 182 /* AM65_CPSW_PN_REG_IET_STATUS register fields */
 183 #define AM65_CPSW_PN_MAC_STATUS                 GENMASK(3, 0)
 184 #define AM65_CPSW_PN_MAC_VERIFIED               BIT(0)
 185 #define AM65_CPSW_PN_MAC_VERIFY_FAIL            BIT(1)
 186 #define AM65_CPSW_PN_MAC_RESPOND_ERR            BIT(2)
 187 #define AM65_CPSW_PN_MAC_VERIFY_ERR             BIT(3)
 188
 189 /* AM65_CPSW_PN_REG_IET_VERIFY register fields */
 190 #define AM65_CPSW_PN_MAC_VERIFY_CNT_MASK        GENMASK(23, 0)
 191 #define AM65_CPSW_PN_MAC_GET_VERIFY_CNT(n)      ((n) & AM65_CPSW_PN_MAC_VERIFY_CNT_MASK)
 192 /* 10 msec converted to NSEC */
 193 #define AM65_CPSW_IET_VERIFY_CNT_MS             (10)
 194 #define AM65_CPSW_IET_VERIFY_CNT_NS             (AM65_CPSW_IET_VERIFY_CNT_MS * \
 195                                                  NSEC_PER_MSEC)
 196
 197 /* AM65_CPSW_PN_REG_FIFO_STATUS register fields */
 198 #define AM65_CPSW_PN_FST_TX_PRI_ACTIVE_MSK      GENMASK(7, 0)
 199 #define AM65_CPSW_PN_FST_TX_E_MAC_ALLOW_MSK     GENMASK(15, 8)
 200 #define AM65_CPSW_PN_FST_EST_CNT_ERR            BIT(16)
 201 #define AM65_CPSW_PN_FST_EST_ADD_ERR            BIT(17)
 202 #define AM65_CPSW_PN_FST_EST_BUFACT             BIT(18)
 203
 204 /* EST FETCH COMMAND RAM */
 205 #define AM65_CPSW_FETCH_RAM_CMD_NUM             0x80
 206 #define AM65_CPSW_FETCH_CNT_MSK                 GENMASK(21, 8)
 207 #define AM65_CPSW_FETCH_CNT_MAX                 (AM65_CPSW_FETCH_CNT_MSK >> 8)
 208 #define AM65_CPSW_FETCH_CNT_OFFSET              8
 209 #define AM65_CPSW_FETCH_ALLOW_MSK               GENMASK(7, 0)
 210 #define AM65_CPSW_FETCH_ALLOW_MAX               AM65_CPSW_FETCH_ALLOW_MSK
 211
 212 /* AM65_CPSW_PN_REG_MAX_BLKS fields for IET and No IET cases */
 213 /* 7 blocks for pn_rx_max_blks, 13 for pn_tx_max_blks*/
 214 #define AM65_CPSW_PN_TX_RX_MAX_BLKS_IET         0xD07
 215
 216 /* Slave IET Stats. register offsets */
 217 #define AM65_CPSW_STATN_IET_RX_ASSEMBLY_ERROR   0x140
 218 #define AM65_CPSW_STATN_IET_RX_ASSEMBLY_OK      0x144
 219 #define AM65_CPSW_STATN_IET_RX_SMD_ERROR        0x148
 220 #define AM65_CPSW_STATN_IET_RX_FRAG             0x14c
 221 #define AM65_CPSW_STATN_IET_TX_HOLD             0x150
 222 #define AM65_CPSW_STATN_IET_TX_FRAG             0x154
 223
 224 /* number of priority queues per port FIFO */
 225 #define AM65_CPSW_PN_FIFO_PRIO_NUM              8
 226
 227 #endif /* AM65_CPSW_QOS_H_ */