1 // SPDX-License-Identifier: GPL-2.0
2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
9 #include <linux/etherdevice.h>
10 #include <linux/if_vlan.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel.h>
13 #include <linux/kmemleak.h>
14 #include <linux/module.h>
15 #include <linux/netdevice.h>
16 #include <linux/net_tstamp.h>
18 #include <linux/of_mdio.h>
19 #include <linux/of_net.h>
20 #include <linux/of_device.h>
21 #include <linux/phy.h>
22 #include <linux/phy/phy.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/regmap.h>
26 #include <linux/mfd/syscon.h>
27 #include <linux/sys_soc.h>
28 #include <linux/dma/ti-cppi5.h>
29 #include <linux/dma/k3-udma-glue.h>
33 #include "am65-cpsw-nuss.h"
34 #include "k3-cppi-desc-pool.h"
35 #include "am65-cpts.h"
37 #define AM65_CPSW_SS_BASE 0x0
38 #define AM65_CPSW_SGMII_BASE 0x100
39 #define AM65_CPSW_XGMII_BASE 0x2100
40 #define AM65_CPSW_CPSW_NU_BASE 0x20000
41 #define AM65_CPSW_NU_PORTS_BASE 0x1000
42 #define AM65_CPSW_NU_FRAM_BASE 0x12000
43 #define AM65_CPSW_NU_STATS_BASE 0x1a000
44 #define AM65_CPSW_NU_ALE_BASE 0x1e000
45 #define AM65_CPSW_NU_CPTS_BASE 0x1d000
47 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000
48 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200
49 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200
51 #define AM65_CPSW_MAX_PORTS 8
53 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN
54 #define AM65_CPSW_MAX_PACKET_SIZE 2024
56 #define AM65_CPSW_REG_CTL 0x004
57 #define AM65_CPSW_REG_STAT_PORT_EN 0x014
58 #define AM65_CPSW_REG_PTYPE 0x018
60 #define AM65_CPSW_P0_REG_CTL 0x004
61 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008
63 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c
64 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020
65 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024
67 #define AM65_CPSW_PORTN_REG_SA_L 0x308
68 #define AM65_CPSW_PORTN_REG_SA_H 0x30c
69 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310
70 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314
71 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318
72 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C
74 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1)
75 #define AM65_CPSW_CTL_P0_ENABLE BIT(2)
76 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13)
77 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14)
79 /* AM65_CPSW_P0_REG_CTL */
80 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0)
82 /* AM65_CPSW_PORT_REG_PRI_CTL */
83 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8)
85 /* AM65_CPSW_PN_TS_CTL register fields */
86 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4)
87 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5)
88 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6)
89 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7)
90 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10)
91 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11)
92 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16
94 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */
95 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16
97 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */
98 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16)
99 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17)
100 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18)
101 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19)
102 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20)
103 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21)
104 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22)
105 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23)
107 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
108 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3))
110 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e)
112 #define AM65_CPSW_TS_TX_ANX_ALL_EN \
113 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \
114 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \
115 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN)
117 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30
118 /* Number of TX/RX descriptors */
119 #define AM65_CPSW_MAX_TX_DESC 500
120 #define AM65_CPSW_MAX_RX_DESC 500
122 #define AM65_CPSW_NAV_PS_DATA_SIZE 16
123 #define AM65_CPSW_NAV_SW_DATA_SIZE 16
125 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \
126 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \
127 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
129 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave,
132 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) |
133 (dev_addr[2] << 16) | (dev_addr[3] << 24);
134 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8);
136 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H);
137 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L);
140 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port)
142 cpsw_sl_reset(port->slave.mac_sl, 100);
143 /* Max length register has to be restored after MAC SL reset */
144 writel(AM65_CPSW_MAX_PACKET_SIZE,
145 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN);
148 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common)
150 common->nuss_ver = readl(common->ss_base);
151 common->cpsw_ver = readl(common->cpsw_base);
152 dev_info(common->dev,
153 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n",
156 common->port_num + 1,
157 common->pdata.quirks);
160 void am65_cpsw_nuss_adjust_link(struct net_device *ndev)
162 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
163 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
164 struct phy_device *phy = port->slave.phy;
171 mac_control = CPSW_SL_CTL_GMII_EN;
173 if (phy->speed == 1000)
174 mac_control |= CPSW_SL_CTL_GIG;
175 if (phy->speed == 10 && phy_interface_is_rgmii(phy))
176 /* Can be used with in band mode only */
177 mac_control |= CPSW_SL_CTL_EXT_EN;
178 if (phy->speed == 100 && phy->interface == PHY_INTERFACE_MODE_RMII)
179 mac_control |= CPSW_SL_CTL_IFCTL_A;
181 mac_control |= CPSW_SL_CTL_FULLDUPLEX;
183 /* RGMII speed is 100M if !CPSW_SL_CTL_GIG*/
185 /* rx_pause/tx_pause */
186 if (port->slave.rx_pause)
187 mac_control |= CPSW_SL_CTL_RX_FLOW_EN;
189 if (port->slave.tx_pause)
190 mac_control |= CPSW_SL_CTL_TX_FLOW_EN;
192 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control);
194 /* enable forwarding */
195 cpsw_ale_control_set(common->ale, port->port_id,
196 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
198 am65_cpsw_qos_link_up(ndev, phy->speed);
199 netif_tx_wake_all_queues(ndev);
203 /* disable forwarding */
204 cpsw_ale_control_set(common->ale, port->port_id,
205 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
207 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE);
209 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100);
210 dev_dbg(common->dev, "donw msc_sl %08x tmo %d\n",
211 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS),
214 cpsw_sl_ctl_reset(port->slave.mac_sl);
216 am65_cpsw_qos_link_down(ndev);
217 netif_tx_stop_all_queues(ndev);
220 phy_print_status(phy);
223 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev,
224 __be16 proto, u16 vid)
226 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
227 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
228 u32 port_mask, unreg_mcast = 0;
231 if (!netif_running(ndev) || !vid)
234 ret = pm_runtime_get_sync(common->dev);
236 pm_runtime_put_noidle(common->dev);
240 port_mask = BIT(port->port_id) | ALE_PORT_HOST;
242 unreg_mcast = port_mask;
243 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid);
244 ret = cpsw_ale_add_vlan(common->ale, vid, port_mask,
245 unreg_mcast, port_mask, 0);
247 pm_runtime_put(common->dev);
251 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev,
252 __be16 proto, u16 vid)
254 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
257 if (!netif_running(ndev) || !vid)
260 ret = pm_runtime_get_sync(common->dev);
262 pm_runtime_put_noidle(common->dev);
266 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid);
267 ret = cpsw_ale_del_vlan(common->ale, vid, 0);
269 pm_runtime_put(common->dev);
273 static void am65_cpsw_slave_set_promisc_2g(struct am65_cpsw_port *port,
276 struct am65_cpsw_common *common = port->common;
279 /* Enable promiscuous mode */
280 cpsw_ale_control_set(common->ale, port->port_id,
281 ALE_PORT_MACONLY_CAF, 1);
282 dev_dbg(common->dev, "promisc enabled\n");
284 /* Disable promiscuous mode */
285 cpsw_ale_control_set(common->ale, port->port_id,
286 ALE_PORT_MACONLY_CAF, 0);
287 dev_dbg(common->dev, "promisc disabled\n");
291 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev)
293 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
294 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
298 promisc = !!(ndev->flags & IFF_PROMISC);
299 am65_cpsw_slave_set_promisc_2g(port, promisc);
304 /* Restore allmulti on vlans if necessary */
305 cpsw_ale_set_allmulti(common->ale,
306 ndev->flags & IFF_ALLMULTI, port->port_id);
308 port_mask = ALE_PORT_HOST;
309 /* Clear all mcast from ALE */
310 cpsw_ale_flush_multicast(common->ale, port_mask, -1);
312 if (!netdev_mc_empty(ndev)) {
313 struct netdev_hw_addr *ha;
315 /* program multicast address list into ALE register */
316 netdev_for_each_mc_addr(ha, ndev) {
317 cpsw_ale_add_mcast(common->ale, ha->addr,
323 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev,
324 unsigned int txqueue)
326 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
327 struct am65_cpsw_tx_chn *tx_chn;
328 struct netdev_queue *netif_txq;
329 unsigned long trans_start;
331 netif_txq = netdev_get_tx_queue(ndev, txqueue);
332 tx_chn = &common->tx_chns[txqueue];
333 trans_start = netif_txq->trans_start;
335 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n",
337 netif_tx_queue_stopped(netif_txq),
338 jiffies_to_msecs(jiffies - trans_start),
339 dql_avail(&netif_txq->dql),
340 k3_cppi_desc_pool_avail(tx_chn->desc_pool));
342 if (netif_tx_queue_stopped(netif_txq)) {
343 /* try recover if stopped by us */
344 txq_trans_update(netif_txq);
345 netif_tx_wake_queue(netif_txq);
349 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common,
352 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns;
353 struct cppi5_host_desc_t *desc_rx;
354 struct device *dev = common->dev;
355 u32 pkt_len = skb_tailroom(skb);
360 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool);
362 dev_err(dev, "Failed to allocate RXFDQ descriptor\n");
365 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx);
367 buf_dma = dma_map_single(dev, skb->data, pkt_len, DMA_FROM_DEVICE);
368 if (unlikely(dma_mapping_error(dev, buf_dma))) {
369 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx);
370 dev_err(dev, "Failed to map rx skb buffer\n");
374 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT,
375 AM65_CPSW_NAV_PS_DATA_SIZE);
376 cppi5_hdesc_attach_buf(desc_rx, 0, 0, buf_dma, skb_tailroom(skb));
377 swdata = cppi5_hdesc_get_swdata(desc_rx);
378 *((void **)swdata) = skb;
380 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma);
383 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common)
385 struct am65_cpsw_host *host_p = am65_common_get_host(common);
388 /* P0 set Receive Priority Type */
389 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL);
391 if (common->pf_p0_rx_ptype_rrobin) {
392 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN;
393 /* Enet Ports fifos works in fixed priority mode only, so
394 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0
398 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN;
399 /* restore P0_Rx_Pri_Map */
400 pri_map = 0x76543210;
403 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP);
404 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL);
407 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common,
408 netdev_features_t features)
410 struct am65_cpsw_host *host_p = am65_common_get_host(common);
411 int port_idx, i, ret;
415 if (common->usage_count)
418 /* Control register */
419 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE |
420 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD,
421 common->cpsw_base + AM65_CPSW_REG_CTL);
422 /* Max length register */
423 writel(AM65_CPSW_MAX_PACKET_SIZE,
424 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN);
425 /* set base flow_id */
426 writel(common->rx_flow_id_base,
427 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET);
428 /* en tx crc offload */
429 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN, host_p->port_base + AM65_CPSW_P0_REG_CTL);
431 am65_cpsw_nuss_set_p0_ptype(common);
433 /* enable statistic */
434 val = BIT(HOST_PORT_NUM);
435 for (port_idx = 0; port_idx < common->port_num; port_idx++) {
436 struct am65_cpsw_port *port = &common->ports[port_idx];
439 val |= BIT(port->port_id);
441 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN);
443 /* disable priority elevation */
444 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE);
446 cpsw_ale_start(common->ale);
448 /* limit to one RX flow only */
449 cpsw_ale_control_set(common->ale, HOST_PORT_NUM,
450 ALE_DEFAULT_THREAD_ID, 0);
451 cpsw_ale_control_set(common->ale, HOST_PORT_NUM,
452 ALE_DEFAULT_THREAD_ENABLE, 1);
453 if (AM65_CPSW_IS_CPSW2G(common))
454 cpsw_ale_control_set(common->ale, HOST_PORT_NUM,
455 ALE_PORT_NOLEARN, 1);
456 /* switch to vlan unaware mode */
457 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1);
458 cpsw_ale_control_set(common->ale, HOST_PORT_NUM,
459 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
461 /* default vlan cfg: create mask based on enabled ports */
462 port_mask = GENMASK(common->port_num, 0) &
463 ~common->disabled_ports_mask;
465 cpsw_ale_add_vlan(common->ale, 0, port_mask,
466 port_mask, port_mask,
467 port_mask & ~ALE_PORT_HOST);
469 for (i = 0; i < common->rx_chns.descs_num; i++) {
470 skb = __netdev_alloc_skb_ip_align(NULL,
471 AM65_CPSW_MAX_PACKET_SIZE,
474 dev_err(common->dev, "cannot allocate skb\n");
478 ret = am65_cpsw_nuss_rx_push(common, skb);
481 "cannot submit skb to channel rx, error %d\n",
486 kmemleak_not_leak(skb);
488 k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn);
490 for (i = 0; i < common->tx_ch_num; i++) {
491 ret = k3_udma_glue_enable_tx_chn(common->tx_chns[i].tx_chn);
494 napi_enable(&common->tx_chns[i].napi_tx);
497 napi_enable(&common->napi_rx);
499 dev_dbg(common->dev, "cpsw_nuss started\n");
503 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma);
504 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma);
506 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common)
510 if (common->usage_count != 1)
513 cpsw_ale_control_set(common->ale, HOST_PORT_NUM,
514 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
516 /* shutdown tx channels */
517 atomic_set(&common->tdown_cnt, common->tx_ch_num);
518 /* ensure new tdown_cnt value is visible */
519 smp_mb__after_atomic();
520 reinit_completion(&common->tdown_complete);
522 for (i = 0; i < common->tx_ch_num; i++)
523 k3_udma_glue_tdown_tx_chn(common->tx_chns[i].tx_chn, false);
525 i = wait_for_completion_timeout(&common->tdown_complete,
526 msecs_to_jiffies(1000));
528 dev_err(common->dev, "tx timeout\n");
529 for (i = 0; i < common->tx_ch_num; i++)
530 napi_disable(&common->tx_chns[i].napi_tx);
532 for (i = 0; i < common->tx_ch_num; i++) {
533 k3_udma_glue_reset_tx_chn(common->tx_chns[i].tx_chn,
535 am65_cpsw_nuss_tx_cleanup);
536 k3_udma_glue_disable_tx_chn(common->tx_chns[i].tx_chn);
539 k3_udma_glue_tdown_rx_chn(common->rx_chns.rx_chn, true);
540 napi_disable(&common->napi_rx);
542 for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++)
543 k3_udma_glue_reset_rx_chn(common->rx_chns.rx_chn, i,
545 am65_cpsw_nuss_rx_cleanup, !!i);
547 k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn);
549 cpsw_ale_stop(common->ale);
551 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL);
552 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN);
554 dev_dbg(common->dev, "cpsw_nuss stopped\n");
558 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev)
560 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
561 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
565 phy_stop(port->slave.phy);
567 netif_tx_stop_all_queues(ndev);
569 if (port->slave.phy) {
570 phy_disconnect(port->slave.phy);
571 port->slave.phy = NULL;
574 ret = am65_cpsw_nuss_common_stop(common);
578 common->usage_count--;
579 pm_runtime_put(common->dev);
583 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg)
585 struct am65_cpsw_port *port = arg;
590 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid);
593 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev)
595 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
596 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
600 ret = pm_runtime_get_sync(common->dev);
602 pm_runtime_put_noidle(common->dev);
606 /* Notify the stack of the actual queue counts. */
607 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num);
609 dev_err(common->dev, "cannot set real number of tx queues\n");
613 ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES);
615 dev_err(common->dev, "cannot set real number of rx queues\n");
619 for (i = 0; i < common->tx_ch_num; i++)
620 netdev_tx_reset_queue(netdev_get_tx_queue(ndev, i));
622 ret = am65_cpsw_nuss_common_open(common, ndev->features);
626 common->usage_count++;
628 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr);
630 if (port->slave.mac_only)
631 /* enable mac-only mode on port */
632 cpsw_ale_control_set(common->ale, port->port_id,
633 ALE_PORT_MACONLY, 1);
634 if (AM65_CPSW_IS_CPSW2G(common))
635 cpsw_ale_control_set(common->ale, port->port_id,
636 ALE_PORT_NOLEARN, 1);
638 port_mask = BIT(port->port_id) | ALE_PORT_HOST;
639 cpsw_ale_add_ucast(common->ale, ndev->dev_addr,
640 HOST_PORT_NUM, ALE_SECURE, 0);
641 cpsw_ale_add_mcast(common->ale, ndev->broadcast,
642 port_mask, 0, 0, ALE_MCAST_FWD_2);
644 /* mac_sl should be configured via phy-link interface */
645 am65_cpsw_sl_ctl_reset(port);
647 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET,
652 if (port->slave.phy_node) {
653 port->slave.phy = of_phy_connect(ndev,
654 port->slave.phy_node,
655 &am65_cpsw_nuss_adjust_link,
656 0, port->slave.phy_if);
657 if (!port->slave.phy) {
658 dev_err(common->dev, "phy %pOF not found on slave %d\n",
659 port->slave.phy_node,
666 /* restore vlan configurations */
667 vlan_for_each(ndev, cpsw_restore_vlans, port);
669 phy_attached_info(port->slave.phy);
670 phy_start(port->slave.phy);
675 am65_cpsw_nuss_ndo_slave_stop(ndev);
679 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma)
681 struct am65_cpsw_rx_chn *rx_chn = data;
682 struct cppi5_host_desc_t *desc_rx;
688 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma);
689 swdata = cppi5_hdesc_get_swdata(desc_rx);
691 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len);
693 dma_unmap_single(rx_chn->dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE);
694 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx);
696 dev_kfree_skb_any(skb);
699 static void am65_cpsw_nuss_rx_ts(struct sk_buff *skb, u32 *psdata)
701 struct skb_shared_hwtstamps *ssh;
704 ns = ((u64)psdata[1] << 32) | psdata[0];
706 ssh = skb_hwtstamps(skb);
707 memset(ssh, 0, sizeof(*ssh));
708 ssh->hwtstamp = ns_to_ktime(ns);
711 /* RX psdata[2] word format - checksum information */
712 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0)
713 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16)
714 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17)
715 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18)
716 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19)
717 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20)
719 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info)
721 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum
722 * csum information provides in psdata[2] word:
723 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error
724 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID
725 * bits - indicates IPv4/IPv6 packet
726 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet
727 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets
728 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR
730 skb_checksum_none_assert(skb);
732 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM)))
735 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID |
736 AM65_CPSW_RX_PSD_IPV4_VALID)) &&
737 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) {
738 /* csum for fragmented packets is unsupported */
739 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT))
740 skb->ip_summed = CHECKSUM_UNNECESSARY;
744 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common,
747 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns;
748 u32 buf_dma_len, pkt_len, port_id = 0, csum_info;
749 struct am65_cpsw_ndev_priv *ndev_priv;
750 struct am65_cpsw_ndev_stats *stats;
751 struct cppi5_host_desc_t *desc_rx;
752 struct device *dev = common->dev;
753 struct sk_buff *skb, *new_skb;
754 dma_addr_t desc_dma, buf_dma;
755 struct am65_cpsw_port *port;
756 struct net_device *ndev;
761 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma);
764 dev_err(dev, "RX: pop chn fail %d\n", ret);
768 if (desc_dma & 0x1) {
769 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx);
773 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma);
774 dev_dbg(dev, "%s flow_idx: %u desc %pad\n",
775 __func__, flow_idx, &desc_dma);
777 swdata = cppi5_hdesc_get_swdata(desc_rx);
779 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len);
780 pkt_len = cppi5_hdesc_get_pktlen(desc_rx);
781 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL);
782 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id);
783 port = am65_common_get_port(common, port_id);
787 psdata = cppi5_hdesc_get_psdata(desc_rx);
788 /* add RX timestamp */
789 if (port->rx_ts_enabled)
790 am65_cpsw_nuss_rx_ts(skb, psdata);
791 csum_info = psdata[2];
792 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info);
794 dma_unmap_single(dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE);
796 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx);
798 new_skb = netdev_alloc_skb_ip_align(ndev, AM65_CPSW_MAX_PACKET_SIZE);
800 skb_put(skb, pkt_len);
801 skb->protocol = eth_type_trans(skb, ndev);
802 am65_cpsw_nuss_rx_csum(skb, csum_info);
803 napi_gro_receive(&common->napi_rx, skb);
805 ndev_priv = netdev_priv(ndev);
806 stats = this_cpu_ptr(ndev_priv->stats);
808 u64_stats_update_begin(&stats->syncp);
810 stats->rx_bytes += pkt_len;
811 u64_stats_update_end(&stats->syncp);
812 kmemleak_not_leak(new_skb);
814 ndev->stats.rx_dropped++;
818 if (netif_dormant(ndev)) {
819 dev_kfree_skb_any(new_skb);
820 ndev->stats.rx_dropped++;
824 ret = am65_cpsw_nuss_rx_push(common, new_skb);
825 if (WARN_ON(ret < 0)) {
826 dev_kfree_skb_any(new_skb);
827 ndev->stats.rx_errors++;
828 ndev->stats.rx_dropped++;
834 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget)
836 struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx);
837 int flow = AM65_CPSW_MAX_RX_FLOWS;
841 /* process every flow */
843 cur_budget = budget - num_rx;
845 while (cur_budget--) {
846 ret = am65_cpsw_nuss_rx_packets(common, flow);
852 if (num_rx >= budget)
856 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget);
858 if (num_rx < budget && napi_complete_done(napi_rx, num_rx))
859 enable_irq(common->rx_chns.irq);
864 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn,
866 struct cppi5_host_desc_t *desc)
868 struct cppi5_host_desc_t *first_desc, *next_desc;
869 dma_addr_t buf_dma, next_desc_dma;
873 next_desc = first_desc;
875 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len);
877 dma_unmap_single(dev, buf_dma, buf_dma_len,
880 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc);
881 while (next_desc_dma) {
882 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool,
884 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len);
886 dma_unmap_page(dev, buf_dma, buf_dma_len,
889 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc);
891 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc);
894 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc);
897 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma)
899 struct am65_cpsw_tx_chn *tx_chn = data;
900 struct cppi5_host_desc_t *desc_tx;
904 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma);
905 swdata = cppi5_hdesc_get_swdata(desc_tx);
907 am65_cpsw_nuss_xmit_free(tx_chn, tx_chn->common->dev, desc_tx);
909 dev_kfree_skb_any(skb);
912 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common,
913 int chn, unsigned int budget)
915 struct cppi5_host_desc_t *desc_tx;
916 struct device *dev = common->dev;
917 struct am65_cpsw_tx_chn *tx_chn;
918 struct netdev_queue *netif_txq;
919 unsigned int total_bytes = 0;
920 struct net_device *ndev;
926 tx_chn = &common->tx_chns[chn];
929 struct am65_cpsw_ndev_priv *ndev_priv;
930 struct am65_cpsw_ndev_stats *stats;
932 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma);
936 if (desc_dma & 0x1) {
937 if (atomic_dec_and_test(&common->tdown_cnt))
938 complete(&common->tdown_complete);
942 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool,
944 swdata = cppi5_hdesc_get_swdata(desc_tx);
946 am65_cpsw_nuss_xmit_free(tx_chn, dev, desc_tx);
950 am65_cpts_tx_timestamp(common->cpts, skb);
952 ndev_priv = netdev_priv(ndev);
953 stats = this_cpu_ptr(ndev_priv->stats);
954 u64_stats_update_begin(&stats->syncp);
956 stats->tx_bytes += skb->len;
957 u64_stats_update_end(&stats->syncp);
959 total_bytes += skb->len;
960 napi_consume_skb(skb, budget);
967 netif_txq = netdev_get_tx_queue(ndev, chn);
969 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes);
971 if (netif_tx_queue_stopped(netif_txq)) {
972 /* Check whether the queue is stopped due to stalled tx dma,
973 * if the queue is stopped then wake the queue as
974 * we have free desc for tx
976 __netif_tx_lock(netif_txq, smp_processor_id());
977 if (netif_running(ndev) &&
978 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >=
980 netif_tx_wake_queue(netif_txq);
982 __netif_tx_unlock(netif_txq);
984 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx);
989 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget)
991 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx);
994 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, tx_chn->id,
996 num_tx = min(num_tx, budget);
997 if (num_tx < budget) {
998 napi_complete(napi_tx);
999 enable_irq(tx_chn->irq);
1005 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id)
1007 struct am65_cpsw_common *common = dev_id;
1009 disable_irq_nosync(irq);
1010 napi_schedule(&common->napi_rx);
1015 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id)
1017 struct am65_cpsw_tx_chn *tx_chn = dev_id;
1019 disable_irq_nosync(irq);
1020 napi_schedule(&tx_chn->napi_tx);
1025 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb,
1026 struct net_device *ndev)
1028 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
1029 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc;
1030 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1031 struct device *dev = common->dev;
1032 struct am65_cpsw_tx_chn *tx_chn;
1033 struct netdev_queue *netif_txq;
1034 dma_addr_t desc_dma, buf_dma;
1040 /* padding enabled in hw */
1041 pkt_len = skb_headlen(skb);
1043 /* SKB TX timestamp */
1044 if (port->tx_ts_enabled)
1045 am65_cpts_prep_tx_timestamp(common->cpts, skb);
1047 q_idx = skb_get_queue_mapping(skb);
1048 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx);
1050 tx_chn = &common->tx_chns[q_idx];
1051 netif_txq = netdev_get_tx_queue(ndev, q_idx);
1053 /* Map the linear buffer */
1054 buf_dma = dma_map_single(dev, skb->data, pkt_len,
1056 if (unlikely(dma_mapping_error(dev, buf_dma))) {
1057 dev_err(dev, "Failed to map tx skb buffer\n");
1058 ndev->stats.tx_errors++;
1062 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool);
1064 dev_dbg(dev, "Failed to allocate descriptor\n");
1065 dma_unmap_single(dev, buf_dma, pkt_len, DMA_TO_DEVICE);
1069 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT,
1070 AM65_CPSW_NAV_PS_DATA_SIZE);
1071 cppi5_desc_set_pktids(&first_desc->hdr, 0, 0x3FFF);
1072 cppi5_hdesc_set_pkttype(first_desc, 0x7);
1073 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id);
1075 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len);
1076 swdata = cppi5_hdesc_get_swdata(first_desc);
1078 psdata = cppi5_hdesc_get_psdata(first_desc);
1080 /* HW csum offload if enabled */
1082 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1083 unsigned int cs_start, cs_offset;
1085 cs_start = skb_transport_offset(skb);
1086 cs_offset = cs_start + skb->csum_offset;
1087 /* HW numerates bytes starting from 1 */
1088 psdata[2] = ((cs_offset + 1) << 24) |
1089 ((cs_start + 1) << 16) | (skb->len - cs_start);
1090 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]);
1093 if (!skb_is_nonlinear(skb))
1096 dev_dbg(dev, "fragmented SKB\n");
1098 /* Handle the case where skb is fragmented in pages */
1099 cur_desc = first_desc;
1100 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1101 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1102 u32 frag_size = skb_frag_size(frag);
1104 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool);
1106 dev_err(dev, "Failed to allocate descriptor\n");
1107 goto busy_free_descs;
1110 buf_dma = skb_frag_dma_map(dev, frag, 0, frag_size,
1112 if (unlikely(dma_mapping_error(dev, buf_dma))) {
1113 dev_err(dev, "Failed to map tx skb page\n");
1114 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc);
1115 ndev->stats.tx_errors++;
1116 goto err_free_descs;
1119 cppi5_hdesc_reset_hbdesc(next_desc);
1120 cppi5_hdesc_attach_buf(next_desc,
1121 buf_dma, frag_size, buf_dma, frag_size);
1123 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool,
1125 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma);
1127 pkt_len += frag_size;
1128 cur_desc = next_desc;
1130 WARN_ON(pkt_len != skb->len);
1133 skb_tx_timestamp(skb);
1135 /* report bql before sending packet */
1136 netdev_tx_sent_queue(netif_txq, pkt_len);
1138 cppi5_hdesc_set_pktlen(first_desc, pkt_len);
1139 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc);
1140 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma);
1142 dev_err(dev, "can't push desc %d\n", ret);
1144 netdev_tx_completed_queue(netif_txq, 1, pkt_len);
1145 ndev->stats.tx_errors++;
1146 goto err_free_descs;
1149 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) {
1150 netif_tx_stop_queue(netif_txq);
1151 /* Barrier, so that stop_queue visible to other cpus */
1152 smp_mb__after_atomic();
1153 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx);
1155 /* re-check for smp */
1156 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >=
1158 netif_tx_wake_queue(netif_txq);
1159 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx);
1163 return NETDEV_TX_OK;
1166 am65_cpsw_nuss_xmit_free(tx_chn, dev, first_desc);
1168 ndev->stats.tx_dropped++;
1169 dev_kfree_skb_any(skb);
1170 return NETDEV_TX_OK;
1173 am65_cpsw_nuss_xmit_free(tx_chn, dev, first_desc);
1175 netif_tx_stop_queue(netif_txq);
1176 return NETDEV_TX_BUSY;
1179 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev,
1182 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
1183 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1184 struct sockaddr *sockaddr = (struct sockaddr *)addr;
1187 ret = eth_prepare_mac_addr_change(ndev, addr);
1191 ret = pm_runtime_get_sync(common->dev);
1193 pm_runtime_put_noidle(common->dev);
1197 cpsw_ale_del_ucast(common->ale, ndev->dev_addr,
1198 HOST_PORT_NUM, 0, 0);
1199 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data,
1200 HOST_PORT_NUM, ALE_SECURE, 0);
1202 am65_cpsw_port_set_sl_mac(port, addr);
1203 eth_commit_mac_addr_change(ndev, sockaddr);
1205 pm_runtime_put(common->dev);
1210 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev,
1213 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
1214 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1215 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype;
1216 struct hwtstamp_config cfg;
1218 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS))
1221 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1224 /* TX HW timestamp */
1225 switch (cfg.tx_type) {
1226 case HWTSTAMP_TX_OFF:
1227 case HWTSTAMP_TX_ON:
1233 switch (cfg.rx_filter) {
1234 case HWTSTAMP_FILTER_NONE:
1235 port->rx_ts_enabled = false;
1237 case HWTSTAMP_FILTER_ALL:
1238 case HWTSTAMP_FILTER_SOME:
1239 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1240 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1241 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1242 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1243 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1244 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1245 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1246 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1247 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1248 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1249 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1250 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1251 case HWTSTAMP_FILTER_NTP_ALL:
1252 port->rx_ts_enabled = true;
1253 cfg.rx_filter = HWTSTAMP_FILTER_ALL;
1259 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON);
1261 /* cfg TX timestamp */
1262 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET <<
1263 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588;
1265 ts_vlan_ltype = ETH_P_8021Q;
1267 ts_ctrl_ltype2 = ETH_P_1588 |
1268 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 |
1269 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 |
1270 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 |
1271 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 |
1272 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 |
1273 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 |
1274 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 |
1275 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO;
1277 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS <<
1278 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT;
1280 if (port->tx_ts_enabled)
1281 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN |
1282 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN;
1284 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG);
1285 writel(ts_vlan_ltype, port->port_base +
1286 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG);
1287 writel(ts_ctrl_ltype2, port->port_base +
1288 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2);
1289 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL);
1291 /* en/dis RX timestamp */
1292 am65_cpts_rx_enable(common->cpts, port->rx_ts_enabled);
1294 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1297 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev,
1300 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1301 struct hwtstamp_config cfg;
1303 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS))
1307 cfg.tx_type = port->tx_ts_enabled ?
1308 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1309 cfg.rx_filter = port->rx_ts_enabled ?
1310 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE;
1312 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1315 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev,
1316 struct ifreq *req, int cmd)
1318 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1320 if (!netif_running(ndev))
1325 return am65_cpsw_nuss_hwtstamp_set(ndev, req);
1327 return am65_cpsw_nuss_hwtstamp_get(ndev, req);
1330 if (!port->slave.phy)
1333 return phy_mii_ioctl(port->slave.phy, req, cmd);
1336 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev,
1337 struct rtnl_link_stats64 *stats)
1339 struct am65_cpsw_ndev_priv *ndev_priv = netdev_priv(dev);
1343 for_each_possible_cpu(cpu) {
1344 struct am65_cpsw_ndev_stats *cpu_stats;
1350 cpu_stats = per_cpu_ptr(ndev_priv->stats, cpu);
1352 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
1353 rx_packets = cpu_stats->rx_packets;
1354 rx_bytes = cpu_stats->rx_bytes;
1355 tx_packets = cpu_stats->tx_packets;
1356 tx_bytes = cpu_stats->tx_bytes;
1357 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
1359 stats->rx_packets += rx_packets;
1360 stats->rx_bytes += rx_bytes;
1361 stats->tx_packets += tx_packets;
1362 stats->tx_bytes += tx_bytes;
1365 stats->rx_errors = dev->stats.rx_errors;
1366 stats->rx_dropped = dev->stats.rx_dropped;
1367 stats->tx_dropped = dev->stats.tx_dropped;
1370 static const struct net_device_ops am65_cpsw_nuss_netdev_ops_2g = {
1371 .ndo_open = am65_cpsw_nuss_ndo_slave_open,
1372 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop,
1373 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit,
1374 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode,
1375 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats,
1376 .ndo_validate_addr = eth_validate_addr,
1377 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address,
1378 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout,
1379 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid,
1380 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid,
1381 .ndo_do_ioctl = am65_cpsw_nuss_ndo_slave_ioctl,
1382 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc,
1385 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port)
1387 struct am65_cpsw_common *common = port->common;
1389 if (!port->disabled)
1392 common->disabled_ports_mask |= BIT(port->port_id);
1393 cpsw_ale_control_set(common->ale, port->port_id,
1394 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1396 cpsw_sl_reset(port->slave.mac_sl, 100);
1397 cpsw_sl_ctl_reset(port->slave.mac_sl);
1400 static void am65_cpsw_nuss_free_tx_chns(void *data)
1402 struct am65_cpsw_common *common = data;
1405 for (i = 0; i < common->tx_ch_num; i++) {
1406 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i];
1408 if (!IS_ERR_OR_NULL(tx_chn->desc_pool))
1409 k3_cppi_desc_pool_destroy(tx_chn->desc_pool);
1411 if (!IS_ERR_OR_NULL(tx_chn->tx_chn))
1412 k3_udma_glue_release_tx_chn(tx_chn->tx_chn);
1414 memset(tx_chn, 0, sizeof(*tx_chn));
1418 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common)
1420 struct device *dev = common->dev;
1423 devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common);
1425 for (i = 0; i < common->tx_ch_num; i++) {
1426 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i];
1429 devm_free_irq(dev, tx_chn->irq, tx_chn);
1431 netif_napi_del(&tx_chn->napi_tx);
1433 if (!IS_ERR_OR_NULL(tx_chn->desc_pool))
1434 k3_cppi_desc_pool_destroy(tx_chn->desc_pool);
1436 if (!IS_ERR_OR_NULL(tx_chn->tx_chn))
1437 k3_udma_glue_release_tx_chn(tx_chn->tx_chn);
1439 memset(tx_chn, 0, sizeof(*tx_chn));
1443 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common)
1445 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS);
1446 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 };
1447 struct device *dev = common->dev;
1448 struct k3_ring_cfg ring_cfg = {
1449 .elm_size = K3_RINGACC_RING_ELSIZE_8,
1450 .mode = K3_RINGACC_RING_MODE_RING,
1456 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE,
1457 AM65_CPSW_NAV_SW_DATA_SIZE);
1459 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE;
1460 tx_cfg.tx_cfg = ring_cfg;
1461 tx_cfg.txcq_cfg = ring_cfg;
1462 tx_cfg.tx_cfg.size = max_desc_num;
1463 tx_cfg.txcq_cfg.size = max_desc_num;
1465 for (i = 0; i < common->tx_ch_num; i++) {
1466 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i];
1468 snprintf(tx_chn->tx_chn_name,
1469 sizeof(tx_chn->tx_chn_name), "tx%d", i);
1471 tx_chn->common = common;
1473 tx_chn->descs_num = max_desc_num;
1475 k3_cppi_desc_pool_create_name(dev,
1478 tx_chn->tx_chn_name);
1479 if (IS_ERR(tx_chn->desc_pool)) {
1480 ret = PTR_ERR(tx_chn->desc_pool);
1481 dev_err(dev, "Failed to create poll %d\n", ret);
1486 k3_udma_glue_request_tx_chn(dev,
1487 tx_chn->tx_chn_name,
1489 if (IS_ERR(tx_chn->tx_chn)) {
1490 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn),
1491 "Failed to request tx dma channel\n");
1495 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn);
1496 if (tx_chn->irq <= 0) {
1497 dev_err(dev, "Failed to get tx dma irq %d\n",
1499 ret = tx_chn->irq ?: -ENXIO;
1503 snprintf(tx_chn->tx_chn_name,
1504 sizeof(tx_chn->tx_chn_name), "%s-tx%d",
1505 dev_name(dev), tx_chn->id);
1509 i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common);
1511 dev_err(dev, "Failed to add free_tx_chns action %d\n", i);
1518 static void am65_cpsw_nuss_free_rx_chns(void *data)
1520 struct am65_cpsw_common *common = data;
1521 struct am65_cpsw_rx_chn *rx_chn;
1523 rx_chn = &common->rx_chns;
1525 if (!IS_ERR_OR_NULL(rx_chn->desc_pool))
1526 k3_cppi_desc_pool_destroy(rx_chn->desc_pool);
1528 if (!IS_ERR_OR_NULL(rx_chn->rx_chn))
1529 k3_udma_glue_release_rx_chn(rx_chn->rx_chn);
1532 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common)
1534 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns;
1535 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 };
1536 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC;
1537 struct device *dev = common->dev;
1542 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE,
1543 AM65_CPSW_NAV_SW_DATA_SIZE);
1545 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE;
1546 rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS;
1547 rx_cfg.flow_id_base = common->rx_flow_id_base;
1549 /* init all flows */
1551 rx_chn->descs_num = max_desc_num;
1552 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(dev,
1555 if (IS_ERR(rx_chn->desc_pool)) {
1556 ret = PTR_ERR(rx_chn->desc_pool);
1557 dev_err(dev, "Failed to create rx poll %d\n", ret);
1561 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg);
1562 if (IS_ERR(rx_chn->rx_chn)) {
1563 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn),
1564 "Failed to request rx dma channel\n");
1568 common->rx_flow_id_base =
1569 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn);
1570 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base);
1572 fdqring_id = K3_RINGACC_RING_ID_ANY;
1573 for (i = 0; i < rx_cfg.flow_id_num; i++) {
1574 struct k3_ring_cfg rxring_cfg = {
1575 .elm_size = K3_RINGACC_RING_ELSIZE_8,
1576 .mode = K3_RINGACC_RING_MODE_RING,
1579 struct k3_ring_cfg fdqring_cfg = {
1580 .elm_size = K3_RINGACC_RING_ELSIZE_8,
1581 .mode = K3_RINGACC_RING_MODE_MESSAGE,
1582 .flags = K3_RINGACC_RING_SHARED,
1584 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = {
1585 .rx_cfg = rxring_cfg,
1586 .rxfdq_cfg = fdqring_cfg,
1587 .ring_rxq_id = K3_RINGACC_RING_ID_ANY,
1589 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG,
1592 rx_flow_cfg.ring_rxfdq0_id = fdqring_id;
1593 rx_flow_cfg.rx_cfg.size = max_desc_num;
1594 rx_flow_cfg.rxfdq_cfg.size = max_desc_num;
1596 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn,
1599 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret);
1604 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn,
1607 rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i);
1609 if (rx_chn->irq <= 0) {
1610 dev_err(dev, "Failed to get rx dma irq %d\n",
1618 i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common);
1620 dev_err(dev, "Failed to add free_rx_chns action %d\n", i);
1627 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common)
1629 struct am65_cpsw_host *host_p = am65_common_get_host(common);
1631 host_p->common = common;
1632 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE;
1633 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE;
1638 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node,
1639 int slave, u8 *mac_addr)
1641 u32 mac_lo, mac_hi, offset;
1642 struct regmap *syscon;
1645 syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse");
1646 if (IS_ERR(syscon)) {
1647 if (PTR_ERR(syscon) == -ENODEV)
1649 return PTR_ERR(syscon);
1652 ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1,
1657 regmap_read(syscon, offset, &mac_lo);
1658 regmap_read(syscon, offset + 4, &mac_hi);
1660 mac_addr[0] = (mac_hi >> 8) & 0xff;
1661 mac_addr[1] = mac_hi & 0xff;
1662 mac_addr[2] = (mac_lo >> 24) & 0xff;
1663 mac_addr[3] = (mac_lo >> 16) & 0xff;
1664 mac_addr[4] = (mac_lo >> 8) & 0xff;
1665 mac_addr[5] = mac_lo & 0xff;
1670 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common)
1672 struct device *dev = common->dev;
1673 struct device_node *node;
1674 struct am65_cpts *cpts;
1675 void __iomem *reg_base;
1677 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS))
1680 node = of_get_child_by_name(dev->of_node, "cpts");
1682 dev_err(dev, "%s cpts not found\n", __func__);
1686 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE;
1687 cpts = am65_cpts_create(dev, reg_base, node);
1689 int ret = PTR_ERR(cpts);
1692 if (ret == -EOPNOTSUPP) {
1693 dev_info(dev, "cpts disabled\n");
1697 dev_err(dev, "cpts create err %d\n", ret);
1700 common->cpts = cpts;
1705 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common)
1707 struct device_node *node, *port_np;
1708 struct device *dev = common->dev;
1711 node = of_get_child_by_name(dev->of_node, "ethernet-ports");
1715 for_each_child_of_node(node, port_np) {
1716 struct am65_cpsw_port *port;
1717 const void *mac_addr;
1720 /* it is not a slave port node, continue */
1721 if (strcmp(port_np->name, "port"))
1724 ret = of_property_read_u32(port_np, "reg", &port_id);
1726 dev_err(dev, "%pOF error reading port_id %d\n",
1731 if (!port_id || port_id > common->port_num) {
1732 dev_err(dev, "%pOF has invalid port_id %u %s\n",
1733 port_np, port_id, port_np->name);
1738 port = am65_common_get_port(common, port_id);
1739 port->port_id = port_id;
1740 port->common = common;
1741 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE +
1742 AM65_CPSW_NU_PORTS_OFFSET * (port_id);
1743 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE +
1744 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id);
1745 port->name = of_get_property(port_np, "label", NULL);
1746 port->fetch_ram_base =
1747 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE +
1748 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1));
1750 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base);
1751 if (IS_ERR(port->slave.mac_sl)) {
1752 ret = PTR_ERR(port->slave.mac_sl);
1756 port->disabled = !of_device_is_available(port_np);
1760 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL);
1761 if (IS_ERR(port->slave.ifphy)) {
1762 ret = PTR_ERR(port->slave.ifphy);
1763 dev_err(dev, "%pOF error retrieving port phy: %d\n",
1768 port->slave.mac_only =
1769 of_property_read_bool(port_np, "ti,mac-only");
1771 /* get phy/link info */
1772 if (of_phy_is_fixed_link(port_np)) {
1773 ret = of_phy_register_fixed_link(port_np);
1775 ret = dev_err_probe(dev, ret,
1776 "failed to register fixed-link phy %pOF\n",
1780 port->slave.phy_node = of_node_get(port_np);
1782 port->slave.phy_node =
1783 of_parse_phandle(port_np, "phy-handle", 0);
1786 if (!port->slave.phy_node) {
1788 "slave[%d] no phy found\n", port_id);
1793 ret = of_get_phy_mode(port_np, &port->slave.phy_if);
1795 dev_err(dev, "%pOF read phy-mode err %d\n",
1800 mac_addr = of_get_mac_address(port_np);
1801 if (!IS_ERR(mac_addr)) {
1802 ether_addr_copy(port->slave.mac_addr, mac_addr);
1803 } else if (am65_cpsw_am654_get_efuse_macid(port_np,
1805 port->slave.mac_addr) ||
1806 !is_valid_ether_addr(port->slave.mac_addr)) {
1807 random_ether_addr(port->slave.mac_addr);
1808 dev_err(dev, "Use random MAC address\n");
1816 of_node_put(port_np);
1821 static void am65_cpsw_pcpu_stats_free(void *data)
1823 struct am65_cpsw_ndev_stats __percpu *stats = data;
1828 static int am65_cpsw_nuss_init_ndev_2g(struct am65_cpsw_common *common)
1830 struct am65_cpsw_ndev_priv *ndev_priv;
1831 struct device *dev = common->dev;
1832 struct am65_cpsw_port *port;
1835 port = am65_common_get_port(common, 1);
1838 port->ndev = devm_alloc_etherdev_mqs(common->dev,
1839 sizeof(struct am65_cpsw_ndev_priv),
1840 AM65_CPSW_MAX_TX_QUEUES,
1841 AM65_CPSW_MAX_RX_QUEUES);
1843 dev_err(dev, "error allocating slave net_device %u\n",
1848 ndev_priv = netdev_priv(port->ndev);
1849 ndev_priv->port = port;
1850 ndev_priv->msg_enable = AM65_CPSW_DEBUG;
1851 SET_NETDEV_DEV(port->ndev, dev);
1853 ether_addr_copy(port->ndev->dev_addr, port->slave.mac_addr);
1855 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE;
1856 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE -
1857 (VLAN_ETH_HLEN + ETH_FCS_LEN);
1858 port->ndev->hw_features = NETIF_F_SG |
1862 port->ndev->features = port->ndev->hw_features |
1863 NETIF_F_HW_VLAN_CTAG_FILTER;
1864 port->ndev->vlan_features |= NETIF_F_SG;
1865 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops_2g;
1866 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave;
1868 /* Disable TX checksum offload by default due to HW bug */
1869 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM)
1870 port->ndev->features &= ~NETIF_F_HW_CSUM;
1872 ndev_priv->stats = netdev_alloc_pcpu_stats(struct am65_cpsw_ndev_stats);
1873 if (!ndev_priv->stats)
1876 ret = devm_add_action_or_reset(dev, am65_cpsw_pcpu_stats_free,
1879 dev_err(dev, "Failed to add percpu stat free action %d\n", ret);
1883 netif_napi_add(port->ndev, &common->napi_rx,
1884 am65_cpsw_nuss_rx_poll, NAPI_POLL_WEIGHT);
1889 static int am65_cpsw_nuss_ndev_add_napi_2g(struct am65_cpsw_common *common)
1891 struct device *dev = common->dev;
1892 struct am65_cpsw_port *port;
1895 port = am65_common_get_port(common, 1);
1897 for (i = 0; i < common->tx_ch_num; i++) {
1898 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i];
1900 netif_tx_napi_add(port->ndev, &tx_chn->napi_tx,
1901 am65_cpsw_nuss_tx_poll, NAPI_POLL_WEIGHT);
1903 ret = devm_request_irq(dev, tx_chn->irq,
1904 am65_cpsw_nuss_tx_irq,
1906 tx_chn->tx_chn_name, tx_chn);
1908 dev_err(dev, "failure requesting tx%u irq %u, %d\n",
1909 tx_chn->id, tx_chn->irq, ret);
1918 static int am65_cpsw_nuss_ndev_reg_2g(struct am65_cpsw_common *common)
1920 struct device *dev = common->dev;
1921 struct am65_cpsw_port *port;
1924 port = am65_common_get_port(common, 1);
1925 ret = am65_cpsw_nuss_ndev_add_napi_2g(common);
1929 ret = devm_request_irq(dev, common->rx_chns.irq,
1930 am65_cpsw_nuss_rx_irq,
1931 IRQF_TRIGGER_HIGH, dev_name(dev), common);
1933 dev_err(dev, "failure requesting rx irq %u, %d\n",
1934 common->rx_chns.irq, ret);
1938 ret = register_netdev(port->ndev);
1940 dev_err(dev, "error registering slave net device %d\n", ret);
1942 /* can't auto unregister ndev using devm_add_action() due to
1943 * devres release sequence in DD core for DMA
1949 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx)
1953 common->tx_ch_num = num_tx;
1954 ret = am65_cpsw_nuss_init_tx_chns(common);
1958 return am65_cpsw_nuss_ndev_add_napi_2g(common);
1961 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common)
1963 struct am65_cpsw_port *port;
1966 for (i = 0; i < common->port_num; i++) {
1967 port = &common->ports[i];
1969 unregister_netdev(port->ndev);
1973 struct am65_cpsw_soc_pdata {
1977 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = {
1978 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM,
1981 static const struct soc_device_attribute am65_cpsw_socinfo[] = {
1982 { .family = "AM65X",
1983 .revision = "SR2.0",
1984 .data = &am65x_soc_sr2_0
1989 static const struct am65_cpsw_pdata am65x_sr1_0 = {
1990 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM,
1993 static const struct am65_cpsw_pdata j721e_pdata = {
1997 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = {
1998 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0},
1999 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata},
2002 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable);
2004 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common)
2006 const struct soc_device_attribute *soc;
2008 soc = soc_device_match(am65_cpsw_socinfo);
2009 if (soc && soc->data) {
2010 const struct am65_cpsw_soc_pdata *socdata = soc->data;
2012 /* disable quirks */
2013 common->pdata.quirks &= ~socdata->quirks_dis;
2017 static int am65_cpsw_nuss_probe(struct platform_device *pdev)
2019 struct cpsw_ale_params ale_params = { 0 };
2020 const struct of_device_id *of_id;
2021 struct device *dev = &pdev->dev;
2022 struct am65_cpsw_common *common;
2023 struct device_node *node;
2024 struct resource *res;
2028 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL);
2033 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev);
2036 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data;
2038 am65_cpsw_nuss_apply_socinfo(common);
2040 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss");
2041 common->ss_base = devm_ioremap_resource(&pdev->dev, res);
2042 if (IS_ERR(common->ss_base))
2043 return PTR_ERR(common->ss_base);
2044 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE;
2046 node = of_get_child_by_name(dev->of_node, "ethernet-ports");
2049 common->port_num = of_get_child_count(node);
2051 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS)
2054 if (common->port_num != 1)
2057 common->rx_flow_id_base = -1;
2058 init_completion(&common->tdown_complete);
2059 common->tx_ch_num = 1;
2060 common->pf_p0_rx_ptype_rrobin = false;
2062 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(48));
2064 dev_err(dev, "error setting dma mask: %d\n", ret);
2068 common->ports = devm_kcalloc(dev, common->port_num,
2069 sizeof(*common->ports),
2074 clk = devm_clk_get(dev, "fck");
2076 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n");
2077 common->bus_freq = clk_get_rate(clk);
2079 pm_runtime_enable(dev);
2080 ret = pm_runtime_get_sync(dev);
2082 pm_runtime_put_noidle(dev);
2083 pm_runtime_disable(dev);
2087 node = of_get_child_by_name(dev->of_node, "mdio");
2089 dev_warn(dev, "MDIO node not found\n");
2090 } else if (of_device_is_available(node)) {
2091 struct platform_device *mdio_pdev;
2093 mdio_pdev = of_platform_device_create(node, NULL, dev);
2099 common->mdio_dev = &mdio_pdev->dev;
2103 am65_cpsw_nuss_get_ver(common);
2105 /* init tx channels */
2106 ret = am65_cpsw_nuss_init_tx_chns(common);
2109 ret = am65_cpsw_nuss_init_rx_chns(common);
2113 ret = am65_cpsw_nuss_init_host_p(common);
2117 ret = am65_cpsw_nuss_init_slave_ports(common);
2121 /* init common data */
2122 ale_params.dev = dev;
2123 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT;
2124 ale_params.ale_ports = common->port_num + 1;
2125 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE;
2126 ale_params.dev_id = "am65x-cpsw2g";
2127 ale_params.bus_freq = common->bus_freq;
2129 common->ale = cpsw_ale_create(&ale_params);
2130 if (IS_ERR(common->ale)) {
2131 dev_err(dev, "error initializing ale engine\n");
2132 ret = PTR_ERR(common->ale);
2136 ret = am65_cpsw_init_cpts(common);
2141 for (i = 0; i < common->port_num; i++)
2142 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]);
2144 dev_set_drvdata(dev, common);
2146 ret = am65_cpsw_nuss_init_ndev_2g(common);
2150 ret = am65_cpsw_nuss_ndev_reg_2g(common);
2154 pm_runtime_put(dev);
2158 if (common->mdio_dev)
2159 of_platform_device_destroy(common->mdio_dev, NULL);
2161 pm_runtime_put_sync(dev);
2162 pm_runtime_disable(dev);
2166 static int am65_cpsw_nuss_remove(struct platform_device *pdev)
2168 struct device *dev = &pdev->dev;
2169 struct am65_cpsw_common *common;
2172 common = dev_get_drvdata(dev);
2174 ret = pm_runtime_get_sync(&pdev->dev);
2176 pm_runtime_put_noidle(&pdev->dev);
2180 /* must unregister ndevs here because DD release_driver routine calls
2181 * dma_deconfigure(dev) before devres_release_all(dev)
2183 am65_cpsw_nuss_cleanup_ndev(common);
2185 if (common->mdio_dev)
2186 of_platform_device_destroy(common->mdio_dev, NULL);
2188 pm_runtime_put_sync(&pdev->dev);
2189 pm_runtime_disable(&pdev->dev);
2193 static struct platform_driver am65_cpsw_nuss_driver = {
2195 .name = AM65_CPSW_DRV_NAME,
2196 .of_match_table = am65_cpsw_nuss_of_mtable,
2198 .probe = am65_cpsw_nuss_probe,
2199 .remove = am65_cpsw_nuss_remove,
2202 module_platform_driver(am65_cpsw_nuss_driver);
2204 MODULE_LICENSE("GPL v2");
2205 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>");
2206 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver");