1 /* niu.c: Neptune ethernet driver.
3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/netdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/etherdevice.h>
16 #include <linux/platform_device.h>
17 #include <linux/delay.h>
18 #include <linux/bitops.h>
19 #include <linux/mii.h>
21 #include <linux/if_ether.h>
22 #include <linux/if_vlan.h>
25 #include <linux/ipv6.h>
26 #include <linux/log2.h>
27 #include <linux/jiffies.h>
28 #include <linux/crc32.h>
29 #include <linux/list.h>
30 #include <linux/slab.h>
33 #include <linux/of_device.h>
37 #define DRV_MODULE_NAME "niu"
38 #define DRV_MODULE_VERSION "1.1"
39 #define DRV_MODULE_RELDATE "Apr 22, 2010"
41 static char version[] =
42 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
44 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
45 MODULE_DESCRIPTION("NIU ethernet driver");
46 MODULE_LICENSE("GPL");
47 MODULE_VERSION(DRV_MODULE_VERSION);
50 static u64 readq(void __iomem *reg)
52 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
55 static void writeq(u64 val, void __iomem *reg)
57 writel(val & 0xffffffff, reg);
58 writel(val >> 32, reg + 0x4UL);
62 static const struct pci_device_id niu_pci_tbl[] = {
63 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
67 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
69 #define NIU_TX_TIMEOUT (5 * HZ)
71 #define nr64(reg) readq(np->regs + (reg))
72 #define nw64(reg, val) writeq((val), np->regs + (reg))
74 #define nr64_mac(reg) readq(np->mac_regs + (reg))
75 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
77 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
78 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
80 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
81 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
83 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
84 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
86 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
89 static int debug = -1;
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "NIU debug level");
93 #define niu_lock_parent(np, flags) \
94 spin_lock_irqsave(&np->parent->lock, flags)
95 #define niu_unlock_parent(np, flags) \
96 spin_unlock_irqrestore(&np->parent->lock, flags)
98 static int serdes_init_10g_serdes(struct niu *np);
100 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
101 u64 bits, int limit, int delay)
103 while (--limit >= 0) {
104 u64 val = nr64_mac(reg);
115 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
116 u64 bits, int limit, int delay,
117 const char *reg_name)
122 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
124 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
125 (unsigned long long)bits, reg_name,
126 (unsigned long long)nr64_mac(reg));
130 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
131 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
132 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
135 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
136 u64 bits, int limit, int delay)
138 while (--limit >= 0) {
139 u64 val = nr64_ipp(reg);
150 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
151 u64 bits, int limit, int delay,
152 const char *reg_name)
161 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
163 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
164 (unsigned long long)bits, reg_name,
165 (unsigned long long)nr64_ipp(reg));
169 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
170 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
171 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
174 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
175 u64 bits, int limit, int delay)
177 while (--limit >= 0) {
189 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
190 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
191 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
194 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
195 u64 bits, int limit, int delay,
196 const char *reg_name)
201 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
203 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
204 (unsigned long long)bits, reg_name,
205 (unsigned long long)nr64(reg));
209 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
210 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
211 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
214 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
216 u64 val = (u64) lp->timer;
219 val |= LDG_IMGMT_ARM;
221 nw64(LDG_IMGMT(lp->ldg_num), val);
224 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
226 unsigned long mask_reg, bits;
229 if (ldn < 0 || ldn > LDN_MAX)
233 mask_reg = LD_IM0(ldn);
236 mask_reg = LD_IM1(ldn - 64);
240 val = nr64(mask_reg);
250 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
252 struct niu_parent *parent = np->parent;
255 for (i = 0; i <= LDN_MAX; i++) {
258 if (parent->ldg_map[i] != lp->ldg_num)
261 err = niu_ldn_irq_enable(np, i, on);
268 static int niu_enable_interrupts(struct niu *np, int on)
272 for (i = 0; i < np->num_ldg; i++) {
273 struct niu_ldg *lp = &np->ldg[i];
276 err = niu_enable_ldn_in_ldg(np, lp, on);
280 for (i = 0; i < np->num_ldg; i++)
281 niu_ldg_rearm(np, &np->ldg[i], on);
286 static u32 phy_encode(u32 type, int port)
288 return type << (port * 2);
291 static u32 phy_decode(u32 val, int port)
293 return (val >> (port * 2)) & PORT_TYPE_MASK;
296 static int mdio_wait(struct niu *np)
301 while (--limit > 0) {
302 val = nr64(MIF_FRAME_OUTPUT);
303 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
304 return val & MIF_FRAME_OUTPUT_DATA;
312 static int mdio_read(struct niu *np, int port, int dev, int reg)
316 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
321 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
322 return mdio_wait(np);
325 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
329 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
334 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
342 static int mii_read(struct niu *np, int port, int reg)
344 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
345 return mdio_wait(np);
348 static int mii_write(struct niu *np, int port, int reg, int data)
352 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
360 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
364 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
365 ESR2_TI_PLL_TX_CFG_L(channel),
368 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
369 ESR2_TI_PLL_TX_CFG_H(channel),
374 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
378 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
379 ESR2_TI_PLL_RX_CFG_L(channel),
382 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
383 ESR2_TI_PLL_RX_CFG_H(channel),
388 /* Mode is always 10G fiber. */
389 static int serdes_init_niu_10g_fiber(struct niu *np)
391 struct niu_link_config *lp = &np->link_config;
395 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
396 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
397 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
398 PLL_RX_CFG_EQ_LP_ADAPTIVE);
400 if (lp->loopback_mode == LOOPBACK_PHY) {
401 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
403 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
404 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
406 tx_cfg |= PLL_TX_CFG_ENTEST;
407 rx_cfg |= PLL_RX_CFG_ENTEST;
410 /* Initialize all 4 lanes of the SERDES. */
411 for (i = 0; i < 4; i++) {
412 int err = esr2_set_tx_cfg(np, i, tx_cfg);
417 for (i = 0; i < 4; i++) {
418 int err = esr2_set_rx_cfg(np, i, rx_cfg);
426 static int serdes_init_niu_1g_serdes(struct niu *np)
428 struct niu_link_config *lp = &np->link_config;
429 u16 pll_cfg, pll_sts;
431 u64 uninitialized_var(sig), mask, val;
436 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
437 PLL_TX_CFG_RATE_HALF);
438 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
439 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
440 PLL_RX_CFG_RATE_HALF);
443 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
445 if (lp->loopback_mode == LOOPBACK_PHY) {
446 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
448 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
449 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
451 tx_cfg |= PLL_TX_CFG_ENTEST;
452 rx_cfg |= PLL_RX_CFG_ENTEST;
455 /* Initialize PLL for 1G */
456 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
458 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
459 ESR2_TI_PLL_CFG_L, pll_cfg);
461 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
466 pll_sts = PLL_CFG_ENPLL;
468 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
469 ESR2_TI_PLL_STS_L, pll_sts);
471 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
478 /* Initialize all 4 lanes of the SERDES. */
479 for (i = 0; i < 4; i++) {
480 err = esr2_set_tx_cfg(np, i, tx_cfg);
485 for (i = 0; i < 4; i++) {
486 err = esr2_set_rx_cfg(np, i, rx_cfg);
493 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
498 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
506 while (max_retry--) {
507 sig = nr64(ESR_INT_SIGNALS);
508 if ((sig & mask) == val)
514 if ((sig & mask) != val) {
515 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
516 np->port, (int)(sig & mask), (int)val);
523 static int serdes_init_niu_10g_serdes(struct niu *np)
525 struct niu_link_config *lp = &np->link_config;
526 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
528 u64 uninitialized_var(sig), mask, val;
532 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
533 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
534 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
535 PLL_RX_CFG_EQ_LP_ADAPTIVE);
537 if (lp->loopback_mode == LOOPBACK_PHY) {
538 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
540 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
541 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
543 tx_cfg |= PLL_TX_CFG_ENTEST;
544 rx_cfg |= PLL_RX_CFG_ENTEST;
547 /* Initialize PLL for 10G */
548 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
550 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
551 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
553 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
558 pll_sts = PLL_CFG_ENPLL;
560 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
561 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
563 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
570 /* Initialize all 4 lanes of the SERDES. */
571 for (i = 0; i < 4; i++) {
572 err = esr2_set_tx_cfg(np, i, tx_cfg);
577 for (i = 0; i < 4; i++) {
578 err = esr2_set_rx_cfg(np, i, rx_cfg);
583 /* check if serdes is ready */
587 mask = ESR_INT_SIGNALS_P0_BITS;
588 val = (ESR_INT_SRDY0_P0 |
598 mask = ESR_INT_SIGNALS_P1_BITS;
599 val = (ESR_INT_SRDY0_P1 |
612 while (max_retry--) {
613 sig = nr64(ESR_INT_SIGNALS);
614 if ((sig & mask) == val)
620 if ((sig & mask) != val) {
621 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
622 np->port, (int)(sig & mask), (int)val);
624 /* 10G failed, try initializing at 1G */
625 err = serdes_init_niu_1g_serdes(np);
627 np->flags &= ~NIU_FLAGS_10G;
628 np->mac_xcvr = MAC_XCVR_PCS;
630 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
638 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
642 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
644 *val = (err & 0xffff);
645 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
646 ESR_RXTX_CTRL_H(chan));
648 *val |= ((err & 0xffff) << 16);
654 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
658 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
659 ESR_GLUE_CTRL0_L(chan));
661 *val = (err & 0xffff);
662 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
663 ESR_GLUE_CTRL0_H(chan));
665 *val |= ((err & 0xffff) << 16);
672 static int esr_read_reset(struct niu *np, u32 *val)
676 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
677 ESR_RXTX_RESET_CTRL_L);
679 *val = (err & 0xffff);
680 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
681 ESR_RXTX_RESET_CTRL_H);
683 *val |= ((err & 0xffff) << 16);
690 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
694 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
695 ESR_RXTX_CTRL_L(chan), val & 0xffff);
697 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
698 ESR_RXTX_CTRL_H(chan), (val >> 16));
702 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
706 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
707 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
709 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
710 ESR_GLUE_CTRL0_H(chan), (val >> 16));
714 static int esr_reset(struct niu *np)
716 u32 uninitialized_var(reset);
719 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
720 ESR_RXTX_RESET_CTRL_L, 0x0000);
723 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
724 ESR_RXTX_RESET_CTRL_H, 0xffff);
729 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
730 ESR_RXTX_RESET_CTRL_L, 0xffff);
735 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
736 ESR_RXTX_RESET_CTRL_H, 0x0000);
741 err = esr_read_reset(np, &reset);
745 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
753 static int serdes_init_10g(struct niu *np)
755 struct niu_link_config *lp = &np->link_config;
756 unsigned long ctrl_reg, test_cfg_reg, i;
757 u64 ctrl_val, test_cfg_val, sig, mask, val;
762 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
763 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
766 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
767 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
773 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
774 ENET_SERDES_CTRL_SDET_1 |
775 ENET_SERDES_CTRL_SDET_2 |
776 ENET_SERDES_CTRL_SDET_3 |
777 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
778 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
779 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
780 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
781 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
782 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
783 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
784 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
787 if (lp->loopback_mode == LOOPBACK_PHY) {
788 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
789 ENET_SERDES_TEST_MD_0_SHIFT) |
790 (ENET_TEST_MD_PAD_LOOPBACK <<
791 ENET_SERDES_TEST_MD_1_SHIFT) |
792 (ENET_TEST_MD_PAD_LOOPBACK <<
793 ENET_SERDES_TEST_MD_2_SHIFT) |
794 (ENET_TEST_MD_PAD_LOOPBACK <<
795 ENET_SERDES_TEST_MD_3_SHIFT));
798 nw64(ctrl_reg, ctrl_val);
799 nw64(test_cfg_reg, test_cfg_val);
801 /* Initialize all 4 lanes of the SERDES. */
802 for (i = 0; i < 4; i++) {
803 u32 rxtx_ctrl, glue0;
805 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
808 err = esr_read_glue0(np, i, &glue0);
812 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
813 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
814 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
816 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
817 ESR_GLUE_CTRL0_THCNT |
818 ESR_GLUE_CTRL0_BLTIME);
819 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
820 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
821 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
822 (BLTIME_300_CYCLES <<
823 ESR_GLUE_CTRL0_BLTIME_SHIFT));
825 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
828 err = esr_write_glue0(np, i, glue0);
837 sig = nr64(ESR_INT_SIGNALS);
840 mask = ESR_INT_SIGNALS_P0_BITS;
841 val = (ESR_INT_SRDY0_P0 |
851 mask = ESR_INT_SIGNALS_P1_BITS;
852 val = (ESR_INT_SRDY0_P1 |
865 if ((sig & mask) != val) {
866 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
867 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
870 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
871 np->port, (int)(sig & mask), (int)val);
874 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
875 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
879 static int serdes_init_1g(struct niu *np)
883 val = nr64(ENET_SERDES_1_PLL_CFG);
884 val &= ~ENET_SERDES_PLL_FBDIV2;
887 val |= ENET_SERDES_PLL_HRATE0;
890 val |= ENET_SERDES_PLL_HRATE1;
893 val |= ENET_SERDES_PLL_HRATE2;
896 val |= ENET_SERDES_PLL_HRATE3;
901 nw64(ENET_SERDES_1_PLL_CFG, val);
906 static int serdes_init_1g_serdes(struct niu *np)
908 struct niu_link_config *lp = &np->link_config;
909 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
910 u64 ctrl_val, test_cfg_val, sig, mask, val;
912 u64 reset_val, val_rd;
914 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
915 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
916 ENET_SERDES_PLL_FBDIV0;
919 reset_val = ENET_SERDES_RESET_0;
920 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
921 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
922 pll_cfg = ENET_SERDES_0_PLL_CFG;
925 reset_val = ENET_SERDES_RESET_1;
926 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
927 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
928 pll_cfg = ENET_SERDES_1_PLL_CFG;
934 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
935 ENET_SERDES_CTRL_SDET_1 |
936 ENET_SERDES_CTRL_SDET_2 |
937 ENET_SERDES_CTRL_SDET_3 |
938 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
939 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
940 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
941 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
942 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
943 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
944 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
945 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
948 if (lp->loopback_mode == LOOPBACK_PHY) {
949 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
950 ENET_SERDES_TEST_MD_0_SHIFT) |
951 (ENET_TEST_MD_PAD_LOOPBACK <<
952 ENET_SERDES_TEST_MD_1_SHIFT) |
953 (ENET_TEST_MD_PAD_LOOPBACK <<
954 ENET_SERDES_TEST_MD_2_SHIFT) |
955 (ENET_TEST_MD_PAD_LOOPBACK <<
956 ENET_SERDES_TEST_MD_3_SHIFT));
959 nw64(ENET_SERDES_RESET, reset_val);
961 val_rd = nr64(ENET_SERDES_RESET);
962 val_rd &= ~reset_val;
964 nw64(ctrl_reg, ctrl_val);
965 nw64(test_cfg_reg, test_cfg_val);
966 nw64(ENET_SERDES_RESET, val_rd);
969 /* Initialize all 4 lanes of the SERDES. */
970 for (i = 0; i < 4; i++) {
971 u32 rxtx_ctrl, glue0;
973 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
976 err = esr_read_glue0(np, i, &glue0);
980 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
981 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
982 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
984 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
985 ESR_GLUE_CTRL0_THCNT |
986 ESR_GLUE_CTRL0_BLTIME);
987 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
988 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
989 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
990 (BLTIME_300_CYCLES <<
991 ESR_GLUE_CTRL0_BLTIME_SHIFT));
993 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
996 err = esr_write_glue0(np, i, glue0);
1002 sig = nr64(ESR_INT_SIGNALS);
1005 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1010 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1018 if ((sig & mask) != val) {
1019 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1020 np->port, (int)(sig & mask), (int)val);
1027 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1029 struct niu_link_config *lp = &np->link_config;
1033 unsigned long flags;
1037 current_speed = SPEED_INVALID;
1038 current_duplex = DUPLEX_INVALID;
1040 spin_lock_irqsave(&np->lock, flags);
1042 val = nr64_pcs(PCS_MII_STAT);
1044 if (val & PCS_MII_STAT_LINK_STATUS) {
1046 current_speed = SPEED_1000;
1047 current_duplex = DUPLEX_FULL;
1050 lp->active_speed = current_speed;
1051 lp->active_duplex = current_duplex;
1052 spin_unlock_irqrestore(&np->lock, flags);
1054 *link_up_p = link_up;
1058 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1060 unsigned long flags;
1061 struct niu_link_config *lp = &np->link_config;
1068 if (!(np->flags & NIU_FLAGS_10G))
1069 return link_status_1g_serdes(np, link_up_p);
1071 current_speed = SPEED_INVALID;
1072 current_duplex = DUPLEX_INVALID;
1073 spin_lock_irqsave(&np->lock, flags);
1075 val = nr64_xpcs(XPCS_STATUS(0));
1076 val2 = nr64_mac(XMAC_INTER2);
1077 if (val2 & 0x01000000)
1080 if ((val & 0x1000ULL) && link_ok) {
1082 current_speed = SPEED_10000;
1083 current_duplex = DUPLEX_FULL;
1085 lp->active_speed = current_speed;
1086 lp->active_duplex = current_duplex;
1087 spin_unlock_irqrestore(&np->lock, flags);
1088 *link_up_p = link_up;
1092 static int link_status_mii(struct niu *np, int *link_up_p)
1094 struct niu_link_config *lp = &np->link_config;
1096 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1097 int supported, advertising, active_speed, active_duplex;
1099 err = mii_read(np, np->phy_addr, MII_BMCR);
1100 if (unlikely(err < 0))
1104 err = mii_read(np, np->phy_addr, MII_BMSR);
1105 if (unlikely(err < 0))
1109 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1110 if (unlikely(err < 0))
1114 err = mii_read(np, np->phy_addr, MII_LPA);
1115 if (unlikely(err < 0))
1119 if (likely(bmsr & BMSR_ESTATEN)) {
1120 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1121 if (unlikely(err < 0))
1125 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1126 if (unlikely(err < 0))
1130 err = mii_read(np, np->phy_addr, MII_STAT1000);
1131 if (unlikely(err < 0))
1135 estatus = ctrl1000 = stat1000 = 0;
1138 if (bmsr & BMSR_ANEGCAPABLE)
1139 supported |= SUPPORTED_Autoneg;
1140 if (bmsr & BMSR_10HALF)
1141 supported |= SUPPORTED_10baseT_Half;
1142 if (bmsr & BMSR_10FULL)
1143 supported |= SUPPORTED_10baseT_Full;
1144 if (bmsr & BMSR_100HALF)
1145 supported |= SUPPORTED_100baseT_Half;
1146 if (bmsr & BMSR_100FULL)
1147 supported |= SUPPORTED_100baseT_Full;
1148 if (estatus & ESTATUS_1000_THALF)
1149 supported |= SUPPORTED_1000baseT_Half;
1150 if (estatus & ESTATUS_1000_TFULL)
1151 supported |= SUPPORTED_1000baseT_Full;
1152 lp->supported = supported;
1154 advertising = mii_adv_to_ethtool_adv_t(advert);
1155 advertising |= mii_ctrl1000_to_ethtool_adv_t(ctrl1000);
1157 if (bmcr & BMCR_ANENABLE) {
1160 lp->active_autoneg = 1;
1161 advertising |= ADVERTISED_Autoneg;
1164 neg1000 = (ctrl1000 << 2) & stat1000;
1166 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1167 active_speed = SPEED_1000;
1168 else if (neg & LPA_100)
1169 active_speed = SPEED_100;
1170 else if (neg & (LPA_10HALF | LPA_10FULL))
1171 active_speed = SPEED_10;
1173 active_speed = SPEED_INVALID;
1175 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1176 active_duplex = DUPLEX_FULL;
1177 else if (active_speed != SPEED_INVALID)
1178 active_duplex = DUPLEX_HALF;
1180 active_duplex = DUPLEX_INVALID;
1182 lp->active_autoneg = 0;
1184 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1185 active_speed = SPEED_1000;
1186 else if (bmcr & BMCR_SPEED100)
1187 active_speed = SPEED_100;
1189 active_speed = SPEED_10;
1191 if (bmcr & BMCR_FULLDPLX)
1192 active_duplex = DUPLEX_FULL;
1194 active_duplex = DUPLEX_HALF;
1197 lp->active_advertising = advertising;
1198 lp->active_speed = active_speed;
1199 lp->active_duplex = active_duplex;
1200 *link_up_p = !!(bmsr & BMSR_LSTATUS);
1205 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1207 struct niu_link_config *lp = &np->link_config;
1208 u16 current_speed, bmsr;
1209 unsigned long flags;
1214 current_speed = SPEED_INVALID;
1215 current_duplex = DUPLEX_INVALID;
1217 spin_lock_irqsave(&np->lock, flags);
1221 err = mii_read(np, np->phy_addr, MII_BMSR);
1226 if (bmsr & BMSR_LSTATUS) {
1229 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1234 err = mii_read(np, np->phy_addr, MII_LPA);
1239 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1243 current_speed = SPEED_1000;
1244 current_duplex = DUPLEX_FULL;
1247 lp->active_speed = current_speed;
1248 lp->active_duplex = current_duplex;
1252 spin_unlock_irqrestore(&np->lock, flags);
1254 *link_up_p = link_up;
1258 static int link_status_1g(struct niu *np, int *link_up_p)
1260 struct niu_link_config *lp = &np->link_config;
1261 unsigned long flags;
1264 spin_lock_irqsave(&np->lock, flags);
1266 err = link_status_mii(np, link_up_p);
1267 lp->supported |= SUPPORTED_TP;
1268 lp->active_advertising |= ADVERTISED_TP;
1270 spin_unlock_irqrestore(&np->lock, flags);
1274 static int bcm8704_reset(struct niu *np)
1278 err = mdio_read(np, np->phy_addr,
1279 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1280 if (err < 0 || err == 0xffff)
1283 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1289 while (--limit >= 0) {
1290 err = mdio_read(np, np->phy_addr,
1291 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1294 if (!(err & BMCR_RESET))
1298 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1299 np->port, (err & 0xffff));
1305 /* When written, certain PHY registers need to be read back twice
1306 * in order for the bits to settle properly.
1308 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1310 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1313 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1319 static int bcm8706_init_user_dev3(struct niu *np)
1324 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1325 BCM8704_USER_OPT_DIGITAL_CTRL);
1328 err &= ~USER_ODIG_CTRL_GPIOS;
1329 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1330 err |= USER_ODIG_CTRL_RESV2;
1331 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1332 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1341 static int bcm8704_init_user_dev3(struct niu *np)
1345 err = mdio_write(np, np->phy_addr,
1346 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1347 (USER_CONTROL_OPTXRST_LVL |
1348 USER_CONTROL_OPBIASFLT_LVL |
1349 USER_CONTROL_OBTMPFLT_LVL |
1350 USER_CONTROL_OPPRFLT_LVL |
1351 USER_CONTROL_OPTXFLT_LVL |
1352 USER_CONTROL_OPRXLOS_LVL |
1353 USER_CONTROL_OPRXFLT_LVL |
1354 USER_CONTROL_OPTXON_LVL |
1355 (0x3f << USER_CONTROL_RES1_SHIFT)));
1359 err = mdio_write(np, np->phy_addr,
1360 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1361 (USER_PMD_TX_CTL_XFP_CLKEN |
1362 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1363 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1364 USER_PMD_TX_CTL_TSCK_LPWREN));
1368 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1371 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1375 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1376 BCM8704_USER_OPT_DIGITAL_CTRL);
1379 err &= ~USER_ODIG_CTRL_GPIOS;
1380 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1381 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1382 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1391 static int mrvl88x2011_act_led(struct niu *np, int val)
1395 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1396 MRVL88X2011_LED_8_TO_11_CTL);
1400 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1401 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1403 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1404 MRVL88X2011_LED_8_TO_11_CTL, err);
1407 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1411 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1412 MRVL88X2011_LED_BLINK_CTL);
1414 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1417 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1418 MRVL88X2011_LED_BLINK_CTL, err);
1424 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1428 /* Set LED functions */
1429 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1434 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1438 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1439 MRVL88X2011_GENERAL_CTL);
1443 err |= MRVL88X2011_ENA_XFPREFCLK;
1445 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1446 MRVL88X2011_GENERAL_CTL, err);
1450 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1451 MRVL88X2011_PMA_PMD_CTL_1);
1455 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1456 err |= MRVL88X2011_LOOPBACK;
1458 err &= ~MRVL88X2011_LOOPBACK;
1460 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1461 MRVL88X2011_PMA_PMD_CTL_1, err);
1466 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1467 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1471 static int xcvr_diag_bcm870x(struct niu *np)
1473 u16 analog_stat0, tx_alarm_status;
1477 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1481 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
1483 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1486 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
1488 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1492 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
1495 /* XXX dig this out it might not be so useful XXX */
1496 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1497 BCM8704_USER_ANALOG_STATUS0);
1500 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1501 BCM8704_USER_ANALOG_STATUS0);
1506 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1507 BCM8704_USER_TX_ALARM_STATUS);
1510 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1511 BCM8704_USER_TX_ALARM_STATUS);
1514 tx_alarm_status = err;
1516 if (analog_stat0 != 0x03fc) {
1517 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1518 pr_info("Port %u cable not connected or bad cable\n",
1520 } else if (analog_stat0 == 0x639c) {
1521 pr_info("Port %u optical module is bad or missing\n",
1529 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1531 struct niu_link_config *lp = &np->link_config;
1534 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1539 err &= ~BMCR_LOOPBACK;
1541 if (lp->loopback_mode == LOOPBACK_MAC)
1542 err |= BMCR_LOOPBACK;
1544 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1552 static int xcvr_init_10g_bcm8706(struct niu *np)
1557 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1558 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1561 val = nr64_mac(XMAC_CONFIG);
1562 val &= ~XMAC_CONFIG_LED_POLARITY;
1563 val |= XMAC_CONFIG_FORCE_LED_ON;
1564 nw64_mac(XMAC_CONFIG, val);
1566 val = nr64(MIF_CONFIG);
1567 val |= MIF_CONFIG_INDIRECT_MODE;
1568 nw64(MIF_CONFIG, val);
1570 err = bcm8704_reset(np);
1574 err = xcvr_10g_set_lb_bcm870x(np);
1578 err = bcm8706_init_user_dev3(np);
1582 err = xcvr_diag_bcm870x(np);
1589 static int xcvr_init_10g_bcm8704(struct niu *np)
1593 err = bcm8704_reset(np);
1597 err = bcm8704_init_user_dev3(np);
1601 err = xcvr_10g_set_lb_bcm870x(np);
1605 err = xcvr_diag_bcm870x(np);
1612 static int xcvr_init_10g(struct niu *np)
1617 val = nr64_mac(XMAC_CONFIG);
1618 val &= ~XMAC_CONFIG_LED_POLARITY;
1619 val |= XMAC_CONFIG_FORCE_LED_ON;
1620 nw64_mac(XMAC_CONFIG, val);
1622 /* XXX shared resource, lock parent XXX */
1623 val = nr64(MIF_CONFIG);
1624 val |= MIF_CONFIG_INDIRECT_MODE;
1625 nw64(MIF_CONFIG, val);
1627 phy_id = phy_decode(np->parent->port_phy, np->port);
1628 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1630 /* handle different phy types */
1631 switch (phy_id & NIU_PHY_ID_MASK) {
1632 case NIU_PHY_ID_MRVL88X2011:
1633 err = xcvr_init_10g_mrvl88x2011(np);
1636 default: /* bcom 8704 */
1637 err = xcvr_init_10g_bcm8704(np);
1644 static int mii_reset(struct niu *np)
1648 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1653 while (--limit >= 0) {
1655 err = mii_read(np, np->phy_addr, MII_BMCR);
1658 if (!(err & BMCR_RESET))
1662 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1670 static int xcvr_init_1g_rgmii(struct niu *np)
1674 u16 bmcr, bmsr, estat;
1676 val = nr64(MIF_CONFIG);
1677 val &= ~MIF_CONFIG_INDIRECT_MODE;
1678 nw64(MIF_CONFIG, val);
1680 err = mii_reset(np);
1684 err = mii_read(np, np->phy_addr, MII_BMSR);
1690 if (bmsr & BMSR_ESTATEN) {
1691 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1698 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1702 if (bmsr & BMSR_ESTATEN) {
1705 if (estat & ESTATUS_1000_TFULL)
1706 ctrl1000 |= ADVERTISE_1000FULL;
1707 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1712 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1714 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1718 err = mii_read(np, np->phy_addr, MII_BMCR);
1721 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1723 err = mii_read(np, np->phy_addr, MII_BMSR);
1730 static int mii_init_common(struct niu *np)
1732 struct niu_link_config *lp = &np->link_config;
1733 u16 bmcr, bmsr, adv, estat;
1736 err = mii_reset(np);
1740 err = mii_read(np, np->phy_addr, MII_BMSR);
1746 if (bmsr & BMSR_ESTATEN) {
1747 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1754 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1758 if (lp->loopback_mode == LOOPBACK_MAC) {
1759 bmcr |= BMCR_LOOPBACK;
1760 if (lp->active_speed == SPEED_1000)
1761 bmcr |= BMCR_SPEED1000;
1762 if (lp->active_duplex == DUPLEX_FULL)
1763 bmcr |= BMCR_FULLDPLX;
1766 if (lp->loopback_mode == LOOPBACK_PHY) {
1769 aux = (BCM5464R_AUX_CTL_EXT_LB |
1770 BCM5464R_AUX_CTL_WRITE_1);
1771 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1779 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1780 if ((bmsr & BMSR_10HALF) &&
1781 (lp->advertising & ADVERTISED_10baseT_Half))
1782 adv |= ADVERTISE_10HALF;
1783 if ((bmsr & BMSR_10FULL) &&
1784 (lp->advertising & ADVERTISED_10baseT_Full))
1785 adv |= ADVERTISE_10FULL;
1786 if ((bmsr & BMSR_100HALF) &&
1787 (lp->advertising & ADVERTISED_100baseT_Half))
1788 adv |= ADVERTISE_100HALF;
1789 if ((bmsr & BMSR_100FULL) &&
1790 (lp->advertising & ADVERTISED_100baseT_Full))
1791 adv |= ADVERTISE_100FULL;
1792 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1796 if (likely(bmsr & BMSR_ESTATEN)) {
1798 if ((estat & ESTATUS_1000_THALF) &&
1799 (lp->advertising & ADVERTISED_1000baseT_Half))
1800 ctrl1000 |= ADVERTISE_1000HALF;
1801 if ((estat & ESTATUS_1000_TFULL) &&
1802 (lp->advertising & ADVERTISED_1000baseT_Full))
1803 ctrl1000 |= ADVERTISE_1000FULL;
1804 err = mii_write(np, np->phy_addr,
1805 MII_CTRL1000, ctrl1000);
1810 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1815 if (lp->duplex == DUPLEX_FULL) {
1816 bmcr |= BMCR_FULLDPLX;
1818 } else if (lp->duplex == DUPLEX_HALF)
1823 if (lp->speed == SPEED_1000) {
1824 /* if X-full requested while not supported, or
1825 X-half requested while not supported... */
1826 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1827 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1829 bmcr |= BMCR_SPEED1000;
1830 } else if (lp->speed == SPEED_100) {
1831 if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1832 (!fulldpx && !(bmsr & BMSR_100HALF)))
1834 bmcr |= BMCR_SPEED100;
1835 } else if (lp->speed == SPEED_10) {
1836 if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1837 (!fulldpx && !(bmsr & BMSR_10HALF)))
1843 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1848 err = mii_read(np, np->phy_addr, MII_BMCR);
1853 err = mii_read(np, np->phy_addr, MII_BMSR);
1858 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1859 np->port, bmcr, bmsr);
1865 static int xcvr_init_1g(struct niu *np)
1869 /* XXX shared resource, lock parent XXX */
1870 val = nr64(MIF_CONFIG);
1871 val &= ~MIF_CONFIG_INDIRECT_MODE;
1872 nw64(MIF_CONFIG, val);
1874 return mii_init_common(np);
1877 static int niu_xcvr_init(struct niu *np)
1879 const struct niu_phy_ops *ops = np->phy_ops;
1884 err = ops->xcvr_init(np);
1889 static int niu_serdes_init(struct niu *np)
1891 const struct niu_phy_ops *ops = np->phy_ops;
1895 if (ops->serdes_init)
1896 err = ops->serdes_init(np);
1901 static void niu_init_xif(struct niu *);
1902 static void niu_handle_led(struct niu *, int status);
1904 static int niu_link_status_common(struct niu *np, int link_up)
1906 struct niu_link_config *lp = &np->link_config;
1907 struct net_device *dev = np->dev;
1908 unsigned long flags;
1910 if (!netif_carrier_ok(dev) && link_up) {
1911 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1912 lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1913 lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1914 lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1916 lp->active_duplex == DUPLEX_FULL ? "full" : "half");
1918 spin_lock_irqsave(&np->lock, flags);
1920 niu_handle_led(np, 1);
1921 spin_unlock_irqrestore(&np->lock, flags);
1923 netif_carrier_on(dev);
1924 } else if (netif_carrier_ok(dev) && !link_up) {
1925 netif_warn(np, link, dev, "Link is down\n");
1926 spin_lock_irqsave(&np->lock, flags);
1927 niu_handle_led(np, 0);
1928 spin_unlock_irqrestore(&np->lock, flags);
1929 netif_carrier_off(dev);
1935 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1937 int err, link_up, pma_status, pcs_status;
1941 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1942 MRVL88X2011_10G_PMD_STATUS_2);
1946 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1947 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1948 MRVL88X2011_PMA_PMD_STATUS_1);
1952 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1954 /* Check PMC Register : 3.0001.2 == 1: read twice */
1955 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1956 MRVL88X2011_PMA_PMD_STATUS_1);
1960 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1961 MRVL88X2011_PMA_PMD_STATUS_1);
1965 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1967 /* Check XGXS Register : 4.0018.[0-3,12] */
1968 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1969 MRVL88X2011_10G_XGXS_LANE_STAT);
1973 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1974 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1975 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1977 link_up = (pma_status && pcs_status) ? 1 : 0;
1979 np->link_config.active_speed = SPEED_10000;
1980 np->link_config.active_duplex = DUPLEX_FULL;
1983 mrvl88x2011_act_led(np, (link_up ?
1984 MRVL88X2011_LED_CTL_PCS_ACT :
1985 MRVL88X2011_LED_CTL_OFF));
1987 *link_up_p = link_up;
1991 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
1996 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1997 BCM8704_PMD_RCV_SIGDET);
1998 if (err < 0 || err == 0xffff)
2000 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2005 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2006 BCM8704_PCS_10G_R_STATUS);
2010 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2015 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2016 BCM8704_PHYXS_XGXS_LANE_STAT);
2019 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2020 PHYXS_XGXS_LANE_STAT_MAGIC |
2021 PHYXS_XGXS_LANE_STAT_PATTEST |
2022 PHYXS_XGXS_LANE_STAT_LANE3 |
2023 PHYXS_XGXS_LANE_STAT_LANE2 |
2024 PHYXS_XGXS_LANE_STAT_LANE1 |
2025 PHYXS_XGXS_LANE_STAT_LANE0)) {
2027 np->link_config.active_speed = SPEED_INVALID;
2028 np->link_config.active_duplex = DUPLEX_INVALID;
2033 np->link_config.active_speed = SPEED_10000;
2034 np->link_config.active_duplex = DUPLEX_FULL;
2038 *link_up_p = link_up;
2042 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2048 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2049 BCM8704_PMD_RCV_SIGDET);
2052 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2057 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2058 BCM8704_PCS_10G_R_STATUS);
2061 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2066 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2067 BCM8704_PHYXS_XGXS_LANE_STAT);
2071 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2072 PHYXS_XGXS_LANE_STAT_MAGIC |
2073 PHYXS_XGXS_LANE_STAT_LANE3 |
2074 PHYXS_XGXS_LANE_STAT_LANE2 |
2075 PHYXS_XGXS_LANE_STAT_LANE1 |
2076 PHYXS_XGXS_LANE_STAT_LANE0)) {
2082 np->link_config.active_speed = SPEED_10000;
2083 np->link_config.active_duplex = DUPLEX_FULL;
2087 *link_up_p = link_up;
2091 static int link_status_10g(struct niu *np, int *link_up_p)
2093 unsigned long flags;
2096 spin_lock_irqsave(&np->lock, flags);
2098 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2101 phy_id = phy_decode(np->parent->port_phy, np->port);
2102 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2104 /* handle different phy types */
2105 switch (phy_id & NIU_PHY_ID_MASK) {
2106 case NIU_PHY_ID_MRVL88X2011:
2107 err = link_status_10g_mrvl(np, link_up_p);
2110 default: /* bcom 8704 */
2111 err = link_status_10g_bcom(np, link_up_p);
2116 spin_unlock_irqrestore(&np->lock, flags);
2121 static int niu_10g_phy_present(struct niu *np)
2125 sig = nr64(ESR_INT_SIGNALS);
2128 mask = ESR_INT_SIGNALS_P0_BITS;
2129 val = (ESR_INT_SRDY0_P0 |
2132 ESR_INT_XDP_P0_CH3 |
2133 ESR_INT_XDP_P0_CH2 |
2134 ESR_INT_XDP_P0_CH1 |
2135 ESR_INT_XDP_P0_CH0);
2139 mask = ESR_INT_SIGNALS_P1_BITS;
2140 val = (ESR_INT_SRDY0_P1 |
2143 ESR_INT_XDP_P1_CH3 |
2144 ESR_INT_XDP_P1_CH2 |
2145 ESR_INT_XDP_P1_CH1 |
2146 ESR_INT_XDP_P1_CH0);
2153 if ((sig & mask) != val)
2158 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2160 unsigned long flags;
2163 int phy_present_prev;
2165 spin_lock_irqsave(&np->lock, flags);
2167 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2168 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2170 phy_present = niu_10g_phy_present(np);
2171 if (phy_present != phy_present_prev) {
2174 /* A NEM was just plugged in */
2175 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2176 if (np->phy_ops->xcvr_init)
2177 err = np->phy_ops->xcvr_init(np);
2179 err = mdio_read(np, np->phy_addr,
2180 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2181 if (err == 0xffff) {
2182 /* No mdio, back-to-back XAUI */
2186 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2189 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2191 netif_warn(np, link, np->dev,
2192 "Hotplug PHY Removed\n");
2196 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
2197 err = link_status_10g_bcm8706(np, link_up_p);
2198 if (err == 0xffff) {
2199 /* No mdio, back-to-back XAUI: it is C10NEM */
2201 np->link_config.active_speed = SPEED_10000;
2202 np->link_config.active_duplex = DUPLEX_FULL;
2207 spin_unlock_irqrestore(&np->lock, flags);
2212 static int niu_link_status(struct niu *np, int *link_up_p)
2214 const struct niu_phy_ops *ops = np->phy_ops;
2218 if (ops->link_status)
2219 err = ops->link_status(np, link_up_p);
2224 static void niu_timer(unsigned long __opaque)
2226 struct niu *np = (struct niu *) __opaque;
2230 err = niu_link_status(np, &link_up);
2232 niu_link_status_common(np, link_up);
2234 if (netif_carrier_ok(np->dev))
2238 np->timer.expires = jiffies + off;
2240 add_timer(&np->timer);
2243 static const struct niu_phy_ops phy_ops_10g_serdes = {
2244 .serdes_init = serdes_init_10g_serdes,
2245 .link_status = link_status_10g_serdes,
2248 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2249 .serdes_init = serdes_init_niu_10g_serdes,
2250 .link_status = link_status_10g_serdes,
2253 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2254 .serdes_init = serdes_init_niu_1g_serdes,
2255 .link_status = link_status_1g_serdes,
2258 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2259 .xcvr_init = xcvr_init_1g_rgmii,
2260 .link_status = link_status_1g_rgmii,
2263 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2264 .serdes_init = serdes_init_niu_10g_fiber,
2265 .xcvr_init = xcvr_init_10g,
2266 .link_status = link_status_10g,
2269 static const struct niu_phy_ops phy_ops_10g_fiber = {
2270 .serdes_init = serdes_init_10g,
2271 .xcvr_init = xcvr_init_10g,
2272 .link_status = link_status_10g,
2275 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2276 .serdes_init = serdes_init_10g,
2277 .xcvr_init = xcvr_init_10g_bcm8706,
2278 .link_status = link_status_10g_hotplug,
2281 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2282 .serdes_init = serdes_init_niu_10g_fiber,
2283 .xcvr_init = xcvr_init_10g_bcm8706,
2284 .link_status = link_status_10g_hotplug,
2287 static const struct niu_phy_ops phy_ops_10g_copper = {
2288 .serdes_init = serdes_init_10g,
2289 .link_status = link_status_10g, /* XXX */
2292 static const struct niu_phy_ops phy_ops_1g_fiber = {
2293 .serdes_init = serdes_init_1g,
2294 .xcvr_init = xcvr_init_1g,
2295 .link_status = link_status_1g,
2298 static const struct niu_phy_ops phy_ops_1g_copper = {
2299 .xcvr_init = xcvr_init_1g,
2300 .link_status = link_status_1g,
2303 struct niu_phy_template {
2304 const struct niu_phy_ops *ops;
2308 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2309 .ops = &phy_ops_10g_fiber_niu,
2310 .phy_addr_base = 16,
2313 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2314 .ops = &phy_ops_10g_serdes_niu,
2318 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2319 .ops = &phy_ops_1g_serdes_niu,
2323 static const struct niu_phy_template phy_template_10g_fiber = {
2324 .ops = &phy_ops_10g_fiber,
2328 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2329 .ops = &phy_ops_10g_fiber_hotplug,
2333 static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2334 .ops = &phy_ops_niu_10g_hotplug,
2338 static const struct niu_phy_template phy_template_10g_copper = {
2339 .ops = &phy_ops_10g_copper,
2340 .phy_addr_base = 10,
2343 static const struct niu_phy_template phy_template_1g_fiber = {
2344 .ops = &phy_ops_1g_fiber,
2348 static const struct niu_phy_template phy_template_1g_copper = {
2349 .ops = &phy_ops_1g_copper,
2353 static const struct niu_phy_template phy_template_1g_rgmii = {
2354 .ops = &phy_ops_1g_rgmii,
2358 static const struct niu_phy_template phy_template_10g_serdes = {
2359 .ops = &phy_ops_10g_serdes,
2363 static int niu_atca_port_num[4] = {
2367 static int serdes_init_10g_serdes(struct niu *np)
2369 struct niu_link_config *lp = &np->link_config;
2370 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2371 u64 ctrl_val, test_cfg_val, sig, mask, val;
2375 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2376 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2377 pll_cfg = ENET_SERDES_0_PLL_CFG;
2380 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2381 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2382 pll_cfg = ENET_SERDES_1_PLL_CFG;
2388 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2389 ENET_SERDES_CTRL_SDET_1 |
2390 ENET_SERDES_CTRL_SDET_2 |
2391 ENET_SERDES_CTRL_SDET_3 |
2392 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2393 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2394 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2395 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2396 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2397 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2398 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2399 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2402 if (lp->loopback_mode == LOOPBACK_PHY) {
2403 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2404 ENET_SERDES_TEST_MD_0_SHIFT) |
2405 (ENET_TEST_MD_PAD_LOOPBACK <<
2406 ENET_SERDES_TEST_MD_1_SHIFT) |
2407 (ENET_TEST_MD_PAD_LOOPBACK <<
2408 ENET_SERDES_TEST_MD_2_SHIFT) |
2409 (ENET_TEST_MD_PAD_LOOPBACK <<
2410 ENET_SERDES_TEST_MD_3_SHIFT));
2414 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2415 nw64(ctrl_reg, ctrl_val);
2416 nw64(test_cfg_reg, test_cfg_val);
2418 /* Initialize all 4 lanes of the SERDES. */
2419 for (i = 0; i < 4; i++) {
2420 u32 rxtx_ctrl, glue0;
2423 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2426 err = esr_read_glue0(np, i, &glue0);
2430 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2431 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2432 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2434 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2435 ESR_GLUE_CTRL0_THCNT |
2436 ESR_GLUE_CTRL0_BLTIME);
2437 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2438 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2439 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2440 (BLTIME_300_CYCLES <<
2441 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2443 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2446 err = esr_write_glue0(np, i, glue0);
2452 sig = nr64(ESR_INT_SIGNALS);
2455 mask = ESR_INT_SIGNALS_P0_BITS;
2456 val = (ESR_INT_SRDY0_P0 |
2459 ESR_INT_XDP_P0_CH3 |
2460 ESR_INT_XDP_P0_CH2 |
2461 ESR_INT_XDP_P0_CH1 |
2462 ESR_INT_XDP_P0_CH0);
2466 mask = ESR_INT_SIGNALS_P1_BITS;
2467 val = (ESR_INT_SRDY0_P1 |
2470 ESR_INT_XDP_P1_CH3 |
2471 ESR_INT_XDP_P1_CH2 |
2472 ESR_INT_XDP_P1_CH1 |
2473 ESR_INT_XDP_P1_CH0);
2480 if ((sig & mask) != val) {
2482 err = serdes_init_1g_serdes(np);
2484 np->flags &= ~NIU_FLAGS_10G;
2485 np->mac_xcvr = MAC_XCVR_PCS;
2487 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2496 static int niu_determine_phy_disposition(struct niu *np)
2498 struct niu_parent *parent = np->parent;
2499 u8 plat_type = parent->plat_type;
2500 const struct niu_phy_template *tp;
2501 u32 phy_addr_off = 0;
2503 if (plat_type == PLAT_TYPE_NIU) {
2507 NIU_FLAGS_XCVR_SERDES)) {
2508 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2510 tp = &phy_template_niu_10g_serdes;
2512 case NIU_FLAGS_XCVR_SERDES:
2514 tp = &phy_template_niu_1g_serdes;
2516 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2519 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2520 tp = &phy_template_niu_10g_hotplug;
2526 tp = &phy_template_niu_10g_fiber;
2527 phy_addr_off += np->port;
2535 NIU_FLAGS_XCVR_SERDES)) {
2538 tp = &phy_template_1g_copper;
2539 if (plat_type == PLAT_TYPE_VF_P0)
2541 else if (plat_type == PLAT_TYPE_VF_P1)
2544 phy_addr_off += (np->port ^ 0x3);
2549 tp = &phy_template_10g_copper;
2552 case NIU_FLAGS_FIBER:
2554 tp = &phy_template_1g_fiber;
2557 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2559 tp = &phy_template_10g_fiber;
2560 if (plat_type == PLAT_TYPE_VF_P0 ||
2561 plat_type == PLAT_TYPE_VF_P1)
2563 phy_addr_off += np->port;
2564 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2565 tp = &phy_template_10g_fiber_hotplug;
2573 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2574 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2575 case NIU_FLAGS_XCVR_SERDES:
2579 tp = &phy_template_10g_serdes;
2583 tp = &phy_template_1g_rgmii;
2588 phy_addr_off = niu_atca_port_num[np->port];
2596 np->phy_ops = tp->ops;
2597 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2602 static int niu_init_link(struct niu *np)
2604 struct niu_parent *parent = np->parent;
2607 if (parent->plat_type == PLAT_TYPE_NIU) {
2608 err = niu_xcvr_init(np);
2613 err = niu_serdes_init(np);
2614 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2617 err = niu_xcvr_init(np);
2618 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2619 niu_link_status(np, &ignore);
2623 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2625 u16 reg0 = addr[4] << 8 | addr[5];
2626 u16 reg1 = addr[2] << 8 | addr[3];
2627 u16 reg2 = addr[0] << 8 | addr[1];
2629 if (np->flags & NIU_FLAGS_XMAC) {
2630 nw64_mac(XMAC_ADDR0, reg0);
2631 nw64_mac(XMAC_ADDR1, reg1);
2632 nw64_mac(XMAC_ADDR2, reg2);
2634 nw64_mac(BMAC_ADDR0, reg0);
2635 nw64_mac(BMAC_ADDR1, reg1);
2636 nw64_mac(BMAC_ADDR2, reg2);
2640 static int niu_num_alt_addr(struct niu *np)
2642 if (np->flags & NIU_FLAGS_XMAC)
2643 return XMAC_NUM_ALT_ADDR;
2645 return BMAC_NUM_ALT_ADDR;
2648 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2650 u16 reg0 = addr[4] << 8 | addr[5];
2651 u16 reg1 = addr[2] << 8 | addr[3];
2652 u16 reg2 = addr[0] << 8 | addr[1];
2654 if (index >= niu_num_alt_addr(np))
2657 if (np->flags & NIU_FLAGS_XMAC) {
2658 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2659 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2660 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2662 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2663 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2664 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2670 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2675 if (index >= niu_num_alt_addr(np))
2678 if (np->flags & NIU_FLAGS_XMAC) {
2679 reg = XMAC_ADDR_CMPEN;
2682 reg = BMAC_ADDR_CMPEN;
2683 mask = 1 << (index + 1);
2686 val = nr64_mac(reg);
2696 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2697 int num, int mac_pref)
2699 u64 val = nr64_mac(reg);
2700 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2703 val |= HOST_INFO_MPR;
2707 static int __set_rdc_table_num(struct niu *np,
2708 int xmac_index, int bmac_index,
2709 int rdc_table_num, int mac_pref)
2713 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2715 if (np->flags & NIU_FLAGS_XMAC)
2716 reg = XMAC_HOST_INFO(xmac_index);
2718 reg = BMAC_HOST_INFO(bmac_index);
2719 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2723 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2726 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2729 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2732 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2735 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2736 int table_num, int mac_pref)
2738 if (idx >= niu_num_alt_addr(np))
2740 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2743 static u64 vlan_entry_set_parity(u64 reg_val)
2748 port01_mask = 0x00ff;
2749 port23_mask = 0xff00;
2751 if (hweight64(reg_val & port01_mask) & 1)
2752 reg_val |= ENET_VLAN_TBL_PARITY0;
2754 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2756 if (hweight64(reg_val & port23_mask) & 1)
2757 reg_val |= ENET_VLAN_TBL_PARITY1;
2759 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2764 static void vlan_tbl_write(struct niu *np, unsigned long index,
2765 int port, int vpr, int rdc_table)
2767 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2769 reg_val &= ~((ENET_VLAN_TBL_VPR |
2770 ENET_VLAN_TBL_VLANRDCTBLN) <<
2771 ENET_VLAN_TBL_SHIFT(port));
2773 reg_val |= (ENET_VLAN_TBL_VPR <<
2774 ENET_VLAN_TBL_SHIFT(port));
2775 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2777 reg_val = vlan_entry_set_parity(reg_val);
2779 nw64(ENET_VLAN_TBL(index), reg_val);
2782 static void vlan_tbl_clear(struct niu *np)
2786 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2787 nw64(ENET_VLAN_TBL(i), 0);
2790 static int tcam_wait_bit(struct niu *np, u64 bit)
2794 while (--limit > 0) {
2795 if (nr64(TCAM_CTL) & bit)
2805 static int tcam_flush(struct niu *np, int index)
2807 nw64(TCAM_KEY_0, 0x00);
2808 nw64(TCAM_KEY_MASK_0, 0xff);
2809 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2811 return tcam_wait_bit(np, TCAM_CTL_STAT);
2815 static int tcam_read(struct niu *np, int index,
2816 u64 *key, u64 *mask)
2820 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2821 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2823 key[0] = nr64(TCAM_KEY_0);
2824 key[1] = nr64(TCAM_KEY_1);
2825 key[2] = nr64(TCAM_KEY_2);
2826 key[3] = nr64(TCAM_KEY_3);
2827 mask[0] = nr64(TCAM_KEY_MASK_0);
2828 mask[1] = nr64(TCAM_KEY_MASK_1);
2829 mask[2] = nr64(TCAM_KEY_MASK_2);
2830 mask[3] = nr64(TCAM_KEY_MASK_3);
2836 static int tcam_write(struct niu *np, int index,
2837 u64 *key, u64 *mask)
2839 nw64(TCAM_KEY_0, key[0]);
2840 nw64(TCAM_KEY_1, key[1]);
2841 nw64(TCAM_KEY_2, key[2]);
2842 nw64(TCAM_KEY_3, key[3]);
2843 nw64(TCAM_KEY_MASK_0, mask[0]);
2844 nw64(TCAM_KEY_MASK_1, mask[1]);
2845 nw64(TCAM_KEY_MASK_2, mask[2]);
2846 nw64(TCAM_KEY_MASK_3, mask[3]);
2847 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2849 return tcam_wait_bit(np, TCAM_CTL_STAT);
2853 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2857 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2858 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2860 *data = nr64(TCAM_KEY_1);
2866 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2868 nw64(TCAM_KEY_1, assoc_data);
2869 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2871 return tcam_wait_bit(np, TCAM_CTL_STAT);
2874 static void tcam_enable(struct niu *np, int on)
2876 u64 val = nr64(FFLP_CFG_1);
2879 val &= ~FFLP_CFG_1_TCAM_DIS;
2881 val |= FFLP_CFG_1_TCAM_DIS;
2882 nw64(FFLP_CFG_1, val);
2885 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2887 u64 val = nr64(FFLP_CFG_1);
2889 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2891 FFLP_CFG_1_CAMRATIO);
2892 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2893 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2894 nw64(FFLP_CFG_1, val);
2896 val = nr64(FFLP_CFG_1);
2897 val |= FFLP_CFG_1_FFLPINITDONE;
2898 nw64(FFLP_CFG_1, val);
2901 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2907 if (class < CLASS_CODE_ETHERTYPE1 ||
2908 class > CLASS_CODE_ETHERTYPE2)
2911 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2923 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2929 if (class < CLASS_CODE_ETHERTYPE1 ||
2930 class > CLASS_CODE_ETHERTYPE2 ||
2931 (ether_type & ~(u64)0xffff) != 0)
2934 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2936 val &= ~L2_CLS_ETYPE;
2937 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2944 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2950 if (class < CLASS_CODE_USER_PROG1 ||
2951 class > CLASS_CODE_USER_PROG4)
2954 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2957 val |= L3_CLS_VALID;
2959 val &= ~L3_CLS_VALID;
2965 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2966 int ipv6, u64 protocol_id,
2967 u64 tos_mask, u64 tos_val)
2972 if (class < CLASS_CODE_USER_PROG1 ||
2973 class > CLASS_CODE_USER_PROG4 ||
2974 (protocol_id & ~(u64)0xff) != 0 ||
2975 (tos_mask & ~(u64)0xff) != 0 ||
2976 (tos_val & ~(u64)0xff) != 0)
2979 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2981 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2982 L3_CLS_TOSMASK | L3_CLS_TOS);
2984 val |= L3_CLS_IPVER;
2985 val |= (protocol_id << L3_CLS_PID_SHIFT);
2986 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2987 val |= (tos_val << L3_CLS_TOS_SHIFT);
2993 static int tcam_early_init(struct niu *np)
2999 tcam_set_lat_and_ratio(np,
3000 DEFAULT_TCAM_LATENCY,
3001 DEFAULT_TCAM_ACCESS_RATIO);
3002 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3003 err = tcam_user_eth_class_enable(np, i, 0);
3007 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3008 err = tcam_user_ip_class_enable(np, i, 0);
3016 static int tcam_flush_all(struct niu *np)
3020 for (i = 0; i < np->parent->tcam_num_entries; i++) {
3021 int err = tcam_flush(np, i);
3028 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3030 return (u64)index | (num_entries == 1 ? HASH_TBL_ADDR_AUTOINC : 0);
3034 static int hash_read(struct niu *np, unsigned long partition,
3035 unsigned long index, unsigned long num_entries,
3038 u64 val = hash_addr_regval(index, num_entries);
3041 if (partition >= FCRAM_NUM_PARTITIONS ||
3042 index + num_entries > FCRAM_SIZE)
3045 nw64(HASH_TBL_ADDR(partition), val);
3046 for (i = 0; i < num_entries; i++)
3047 data[i] = nr64(HASH_TBL_DATA(partition));
3053 static int hash_write(struct niu *np, unsigned long partition,
3054 unsigned long index, unsigned long num_entries,
3057 u64 val = hash_addr_regval(index, num_entries);
3060 if (partition >= FCRAM_NUM_PARTITIONS ||
3061 index + (num_entries * 8) > FCRAM_SIZE)
3064 nw64(HASH_TBL_ADDR(partition), val);
3065 for (i = 0; i < num_entries; i++)
3066 nw64(HASH_TBL_DATA(partition), data[i]);
3071 static void fflp_reset(struct niu *np)
3075 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3077 nw64(FFLP_CFG_1, 0);
3079 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3080 nw64(FFLP_CFG_1, val);
3083 static void fflp_set_timings(struct niu *np)
3085 u64 val = nr64(FFLP_CFG_1);
3087 val &= ~FFLP_CFG_1_FFLPINITDONE;
3088 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3089 nw64(FFLP_CFG_1, val);
3091 val = nr64(FFLP_CFG_1);
3092 val |= FFLP_CFG_1_FFLPINITDONE;
3093 nw64(FFLP_CFG_1, val);
3095 val = nr64(FCRAM_REF_TMR);
3096 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3097 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3098 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3099 nw64(FCRAM_REF_TMR, val);
3102 static int fflp_set_partition(struct niu *np, u64 partition,
3103 u64 mask, u64 base, int enable)
3108 if (partition >= FCRAM_NUM_PARTITIONS ||
3109 (mask & ~(u64)0x1f) != 0 ||
3110 (base & ~(u64)0x1f) != 0)
3113 reg = FLW_PRT_SEL(partition);
3116 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3117 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3118 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3120 val |= FLW_PRT_SEL_EXT;
3126 static int fflp_disable_all_partitions(struct niu *np)
3130 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3131 int err = fflp_set_partition(np, 0, 0, 0, 0);
3138 static void fflp_llcsnap_enable(struct niu *np, int on)
3140 u64 val = nr64(FFLP_CFG_1);
3143 val |= FFLP_CFG_1_LLCSNAP;
3145 val &= ~FFLP_CFG_1_LLCSNAP;
3146 nw64(FFLP_CFG_1, val);
3149 static void fflp_errors_enable(struct niu *np, int on)
3151 u64 val = nr64(FFLP_CFG_1);
3154 val &= ~FFLP_CFG_1_ERRORDIS;
3156 val |= FFLP_CFG_1_ERRORDIS;
3157 nw64(FFLP_CFG_1, val);
3160 static int fflp_hash_clear(struct niu *np)
3162 struct fcram_hash_ipv4 ent;
3165 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3166 memset(&ent, 0, sizeof(ent));
3167 ent.header = HASH_HEADER_EXT;
3169 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3170 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3177 static int fflp_early_init(struct niu *np)
3179 struct niu_parent *parent;
3180 unsigned long flags;
3183 niu_lock_parent(np, flags);
3185 parent = np->parent;
3187 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3188 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3190 fflp_set_timings(np);
3191 err = fflp_disable_all_partitions(np);
3193 netif_printk(np, probe, KERN_DEBUG, np->dev,
3194 "fflp_disable_all_partitions failed, err=%d\n",
3200 err = tcam_early_init(np);
3202 netif_printk(np, probe, KERN_DEBUG, np->dev,
3203 "tcam_early_init failed, err=%d\n", err);
3206 fflp_llcsnap_enable(np, 1);
3207 fflp_errors_enable(np, 0);
3211 err = tcam_flush_all(np);
3213 netif_printk(np, probe, KERN_DEBUG, np->dev,
3214 "tcam_flush_all failed, err=%d\n", err);
3217 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3218 err = fflp_hash_clear(np);
3220 netif_printk(np, probe, KERN_DEBUG, np->dev,
3221 "fflp_hash_clear failed, err=%d\n",
3229 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3232 niu_unlock_parent(np, flags);
3236 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3238 if (class_code < CLASS_CODE_USER_PROG1 ||
3239 class_code > CLASS_CODE_SCTP_IPV6)
3242 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3246 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3248 if (class_code < CLASS_CODE_USER_PROG1 ||
3249 class_code > CLASS_CODE_SCTP_IPV6)
3252 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3256 /* Entries for the ports are interleaved in the TCAM */
3257 static u16 tcam_get_index(struct niu *np, u16 idx)
3259 /* One entry reserved for IP fragment rule */
3260 if (idx >= (np->clas.tcam_sz - 1))
3262 return np->clas.tcam_top + ((idx+1) * np->parent->num_ports);
3265 static u16 tcam_get_size(struct niu *np)
3267 /* One entry reserved for IP fragment rule */
3268 return np->clas.tcam_sz - 1;
3271 static u16 tcam_get_valid_entry_cnt(struct niu *np)
3273 /* One entry reserved for IP fragment rule */
3274 return np->clas.tcam_valid_entries - 1;
3277 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3278 u32 offset, u32 size, u32 truesize)
3280 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, offset, size);
3283 skb->data_len += size;
3284 skb->truesize += truesize;
3287 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3290 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3292 return a & (MAX_RBR_RING_SIZE - 1);
3295 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3296 struct page ***link)
3298 unsigned int h = niu_hash_rxaddr(rp, addr);
3299 struct page *p, **pp;
3302 pp = &rp->rxhash[h];
3303 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3304 if (p->index == addr) {
3315 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3317 unsigned int h = niu_hash_rxaddr(rp, base);
3320 page->mapping = (struct address_space *) rp->rxhash[h];
3321 rp->rxhash[h] = page;
3324 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3325 gfp_t mask, int start_index)
3331 page = alloc_page(mask);
3335 addr = np->ops->map_page(np->device, page, 0,
3336 PAGE_SIZE, DMA_FROM_DEVICE);
3342 niu_hash_page(rp, page, addr);
3343 if (rp->rbr_blocks_per_page > 1)
3344 page_ref_add(page, rp->rbr_blocks_per_page - 1);
3346 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3347 __le32 *rbr = &rp->rbr[start_index + i];
3349 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3350 addr += rp->rbr_block_size;
3356 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3358 int index = rp->rbr_index;
3361 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3362 int err = niu_rbr_add_page(np, rp, mask, index);
3364 if (unlikely(err)) {
3369 rp->rbr_index += rp->rbr_blocks_per_page;
3370 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3371 if (rp->rbr_index == rp->rbr_table_size)
3374 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3375 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3376 rp->rbr_pending = 0;
3381 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3383 unsigned int index = rp->rcr_index;
3388 struct page *page, **link;
3394 val = le64_to_cpup(&rp->rcr[index]);
3395 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3396 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3397 page = niu_find_rxpage(rp, addr, &link);
3399 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3400 RCR_ENTRY_PKTBUFSZ_SHIFT];
3401 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3402 *link = (struct page *) page->mapping;
3403 np->ops->unmap_page(np->device, page->index,
3404 PAGE_SIZE, DMA_FROM_DEVICE);
3406 page->mapping = NULL;
3408 rp->rbr_refill_pending++;
3411 index = NEXT_RCR(rp, index);
3412 if (!(val & RCR_ENTRY_MULTI))
3416 rp->rcr_index = index;
3421 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3422 struct rx_ring_info *rp)
3424 unsigned int index = rp->rcr_index;
3425 struct rx_pkt_hdr1 *rh;
3426 struct sk_buff *skb;
3429 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3431 return niu_rx_pkt_ignore(np, rp);
3435 struct page *page, **link;
3436 u32 rcr_size, append_size;
3441 val = le64_to_cpup(&rp->rcr[index]);
3443 len = (val & RCR_ENTRY_L2_LEN) >>
3444 RCR_ENTRY_L2_LEN_SHIFT;
3445 append_size = len + ETH_HLEN + ETH_FCS_LEN;
3447 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3448 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3449 page = niu_find_rxpage(rp, addr, &link);
3451 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3452 RCR_ENTRY_PKTBUFSZ_SHIFT];
3454 off = addr & ~PAGE_MASK;
3458 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3459 if ((ptype == RCR_PKT_TYPE_TCP ||
3460 ptype == RCR_PKT_TYPE_UDP) &&
3461 !(val & (RCR_ENTRY_NOPORT |
3463 skb->ip_summed = CHECKSUM_UNNECESSARY;
3465 skb_checksum_none_assert(skb);
3466 } else if (!(val & RCR_ENTRY_MULTI))
3467 append_size = append_size - skb->len;
3469 niu_rx_skb_append(skb, page, off, append_size, rcr_size);
3470 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3471 *link = (struct page *) page->mapping;
3472 np->ops->unmap_page(np->device, page->index,
3473 PAGE_SIZE, DMA_FROM_DEVICE);
3475 page->mapping = NULL;
3476 rp->rbr_refill_pending++;
3480 index = NEXT_RCR(rp, index);
3481 if (!(val & RCR_ENTRY_MULTI))
3485 rp->rcr_index = index;
3488 len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN);
3489 __pskb_pull_tail(skb, len);
3491 rh = (struct rx_pkt_hdr1 *) skb->data;
3492 if (np->dev->features & NETIF_F_RXHASH)
3494 ((u32)rh->hashval2_0 << 24 |
3495 (u32)rh->hashval2_1 << 16 |
3496 (u32)rh->hashval1_1 << 8 |
3497 (u32)rh->hashval1_2 << 0),
3499 skb_pull(skb, sizeof(*rh));
3502 rp->rx_bytes += skb->len;
3504 skb->protocol = eth_type_trans(skb, np->dev);
3505 skb_record_rx_queue(skb, rp->rx_channel);
3506 napi_gro_receive(napi, skb);
3511 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3513 int blocks_per_page = rp->rbr_blocks_per_page;
3514 int err, index = rp->rbr_index;
3517 while (index < (rp->rbr_table_size - blocks_per_page)) {
3518 err = niu_rbr_add_page(np, rp, mask, index);
3522 index += blocks_per_page;
3525 rp->rbr_index = index;
3529 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3533 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3536 page = rp->rxhash[i];
3538 struct page *next = (struct page *) page->mapping;
3539 u64 base = page->index;
3541 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3544 page->mapping = NULL;
3552 for (i = 0; i < rp->rbr_table_size; i++)
3553 rp->rbr[i] = cpu_to_le32(0);
3557 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3559 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3560 struct sk_buff *skb = tb->skb;
3561 struct tx_pkt_hdr *tp;
3565 tp = (struct tx_pkt_hdr *) skb->data;
3566 tx_flags = le64_to_cpup(&tp->flags);
3569 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3570 ((tx_flags & TXHDR_PAD) / 2));
3572 len = skb_headlen(skb);
3573 np->ops->unmap_single(np->device, tb->mapping,
3574 len, DMA_TO_DEVICE);
3576 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3581 idx = NEXT_TX(rp, idx);
3582 len -= MAX_TX_DESC_LEN;
3585 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3586 tb = &rp->tx_buffs[idx];
3587 BUG_ON(tb->skb != NULL);
3588 np->ops->unmap_page(np->device, tb->mapping,
3589 skb_frag_size(&skb_shinfo(skb)->frags[i]),
3591 idx = NEXT_TX(rp, idx);
3599 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3601 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3603 struct netdev_queue *txq;
3608 index = (rp - np->tx_rings);
3609 txq = netdev_get_tx_queue(np->dev, index);
3612 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3615 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3616 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3617 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3619 rp->last_pkt_cnt = tmp;
3623 netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3624 "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
3627 cons = release_tx_packet(np, rp, cons);
3633 if (unlikely(netif_tx_queue_stopped(txq) &&
3634 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3635 __netif_tx_lock(txq, smp_processor_id());
3636 if (netif_tx_queue_stopped(txq) &&
3637 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3638 netif_tx_wake_queue(txq);
3639 __netif_tx_unlock(txq);
3643 static inline void niu_sync_rx_discard_stats(struct niu *np,
3644 struct rx_ring_info *rp,
3647 /* This elaborate scheme is needed for reading the RX discard
3648 * counters, as they are only 16-bit and can overflow quickly,
3649 * and because the overflow indication bit is not usable as
3650 * the counter value does not wrap, but remains at max value
3653 * In theory and in practice counters can be lost in between
3654 * reading nr64() and clearing the counter nw64(). For this
3655 * reason, the number of counter clearings nw64() is
3656 * limited/reduced though the limit parameter.
3658 int rx_channel = rp->rx_channel;
3661 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3662 * following discard events: IPP (Input Port Process),
3663 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3664 * Block Ring) prefetch buffer is empty.
3666 misc = nr64(RXMISC(rx_channel));
3667 if (unlikely((misc & RXMISC_COUNT) > limit)) {
3668 nw64(RXMISC(rx_channel), 0);
3669 rp->rx_errors += misc & RXMISC_COUNT;
3671 if (unlikely(misc & RXMISC_OFLOW))
3672 dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3675 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3676 "rx-%d: MISC drop=%u over=%u\n",
3677 rx_channel, misc, misc-limit);
3680 /* WRED (Weighted Random Early Discard) by hardware */
3681 wred = nr64(RED_DIS_CNT(rx_channel));
3682 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3683 nw64(RED_DIS_CNT(rx_channel), 0);
3684 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3686 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3687 dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
3689 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3690 "rx-%d: WRED drop=%u over=%u\n",
3691 rx_channel, wred, wred-limit);
3695 static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3696 struct rx_ring_info *rp, int budget)
3698 int qlen, rcr_done = 0, work_done = 0;
3699 struct rxdma_mailbox *mbox = rp->mbox;
3703 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3704 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3706 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3707 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3709 mbox->rx_dma_ctl_stat = 0;
3710 mbox->rcrstat_a = 0;
3712 netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3713 "%s(chan[%d]), stat[%llx] qlen=%d\n",
3714 __func__, rp->rx_channel, (unsigned long long)stat, qlen);
3716 rcr_done = work_done = 0;
3717 qlen = min(qlen, budget);
3718 while (work_done < qlen) {
3719 rcr_done += niu_process_rx_pkt(napi, np, rp);
3723 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3726 for (i = 0; i < rp->rbr_refill_pending; i++)
3727 niu_rbr_refill(np, rp, GFP_ATOMIC);
3728 rp->rbr_refill_pending = 0;
3731 stat = (RX_DMA_CTL_STAT_MEX |
3732 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3733 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3735 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3737 /* Only sync discards stats when qlen indicate potential for drops */
3739 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3744 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3747 u32 tx_vec = (v0 >> 32);
3748 u32 rx_vec = (v0 & 0xffffffff);
3749 int i, work_done = 0;
3751 netif_printk(np, intr, KERN_DEBUG, np->dev,
3752 "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
3754 for (i = 0; i < np->num_tx_rings; i++) {
3755 struct tx_ring_info *rp = &np->tx_rings[i];
3756 if (tx_vec & (1 << rp->tx_channel))
3757 niu_tx_work(np, rp);
3758 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3761 for (i = 0; i < np->num_rx_rings; i++) {
3762 struct rx_ring_info *rp = &np->rx_rings[i];
3764 if (rx_vec & (1 << rp->rx_channel)) {
3767 this_work_done = niu_rx_work(&lp->napi, np, rp,
3770 budget -= this_work_done;
3771 work_done += this_work_done;
3773 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3779 static int niu_poll(struct napi_struct *napi, int budget)
3781 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3782 struct niu *np = lp->np;
3785 work_done = niu_poll_core(np, lp, budget);
3787 if (work_done < budget) {
3788 napi_complete_done(napi, work_done);
3789 niu_ldg_rearm(np, lp, 1);
3794 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3797 netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
3799 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3800 pr_cont("RBR_TMOUT ");
3801 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3802 pr_cont("RSP_CNT ");
3803 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3804 pr_cont("BYTE_EN_BUS ");
3805 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3806 pr_cont("RSP_DAT ");
3807 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3808 pr_cont("RCR_ACK ");
3809 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3810 pr_cont("RCR_SHA_PAR ");
3811 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3812 pr_cont("RBR_PRE_PAR ");
3813 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3815 if (stat & RX_DMA_CTL_STAT_RCRINCON)
3816 pr_cont("RCRINCON ");
3817 if (stat & RX_DMA_CTL_STAT_RCRFULL)
3818 pr_cont("RCRFULL ");
3819 if (stat & RX_DMA_CTL_STAT_RBRFULL)
3820 pr_cont("RBRFULL ");
3821 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3822 pr_cont("RBRLOGPAGE ");
3823 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3824 pr_cont("CFIGLOGPAGE ");
3825 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3826 pr_cont("DC_FIDO ");
3831 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3833 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3837 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3838 RX_DMA_CTL_STAT_PORT_FATAL))
3842 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3844 (unsigned long long) stat);
3846 niu_log_rxchan_errors(np, rp, stat);
3849 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3850 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3855 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3858 netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
3860 if (cs & TX_CS_MBOX_ERR)
3862 if (cs & TX_CS_PKT_SIZE_ERR)
3863 pr_cont("PKT_SIZE ");
3864 if (cs & TX_CS_TX_RING_OFLOW)
3865 pr_cont("TX_RING_OFLOW ");
3866 if (cs & TX_CS_PREF_BUF_PAR_ERR)
3867 pr_cont("PREF_BUF_PAR ");
3868 if (cs & TX_CS_NACK_PREF)
3869 pr_cont("NACK_PREF ");
3870 if (cs & TX_CS_NACK_PKT_RD)
3871 pr_cont("NACK_PKT_RD ");
3872 if (cs & TX_CS_CONF_PART_ERR)
3873 pr_cont("CONF_PART ");
3874 if (cs & TX_CS_PKT_PRT_ERR)
3875 pr_cont("PKT_PTR ");
3880 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3884 cs = nr64(TX_CS(rp->tx_channel));
3885 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3886 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3888 netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3890 (unsigned long long)cs,
3891 (unsigned long long)logh,
3892 (unsigned long long)logl);
3894 niu_log_txchan_errors(np, rp, cs);
3899 static int niu_mif_interrupt(struct niu *np)
3901 u64 mif_status = nr64(MIF_STATUS);
3904 if (np->flags & NIU_FLAGS_XMAC) {
3905 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3907 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3911 netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3912 (unsigned long long)mif_status, phy_mdint);
3917 static void niu_xmac_interrupt(struct niu *np)
3919 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3922 val = nr64_mac(XTXMAC_STATUS);
3923 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3924 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3925 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3926 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3927 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3928 mp->tx_fifo_errors++;
3929 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3930 mp->tx_overflow_errors++;
3931 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3932 mp->tx_max_pkt_size_errors++;
3933 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3934 mp->tx_underflow_errors++;
3936 val = nr64_mac(XRXMAC_STATUS);
3937 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3938 mp->rx_local_faults++;
3939 if (val & XRXMAC_STATUS_RFLT_DET)
3940 mp->rx_remote_faults++;
3941 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3942 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3943 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3944 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3945 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3946 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3947 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3948 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3949 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3950 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3951 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3952 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3953 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3954 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3955 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3956 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3957 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3958 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3959 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3960 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3961 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3962 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3963 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3964 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3965 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
3966 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3967 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3968 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3969 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3970 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3971 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3972 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3973 if (val & XRXMAC_STATUS_RXUFLOW)
3974 mp->rx_underflows++;
3975 if (val & XRXMAC_STATUS_RXOFLOW)
3978 val = nr64_mac(XMAC_FC_STAT);
3979 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3980 mp->pause_off_state++;
3981 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3982 mp->pause_on_state++;
3983 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3984 mp->pause_received++;
3987 static void niu_bmac_interrupt(struct niu *np)
3989 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
3992 val = nr64_mac(BTXMAC_STATUS);
3993 if (val & BTXMAC_STATUS_UNDERRUN)
3994 mp->tx_underflow_errors++;
3995 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
3996 mp->tx_max_pkt_size_errors++;
3997 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
3998 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
3999 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4000 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4002 val = nr64_mac(BRXMAC_STATUS);
4003 if (val & BRXMAC_STATUS_OVERFLOW)
4005 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4006 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4007 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4008 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4009 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4010 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4011 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4012 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4014 val = nr64_mac(BMAC_CTRL_STATUS);
4015 if (val & BMAC_CTRL_STATUS_NOPAUSE)
4016 mp->pause_off_state++;
4017 if (val & BMAC_CTRL_STATUS_PAUSE)
4018 mp->pause_on_state++;
4019 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4020 mp->pause_received++;
4023 static int niu_mac_interrupt(struct niu *np)
4025 if (np->flags & NIU_FLAGS_XMAC)
4026 niu_xmac_interrupt(np);
4028 niu_bmac_interrupt(np);
4033 static void niu_log_device_error(struct niu *np, u64 stat)
4035 netdev_err(np->dev, "Core device errors ( ");
4037 if (stat & SYS_ERR_MASK_META2)
4039 if (stat & SYS_ERR_MASK_META1)
4041 if (stat & SYS_ERR_MASK_PEU)
4043 if (stat & SYS_ERR_MASK_TXC)
4045 if (stat & SYS_ERR_MASK_RDMC)
4047 if (stat & SYS_ERR_MASK_TDMC)
4049 if (stat & SYS_ERR_MASK_ZCP)
4051 if (stat & SYS_ERR_MASK_FFLP)
4053 if (stat & SYS_ERR_MASK_IPP)
4055 if (stat & SYS_ERR_MASK_MAC)
4057 if (stat & SYS_ERR_MASK_SMX)
4063 static int niu_device_error(struct niu *np)
4065 u64 stat = nr64(SYS_ERR_STAT);
4067 netdev_err(np->dev, "Core device error, stat[%llx]\n",
4068 (unsigned long long)stat);
4070 niu_log_device_error(np, stat);
4075 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4076 u64 v0, u64 v1, u64 v2)
4085 if (v1 & 0x00000000ffffffffULL) {
4086 u32 rx_vec = (v1 & 0xffffffff);
4088 for (i = 0; i < np->num_rx_rings; i++) {
4089 struct rx_ring_info *rp = &np->rx_rings[i];
4091 if (rx_vec & (1 << rp->rx_channel)) {
4092 int r = niu_rx_error(np, rp);
4097 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4098 RX_DMA_CTL_STAT_MEX);
4103 if (v1 & 0x7fffffff00000000ULL) {
4104 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4106 for (i = 0; i < np->num_tx_rings; i++) {
4107 struct tx_ring_info *rp = &np->tx_rings[i];
4109 if (tx_vec & (1 << rp->tx_channel)) {
4110 int r = niu_tx_error(np, rp);
4116 if ((v0 | v1) & 0x8000000000000000ULL) {
4117 int r = niu_mif_interrupt(np);
4123 int r = niu_mac_interrupt(np);
4128 int r = niu_device_error(np);
4135 niu_enable_interrupts(np, 0);
4140 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4143 struct rxdma_mailbox *mbox = rp->mbox;
4144 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4146 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4147 RX_DMA_CTL_STAT_RCRTO);
4148 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4150 netif_printk(np, intr, KERN_DEBUG, np->dev,
4151 "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
4154 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4157 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4159 netif_printk(np, intr, KERN_DEBUG, np->dev,
4160 "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
4163 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4165 struct niu_parent *parent = np->parent;
4169 tx_vec = (v0 >> 32);
4170 rx_vec = (v0 & 0xffffffff);
4172 for (i = 0; i < np->num_rx_rings; i++) {
4173 struct rx_ring_info *rp = &np->rx_rings[i];
4174 int ldn = LDN_RXDMA(rp->rx_channel);
4176 if (parent->ldg_map[ldn] != ldg)
4179 nw64(LD_IM0(ldn), LD_IM0_MASK);
4180 if (rx_vec & (1 << rp->rx_channel))
4181 niu_rxchan_intr(np, rp, ldn);
4184 for (i = 0; i < np->num_tx_rings; i++) {
4185 struct tx_ring_info *rp = &np->tx_rings[i];
4186 int ldn = LDN_TXDMA(rp->tx_channel);
4188 if (parent->ldg_map[ldn] != ldg)
4191 nw64(LD_IM0(ldn), LD_IM0_MASK);
4192 if (tx_vec & (1 << rp->tx_channel))
4193 niu_txchan_intr(np, rp, ldn);
4197 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4198 u64 v0, u64 v1, u64 v2)
4200 if (likely(napi_schedule_prep(&lp->napi))) {
4204 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4205 __napi_schedule(&lp->napi);
4209 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4211 struct niu_ldg *lp = dev_id;
4212 struct niu *np = lp->np;
4213 int ldg = lp->ldg_num;
4214 unsigned long flags;
4217 if (netif_msg_intr(np))
4218 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4221 spin_lock_irqsave(&np->lock, flags);
4223 v0 = nr64(LDSV0(ldg));
4224 v1 = nr64(LDSV1(ldg));
4225 v2 = nr64(LDSV2(ldg));
4227 if (netif_msg_intr(np))
4228 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
4229 (unsigned long long) v0,
4230 (unsigned long long) v1,
4231 (unsigned long long) v2);
4233 if (unlikely(!v0 && !v1 && !v2)) {
4234 spin_unlock_irqrestore(&np->lock, flags);
4238 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4239 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4243 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4244 niu_schedule_napi(np, lp, v0, v1, v2);
4246 niu_ldg_rearm(np, lp, 1);
4248 spin_unlock_irqrestore(&np->lock, flags);
4253 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4256 np->ops->free_coherent(np->device,
4257 sizeof(struct rxdma_mailbox),
4258 rp->mbox, rp->mbox_dma);
4262 np->ops->free_coherent(np->device,
4263 MAX_RCR_RING_SIZE * sizeof(__le64),
4264 rp->rcr, rp->rcr_dma);
4266 rp->rcr_table_size = 0;
4270 niu_rbr_free(np, rp);
4272 np->ops->free_coherent(np->device,
4273 MAX_RBR_RING_SIZE * sizeof(__le32),
4274 rp->rbr, rp->rbr_dma);
4276 rp->rbr_table_size = 0;
4283 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4286 np->ops->free_coherent(np->device,
4287 sizeof(struct txdma_mailbox),
4288 rp->mbox, rp->mbox_dma);
4294 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4295 if (rp->tx_buffs[i].skb)
4296 (void) release_tx_packet(np, rp, i);
4299 np->ops->free_coherent(np->device,
4300 MAX_TX_RING_SIZE * sizeof(__le64),
4301 rp->descr, rp->descr_dma);
4310 static void niu_free_channels(struct niu *np)
4315 for (i = 0; i < np->num_rx_rings; i++) {
4316 struct rx_ring_info *rp = &np->rx_rings[i];
4318 niu_free_rx_ring_info(np, rp);
4320 kfree(np->rx_rings);
4321 np->rx_rings = NULL;
4322 np->num_rx_rings = 0;
4326 for (i = 0; i < np->num_tx_rings; i++) {
4327 struct tx_ring_info *rp = &np->tx_rings[i];
4329 niu_free_tx_ring_info(np, rp);
4331 kfree(np->tx_rings);
4332 np->tx_rings = NULL;
4333 np->num_tx_rings = 0;
4337 static int niu_alloc_rx_ring_info(struct niu *np,
4338 struct rx_ring_info *rp)
4340 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4342 rp->rxhash = kcalloc(MAX_RBR_RING_SIZE, sizeof(struct page *),
4347 rp->mbox = np->ops->alloc_coherent(np->device,
4348 sizeof(struct rxdma_mailbox),
4349 &rp->mbox_dma, GFP_KERNEL);
4352 if ((unsigned long)rp->mbox & (64UL - 1)) {
4353 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4358 rp->rcr = np->ops->alloc_coherent(np->device,
4359 MAX_RCR_RING_SIZE * sizeof(__le64),
4360 &rp->rcr_dma, GFP_KERNEL);
4363 if ((unsigned long)rp->rcr & (64UL - 1)) {
4364 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4368 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4371 rp->rbr = np->ops->alloc_coherent(np->device,
4372 MAX_RBR_RING_SIZE * sizeof(__le32),
4373 &rp->rbr_dma, GFP_KERNEL);
4376 if ((unsigned long)rp->rbr & (64UL - 1)) {
4377 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4381 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4383 rp->rbr_pending = 0;
4388 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4390 int mtu = np->dev->mtu;
4392 /* These values are recommended by the HW designers for fair
4393 * utilization of DRR amongst the rings.
4395 rp->max_burst = mtu + 32;
4396 if (rp->max_burst > 4096)
4397 rp->max_burst = 4096;
4400 static int niu_alloc_tx_ring_info(struct niu *np,
4401 struct tx_ring_info *rp)
4403 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4405 rp->mbox = np->ops->alloc_coherent(np->device,
4406 sizeof(struct txdma_mailbox),
4407 &rp->mbox_dma, GFP_KERNEL);
4410 if ((unsigned long)rp->mbox & (64UL - 1)) {
4411 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4416 rp->descr = np->ops->alloc_coherent(np->device,
4417 MAX_TX_RING_SIZE * sizeof(__le64),
4418 &rp->descr_dma, GFP_KERNEL);
4421 if ((unsigned long)rp->descr & (64UL - 1)) {
4422 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4427 rp->pending = MAX_TX_RING_SIZE;
4432 /* XXX make these configurable... XXX */
4433 rp->mark_freq = rp->pending / 4;
4435 niu_set_max_burst(np, rp);
4440 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4444 bss = min(PAGE_SHIFT, 15);
4446 rp->rbr_block_size = 1 << bss;
4447 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4449 rp->rbr_sizes[0] = 256;
4450 rp->rbr_sizes[1] = 1024;
4451 if (np->dev->mtu > ETH_DATA_LEN) {
4452 switch (PAGE_SIZE) {
4454 rp->rbr_sizes[2] = 4096;
4458 rp->rbr_sizes[2] = 8192;
4462 rp->rbr_sizes[2] = 2048;
4464 rp->rbr_sizes[3] = rp->rbr_block_size;
4467 static int niu_alloc_channels(struct niu *np)
4469 struct niu_parent *parent = np->parent;
4470 int first_rx_channel, first_tx_channel;
4471 int num_rx_rings, num_tx_rings;
4472 struct rx_ring_info *rx_rings;
4473 struct tx_ring_info *tx_rings;
4477 first_rx_channel = first_tx_channel = 0;
4478 for (i = 0; i < port; i++) {
4479 first_rx_channel += parent->rxchan_per_port[i];
4480 first_tx_channel += parent->txchan_per_port[i];
4483 num_rx_rings = parent->rxchan_per_port[port];
4484 num_tx_rings = parent->txchan_per_port[port];
4486 rx_rings = kcalloc(num_rx_rings, sizeof(struct rx_ring_info),
4492 np->num_rx_rings = num_rx_rings;
4494 np->rx_rings = rx_rings;
4496 netif_set_real_num_rx_queues(np->dev, num_rx_rings);
4498 for (i = 0; i < np->num_rx_rings; i++) {
4499 struct rx_ring_info *rp = &np->rx_rings[i];
4502 rp->rx_channel = first_rx_channel + i;
4504 err = niu_alloc_rx_ring_info(np, rp);
4508 niu_size_rbr(np, rp);
4510 /* XXX better defaults, configurable, etc... XXX */
4511 rp->nonsyn_window = 64;
4512 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4513 rp->syn_window = 64;
4514 rp->syn_threshold = rp->rcr_table_size - 64;
4515 rp->rcr_pkt_threshold = 16;
4516 rp->rcr_timeout = 8;
4517 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4518 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4519 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4521 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4526 tx_rings = kcalloc(num_tx_rings, sizeof(struct tx_ring_info),
4532 np->num_tx_rings = num_tx_rings;
4534 np->tx_rings = tx_rings;
4536 netif_set_real_num_tx_queues(np->dev, num_tx_rings);
4538 for (i = 0; i < np->num_tx_rings; i++) {
4539 struct tx_ring_info *rp = &np->tx_rings[i];
4542 rp->tx_channel = first_tx_channel + i;
4544 err = niu_alloc_tx_ring_info(np, rp);
4552 niu_free_channels(np);
4556 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4560 while (--limit > 0) {
4561 u64 val = nr64(TX_CS(channel));
4562 if (val & TX_CS_SNG_STATE)
4568 static int niu_tx_channel_stop(struct niu *np, int channel)
4570 u64 val = nr64(TX_CS(channel));
4572 val |= TX_CS_STOP_N_GO;
4573 nw64(TX_CS(channel), val);
4575 return niu_tx_cs_sng_poll(np, channel);
4578 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4582 while (--limit > 0) {
4583 u64 val = nr64(TX_CS(channel));
4584 if (!(val & TX_CS_RST))
4590 static int niu_tx_channel_reset(struct niu *np, int channel)
4592 u64 val = nr64(TX_CS(channel));
4596 nw64(TX_CS(channel), val);
4598 err = niu_tx_cs_reset_poll(np, channel);
4600 nw64(TX_RING_KICK(channel), 0);
4605 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4609 nw64(TX_LOG_MASK1(channel), 0);
4610 nw64(TX_LOG_VAL1(channel), 0);
4611 nw64(TX_LOG_MASK2(channel), 0);
4612 nw64(TX_LOG_VAL2(channel), 0);
4613 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4614 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4615 nw64(TX_LOG_PAGE_HDL(channel), 0);
4617 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4618 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4619 nw64(TX_LOG_PAGE_VLD(channel), val);
4621 /* XXX TXDMA 32bit mode? XXX */
4626 static void niu_txc_enable_port(struct niu *np, int on)
4628 unsigned long flags;
4631 niu_lock_parent(np, flags);
4632 val = nr64(TXC_CONTROL);
4633 mask = (u64)1 << np->port;
4635 val |= TXC_CONTROL_ENABLE | mask;
4638 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4639 val &= ~TXC_CONTROL_ENABLE;
4641 nw64(TXC_CONTROL, val);
4642 niu_unlock_parent(np, flags);
4645 static void niu_txc_set_imask(struct niu *np, u64 imask)
4647 unsigned long flags;
4650 niu_lock_parent(np, flags);
4651 val = nr64(TXC_INT_MASK);
4652 val &= ~TXC_INT_MASK_VAL(np->port);
4653 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4654 niu_unlock_parent(np, flags);
4657 static void niu_txc_port_dma_enable(struct niu *np, int on)
4664 for (i = 0; i < np->num_tx_rings; i++)
4665 val |= (1 << np->tx_rings[i].tx_channel);
4667 nw64(TXC_PORT_DMA(np->port), val);
4670 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4672 int err, channel = rp->tx_channel;
4675 err = niu_tx_channel_stop(np, channel);
4679 err = niu_tx_channel_reset(np, channel);
4683 err = niu_tx_channel_lpage_init(np, channel);
4687 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4688 nw64(TX_ENT_MSK(channel), 0);
4690 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4691 TX_RNG_CFIG_STADDR)) {
4692 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4693 channel, (unsigned long long)rp->descr_dma);
4697 /* The length field in TX_RNG_CFIG is measured in 64-byte
4698 * blocks. rp->pending is the number of TX descriptors in
4699 * our ring, 8 bytes each, thus we divide by 8 bytes more
4700 * to get the proper value the chip wants.
4702 ring_len = (rp->pending / 8);
4704 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4706 nw64(TX_RNG_CFIG(channel), val);
4708 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4709 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4710 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4711 channel, (unsigned long long)rp->mbox_dma);
4714 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4715 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4717 nw64(TX_CS(channel), 0);
4719 rp->last_pkt_cnt = 0;
4724 static void niu_init_rdc_groups(struct niu *np)
4726 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4727 int i, first_table_num = tp->first_table_num;
4729 for (i = 0; i < tp->num_tables; i++) {
4730 struct rdc_table *tbl = &tp->tables[i];
4731 int this_table = first_table_num + i;
4734 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4735 nw64(RDC_TBL(this_table, slot),
4736 tbl->rxdma_channel[slot]);
4739 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4742 static void niu_init_drr_weight(struct niu *np)
4744 int type = phy_decode(np->parent->port_phy, np->port);
4749 val = PT_DRR_WEIGHT_DEFAULT_10G;
4754 val = PT_DRR_WEIGHT_DEFAULT_1G;
4757 nw64(PT_DRR_WT(np->port), val);
4760 static int niu_init_hostinfo(struct niu *np)
4762 struct niu_parent *parent = np->parent;
4763 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4764 int i, err, num_alt = niu_num_alt_addr(np);
4765 int first_rdc_table = tp->first_table_num;
4767 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4771 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4775 for (i = 0; i < num_alt; i++) {
4776 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4784 static int niu_rx_channel_reset(struct niu *np, int channel)
4786 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4787 RXDMA_CFIG1_RST, 1000, 10,
4791 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4795 nw64(RX_LOG_MASK1(channel), 0);
4796 nw64(RX_LOG_VAL1(channel), 0);
4797 nw64(RX_LOG_MASK2(channel), 0);
4798 nw64(RX_LOG_VAL2(channel), 0);
4799 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4800 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4801 nw64(RX_LOG_PAGE_HDL(channel), 0);
4803 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4804 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4805 nw64(RX_LOG_PAGE_VLD(channel), val);
4810 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4814 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4815 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4816 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4817 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4818 nw64(RDC_RED_PARA(rp->rx_channel), val);
4821 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4826 switch (rp->rbr_block_size) {
4828 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4831 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4834 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4837 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4842 val |= RBR_CFIG_B_VLD2;
4843 switch (rp->rbr_sizes[2]) {
4845 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4848 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4851 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4854 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4860 val |= RBR_CFIG_B_VLD1;
4861 switch (rp->rbr_sizes[1]) {
4863 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4866 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4869 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4872 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4878 val |= RBR_CFIG_B_VLD0;
4879 switch (rp->rbr_sizes[0]) {
4881 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4884 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4887 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4890 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4901 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4903 u64 val = nr64(RXDMA_CFIG1(channel));
4907 val |= RXDMA_CFIG1_EN;
4909 val &= ~RXDMA_CFIG1_EN;
4910 nw64(RXDMA_CFIG1(channel), val);
4913 while (--limit > 0) {
4914 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4923 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4925 int err, channel = rp->rx_channel;
4928 err = niu_rx_channel_reset(np, channel);
4932 err = niu_rx_channel_lpage_init(np, channel);
4936 niu_rx_channel_wred_init(np, rp);
4938 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4939 nw64(RX_DMA_CTL_STAT(channel),
4940 (RX_DMA_CTL_STAT_MEX |
4941 RX_DMA_CTL_STAT_RCRTHRES |
4942 RX_DMA_CTL_STAT_RCRTO |
4943 RX_DMA_CTL_STAT_RBR_EMPTY));
4944 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4945 nw64(RXDMA_CFIG2(channel),
4946 ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) |
4947 RXDMA_CFIG2_FULL_HDR));
4948 nw64(RBR_CFIG_A(channel),
4949 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4950 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4951 err = niu_compute_rbr_cfig_b(rp, &val);
4954 nw64(RBR_CFIG_B(channel), val);
4955 nw64(RCRCFIG_A(channel),
4956 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4957 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4958 nw64(RCRCFIG_B(channel),
4959 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4961 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4963 err = niu_enable_rx_channel(np, channel, 1);
4967 nw64(RBR_KICK(channel), rp->rbr_index);
4969 val = nr64(RX_DMA_CTL_STAT(channel));
4970 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4971 nw64(RX_DMA_CTL_STAT(channel), val);
4976 static int niu_init_rx_channels(struct niu *np)
4978 unsigned long flags;
4979 u64 seed = jiffies_64;
4982 niu_lock_parent(np, flags);
4983 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4984 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4985 niu_unlock_parent(np, flags);
4987 /* XXX RXDMA 32bit mode? XXX */
4989 niu_init_rdc_groups(np);
4990 niu_init_drr_weight(np);
4992 err = niu_init_hostinfo(np);
4996 for (i = 0; i < np->num_rx_rings; i++) {
4997 struct rx_ring_info *rp = &np->rx_rings[i];
4999 err = niu_init_one_rx_channel(np, rp);
5007 static int niu_set_ip_frag_rule(struct niu *np)
5009 struct niu_parent *parent = np->parent;
5010 struct niu_classifier *cp = &np->clas;
5011 struct niu_tcam_entry *tp;
5014 index = cp->tcam_top;
5015 tp = &parent->tcam[index];
5017 /* Note that the noport bit is the same in both ipv4 and
5018 * ipv6 format TCAM entries.
5020 memset(tp, 0, sizeof(*tp));
5021 tp->key[1] = TCAM_V4KEY1_NOPORT;
5022 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5023 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5024 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5025 err = tcam_write(np, index, tp->key, tp->key_mask);
5028 err = tcam_assoc_write(np, index, tp->assoc_data);
5032 cp->tcam_valid_entries++;
5037 static int niu_init_classifier_hw(struct niu *np)
5039 struct niu_parent *parent = np->parent;
5040 struct niu_classifier *cp = &np->clas;
5043 nw64(H1POLY, cp->h1_init);
5044 nw64(H2POLY, cp->h2_init);
5046 err = niu_init_hostinfo(np);
5050 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5051 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5053 vlan_tbl_write(np, i, np->port,
5054 vp->vlan_pref, vp->rdc_num);
5057 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5058 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5060 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5061 ap->rdc_num, ap->mac_pref);
5066 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5067 int index = i - CLASS_CODE_USER_PROG1;
5069 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5072 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5077 err = niu_set_ip_frag_rule(np);
5086 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5088 nw64(ZCP_RAM_DATA0, data[0]);
5089 nw64(ZCP_RAM_DATA1, data[1]);
5090 nw64(ZCP_RAM_DATA2, data[2]);
5091 nw64(ZCP_RAM_DATA3, data[3]);
5092 nw64(ZCP_RAM_DATA4, data[4]);
5093 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5095 (ZCP_RAM_ACC_WRITE |
5096 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5097 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5099 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5103 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5107 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5110 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5111 (unsigned long long)nr64(ZCP_RAM_ACC));
5117 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5118 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5120 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5123 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5124 (unsigned long long)nr64(ZCP_RAM_ACC));
5128 data[0] = nr64(ZCP_RAM_DATA0);
5129 data[1] = nr64(ZCP_RAM_DATA1);
5130 data[2] = nr64(ZCP_RAM_DATA2);
5131 data[3] = nr64(ZCP_RAM_DATA3);
5132 data[4] = nr64(ZCP_RAM_DATA4);
5137 static void niu_zcp_cfifo_reset(struct niu *np)
5139 u64 val = nr64(RESET_CFIFO);
5141 val |= RESET_CFIFO_RST(np->port);
5142 nw64(RESET_CFIFO, val);
5145 val &= ~RESET_CFIFO_RST(np->port);
5146 nw64(RESET_CFIFO, val);
5149 static int niu_init_zcp(struct niu *np)
5151 u64 data[5], rbuf[5];
5154 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5155 if (np->port == 0 || np->port == 1)
5156 max = ATLAS_P0_P1_CFIFO_ENTRIES;
5158 max = ATLAS_P2_P3_CFIFO_ENTRIES;
5160 max = NIU_CFIFO_ENTRIES;
5168 for (i = 0; i < max; i++) {
5169 err = niu_zcp_write(np, i, data);
5172 err = niu_zcp_read(np, i, rbuf);
5177 niu_zcp_cfifo_reset(np);
5178 nw64(CFIFO_ECC(np->port), 0);
5179 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5180 (void) nr64(ZCP_INT_STAT);
5181 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5186 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5188 u64 val = nr64_ipp(IPP_CFIG);
5190 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5191 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5192 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5193 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5194 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5195 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5196 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5197 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5200 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5202 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5203 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5204 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5205 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5206 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5207 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5210 static int niu_ipp_reset(struct niu *np)
5212 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5213 1000, 100, "IPP_CFIG");
5216 static int niu_init_ipp(struct niu *np)
5218 u64 data[5], rbuf[5], val;
5221 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5222 if (np->port == 0 || np->port == 1)
5223 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5225 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5227 max = NIU_DFIFO_ENTRIES;
5235 for (i = 0; i < max; i++) {
5236 niu_ipp_write(np, i, data);
5237 niu_ipp_read(np, i, rbuf);
5240 (void) nr64_ipp(IPP_INT_STAT);
5241 (void) nr64_ipp(IPP_INT_STAT);
5243 err = niu_ipp_reset(np);
5247 (void) nr64_ipp(IPP_PKT_DIS);
5248 (void) nr64_ipp(IPP_BAD_CS_CNT);
5249 (void) nr64_ipp(IPP_ECC);
5251 (void) nr64_ipp(IPP_INT_STAT);
5253 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5255 val = nr64_ipp(IPP_CFIG);
5256 val &= ~IPP_CFIG_IP_MAX_PKT;
5257 val |= (IPP_CFIG_IPP_ENABLE |
5258 IPP_CFIG_DFIFO_ECC_EN |
5259 IPP_CFIG_DROP_BAD_CRC |
5261 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5262 nw64_ipp(IPP_CFIG, val);
5267 static void niu_handle_led(struct niu *np, int status)
5270 val = nr64_mac(XMAC_CONFIG);
5272 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5273 (np->flags & NIU_FLAGS_FIBER) != 0) {
5275 val |= XMAC_CONFIG_LED_POLARITY;
5276 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5278 val |= XMAC_CONFIG_FORCE_LED_ON;
5279 val &= ~XMAC_CONFIG_LED_POLARITY;
5283 nw64_mac(XMAC_CONFIG, val);
5286 static void niu_init_xif_xmac(struct niu *np)
5288 struct niu_link_config *lp = &np->link_config;
5291 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5292 val = nr64(MIF_CONFIG);
5293 val |= MIF_CONFIG_ATCA_GE;
5294 nw64(MIF_CONFIG, val);
5297 val = nr64_mac(XMAC_CONFIG);
5298 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5300 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5302 if (lp->loopback_mode == LOOPBACK_MAC) {
5303 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5304 val |= XMAC_CONFIG_LOOPBACK;
5306 val &= ~XMAC_CONFIG_LOOPBACK;
5309 if (np->flags & NIU_FLAGS_10G) {
5310 val &= ~XMAC_CONFIG_LFS_DISABLE;
5312 val |= XMAC_CONFIG_LFS_DISABLE;
5313 if (!(np->flags & NIU_FLAGS_FIBER) &&
5314 !(np->flags & NIU_FLAGS_XCVR_SERDES))
5315 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5317 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5320 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5322 if (lp->active_speed == SPEED_100)
5323 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5325 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5327 nw64_mac(XMAC_CONFIG, val);
5329 val = nr64_mac(XMAC_CONFIG);
5330 val &= ~XMAC_CONFIG_MODE_MASK;
5331 if (np->flags & NIU_FLAGS_10G) {
5332 val |= XMAC_CONFIG_MODE_XGMII;
5334 if (lp->active_speed == SPEED_1000)
5335 val |= XMAC_CONFIG_MODE_GMII;
5337 val |= XMAC_CONFIG_MODE_MII;
5340 nw64_mac(XMAC_CONFIG, val);
5343 static void niu_init_xif_bmac(struct niu *np)
5345 struct niu_link_config *lp = &np->link_config;
5348 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5350 if (lp->loopback_mode == LOOPBACK_MAC)
5351 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5353 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5355 if (lp->active_speed == SPEED_1000)
5356 val |= BMAC_XIF_CONFIG_GMII_MODE;
5358 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5360 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5361 BMAC_XIF_CONFIG_LED_POLARITY);
5363 if (!(np->flags & NIU_FLAGS_10G) &&
5364 !(np->flags & NIU_FLAGS_FIBER) &&
5365 lp->active_speed == SPEED_100)
5366 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5368 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5370 nw64_mac(BMAC_XIF_CONFIG, val);
5373 static void niu_init_xif(struct niu *np)
5375 if (np->flags & NIU_FLAGS_XMAC)
5376 niu_init_xif_xmac(np);
5378 niu_init_xif_bmac(np);
5381 static void niu_pcs_mii_reset(struct niu *np)
5384 u64 val = nr64_pcs(PCS_MII_CTL);
5385 val |= PCS_MII_CTL_RST;
5386 nw64_pcs(PCS_MII_CTL, val);
5387 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5389 val = nr64_pcs(PCS_MII_CTL);
5393 static void niu_xpcs_reset(struct niu *np)
5396 u64 val = nr64_xpcs(XPCS_CONTROL1);
5397 val |= XPCS_CONTROL1_RESET;
5398 nw64_xpcs(XPCS_CONTROL1, val);
5399 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5401 val = nr64_xpcs(XPCS_CONTROL1);
5405 static int niu_init_pcs(struct niu *np)
5407 struct niu_link_config *lp = &np->link_config;
5410 switch (np->flags & (NIU_FLAGS_10G |
5412 NIU_FLAGS_XCVR_SERDES)) {
5413 case NIU_FLAGS_FIBER:
5415 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5416 nw64_pcs(PCS_DPATH_MODE, 0);
5417 niu_pcs_mii_reset(np);
5421 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5422 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5424 if (!(np->flags & NIU_FLAGS_XMAC))
5427 /* 10G copper or fiber */
5428 val = nr64_mac(XMAC_CONFIG);
5429 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5430 nw64_mac(XMAC_CONFIG, val);
5434 val = nr64_xpcs(XPCS_CONTROL1);
5435 if (lp->loopback_mode == LOOPBACK_PHY)
5436 val |= XPCS_CONTROL1_LOOPBACK;
5438 val &= ~XPCS_CONTROL1_LOOPBACK;
5439 nw64_xpcs(XPCS_CONTROL1, val);
5441 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5442 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5443 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5447 case NIU_FLAGS_XCVR_SERDES:
5449 niu_pcs_mii_reset(np);
5450 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5451 nw64_pcs(PCS_DPATH_MODE, 0);
5456 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5457 /* 1G RGMII FIBER */
5458 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5459 niu_pcs_mii_reset(np);
5469 static int niu_reset_tx_xmac(struct niu *np)
5471 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5472 (XTXMAC_SW_RST_REG_RS |
5473 XTXMAC_SW_RST_SOFT_RST),
5474 1000, 100, "XTXMAC_SW_RST");
5477 static int niu_reset_tx_bmac(struct niu *np)
5481 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5483 while (--limit >= 0) {
5484 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5489 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
5491 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5498 static int niu_reset_tx_mac(struct niu *np)
5500 if (np->flags & NIU_FLAGS_XMAC)
5501 return niu_reset_tx_xmac(np);
5503 return niu_reset_tx_bmac(np);
5506 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5510 val = nr64_mac(XMAC_MIN);
5511 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5512 XMAC_MIN_RX_MIN_PKT_SIZE);
5513 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5514 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5515 nw64_mac(XMAC_MIN, val);
5517 nw64_mac(XMAC_MAX, max);
5519 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5521 val = nr64_mac(XMAC_IPG);
5522 if (np->flags & NIU_FLAGS_10G) {
5523 val &= ~XMAC_IPG_IPG_XGMII;
5524 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5526 val &= ~XMAC_IPG_IPG_MII_GMII;
5527 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5529 nw64_mac(XMAC_IPG, val);
5531 val = nr64_mac(XMAC_CONFIG);
5532 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5533 XMAC_CONFIG_STRETCH_MODE |
5534 XMAC_CONFIG_VAR_MIN_IPG_EN |
5535 XMAC_CONFIG_TX_ENABLE);
5536 nw64_mac(XMAC_CONFIG, val);
5538 nw64_mac(TXMAC_FRM_CNT, 0);
5539 nw64_mac(TXMAC_BYTE_CNT, 0);
5542 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5546 nw64_mac(BMAC_MIN_FRAME, min);
5547 nw64_mac(BMAC_MAX_FRAME, max);
5549 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5550 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5551 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5553 val = nr64_mac(BTXMAC_CONFIG);
5554 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5555 BTXMAC_CONFIG_ENABLE);
5556 nw64_mac(BTXMAC_CONFIG, val);
5559 static void niu_init_tx_mac(struct niu *np)
5564 if (np->dev->mtu > ETH_DATA_LEN)
5569 /* The XMAC_MIN register only accepts values for TX min which
5570 * have the low 3 bits cleared.
5574 if (np->flags & NIU_FLAGS_XMAC)
5575 niu_init_tx_xmac(np, min, max);
5577 niu_init_tx_bmac(np, min, max);
5580 static int niu_reset_rx_xmac(struct niu *np)
5584 nw64_mac(XRXMAC_SW_RST,
5585 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5587 while (--limit >= 0) {
5588 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5589 XRXMAC_SW_RST_SOFT_RST)))
5594 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
5596 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5603 static int niu_reset_rx_bmac(struct niu *np)
5607 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5609 while (--limit >= 0) {
5610 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5615 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
5617 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5624 static int niu_reset_rx_mac(struct niu *np)
5626 if (np->flags & NIU_FLAGS_XMAC)
5627 return niu_reset_rx_xmac(np);
5629 return niu_reset_rx_bmac(np);
5632 static void niu_init_rx_xmac(struct niu *np)
5634 struct niu_parent *parent = np->parent;
5635 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5636 int first_rdc_table = tp->first_table_num;
5640 nw64_mac(XMAC_ADD_FILT0, 0);
5641 nw64_mac(XMAC_ADD_FILT1, 0);
5642 nw64_mac(XMAC_ADD_FILT2, 0);
5643 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5644 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5645 for (i = 0; i < MAC_NUM_HASH; i++)
5646 nw64_mac(XMAC_HASH_TBL(i), 0);
5647 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5648 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5649 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5651 val = nr64_mac(XMAC_CONFIG);
5652 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5653 XMAC_CONFIG_PROMISCUOUS |
5654 XMAC_CONFIG_PROMISC_GROUP |
5655 XMAC_CONFIG_ERR_CHK_DIS |
5656 XMAC_CONFIG_RX_CRC_CHK_DIS |
5657 XMAC_CONFIG_RESERVED_MULTICAST |
5658 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5659 XMAC_CONFIG_ADDR_FILTER_EN |
5660 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5661 XMAC_CONFIG_STRIP_CRC |
5662 XMAC_CONFIG_PASS_FLOW_CTRL |
5663 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5664 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5665 nw64_mac(XMAC_CONFIG, val);
5667 nw64_mac(RXMAC_BT_CNT, 0);
5668 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5669 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5670 nw64_mac(RXMAC_FRAG_CNT, 0);
5671 nw64_mac(RXMAC_HIST_CNT1, 0);
5672 nw64_mac(RXMAC_HIST_CNT2, 0);
5673 nw64_mac(RXMAC_HIST_CNT3, 0);
5674 nw64_mac(RXMAC_HIST_CNT4, 0);
5675 nw64_mac(RXMAC_HIST_CNT5, 0);
5676 nw64_mac(RXMAC_HIST_CNT6, 0);
5677 nw64_mac(RXMAC_HIST_CNT7, 0);
5678 nw64_mac(RXMAC_MPSZER_CNT, 0);
5679 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5680 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5681 nw64_mac(LINK_FAULT_CNT, 0);
5684 static void niu_init_rx_bmac(struct niu *np)
5686 struct niu_parent *parent = np->parent;
5687 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5688 int first_rdc_table = tp->first_table_num;
5692 nw64_mac(BMAC_ADD_FILT0, 0);
5693 nw64_mac(BMAC_ADD_FILT1, 0);
5694 nw64_mac(BMAC_ADD_FILT2, 0);
5695 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5696 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5697 for (i = 0; i < MAC_NUM_HASH; i++)
5698 nw64_mac(BMAC_HASH_TBL(i), 0);
5699 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5700 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5701 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5703 val = nr64_mac(BRXMAC_CONFIG);
5704 val &= ~(BRXMAC_CONFIG_ENABLE |
5705 BRXMAC_CONFIG_STRIP_PAD |
5706 BRXMAC_CONFIG_STRIP_FCS |
5707 BRXMAC_CONFIG_PROMISC |
5708 BRXMAC_CONFIG_PROMISC_GRP |
5709 BRXMAC_CONFIG_ADDR_FILT_EN |
5710 BRXMAC_CONFIG_DISCARD_DIS);
5711 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5712 nw64_mac(BRXMAC_CONFIG, val);
5714 val = nr64_mac(BMAC_ADDR_CMPEN);
5715 val |= BMAC_ADDR_CMPEN_EN0;
5716 nw64_mac(BMAC_ADDR_CMPEN, val);
5719 static void niu_init_rx_mac(struct niu *np)
5721 niu_set_primary_mac(np, np->dev->dev_addr);
5723 if (np->flags & NIU_FLAGS_XMAC)
5724 niu_init_rx_xmac(np);
5726 niu_init_rx_bmac(np);
5729 static void niu_enable_tx_xmac(struct niu *np, int on)
5731 u64 val = nr64_mac(XMAC_CONFIG);
5734 val |= XMAC_CONFIG_TX_ENABLE;
5736 val &= ~XMAC_CONFIG_TX_ENABLE;
5737 nw64_mac(XMAC_CONFIG, val);
5740 static void niu_enable_tx_bmac(struct niu *np, int on)
5742 u64 val = nr64_mac(BTXMAC_CONFIG);
5745 val |= BTXMAC_CONFIG_ENABLE;
5747 val &= ~BTXMAC_CONFIG_ENABLE;
5748 nw64_mac(BTXMAC_CONFIG, val);
5751 static void niu_enable_tx_mac(struct niu *np, int on)
5753 if (np->flags & NIU_FLAGS_XMAC)
5754 niu_enable_tx_xmac(np, on);
5756 niu_enable_tx_bmac(np, on);
5759 static void niu_enable_rx_xmac(struct niu *np, int on)
5761 u64 val = nr64_mac(XMAC_CONFIG);
5763 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5764 XMAC_CONFIG_PROMISCUOUS);
5766 if (np->flags & NIU_FLAGS_MCAST)
5767 val |= XMAC_CONFIG_HASH_FILTER_EN;
5768 if (np->flags & NIU_FLAGS_PROMISC)
5769 val |= XMAC_CONFIG_PROMISCUOUS;
5772 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5774 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5775 nw64_mac(XMAC_CONFIG, val);
5778 static void niu_enable_rx_bmac(struct niu *np, int on)
5780 u64 val = nr64_mac(BRXMAC_CONFIG);
5782 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5783 BRXMAC_CONFIG_PROMISC);
5785 if (np->flags & NIU_FLAGS_MCAST)
5786 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5787 if (np->flags & NIU_FLAGS_PROMISC)
5788 val |= BRXMAC_CONFIG_PROMISC;
5791 val |= BRXMAC_CONFIG_ENABLE;
5793 val &= ~BRXMAC_CONFIG_ENABLE;
5794 nw64_mac(BRXMAC_CONFIG, val);
5797 static void niu_enable_rx_mac(struct niu *np, int on)
5799 if (np->flags & NIU_FLAGS_XMAC)
5800 niu_enable_rx_xmac(np, on);
5802 niu_enable_rx_bmac(np, on);
5805 static int niu_init_mac(struct niu *np)
5810 err = niu_init_pcs(np);
5814 err = niu_reset_tx_mac(np);
5817 niu_init_tx_mac(np);
5818 err = niu_reset_rx_mac(np);
5821 niu_init_rx_mac(np);
5823 /* This looks hookey but the RX MAC reset we just did will
5824 * undo some of the state we setup in niu_init_tx_mac() so we
5825 * have to call it again. In particular, the RX MAC reset will
5826 * set the XMAC_MAX register back to it's default value.
5828 niu_init_tx_mac(np);
5829 niu_enable_tx_mac(np, 1);
5831 niu_enable_rx_mac(np, 1);
5836 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5838 (void) niu_tx_channel_stop(np, rp->tx_channel);
5841 static void niu_stop_tx_channels(struct niu *np)
5845 for (i = 0; i < np->num_tx_rings; i++) {
5846 struct tx_ring_info *rp = &np->tx_rings[i];
5848 niu_stop_one_tx_channel(np, rp);
5852 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5854 (void) niu_tx_channel_reset(np, rp->tx_channel);
5857 static void niu_reset_tx_channels(struct niu *np)
5861 for (i = 0; i < np->num_tx_rings; i++) {
5862 struct tx_ring_info *rp = &np->tx_rings[i];
5864 niu_reset_one_tx_channel(np, rp);
5868 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5870 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5873 static void niu_stop_rx_channels(struct niu *np)
5877 for (i = 0; i < np->num_rx_rings; i++) {
5878 struct rx_ring_info *rp = &np->rx_rings[i];
5880 niu_stop_one_rx_channel(np, rp);
5884 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5886 int channel = rp->rx_channel;
5888 (void) niu_rx_channel_reset(np, channel);
5889 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5890 nw64(RX_DMA_CTL_STAT(channel), 0);
5891 (void) niu_enable_rx_channel(np, channel, 0);
5894 static void niu_reset_rx_channels(struct niu *np)
5898 for (i = 0; i < np->num_rx_rings; i++) {
5899 struct rx_ring_info *rp = &np->rx_rings[i];
5901 niu_reset_one_rx_channel(np, rp);
5905 static void niu_disable_ipp(struct niu *np)
5910 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5911 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5913 while (--limit >= 0 && (rd != wr)) {
5914 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5915 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5918 (rd != 0 && wr != 1)) {
5919 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5920 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5921 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
5924 val = nr64_ipp(IPP_CFIG);
5925 val &= ~(IPP_CFIG_IPP_ENABLE |
5926 IPP_CFIG_DFIFO_ECC_EN |
5927 IPP_CFIG_DROP_BAD_CRC |
5929 nw64_ipp(IPP_CFIG, val);
5931 (void) niu_ipp_reset(np);
5934 static int niu_init_hw(struct niu *np)
5938 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
5939 niu_txc_enable_port(np, 1);
5940 niu_txc_port_dma_enable(np, 1);
5941 niu_txc_set_imask(np, 0);
5943 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
5944 for (i = 0; i < np->num_tx_rings; i++) {
5945 struct tx_ring_info *rp = &np->tx_rings[i];
5947 err = niu_init_one_tx_channel(np, rp);
5952 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
5953 err = niu_init_rx_channels(np);
5955 goto out_uninit_tx_channels;
5957 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
5958 err = niu_init_classifier_hw(np);
5960 goto out_uninit_rx_channels;
5962 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
5963 err = niu_init_zcp(np);
5965 goto out_uninit_rx_channels;
5967 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
5968 err = niu_init_ipp(np);
5970 goto out_uninit_rx_channels;
5972 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
5973 err = niu_init_mac(np);
5975 goto out_uninit_ipp;
5980 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
5981 niu_disable_ipp(np);
5983 out_uninit_rx_channels:
5984 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
5985 niu_stop_rx_channels(np);
5986 niu_reset_rx_channels(np);
5988 out_uninit_tx_channels:
5989 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
5990 niu_stop_tx_channels(np);
5991 niu_reset_tx_channels(np);
5996 static void niu_stop_hw(struct niu *np)
5998 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
5999 niu_enable_interrupts(np, 0);
6001 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
6002 niu_enable_rx_mac(np, 0);
6004 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
6005 niu_disable_ipp(np);
6007 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
6008 niu_stop_tx_channels(np);
6010 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
6011 niu_stop_rx_channels(np);
6013 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
6014 niu_reset_tx_channels(np);
6016 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
6017 niu_reset_rx_channels(np);
6020 static void niu_set_irq_name(struct niu *np)
6022 int port = np->port;
6025 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6028 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6029 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6033 for (i = 0; i < np->num_ldg - j; i++) {
6034 if (i < np->num_rx_rings)
6035 sprintf(np->irq_name[i+j], "%s-rx-%d",
6037 else if (i < np->num_tx_rings + np->num_rx_rings)
6038 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6039 i - np->num_rx_rings);
6043 static int niu_request_irq(struct niu *np)
6047 niu_set_irq_name(np);
6050 for (i = 0; i < np->num_ldg; i++) {
6051 struct niu_ldg *lp = &np->ldg[i];
6053 err = request_irq(lp->irq, niu_interrupt, IRQF_SHARED,
6054 np->irq_name[i], lp);
6063 for (j = 0; j < i; j++) {
6064 struct niu_ldg *lp = &np->ldg[j];
6066 free_irq(lp->irq, lp);
6071 static void niu_free_irq(struct niu *np)
6075 for (i = 0; i < np->num_ldg; i++) {
6076 struct niu_ldg *lp = &np->ldg[i];
6078 free_irq(lp->irq, lp);
6082 static void niu_enable_napi(struct niu *np)
6086 for (i = 0; i < np->num_ldg; i++)
6087 napi_enable(&np->ldg[i].napi);
6090 static void niu_disable_napi(struct niu *np)
6094 for (i = 0; i < np->num_ldg; i++)
6095 napi_disable(&np->ldg[i].napi);
6098 static int niu_open(struct net_device *dev)
6100 struct niu *np = netdev_priv(dev);
6103 netif_carrier_off(dev);
6105 err = niu_alloc_channels(np);
6109 err = niu_enable_interrupts(np, 0);
6111 goto out_free_channels;
6113 err = niu_request_irq(np);
6115 goto out_free_channels;
6117 niu_enable_napi(np);
6119 spin_lock_irq(&np->lock);
6121 err = niu_init_hw(np);
6123 init_timer(&np->timer);
6124 np->timer.expires = jiffies + HZ;
6125 np->timer.data = (unsigned long) np;
6126 np->timer.function = niu_timer;
6128 err = niu_enable_interrupts(np, 1);
6133 spin_unlock_irq(&np->lock);
6136 niu_disable_napi(np);
6140 netif_tx_start_all_queues(dev);
6142 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6143 netif_carrier_on(dev);
6145 add_timer(&np->timer);
6153 niu_free_channels(np);
6159 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6161 cancel_work_sync(&np->reset_task);
6163 niu_disable_napi(np);
6164 netif_tx_stop_all_queues(dev);
6166 del_timer_sync(&np->timer);
6168 spin_lock_irq(&np->lock);
6172 spin_unlock_irq(&np->lock);
6175 static int niu_close(struct net_device *dev)
6177 struct niu *np = netdev_priv(dev);
6179 niu_full_shutdown(np, dev);
6183 niu_free_channels(np);
6185 niu_handle_led(np, 0);
6190 static void niu_sync_xmac_stats(struct niu *np)
6192 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6194 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6195 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6197 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6198 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6199 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6200 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6201 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6202 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6203 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6204 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6205 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6206 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6207 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6208 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6209 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6210 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6211 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6212 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6215 static void niu_sync_bmac_stats(struct niu *np)
6217 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6219 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6220 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6222 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6223 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6224 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6225 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6228 static void niu_sync_mac_stats(struct niu *np)
6230 if (np->flags & NIU_FLAGS_XMAC)
6231 niu_sync_xmac_stats(np);
6233 niu_sync_bmac_stats(np);
6236 static void niu_get_rx_stats(struct niu *np,
6237 struct rtnl_link_stats64 *stats)
6239 u64 pkts, dropped, errors, bytes;
6240 struct rx_ring_info *rx_rings;
6243 pkts = dropped = errors = bytes = 0;
6245 rx_rings = ACCESS_ONCE(np->rx_rings);
6249 for (i = 0; i < np->num_rx_rings; i++) {
6250 struct rx_ring_info *rp = &rx_rings[i];
6252 niu_sync_rx_discard_stats(np, rp, 0);
6254 pkts += rp->rx_packets;
6255 bytes += rp->rx_bytes;
6256 dropped += rp->rx_dropped;
6257 errors += rp->rx_errors;
6261 stats->rx_packets = pkts;
6262 stats->rx_bytes = bytes;
6263 stats->rx_dropped = dropped;
6264 stats->rx_errors = errors;
6267 static void niu_get_tx_stats(struct niu *np,
6268 struct rtnl_link_stats64 *stats)
6270 u64 pkts, errors, bytes;
6271 struct tx_ring_info *tx_rings;
6274 pkts = errors = bytes = 0;
6276 tx_rings = ACCESS_ONCE(np->tx_rings);
6280 for (i = 0; i < np->num_tx_rings; i++) {
6281 struct tx_ring_info *rp = &tx_rings[i];
6283 pkts += rp->tx_packets;
6284 bytes += rp->tx_bytes;
6285 errors += rp->tx_errors;
6289 stats->tx_packets = pkts;
6290 stats->tx_bytes = bytes;
6291 stats->tx_errors = errors;
6294 static void niu_get_stats(struct net_device *dev,
6295 struct rtnl_link_stats64 *stats)
6297 struct niu *np = netdev_priv(dev);
6299 if (netif_running(dev)) {
6300 niu_get_rx_stats(np, stats);
6301 niu_get_tx_stats(np, stats);
6305 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6309 for (i = 0; i < 16; i++)
6310 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6313 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6317 for (i = 0; i < 16; i++)
6318 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6321 static void niu_load_hash(struct niu *np, u16 *hash)
6323 if (np->flags & NIU_FLAGS_XMAC)
6324 niu_load_hash_xmac(np, hash);
6326 niu_load_hash_bmac(np, hash);
6329 static void niu_set_rx_mode(struct net_device *dev)
6331 struct niu *np = netdev_priv(dev);
6332 int i, alt_cnt, err;
6333 struct netdev_hw_addr *ha;
6334 unsigned long flags;
6335 u16 hash[16] = { 0, };
6337 spin_lock_irqsave(&np->lock, flags);
6338 niu_enable_rx_mac(np, 0);
6340 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6341 if (dev->flags & IFF_PROMISC)
6342 np->flags |= NIU_FLAGS_PROMISC;
6343 if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
6344 np->flags |= NIU_FLAGS_MCAST;
6346 alt_cnt = netdev_uc_count(dev);
6347 if (alt_cnt > niu_num_alt_addr(np)) {
6349 np->flags |= NIU_FLAGS_PROMISC;
6355 netdev_for_each_uc_addr(ha, dev) {
6356 err = niu_set_alt_mac(np, index, ha->addr);
6358 netdev_warn(dev, "Error %d adding alt mac %d\n",
6360 err = niu_enable_alt_mac(np, index, 1);
6362 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6369 if (np->flags & NIU_FLAGS_XMAC)
6373 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6374 err = niu_enable_alt_mac(np, i, 0);
6376 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6380 if (dev->flags & IFF_ALLMULTI) {
6381 for (i = 0; i < 16; i++)
6383 } else if (!netdev_mc_empty(dev)) {
6384 netdev_for_each_mc_addr(ha, dev) {
6385 u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
6388 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6392 if (np->flags & NIU_FLAGS_MCAST)
6393 niu_load_hash(np, hash);
6395 niu_enable_rx_mac(np, 1);
6396 spin_unlock_irqrestore(&np->lock, flags);
6399 static int niu_set_mac_addr(struct net_device *dev, void *p)
6401 struct niu *np = netdev_priv(dev);
6402 struct sockaddr *addr = p;
6403 unsigned long flags;
6405 if (!is_valid_ether_addr(addr->sa_data))
6406 return -EADDRNOTAVAIL;
6408 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6410 if (!netif_running(dev))
6413 spin_lock_irqsave(&np->lock, flags);
6414 niu_enable_rx_mac(np, 0);
6415 niu_set_primary_mac(np, dev->dev_addr);
6416 niu_enable_rx_mac(np, 1);
6417 spin_unlock_irqrestore(&np->lock, flags);
6422 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6427 static void niu_netif_stop(struct niu *np)
6429 netif_trans_update(np->dev); /* prevent tx timeout */
6431 niu_disable_napi(np);
6433 netif_tx_disable(np->dev);
6436 static void niu_netif_start(struct niu *np)
6438 /* NOTE: unconditional netif_wake_queue is only appropriate
6439 * so long as all callers are assured to have free tx slots
6440 * (such as after niu_init_hw).
6442 netif_tx_wake_all_queues(np->dev);
6444 niu_enable_napi(np);
6446 niu_enable_interrupts(np, 1);
6449 static void niu_reset_buffers(struct niu *np)
6454 for (i = 0; i < np->num_rx_rings; i++) {
6455 struct rx_ring_info *rp = &np->rx_rings[i];
6457 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6460 page = rp->rxhash[j];
6463 (struct page *) page->mapping;
6464 u64 base = page->index;
6465 base = base >> RBR_DESCR_ADDR_SHIFT;
6466 rp->rbr[k++] = cpu_to_le32(base);
6470 for (; k < MAX_RBR_RING_SIZE; k++) {
6471 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6476 rp->rbr_index = rp->rbr_table_size - 1;
6478 rp->rbr_pending = 0;
6479 rp->rbr_refill_pending = 0;
6483 for (i = 0; i < np->num_tx_rings; i++) {
6484 struct tx_ring_info *rp = &np->tx_rings[i];
6486 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6487 if (rp->tx_buffs[j].skb)
6488 (void) release_tx_packet(np, rp, j);
6491 rp->pending = MAX_TX_RING_SIZE;
6499 static void niu_reset_task(struct work_struct *work)
6501 struct niu *np = container_of(work, struct niu, reset_task);
6502 unsigned long flags;
6505 spin_lock_irqsave(&np->lock, flags);
6506 if (!netif_running(np->dev)) {
6507 spin_unlock_irqrestore(&np->lock, flags);
6511 spin_unlock_irqrestore(&np->lock, flags);
6513 del_timer_sync(&np->timer);
6517 spin_lock_irqsave(&np->lock, flags);
6521 spin_unlock_irqrestore(&np->lock, flags);
6523 niu_reset_buffers(np);
6525 spin_lock_irqsave(&np->lock, flags);
6527 err = niu_init_hw(np);
6529 np->timer.expires = jiffies + HZ;
6530 add_timer(&np->timer);
6531 niu_netif_start(np);
6534 spin_unlock_irqrestore(&np->lock, flags);
6537 static void niu_tx_timeout(struct net_device *dev)
6539 struct niu *np = netdev_priv(dev);
6541 dev_err(np->device, "%s: Transmit timed out, resetting\n",
6544 schedule_work(&np->reset_task);
6547 static void niu_set_txd(struct tx_ring_info *rp, int index,
6548 u64 mapping, u64 len, u64 mark,
6551 __le64 *desc = &rp->descr[index];
6553 *desc = cpu_to_le64(mark |
6554 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6555 (len << TX_DESC_TR_LEN_SHIFT) |
6556 (mapping & TX_DESC_SAD));
6559 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6560 u64 pad_bytes, u64 len)
6562 u16 eth_proto, eth_proto_inner;
6563 u64 csum_bits, l3off, ihl, ret;
6567 eth_proto = be16_to_cpu(ehdr->h_proto);
6568 eth_proto_inner = eth_proto;
6569 if (eth_proto == ETH_P_8021Q) {
6570 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6571 __be16 val = vp->h_vlan_encapsulated_proto;
6573 eth_proto_inner = be16_to_cpu(val);
6577 switch (skb->protocol) {
6578 case cpu_to_be16(ETH_P_IP):
6579 ip_proto = ip_hdr(skb)->protocol;
6580 ihl = ip_hdr(skb)->ihl;
6582 case cpu_to_be16(ETH_P_IPV6):
6583 ip_proto = ipv6_hdr(skb)->nexthdr;
6592 csum_bits = TXHDR_CSUM_NONE;
6593 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6596 csum_bits = (ip_proto == IPPROTO_TCP ?
6598 (ip_proto == IPPROTO_UDP ?
6599 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6601 start = skb_checksum_start_offset(skb) -
6602 (pad_bytes + sizeof(struct tx_pkt_hdr));
6603 stuff = start + skb->csum_offset;
6605 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6606 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6609 l3off = skb_network_offset(skb) -
6610 (pad_bytes + sizeof(struct tx_pkt_hdr));
6612 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6613 (len << TXHDR_LEN_SHIFT) |
6614 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6615 (ihl << TXHDR_IHL_SHIFT) |
6616 ((eth_proto_inner < ETH_P_802_3_MIN) ? TXHDR_LLC : 0) |
6617 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6618 (ipv6 ? TXHDR_IP_VER : 0) |
6624 static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
6625 struct net_device *dev)
6627 struct niu *np = netdev_priv(dev);
6628 unsigned long align, headroom;
6629 struct netdev_queue *txq;
6630 struct tx_ring_info *rp;
6631 struct tx_pkt_hdr *tp;
6632 unsigned int len, nfg;
6633 struct ethhdr *ehdr;
6637 i = skb_get_queue_mapping(skb);
6638 rp = &np->tx_rings[i];
6639 txq = netdev_get_tx_queue(dev, i);
6641 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6642 netif_tx_stop_queue(txq);
6643 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
6645 return NETDEV_TX_BUSY;
6648 if (eth_skb_pad(skb))
6651 len = sizeof(struct tx_pkt_hdr) + 15;
6652 if (skb_headroom(skb) < len) {
6653 struct sk_buff *skb_new;
6655 skb_new = skb_realloc_headroom(skb, len);
6663 align = ((unsigned long) skb->data & (16 - 1));
6664 headroom = align + sizeof(struct tx_pkt_hdr);
6666 ehdr = (struct ethhdr *) skb->data;
6667 tp = skb_push(skb, headroom);
6669 len = skb->len - sizeof(struct tx_pkt_hdr);
6670 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6673 len = skb_headlen(skb);
6674 mapping = np->ops->map_single(np->device, skb->data,
6675 len, DMA_TO_DEVICE);
6679 rp->tx_buffs[prod].skb = skb;
6680 rp->tx_buffs[prod].mapping = mapping;
6683 if (++rp->mark_counter == rp->mark_freq) {
6684 rp->mark_counter = 0;
6685 mrk |= TX_DESC_MARK;
6690 nfg = skb_shinfo(skb)->nr_frags;
6692 tlen -= MAX_TX_DESC_LEN;
6697 unsigned int this_len = len;
6699 if (this_len > MAX_TX_DESC_LEN)
6700 this_len = MAX_TX_DESC_LEN;
6702 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6705 prod = NEXT_TX(rp, prod);
6706 mapping += this_len;
6710 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6711 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6713 len = skb_frag_size(frag);
6714 mapping = np->ops->map_page(np->device, skb_frag_page(frag),
6715 frag->page_offset, len,
6718 rp->tx_buffs[prod].skb = NULL;
6719 rp->tx_buffs[prod].mapping = mapping;
6721 niu_set_txd(rp, prod, mapping, len, 0, 0);
6723 prod = NEXT_TX(rp, prod);
6726 if (prod < rp->prod)
6727 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6730 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6732 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6733 netif_tx_stop_queue(txq);
6734 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6735 netif_tx_wake_queue(txq);
6739 return NETDEV_TX_OK;
6747 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6749 struct niu *np = netdev_priv(dev);
6750 int err, orig_jumbo, new_jumbo;
6752 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6753 new_jumbo = (new_mtu > ETH_DATA_LEN);
6757 if (!netif_running(dev) ||
6758 (orig_jumbo == new_jumbo))
6761 niu_full_shutdown(np, dev);
6763 niu_free_channels(np);
6765 niu_enable_napi(np);
6767 err = niu_alloc_channels(np);
6771 spin_lock_irq(&np->lock);
6773 err = niu_init_hw(np);
6775 init_timer(&np->timer);
6776 np->timer.expires = jiffies + HZ;
6777 np->timer.data = (unsigned long) np;
6778 np->timer.function = niu_timer;
6780 err = niu_enable_interrupts(np, 1);
6785 spin_unlock_irq(&np->lock);
6788 netif_tx_start_all_queues(dev);
6789 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6790 netif_carrier_on(dev);
6792 add_timer(&np->timer);
6798 static void niu_get_drvinfo(struct net_device *dev,
6799 struct ethtool_drvinfo *info)
6801 struct niu *np = netdev_priv(dev);
6802 struct niu_vpd *vpd = &np->vpd;
6804 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
6805 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
6806 snprintf(info->fw_version, sizeof(info->fw_version), "%d.%d",
6807 vpd->fcode_major, vpd->fcode_minor);
6808 if (np->parent->plat_type != PLAT_TYPE_NIU)
6809 strlcpy(info->bus_info, pci_name(np->pdev),
6810 sizeof(info->bus_info));
6813 static int niu_get_link_ksettings(struct net_device *dev,
6814 struct ethtool_link_ksettings *cmd)
6816 struct niu *np = netdev_priv(dev);
6817 struct niu_link_config *lp;
6819 lp = &np->link_config;
6821 memset(cmd, 0, sizeof(*cmd));
6822 cmd->base.phy_address = np->phy_addr;
6823 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
6825 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
6826 lp->active_advertising);
6827 cmd->base.autoneg = lp->active_autoneg;
6828 cmd->base.speed = lp->active_speed;
6829 cmd->base.duplex = lp->active_duplex;
6830 cmd->base.port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6835 static int niu_set_link_ksettings(struct net_device *dev,
6836 const struct ethtool_link_ksettings *cmd)
6838 struct niu *np = netdev_priv(dev);
6839 struct niu_link_config *lp = &np->link_config;
6841 ethtool_convert_link_mode_to_legacy_u32(&lp->advertising,
6842 cmd->link_modes.advertising);
6843 lp->speed = cmd->base.speed;
6844 lp->duplex = cmd->base.duplex;
6845 lp->autoneg = cmd->base.autoneg;
6846 return niu_init_link(np);
6849 static u32 niu_get_msglevel(struct net_device *dev)
6851 struct niu *np = netdev_priv(dev);
6852 return np->msg_enable;
6855 static void niu_set_msglevel(struct net_device *dev, u32 value)
6857 struct niu *np = netdev_priv(dev);
6858 np->msg_enable = value;
6861 static int niu_nway_reset(struct net_device *dev)
6863 struct niu *np = netdev_priv(dev);
6865 if (np->link_config.autoneg)
6866 return niu_init_link(np);
6871 static int niu_get_eeprom_len(struct net_device *dev)
6873 struct niu *np = netdev_priv(dev);
6875 return np->eeprom_len;
6878 static int niu_get_eeprom(struct net_device *dev,
6879 struct ethtool_eeprom *eeprom, u8 *data)
6881 struct niu *np = netdev_priv(dev);
6882 u32 offset, len, val;
6884 offset = eeprom->offset;
6887 if (offset + len < offset)
6889 if (offset >= np->eeprom_len)
6891 if (offset + len > np->eeprom_len)
6892 len = eeprom->len = np->eeprom_len - offset;
6895 u32 b_offset, b_count;
6897 b_offset = offset & 3;
6898 b_count = 4 - b_offset;
6902 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6903 memcpy(data, ((char *)&val) + b_offset, b_count);
6909 val = nr64(ESPC_NCR(offset / 4));
6910 memcpy(data, &val, 4);
6916 val = nr64(ESPC_NCR(offset / 4));
6917 memcpy(data, &val, len);
6922 static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6924 switch (flow_type) {
6935 *pid = IPPROTO_SCTP;
6951 static int niu_class_to_ethflow(u64 class, int *flow_type)
6954 case CLASS_CODE_TCP_IPV4:
6955 *flow_type = TCP_V4_FLOW;
6957 case CLASS_CODE_UDP_IPV4:
6958 *flow_type = UDP_V4_FLOW;
6960 case CLASS_CODE_AH_ESP_IPV4:
6961 *flow_type = AH_V4_FLOW;
6963 case CLASS_CODE_SCTP_IPV4:
6964 *flow_type = SCTP_V4_FLOW;
6966 case CLASS_CODE_TCP_IPV6:
6967 *flow_type = TCP_V6_FLOW;
6969 case CLASS_CODE_UDP_IPV6:
6970 *flow_type = UDP_V6_FLOW;
6972 case CLASS_CODE_AH_ESP_IPV6:
6973 *flow_type = AH_V6_FLOW;
6975 case CLASS_CODE_SCTP_IPV6:
6976 *flow_type = SCTP_V6_FLOW;
6978 case CLASS_CODE_USER_PROG1:
6979 case CLASS_CODE_USER_PROG2:
6980 case CLASS_CODE_USER_PROG3:
6981 case CLASS_CODE_USER_PROG4:
6982 *flow_type = IP_USER_FLOW;
6991 static int niu_ethflow_to_class(int flow_type, u64 *class)
6993 switch (flow_type) {
6995 *class = CLASS_CODE_TCP_IPV4;
6998 *class = CLASS_CODE_UDP_IPV4;
7000 case AH_ESP_V4_FLOW:
7003 *class = CLASS_CODE_AH_ESP_IPV4;
7006 *class = CLASS_CODE_SCTP_IPV4;
7009 *class = CLASS_CODE_TCP_IPV6;
7012 *class = CLASS_CODE_UDP_IPV6;
7014 case AH_ESP_V6_FLOW:
7017 *class = CLASS_CODE_AH_ESP_IPV6;
7020 *class = CLASS_CODE_SCTP_IPV6;
7029 static u64 niu_flowkey_to_ethflow(u64 flow_key)
7033 if (flow_key & FLOW_KEY_L2DA)
7034 ethflow |= RXH_L2DA;
7035 if (flow_key & FLOW_KEY_VLAN)
7036 ethflow |= RXH_VLAN;
7037 if (flow_key & FLOW_KEY_IPSA)
7038 ethflow |= RXH_IP_SRC;
7039 if (flow_key & FLOW_KEY_IPDA)
7040 ethflow |= RXH_IP_DST;
7041 if (flow_key & FLOW_KEY_PROTO)
7042 ethflow |= RXH_L3_PROTO;
7043 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7044 ethflow |= RXH_L4_B_0_1;
7045 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7046 ethflow |= RXH_L4_B_2_3;
7052 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7056 if (ethflow & RXH_L2DA)
7057 key |= FLOW_KEY_L2DA;
7058 if (ethflow & RXH_VLAN)
7059 key |= FLOW_KEY_VLAN;
7060 if (ethflow & RXH_IP_SRC)
7061 key |= FLOW_KEY_IPSA;
7062 if (ethflow & RXH_IP_DST)
7063 key |= FLOW_KEY_IPDA;
7064 if (ethflow & RXH_L3_PROTO)
7065 key |= FLOW_KEY_PROTO;
7066 if (ethflow & RXH_L4_B_0_1)
7067 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7068 if (ethflow & RXH_L4_B_2_3)
7069 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7077 static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7083 if (!niu_ethflow_to_class(nfc->flow_type, &class))
7086 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7088 nfc->data = RXH_DISCARD;
7090 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
7091 CLASS_CODE_USER_PROG1]);
7095 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7096 struct ethtool_rx_flow_spec *fsp)
7101 tmp = (tp->key[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7102 fsp->h_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7104 tmp = (tp->key[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7105 fsp->h_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
7107 tmp = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7108 fsp->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7110 tmp = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7111 fsp->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
7113 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7114 TCAM_V4KEY2_TOS_SHIFT;
7115 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7116 TCAM_V4KEY2_TOS_SHIFT;
7118 switch (fsp->flow_type) {
7122 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7123 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7124 fsp->h_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7126 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7127 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7128 fsp->h_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
7130 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7131 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7132 fsp->m_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7134 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7135 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7136 fsp->m_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
7140 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7141 TCAM_V4KEY2_PORT_SPI_SHIFT;
7142 fsp->h_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
7144 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7145 TCAM_V4KEY2_PORT_SPI_SHIFT;
7146 fsp->m_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
7149 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7150 TCAM_V4KEY2_PORT_SPI_SHIFT;
7151 fsp->h_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
7153 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7154 TCAM_V4KEY2_PORT_SPI_SHIFT;
7155 fsp->m_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
7157 fsp->h_u.usr_ip4_spec.proto =
7158 (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7159 TCAM_V4KEY2_PROTO_SHIFT;
7160 fsp->m_u.usr_ip4_spec.proto =
7161 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7162 TCAM_V4KEY2_PROTO_SHIFT;
7164 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7171 static int niu_get_ethtool_tcam_entry(struct niu *np,
7172 struct ethtool_rxnfc *nfc)
7174 struct niu_parent *parent = np->parent;
7175 struct niu_tcam_entry *tp;
7176 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7181 idx = tcam_get_index(np, (u16)nfc->fs.location);
7183 tp = &parent->tcam[idx];
7185 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
7186 parent->index, (u16)nfc->fs.location, idx);
7190 /* fill the flow spec entry */
7191 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7192 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7193 ret = niu_class_to_ethflow(class, &fsp->flow_type);
7195 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
7200 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7201 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7202 TCAM_V4KEY2_PROTO_SHIFT;
7203 if (proto == IPPROTO_ESP) {
7204 if (fsp->flow_type == AH_V4_FLOW)
7205 fsp->flow_type = ESP_V4_FLOW;
7207 fsp->flow_type = ESP_V6_FLOW;
7211 switch (fsp->flow_type) {
7217 niu_get_ip4fs_from_tcam_key(tp, fsp);
7224 /* Not yet implemented */
7228 niu_get_ip4fs_from_tcam_key(tp, fsp);
7238 if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7239 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7241 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7242 TCAM_ASSOCDATA_OFFSET_SHIFT;
7244 /* put the tcam size here */
7245 nfc->data = tcam_get_size(np);
7250 static int niu_get_ethtool_tcam_all(struct niu *np,
7251 struct ethtool_rxnfc *nfc,
7254 struct niu_parent *parent = np->parent;
7255 struct niu_tcam_entry *tp;
7257 unsigned long flags;
7260 /* put the tcam size here */
7261 nfc->data = tcam_get_size(np);
7263 niu_lock_parent(np, flags);
7264 for (cnt = 0, i = 0; i < nfc->data; i++) {
7265 idx = tcam_get_index(np, i);
7266 tp = &parent->tcam[idx];
7269 if (cnt == nfc->rule_cnt) {
7276 niu_unlock_parent(np, flags);
7278 nfc->rule_cnt = cnt;
7283 static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7286 struct niu *np = netdev_priv(dev);
7291 ret = niu_get_hash_opts(np, cmd);
7293 case ETHTOOL_GRXRINGS:
7294 cmd->data = np->num_rx_rings;
7296 case ETHTOOL_GRXCLSRLCNT:
7297 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7299 case ETHTOOL_GRXCLSRULE:
7300 ret = niu_get_ethtool_tcam_entry(np, cmd);
7302 case ETHTOOL_GRXCLSRLALL:
7303 ret = niu_get_ethtool_tcam_all(np, cmd, rule_locs);
7313 static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7317 unsigned long flags;
7319 if (!niu_ethflow_to_class(nfc->flow_type, &class))
7322 if (class < CLASS_CODE_USER_PROG1 ||
7323 class > CLASS_CODE_SCTP_IPV6)
7326 if (nfc->data & RXH_DISCARD) {
7327 niu_lock_parent(np, flags);
7328 flow_key = np->parent->tcam_key[class -
7329 CLASS_CODE_USER_PROG1];
7330 flow_key |= TCAM_KEY_DISC;
7331 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7332 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7333 niu_unlock_parent(np, flags);
7336 /* Discard was set before, but is not set now */
7337 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7339 niu_lock_parent(np, flags);
7340 flow_key = np->parent->tcam_key[class -
7341 CLASS_CODE_USER_PROG1];
7342 flow_key &= ~TCAM_KEY_DISC;
7343 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7345 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7347 niu_unlock_parent(np, flags);
7351 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
7354 niu_lock_parent(np, flags);
7355 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7356 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7357 niu_unlock_parent(np, flags);
7362 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7363 struct niu_tcam_entry *tp,
7364 int l2_rdc_tab, u64 class)
7367 u32 sip, dip, sipm, dipm, spi, spim;
7368 u16 sport, dport, spm, dpm;
7370 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7371 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7372 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7373 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7375 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7376 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7377 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7378 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7380 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7383 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7384 tp->key_mask[3] |= dipm;
7386 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7387 TCAM_V4KEY2_TOS_SHIFT);
7388 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7389 TCAM_V4KEY2_TOS_SHIFT);
7390 switch (fsp->flow_type) {
7394 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7395 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7396 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7397 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7399 tp->key[2] |= (((u64)sport << 16) | dport);
7400 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7401 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7405 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7406 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7409 tp->key_mask[2] |= spim;
7410 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7413 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7414 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7417 tp->key_mask[2] |= spim;
7418 pid = fsp->h_u.usr_ip4_spec.proto;
7424 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7426 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7430 static int niu_add_ethtool_tcam_entry(struct niu *np,
7431 struct ethtool_rxnfc *nfc)
7433 struct niu_parent *parent = np->parent;
7434 struct niu_tcam_entry *tp;
7435 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7436 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7437 int l2_rdc_table = rdc_table->first_table_num;
7440 unsigned long flags;
7445 idx = nfc->fs.location;
7446 if (idx >= tcam_get_size(np))
7449 if (fsp->flow_type == IP_USER_FLOW) {
7451 int add_usr_cls = 0;
7452 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7453 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7455 if (uspec->ip_ver != ETH_RX_NFC_IP4)
7458 niu_lock_parent(np, flags);
7460 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7461 if (parent->l3_cls[i]) {
7462 if (uspec->proto == parent->l3_cls_pid[i]) {
7463 class = parent->l3_cls[i];
7464 parent->l3_cls_refcnt[i]++;
7469 /* Program new user IP class */
7472 class = CLASS_CODE_USER_PROG1;
7475 class = CLASS_CODE_USER_PROG2;
7478 class = CLASS_CODE_USER_PROG3;
7481 class = CLASS_CODE_USER_PROG4;
7486 ret = tcam_user_ip_class_set(np, class, 0,
7493 ret = tcam_user_ip_class_enable(np, class, 1);
7496 parent->l3_cls[i] = class;
7497 parent->l3_cls_pid[i] = uspec->proto;
7498 parent->l3_cls_refcnt[i]++;
7504 netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
7505 parent->index, __func__, uspec->proto);
7509 niu_unlock_parent(np, flags);
7511 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7516 niu_lock_parent(np, flags);
7518 idx = tcam_get_index(np, idx);
7519 tp = &parent->tcam[idx];
7521 memset(tp, 0, sizeof(*tp));
7523 /* fill in the tcam key and mask */
7524 switch (fsp->flow_type) {
7530 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7537 /* Not yet implemented */
7538 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7539 parent->index, __func__, fsp->flow_type);
7543 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7546 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
7547 parent->index, __func__, fsp->flow_type);
7552 /* fill in the assoc data */
7553 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7554 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7556 if (fsp->ring_cookie >= np->num_rx_rings) {
7557 netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
7558 parent->index, __func__,
7559 (long long)fsp->ring_cookie);
7563 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7564 (fsp->ring_cookie <<
7565 TCAM_ASSOCDATA_OFFSET_SHIFT));
7568 err = tcam_write(np, idx, tp->key, tp->key_mask);
7573 err = tcam_assoc_write(np, idx, tp->assoc_data);
7579 /* validate the entry */
7581 np->clas.tcam_valid_entries++;
7583 niu_unlock_parent(np, flags);
7588 static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7590 struct niu_parent *parent = np->parent;
7591 struct niu_tcam_entry *tp;
7593 unsigned long flags;
7597 if (loc >= tcam_get_size(np))
7600 niu_lock_parent(np, flags);
7602 idx = tcam_get_index(np, loc);
7603 tp = &parent->tcam[idx];
7605 /* if the entry is of a user defined class, then update*/
7606 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7607 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7609 if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7611 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7612 if (parent->l3_cls[i] == class) {
7613 parent->l3_cls_refcnt[i]--;
7614 if (!parent->l3_cls_refcnt[i]) {
7616 ret = tcam_user_ip_class_enable(np,
7621 parent->l3_cls[i] = 0;
7622 parent->l3_cls_pid[i] = 0;
7627 if (i == NIU_L3_PROG_CLS) {
7628 netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
7629 parent->index, __func__,
7630 (unsigned long long)class);
7636 ret = tcam_flush(np, idx);
7640 /* invalidate the entry */
7642 np->clas.tcam_valid_entries--;
7644 niu_unlock_parent(np, flags);
7649 static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7651 struct niu *np = netdev_priv(dev);
7656 ret = niu_set_hash_opts(np, cmd);
7658 case ETHTOOL_SRXCLSRLINS:
7659 ret = niu_add_ethtool_tcam_entry(np, cmd);
7661 case ETHTOOL_SRXCLSRLDEL:
7662 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7672 static const struct {
7673 const char string[ETH_GSTRING_LEN];
7674 } niu_xmac_stat_keys[] = {
7677 { "tx_fifo_errors" },
7678 { "tx_overflow_errors" },
7679 { "tx_max_pkt_size_errors" },
7680 { "tx_underflow_errors" },
7681 { "rx_local_faults" },
7682 { "rx_remote_faults" },
7683 { "rx_link_faults" },
7684 { "rx_align_errors" },
7696 { "rx_code_violations" },
7697 { "rx_len_errors" },
7698 { "rx_crc_errors" },
7699 { "rx_underflows" },
7701 { "pause_off_state" },
7702 { "pause_on_state" },
7703 { "pause_received" },
7706 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7708 static const struct {
7709 const char string[ETH_GSTRING_LEN];
7710 } niu_bmac_stat_keys[] = {
7711 { "tx_underflow_errors" },
7712 { "tx_max_pkt_size_errors" },
7717 { "rx_align_errors" },
7718 { "rx_crc_errors" },
7719 { "rx_len_errors" },
7720 { "pause_off_state" },
7721 { "pause_on_state" },
7722 { "pause_received" },
7725 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7727 static const struct {
7728 const char string[ETH_GSTRING_LEN];
7729 } niu_rxchan_stat_keys[] = {
7737 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7739 static const struct {
7740 const char string[ETH_GSTRING_LEN];
7741 } niu_txchan_stat_keys[] = {
7748 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7750 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7752 struct niu *np = netdev_priv(dev);
7755 if (stringset != ETH_SS_STATS)
7758 if (np->flags & NIU_FLAGS_XMAC) {
7759 memcpy(data, niu_xmac_stat_keys,
7760 sizeof(niu_xmac_stat_keys));
7761 data += sizeof(niu_xmac_stat_keys);
7763 memcpy(data, niu_bmac_stat_keys,
7764 sizeof(niu_bmac_stat_keys));
7765 data += sizeof(niu_bmac_stat_keys);
7767 for (i = 0; i < np->num_rx_rings; i++) {
7768 memcpy(data, niu_rxchan_stat_keys,
7769 sizeof(niu_rxchan_stat_keys));
7770 data += sizeof(niu_rxchan_stat_keys);
7772 for (i = 0; i < np->num_tx_rings; i++) {
7773 memcpy(data, niu_txchan_stat_keys,
7774 sizeof(niu_txchan_stat_keys));
7775 data += sizeof(niu_txchan_stat_keys);
7779 static int niu_get_sset_count(struct net_device *dev, int stringset)
7781 struct niu *np = netdev_priv(dev);
7783 if (stringset != ETH_SS_STATS)
7786 return (np->flags & NIU_FLAGS_XMAC ?
7787 NUM_XMAC_STAT_KEYS :
7788 NUM_BMAC_STAT_KEYS) +
7789 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7790 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS);
7793 static void niu_get_ethtool_stats(struct net_device *dev,
7794 struct ethtool_stats *stats, u64 *data)
7796 struct niu *np = netdev_priv(dev);
7799 niu_sync_mac_stats(np);
7800 if (np->flags & NIU_FLAGS_XMAC) {
7801 memcpy(data, &np->mac_stats.xmac,
7802 sizeof(struct niu_xmac_stats));
7803 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7805 memcpy(data, &np->mac_stats.bmac,
7806 sizeof(struct niu_bmac_stats));
7807 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7809 for (i = 0; i < np->num_rx_rings; i++) {
7810 struct rx_ring_info *rp = &np->rx_rings[i];
7812 niu_sync_rx_discard_stats(np, rp, 0);
7814 data[0] = rp->rx_channel;
7815 data[1] = rp->rx_packets;
7816 data[2] = rp->rx_bytes;
7817 data[3] = rp->rx_dropped;
7818 data[4] = rp->rx_errors;
7821 for (i = 0; i < np->num_tx_rings; i++) {
7822 struct tx_ring_info *rp = &np->tx_rings[i];
7824 data[0] = rp->tx_channel;
7825 data[1] = rp->tx_packets;
7826 data[2] = rp->tx_bytes;
7827 data[3] = rp->tx_errors;
7832 static u64 niu_led_state_save(struct niu *np)
7834 if (np->flags & NIU_FLAGS_XMAC)
7835 return nr64_mac(XMAC_CONFIG);
7837 return nr64_mac(BMAC_XIF_CONFIG);
7840 static void niu_led_state_restore(struct niu *np, u64 val)
7842 if (np->flags & NIU_FLAGS_XMAC)
7843 nw64_mac(XMAC_CONFIG, val);
7845 nw64_mac(BMAC_XIF_CONFIG, val);
7848 static void niu_force_led(struct niu *np, int on)
7852 if (np->flags & NIU_FLAGS_XMAC) {
7854 bit = XMAC_CONFIG_FORCE_LED_ON;
7856 reg = BMAC_XIF_CONFIG;
7857 bit = BMAC_XIF_CONFIG_LINK_LED;
7860 val = nr64_mac(reg);
7868 static int niu_set_phys_id(struct net_device *dev,
7869 enum ethtool_phys_id_state state)
7872 struct niu *np = netdev_priv(dev);
7874 if (!netif_running(dev))
7878 case ETHTOOL_ID_ACTIVE:
7879 np->orig_led_state = niu_led_state_save(np);
7880 return 1; /* cycle on/off once per second */
7883 niu_force_led(np, 1);
7886 case ETHTOOL_ID_OFF:
7887 niu_force_led(np, 0);
7890 case ETHTOOL_ID_INACTIVE:
7891 niu_led_state_restore(np, np->orig_led_state);
7897 static const struct ethtool_ops niu_ethtool_ops = {
7898 .get_drvinfo = niu_get_drvinfo,
7899 .get_link = ethtool_op_get_link,
7900 .get_msglevel = niu_get_msglevel,
7901 .set_msglevel = niu_set_msglevel,
7902 .nway_reset = niu_nway_reset,
7903 .get_eeprom_len = niu_get_eeprom_len,
7904 .get_eeprom = niu_get_eeprom,
7905 .get_strings = niu_get_strings,
7906 .get_sset_count = niu_get_sset_count,
7907 .get_ethtool_stats = niu_get_ethtool_stats,
7908 .set_phys_id = niu_set_phys_id,
7909 .get_rxnfc = niu_get_nfc,
7910 .set_rxnfc = niu_set_nfc,
7911 .get_link_ksettings = niu_get_link_ksettings,
7912 .set_link_ksettings = niu_set_link_ksettings,
7915 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7918 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7920 if (ldn < 0 || ldn > LDN_MAX)
7923 parent->ldg_map[ldn] = ldg;
7925 if (np->parent->plat_type == PLAT_TYPE_NIU) {
7926 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7927 * the firmware, and we're not supposed to change them.
7928 * Validate the mapping, because if it's wrong we probably
7929 * won't get any interrupts and that's painful to debug.
7931 if (nr64(LDG_NUM(ldn)) != ldg) {
7932 dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
7934 (unsigned long long) nr64(LDG_NUM(ldn)));
7938 nw64(LDG_NUM(ldn), ldg);
7943 static int niu_set_ldg_timer_res(struct niu *np, int res)
7945 if (res < 0 || res > LDG_TIMER_RES_VAL)
7949 nw64(LDG_TIMER_RES, res);
7954 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7956 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7957 (func < 0 || func > 3) ||
7958 (vector < 0 || vector > 0x1f))
7961 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7966 static int niu_pci_eeprom_read(struct niu *np, u32 addr)
7968 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7969 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7972 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7976 nw64(ESPC_PIO_STAT, frame);
7980 frame = nr64(ESPC_PIO_STAT);
7981 if (frame & ESPC_PIO_STAT_READ_END)
7984 if (!(frame & ESPC_PIO_STAT_READ_END)) {
7985 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
7986 (unsigned long long) frame);
7991 nw64(ESPC_PIO_STAT, frame);
7995 frame = nr64(ESPC_PIO_STAT);
7996 if (frame & ESPC_PIO_STAT_READ_END)
7999 if (!(frame & ESPC_PIO_STAT_READ_END)) {
8000 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
8001 (unsigned long long) frame);
8005 frame = nr64(ESPC_PIO_STAT);
8006 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8009 static int niu_pci_eeprom_read16(struct niu *np, u32 off)
8011 int err = niu_pci_eeprom_read(np, off);
8017 err = niu_pci_eeprom_read(np, off + 1);
8020 val |= (err & 0xff);
8025 static int niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8027 int err = niu_pci_eeprom_read(np, off);
8034 err = niu_pci_eeprom_read(np, off + 1);
8038 val |= (err & 0xff) << 8;
8043 static int niu_pci_vpd_get_propname(struct niu *np, u32 off, char *namebuf,
8048 for (i = 0; i < namebuf_len; i++) {
8049 int err = niu_pci_eeprom_read(np, off + i);
8056 if (i >= namebuf_len)
8062 static void niu_vpd_parse_version(struct niu *np)
8064 struct niu_vpd *vpd = &np->vpd;
8065 int len = strlen(vpd->version) + 1;
8066 const char *s = vpd->version;
8069 for (i = 0; i < len - 5; i++) {
8070 if (!strncmp(s + i, "FCode ", 6))
8077 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8079 netif_printk(np, probe, KERN_DEBUG, np->dev,
8080 "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8081 vpd->fcode_major, vpd->fcode_minor);
8082 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8083 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8084 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8085 np->flags |= NIU_FLAGS_VPD_VALID;
8088 /* ESPC_PIO_EN_ENABLE must be set */
8089 static int niu_pci_vpd_scan_props(struct niu *np, u32 start, u32 end)
8091 unsigned int found_mask = 0;
8092 #define FOUND_MASK_MODEL 0x00000001
8093 #define FOUND_MASK_BMODEL 0x00000002
8094 #define FOUND_MASK_VERS 0x00000004
8095 #define FOUND_MASK_MAC 0x00000008
8096 #define FOUND_MASK_NMAC 0x00000010
8097 #define FOUND_MASK_PHY 0x00000020
8098 #define FOUND_MASK_ALL 0x0000003f
8100 netif_printk(np, probe, KERN_DEBUG, np->dev,
8101 "VPD_SCAN: start[%x] end[%x]\n", start, end);
8102 while (start < end) {
8103 int len, err, prop_len;
8108 if (found_mask == FOUND_MASK_ALL) {
8109 niu_vpd_parse_version(np);
8113 err = niu_pci_eeprom_read(np, start + 2);
8119 prop_len = niu_pci_eeprom_read(np, start + 4);
8122 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8128 if (!strcmp(namebuf, "model")) {
8129 prop_buf = np->vpd.model;
8130 max_len = NIU_VPD_MODEL_MAX;
8131 found_mask |= FOUND_MASK_MODEL;
8132 } else if (!strcmp(namebuf, "board-model")) {
8133 prop_buf = np->vpd.board_model;
8134 max_len = NIU_VPD_BD_MODEL_MAX;
8135 found_mask |= FOUND_MASK_BMODEL;
8136 } else if (!strcmp(namebuf, "version")) {
8137 prop_buf = np->vpd.version;
8138 max_len = NIU_VPD_VERSION_MAX;
8139 found_mask |= FOUND_MASK_VERS;
8140 } else if (!strcmp(namebuf, "local-mac-address")) {
8141 prop_buf = np->vpd.local_mac;
8143 found_mask |= FOUND_MASK_MAC;
8144 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8145 prop_buf = &np->vpd.mac_num;
8147 found_mask |= FOUND_MASK_NMAC;
8148 } else if (!strcmp(namebuf, "phy-type")) {
8149 prop_buf = np->vpd.phy_type;
8150 max_len = NIU_VPD_PHY_TYPE_MAX;
8151 found_mask |= FOUND_MASK_PHY;
8154 if (max_len && prop_len > max_len) {
8155 dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
8160 u32 off = start + 5 + err;
8163 netif_printk(np, probe, KERN_DEBUG, np->dev,
8164 "VPD_SCAN: Reading in property [%s] len[%d]\n",
8166 for (i = 0; i < prop_len; i++) {
8167 err = niu_pci_eeprom_read(np, off + i);
8180 /* ESPC_PIO_EN_ENABLE must be set */
8181 static int niu_pci_vpd_fetch(struct niu *np, u32 start)
8186 err = niu_pci_eeprom_read16_swp(np, start + 1);
8192 while (start + offset < ESPC_EEPROM_SIZE) {
8193 u32 here = start + offset;
8196 err = niu_pci_eeprom_read(np, here);
8202 err = niu_pci_eeprom_read16_swp(np, here + 1);
8206 here = start + offset + 3;
8207 end = start + offset + err;
8211 err = niu_pci_vpd_scan_props(np, here, end);
8214 /* ret == 1 is not an error */
8221 /* ESPC_PIO_EN_ENABLE must be set */
8222 static u32 niu_pci_vpd_offset(struct niu *np)
8224 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8227 while (start < end) {
8230 /* ROM header signature? */
8231 err = niu_pci_eeprom_read16(np, start + 0);
8235 /* Apply offset to PCI data structure. */
8236 err = niu_pci_eeprom_read16(np, start + 23);
8241 /* Check for "PCIR" signature. */
8242 err = niu_pci_eeprom_read16(np, start + 0);
8245 err = niu_pci_eeprom_read16(np, start + 2);
8249 /* Check for OBP image type. */
8250 err = niu_pci_eeprom_read(np, start + 20);
8254 err = niu_pci_eeprom_read(np, ret + 2);
8258 start = ret + (err * 512);
8262 err = niu_pci_eeprom_read16_swp(np, start + 8);
8267 err = niu_pci_eeprom_read(np, ret + 0);
8277 static int niu_phy_type_prop_decode(struct niu *np, const char *phy_prop)
8279 if (!strcmp(phy_prop, "mif")) {
8280 /* 1G copper, MII */
8281 np->flags &= ~(NIU_FLAGS_FIBER |
8283 np->mac_xcvr = MAC_XCVR_MII;
8284 } else if (!strcmp(phy_prop, "xgf")) {
8285 /* 10G fiber, XPCS */
8286 np->flags |= (NIU_FLAGS_10G |
8288 np->mac_xcvr = MAC_XCVR_XPCS;
8289 } else if (!strcmp(phy_prop, "pcs")) {
8291 np->flags &= ~NIU_FLAGS_10G;
8292 np->flags |= NIU_FLAGS_FIBER;
8293 np->mac_xcvr = MAC_XCVR_PCS;
8294 } else if (!strcmp(phy_prop, "xgc")) {
8295 /* 10G copper, XPCS */
8296 np->flags |= NIU_FLAGS_10G;
8297 np->flags &= ~NIU_FLAGS_FIBER;
8298 np->mac_xcvr = MAC_XCVR_XPCS;
8299 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8300 /* 10G Serdes or 1G Serdes, default to 10G */
8301 np->flags |= NIU_FLAGS_10G;
8302 np->flags &= ~NIU_FLAGS_FIBER;
8303 np->flags |= NIU_FLAGS_XCVR_SERDES;
8304 np->mac_xcvr = MAC_XCVR_XPCS;
8311 static int niu_pci_vpd_get_nports(struct niu *np)
8315 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8316 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8317 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8318 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8319 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
8321 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8322 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8323 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8324 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
8331 static void niu_pci_vpd_validate(struct niu *np)
8333 struct net_device *dev = np->dev;
8334 struct niu_vpd *vpd = &np->vpd;
8337 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
8338 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
8340 np->flags &= ~NIU_FLAGS_VPD_VALID;
8344 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8345 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8346 np->flags |= NIU_FLAGS_10G;
8347 np->flags &= ~NIU_FLAGS_FIBER;
8348 np->flags |= NIU_FLAGS_XCVR_SERDES;
8349 np->mac_xcvr = MAC_XCVR_PCS;
8351 np->flags |= NIU_FLAGS_FIBER;
8352 np->flags &= ~NIU_FLAGS_10G;
8354 if (np->flags & NIU_FLAGS_10G)
8355 np->mac_xcvr = MAC_XCVR_XPCS;
8356 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8357 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8358 NIU_FLAGS_HOTPLUG_PHY);
8359 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8360 dev_err(np->device, "Illegal phy string [%s]\n",
8362 dev_err(np->device, "Falling back to SPROM\n");
8363 np->flags &= ~NIU_FLAGS_VPD_VALID;
8367 memcpy(dev->dev_addr, vpd->local_mac, ETH_ALEN);
8369 val8 = dev->dev_addr[5];
8370 dev->dev_addr[5] += np->port;
8371 if (dev->dev_addr[5] < val8)
8375 static int niu_pci_probe_sprom(struct niu *np)
8377 struct net_device *dev = np->dev;
8382 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8383 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8386 np->eeprom_len = len;
8388 netif_printk(np, probe, KERN_DEBUG, np->dev,
8389 "SPROM: Image size %llu\n", (unsigned long long)val);
8392 for (i = 0; i < len; i++) {
8393 val = nr64(ESPC_NCR(i));
8394 sum += (val >> 0) & 0xff;
8395 sum += (val >> 8) & 0xff;
8396 sum += (val >> 16) & 0xff;
8397 sum += (val >> 24) & 0xff;
8399 netif_printk(np, probe, KERN_DEBUG, np->dev,
8400 "SPROM: Checksum %x\n", (int)(sum & 0xff));
8401 if ((sum & 0xff) != 0xab) {
8402 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
8406 val = nr64(ESPC_PHY_TYPE);
8409 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
8410 ESPC_PHY_TYPE_PORT0_SHIFT;
8413 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
8414 ESPC_PHY_TYPE_PORT1_SHIFT;
8417 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
8418 ESPC_PHY_TYPE_PORT2_SHIFT;
8421 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
8422 ESPC_PHY_TYPE_PORT3_SHIFT;
8425 dev_err(np->device, "Bogus port number %u\n",
8429 netif_printk(np, probe, KERN_DEBUG, np->dev,
8430 "SPROM: PHY type %x\n", val8);
8433 case ESPC_PHY_TYPE_1G_COPPER:
8434 /* 1G copper, MII */
8435 np->flags &= ~(NIU_FLAGS_FIBER |
8437 np->mac_xcvr = MAC_XCVR_MII;
8440 case ESPC_PHY_TYPE_1G_FIBER:
8442 np->flags &= ~NIU_FLAGS_10G;
8443 np->flags |= NIU_FLAGS_FIBER;
8444 np->mac_xcvr = MAC_XCVR_PCS;
8447 case ESPC_PHY_TYPE_10G_COPPER:
8448 /* 10G copper, XPCS */
8449 np->flags |= NIU_FLAGS_10G;
8450 np->flags &= ~NIU_FLAGS_FIBER;
8451 np->mac_xcvr = MAC_XCVR_XPCS;
8454 case ESPC_PHY_TYPE_10G_FIBER:
8455 /* 10G fiber, XPCS */
8456 np->flags |= (NIU_FLAGS_10G |
8458 np->mac_xcvr = MAC_XCVR_XPCS;
8462 dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
8466 val = nr64(ESPC_MAC_ADDR0);
8467 netif_printk(np, probe, KERN_DEBUG, np->dev,
8468 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
8469 dev->dev_addr[0] = (val >> 0) & 0xff;
8470 dev->dev_addr[1] = (val >> 8) & 0xff;
8471 dev->dev_addr[2] = (val >> 16) & 0xff;
8472 dev->dev_addr[3] = (val >> 24) & 0xff;
8474 val = nr64(ESPC_MAC_ADDR1);
8475 netif_printk(np, probe, KERN_DEBUG, np->dev,
8476 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
8477 dev->dev_addr[4] = (val >> 0) & 0xff;
8478 dev->dev_addr[5] = (val >> 8) & 0xff;
8480 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
8481 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
8486 val8 = dev->dev_addr[5];
8487 dev->dev_addr[5] += np->port;
8488 if (dev->dev_addr[5] < val8)
8491 val = nr64(ESPC_MOD_STR_LEN);
8492 netif_printk(np, probe, KERN_DEBUG, np->dev,
8493 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8497 for (i = 0; i < val; i += 4) {
8498 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8500 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
8501 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
8502 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8503 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8505 np->vpd.model[val] = '\0';
8507 val = nr64(ESPC_BD_MOD_STR_LEN);
8508 netif_printk(np, probe, KERN_DEBUG, np->dev,
8509 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8513 for (i = 0; i < val; i += 4) {
8514 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8516 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
8517 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
8518 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8519 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8521 np->vpd.board_model[val] = '\0';
8524 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
8525 netif_printk(np, probe, KERN_DEBUG, np->dev,
8526 "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
8531 static int niu_get_and_validate_port(struct niu *np)
8533 struct niu_parent *parent = np->parent;
8536 np->flags |= NIU_FLAGS_XMAC;
8538 if (!parent->num_ports) {
8539 if (parent->plat_type == PLAT_TYPE_NIU) {
8540 parent->num_ports = 2;
8542 parent->num_ports = niu_pci_vpd_get_nports(np);
8543 if (!parent->num_ports) {
8544 /* Fall back to SPROM as last resort.
8545 * This will fail on most cards.
8547 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8548 ESPC_NUM_PORTS_MACS_VAL;
8550 /* All of the current probing methods fail on
8551 * Maramba on-board parts.
8553 if (!parent->num_ports)
8554 parent->num_ports = 4;
8559 if (np->port >= parent->num_ports)
8565 static int phy_record(struct niu_parent *parent, struct phy_probe_info *p,
8566 int dev_id_1, int dev_id_2, u8 phy_port, int type)
8568 u32 id = (dev_id_1 << 16) | dev_id_2;
8571 if (dev_id_1 < 0 || dev_id_2 < 0)
8573 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
8574 /* Because of the NIU_PHY_ID_MASK being applied, the 8704
8575 * test covers the 8706 as well.
8577 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
8578 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011))
8581 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8585 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8587 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
8588 type == PHY_TYPE_PCS ? "PCS" : "MII",
8591 if (p->cur[type] >= NIU_MAX_PORTS) {
8592 pr_err("Too many PHY ports\n");
8596 p->phy_id[type][idx] = id;
8597 p->phy_port[type][idx] = phy_port;
8598 p->cur[type] = idx + 1;
8602 static int port_has_10g(struct phy_probe_info *p, int port)
8606 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8607 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8610 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8611 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8618 static int count_10g_ports(struct phy_probe_info *p, int *lowest)
8624 for (port = 8; port < 32; port++) {
8625 if (port_has_10g(p, port)) {
8635 static int count_1g_ports(struct phy_probe_info *p, int *lowest)
8638 if (p->cur[PHY_TYPE_MII])
8639 *lowest = p->phy_port[PHY_TYPE_MII][0];
8641 return p->cur[PHY_TYPE_MII];
8644 static void niu_n2_divide_channels(struct niu_parent *parent)
8646 int num_ports = parent->num_ports;
8649 for (i = 0; i < num_ports; i++) {
8650 parent->rxchan_per_port[i] = (16 / num_ports);
8651 parent->txchan_per_port[i] = (16 / num_ports);
8653 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8655 parent->rxchan_per_port[i],
8656 parent->txchan_per_port[i]);
8660 static void niu_divide_channels(struct niu_parent *parent,
8661 int num_10g, int num_1g)
8663 int num_ports = parent->num_ports;
8664 int rx_chans_per_10g, rx_chans_per_1g;
8665 int tx_chans_per_10g, tx_chans_per_1g;
8666 int i, tot_rx, tot_tx;
8668 if (!num_10g || !num_1g) {
8669 rx_chans_per_10g = rx_chans_per_1g =
8670 (NIU_NUM_RXCHAN / num_ports);
8671 tx_chans_per_10g = tx_chans_per_1g =
8672 (NIU_NUM_TXCHAN / num_ports);
8674 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8675 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8676 (rx_chans_per_1g * num_1g)) /
8679 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8680 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8681 (tx_chans_per_1g * num_1g)) /
8685 tot_rx = tot_tx = 0;
8686 for (i = 0; i < num_ports; i++) {
8687 int type = phy_decode(parent->port_phy, i);
8689 if (type == PORT_TYPE_10G) {
8690 parent->rxchan_per_port[i] = rx_chans_per_10g;
8691 parent->txchan_per_port[i] = tx_chans_per_10g;
8693 parent->rxchan_per_port[i] = rx_chans_per_1g;
8694 parent->txchan_per_port[i] = tx_chans_per_1g;
8696 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8698 parent->rxchan_per_port[i],
8699 parent->txchan_per_port[i]);
8700 tot_rx += parent->rxchan_per_port[i];
8701 tot_tx += parent->txchan_per_port[i];
8704 if (tot_rx > NIU_NUM_RXCHAN) {
8705 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
8706 parent->index, tot_rx);
8707 for (i = 0; i < num_ports; i++)
8708 parent->rxchan_per_port[i] = 1;
8710 if (tot_tx > NIU_NUM_TXCHAN) {
8711 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
8712 parent->index, tot_tx);
8713 for (i = 0; i < num_ports; i++)
8714 parent->txchan_per_port[i] = 1;
8716 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
8717 pr_warn("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8718 parent->index, tot_rx, tot_tx);
8722 static void niu_divide_rdc_groups(struct niu_parent *parent,
8723 int num_10g, int num_1g)
8725 int i, num_ports = parent->num_ports;
8726 int rdc_group, rdc_groups_per_port;
8727 int rdc_channel_base;
8730 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8732 rdc_channel_base = 0;
8734 for (i = 0; i < num_ports; i++) {
8735 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8736 int grp, num_channels = parent->rxchan_per_port[i];
8737 int this_channel_offset;
8739 tp->first_table_num = rdc_group;
8740 tp->num_tables = rdc_groups_per_port;
8741 this_channel_offset = 0;
8742 for (grp = 0; grp < tp->num_tables; grp++) {
8743 struct rdc_table *rt = &tp->tables[grp];
8746 pr_info("niu%d: Port %d RDC tbl(%d) [ ",
8747 parent->index, i, tp->first_table_num + grp);
8748 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8749 rt->rxdma_channel[slot] =
8750 rdc_channel_base + this_channel_offset;
8752 pr_cont("%d ", rt->rxdma_channel[slot]);
8754 if (++this_channel_offset == num_channels)
8755 this_channel_offset = 0;
8760 parent->rdc_default[i] = rdc_channel_base;
8762 rdc_channel_base += num_channels;
8763 rdc_group += rdc_groups_per_port;
8767 static int fill_phy_probe_info(struct niu *np, struct niu_parent *parent,
8768 struct phy_probe_info *info)
8770 unsigned long flags;
8773 memset(info, 0, sizeof(*info));
8775 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8776 niu_lock_parent(np, flags);
8778 for (port = 8; port < 32; port++) {
8779 int dev_id_1, dev_id_2;
8781 dev_id_1 = mdio_read(np, port,
8782 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8783 dev_id_2 = mdio_read(np, port,
8784 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8785 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8789 dev_id_1 = mdio_read(np, port,
8790 NIU_PCS_DEV_ADDR, MII_PHYSID1);
8791 dev_id_2 = mdio_read(np, port,
8792 NIU_PCS_DEV_ADDR, MII_PHYSID2);
8793 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8797 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8798 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8799 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8804 niu_unlock_parent(np, flags);
8809 static int walk_phys(struct niu *np, struct niu_parent *parent)
8811 struct phy_probe_info *info = &parent->phy_probe_info;
8812 int lowest_10g, lowest_1g;
8813 int num_10g, num_1g;
8817 num_10g = num_1g = 0;
8819 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8820 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8823 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8824 parent->num_ports = 4;
8825 val = (phy_encode(PORT_TYPE_1G, 0) |
8826 phy_encode(PORT_TYPE_1G, 1) |
8827 phy_encode(PORT_TYPE_1G, 2) |
8828 phy_encode(PORT_TYPE_1G, 3));
8829 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8832 parent->num_ports = 2;
8833 val = (phy_encode(PORT_TYPE_10G, 0) |
8834 phy_encode(PORT_TYPE_10G, 1));
8835 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8836 (parent->plat_type == PLAT_TYPE_NIU)) {
8837 /* this is the Monza case */
8838 if (np->flags & NIU_FLAGS_10G) {
8839 val = (phy_encode(PORT_TYPE_10G, 0) |
8840 phy_encode(PORT_TYPE_10G, 1));
8842 val = (phy_encode(PORT_TYPE_1G, 0) |
8843 phy_encode(PORT_TYPE_1G, 1));
8846 err = fill_phy_probe_info(np, parent, info);
8850 num_10g = count_10g_ports(info, &lowest_10g);
8851 num_1g = count_1g_ports(info, &lowest_1g);
8853 switch ((num_10g << 4) | num_1g) {
8855 if (lowest_1g == 10)
8856 parent->plat_type = PLAT_TYPE_VF_P0;
8857 else if (lowest_1g == 26)
8858 parent->plat_type = PLAT_TYPE_VF_P1;
8860 goto unknown_vg_1g_port;
8864 val = (phy_encode(PORT_TYPE_10G, 0) |
8865 phy_encode(PORT_TYPE_10G, 1) |
8866 phy_encode(PORT_TYPE_1G, 2) |
8867 phy_encode(PORT_TYPE_1G, 3));
8871 val = (phy_encode(PORT_TYPE_10G, 0) |
8872 phy_encode(PORT_TYPE_10G, 1));
8876 val = phy_encode(PORT_TYPE_10G, np->port);
8880 if (lowest_1g == 10)
8881 parent->plat_type = PLAT_TYPE_VF_P0;
8882 else if (lowest_1g == 26)
8883 parent->plat_type = PLAT_TYPE_VF_P1;
8885 goto unknown_vg_1g_port;
8889 if ((lowest_10g & 0x7) == 0)
8890 val = (phy_encode(PORT_TYPE_10G, 0) |
8891 phy_encode(PORT_TYPE_1G, 1) |
8892 phy_encode(PORT_TYPE_1G, 2) |
8893 phy_encode(PORT_TYPE_1G, 3));
8895 val = (phy_encode(PORT_TYPE_1G, 0) |
8896 phy_encode(PORT_TYPE_10G, 1) |
8897 phy_encode(PORT_TYPE_1G, 2) |
8898 phy_encode(PORT_TYPE_1G, 3));
8902 if (lowest_1g == 10)
8903 parent->plat_type = PLAT_TYPE_VF_P0;
8904 else if (lowest_1g == 26)
8905 parent->plat_type = PLAT_TYPE_VF_P1;
8907 goto unknown_vg_1g_port;
8909 val = (phy_encode(PORT_TYPE_1G, 0) |
8910 phy_encode(PORT_TYPE_1G, 1) |
8911 phy_encode(PORT_TYPE_1G, 2) |
8912 phy_encode(PORT_TYPE_1G, 3));
8916 pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
8922 parent->port_phy = val;
8924 if (parent->plat_type == PLAT_TYPE_NIU)
8925 niu_n2_divide_channels(parent);
8927 niu_divide_channels(parent, num_10g, num_1g);
8929 niu_divide_rdc_groups(parent, num_10g, num_1g);
8934 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
8938 static int niu_probe_ports(struct niu *np)
8940 struct niu_parent *parent = np->parent;
8943 if (parent->port_phy == PORT_PHY_UNKNOWN) {
8944 err = walk_phys(np, parent);
8948 niu_set_ldg_timer_res(np, 2);
8949 for (i = 0; i <= LDN_MAX; i++)
8950 niu_ldn_irq_enable(np, i, 0);
8953 if (parent->port_phy == PORT_PHY_INVALID)
8959 static int niu_classifier_swstate_init(struct niu *np)
8961 struct niu_classifier *cp = &np->clas;
8963 cp->tcam_top = (u16) np->port;
8964 cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
8965 cp->h1_init = 0xffffffff;
8966 cp->h2_init = 0xffff;
8968 return fflp_early_init(np);
8971 static void niu_link_config_init(struct niu *np)
8973 struct niu_link_config *lp = &np->link_config;
8975 lp->advertising = (ADVERTISED_10baseT_Half |
8976 ADVERTISED_10baseT_Full |
8977 ADVERTISED_100baseT_Half |
8978 ADVERTISED_100baseT_Full |
8979 ADVERTISED_1000baseT_Half |
8980 ADVERTISED_1000baseT_Full |
8981 ADVERTISED_10000baseT_Full |
8982 ADVERTISED_Autoneg);
8983 lp->speed = lp->active_speed = SPEED_INVALID;
8984 lp->duplex = DUPLEX_FULL;
8985 lp->active_duplex = DUPLEX_INVALID;
8988 lp->loopback_mode = LOOPBACK_MAC;
8989 lp->active_speed = SPEED_10000;
8990 lp->active_duplex = DUPLEX_FULL;
8992 lp->loopback_mode = LOOPBACK_DISABLED;
8996 static int niu_init_mac_ipp_pcs_base(struct niu *np)
9000 np->mac_regs = np->regs + XMAC_PORT0_OFF;
9001 np->ipp_off = 0x00000;
9002 np->pcs_off = 0x04000;
9003 np->xpcs_off = 0x02000;
9007 np->mac_regs = np->regs + XMAC_PORT1_OFF;
9008 np->ipp_off = 0x08000;
9009 np->pcs_off = 0x0a000;
9010 np->xpcs_off = 0x08000;
9014 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9015 np->ipp_off = 0x04000;
9016 np->pcs_off = 0x0e000;
9017 np->xpcs_off = ~0UL;
9021 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9022 np->ipp_off = 0x0c000;
9023 np->pcs_off = 0x12000;
9024 np->xpcs_off = ~0UL;
9028 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
9035 static void niu_try_msix(struct niu *np, u8 *ldg_num_map)
9037 struct msix_entry msi_vec[NIU_NUM_LDG];
9038 struct niu_parent *parent = np->parent;
9039 struct pci_dev *pdev = np->pdev;
9043 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9044 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9045 ldg_num_map[i] = first_ldg + i;
9047 num_irqs = (parent->rxchan_per_port[np->port] +
9048 parent->txchan_per_port[np->port] +
9049 (np->port == 0 ? 3 : 1));
9050 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9052 for (i = 0; i < num_irqs; i++) {
9053 msi_vec[i].vector = 0;
9054 msi_vec[i].entry = i;
9057 num_irqs = pci_enable_msix_range(pdev, msi_vec, 1, num_irqs);
9059 np->flags &= ~NIU_FLAGS_MSIX;
9063 np->flags |= NIU_FLAGS_MSIX;
9064 for (i = 0; i < num_irqs; i++)
9065 np->ldg[i].irq = msi_vec[i].vector;
9066 np->num_ldg = num_irqs;
9069 static int niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9071 #ifdef CONFIG_SPARC64
9072 struct platform_device *op = np->op;
9073 const u32 *int_prop;
9076 int_prop = of_get_property(op->dev.of_node, "interrupts", NULL);
9080 for (i = 0; i < op->archdata.num_irqs; i++) {
9081 ldg_num_map[i] = int_prop[i];
9082 np->ldg[i].irq = op->archdata.irqs[i];
9085 np->num_ldg = op->archdata.num_irqs;
9093 static int niu_ldg_init(struct niu *np)
9095 struct niu_parent *parent = np->parent;
9096 u8 ldg_num_map[NIU_NUM_LDG];
9097 int first_chan, num_chan;
9098 int i, err, ldg_rotor;
9102 np->ldg[0].irq = np->dev->irq;
9103 if (parent->plat_type == PLAT_TYPE_NIU) {
9104 err = niu_n2_irq_init(np, ldg_num_map);
9108 niu_try_msix(np, ldg_num_map);
9111 for (i = 0; i < np->num_ldg; i++) {
9112 struct niu_ldg *lp = &np->ldg[i];
9114 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9117 lp->ldg_num = ldg_num_map[i];
9118 lp->timer = 2; /* XXX */
9120 /* On N2 NIU the firmware has setup the SID mappings so they go
9121 * to the correct values that will route the LDG to the proper
9122 * interrupt in the NCU interrupt table.
9124 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9125 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9131 /* We adopt the LDG assignment ordering used by the N2 NIU
9132 * 'interrupt' properties because that simplifies a lot of
9133 * things. This ordering is:
9136 * MIF (if port zero)
9137 * SYSERR (if port zero)
9144 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9150 if (ldg_rotor == np->num_ldg)
9154 err = niu_ldg_assign_ldn(np, parent,
9155 ldg_num_map[ldg_rotor],
9161 if (ldg_rotor == np->num_ldg)
9164 err = niu_ldg_assign_ldn(np, parent,
9165 ldg_num_map[ldg_rotor],
9171 if (ldg_rotor == np->num_ldg)
9177 for (i = 0; i < port; i++)
9178 first_chan += parent->rxchan_per_port[i];
9179 num_chan = parent->rxchan_per_port[port];
9181 for (i = first_chan; i < (first_chan + num_chan); i++) {
9182 err = niu_ldg_assign_ldn(np, parent,
9183 ldg_num_map[ldg_rotor],
9188 if (ldg_rotor == np->num_ldg)
9193 for (i = 0; i < port; i++)
9194 first_chan += parent->txchan_per_port[i];
9195 num_chan = parent->txchan_per_port[port];
9196 for (i = first_chan; i < (first_chan + num_chan); i++) {
9197 err = niu_ldg_assign_ldn(np, parent,
9198 ldg_num_map[ldg_rotor],
9203 if (ldg_rotor == np->num_ldg)
9210 static void niu_ldg_free(struct niu *np)
9212 if (np->flags & NIU_FLAGS_MSIX)
9213 pci_disable_msix(np->pdev);
9216 static int niu_get_of_props(struct niu *np)
9218 #ifdef CONFIG_SPARC64
9219 struct net_device *dev = np->dev;
9220 struct device_node *dp;
9221 const char *phy_type;
9226 if (np->parent->plat_type == PLAT_TYPE_NIU)
9227 dp = np->op->dev.of_node;
9229 dp = pci_device_to_OF_node(np->pdev);
9231 phy_type = of_get_property(dp, "phy-type", &prop_len);
9233 netdev_err(dev, "%pOF: OF node lacks phy-type property\n", dp);
9237 if (!strcmp(phy_type, "none"))
9240 strcpy(np->vpd.phy_type, phy_type);
9242 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
9243 netdev_err(dev, "%pOF: Illegal phy string [%s]\n",
9244 dp, np->vpd.phy_type);
9248 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9250 netdev_err(dev, "%pOF: OF node lacks local-mac-address property\n",
9254 if (prop_len != dev->addr_len) {
9255 netdev_err(dev, "%pOF: OF MAC address prop len (%d) is wrong\n",
9258 memcpy(dev->dev_addr, mac_addr, dev->addr_len);
9259 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
9260 netdev_err(dev, "%pOF: OF MAC address is invalid\n", dp);
9261 netdev_err(dev, "%pOF: [ %pM ]\n", dp, dev->dev_addr);
9265 model = of_get_property(dp, "model", &prop_len);
9268 strcpy(np->vpd.model, model);
9270 if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9271 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9272 NIU_FLAGS_HOTPLUG_PHY);
9281 static int niu_get_invariants(struct niu *np)
9283 int err, have_props;
9286 err = niu_get_of_props(np);
9292 err = niu_init_mac_ipp_pcs_base(np);
9297 err = niu_get_and_validate_port(np);
9302 if (np->parent->plat_type == PLAT_TYPE_NIU)
9305 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9306 offset = niu_pci_vpd_offset(np);
9307 netif_printk(np, probe, KERN_DEBUG, np->dev,
9308 "%s() VPD offset [%08x]\n", __func__, offset);
9310 err = niu_pci_vpd_fetch(np, offset);
9314 nw64(ESPC_PIO_EN, 0);
9316 if (np->flags & NIU_FLAGS_VPD_VALID) {
9317 niu_pci_vpd_validate(np);
9318 err = niu_get_and_validate_port(np);
9323 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
9324 err = niu_get_and_validate_port(np);
9327 err = niu_pci_probe_sprom(np);
9333 err = niu_probe_ports(np);
9339 niu_classifier_swstate_init(np);
9340 niu_link_config_init(np);
9342 err = niu_determine_phy_disposition(np);
9344 err = niu_init_link(np);
9349 static LIST_HEAD(niu_parent_list);
9350 static DEFINE_MUTEX(niu_parent_lock);
9351 static int niu_parent_index;
9353 static ssize_t show_port_phy(struct device *dev,
9354 struct device_attribute *attr, char *buf)
9356 struct platform_device *plat_dev = to_platform_device(dev);
9357 struct niu_parent *p = dev_get_platdata(&plat_dev->dev);
9358 u32 port_phy = p->port_phy;
9359 char *orig_buf = buf;
9362 if (port_phy == PORT_PHY_UNKNOWN ||
9363 port_phy == PORT_PHY_INVALID)
9366 for (i = 0; i < p->num_ports; i++) {
9367 const char *type_str;
9370 type = phy_decode(port_phy, i);
9371 if (type == PORT_TYPE_10G)
9376 (i == 0) ? "%s" : " %s",
9379 buf += sprintf(buf, "\n");
9380 return buf - orig_buf;
9383 static ssize_t show_plat_type(struct device *dev,
9384 struct device_attribute *attr, char *buf)
9386 struct platform_device *plat_dev = to_platform_device(dev);
9387 struct niu_parent *p = dev_get_platdata(&plat_dev->dev);
9388 const char *type_str;
9390 switch (p->plat_type) {
9391 case PLAT_TYPE_ATLAS:
9397 case PLAT_TYPE_VF_P0:
9400 case PLAT_TYPE_VF_P1:
9404 type_str = "unknown";
9408 return sprintf(buf, "%s\n", type_str);
9411 static ssize_t __show_chan_per_port(struct device *dev,
9412 struct device_attribute *attr, char *buf,
9415 struct platform_device *plat_dev = to_platform_device(dev);
9416 struct niu_parent *p = dev_get_platdata(&plat_dev->dev);
9417 char *orig_buf = buf;
9421 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9423 for (i = 0; i < p->num_ports; i++) {
9425 (i == 0) ? "%d" : " %d",
9428 buf += sprintf(buf, "\n");
9430 return buf - orig_buf;
9433 static ssize_t show_rxchan_per_port(struct device *dev,
9434 struct device_attribute *attr, char *buf)
9436 return __show_chan_per_port(dev, attr, buf, 1);
9439 static ssize_t show_txchan_per_port(struct device *dev,
9440 struct device_attribute *attr, char *buf)
9442 return __show_chan_per_port(dev, attr, buf, 1);
9445 static ssize_t show_num_ports(struct device *dev,
9446 struct device_attribute *attr, char *buf)
9448 struct platform_device *plat_dev = to_platform_device(dev);
9449 struct niu_parent *p = dev_get_platdata(&plat_dev->dev);
9451 return sprintf(buf, "%d\n", p->num_ports);
9454 static struct device_attribute niu_parent_attributes[] = {
9455 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9456 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9457 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9458 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9459 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9463 static struct niu_parent *niu_new_parent(struct niu *np,
9464 union niu_parent_id *id, u8 ptype)
9466 struct platform_device *plat_dev;
9467 struct niu_parent *p;
9470 plat_dev = platform_device_register_simple("niu-board", niu_parent_index,
9472 if (IS_ERR(plat_dev))
9475 for (i = 0; niu_parent_attributes[i].attr.name; i++) {
9476 int err = device_create_file(&plat_dev->dev,
9477 &niu_parent_attributes[i]);
9479 goto fail_unregister;
9482 p = kzalloc(sizeof(*p), GFP_KERNEL);
9484 goto fail_unregister;
9486 p->index = niu_parent_index++;
9488 plat_dev->dev.platform_data = p;
9489 p->plat_dev = plat_dev;
9491 memcpy(&p->id, id, sizeof(*id));
9492 p->plat_type = ptype;
9493 INIT_LIST_HEAD(&p->list);
9494 atomic_set(&p->refcnt, 0);
9495 list_add(&p->list, &niu_parent_list);
9496 spin_lock_init(&p->lock);
9498 p->rxdma_clock_divider = 7500;
9500 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9501 if (p->plat_type == PLAT_TYPE_NIU)
9502 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9504 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9505 int index = i - CLASS_CODE_USER_PROG1;
9507 p->tcam_key[index] = TCAM_KEY_TSEL;
9508 p->flow_key[index] = (FLOW_KEY_IPSA |
9511 (FLOW_KEY_L4_BYTE12 <<
9512 FLOW_KEY_L4_0_SHIFT) |
9513 (FLOW_KEY_L4_BYTE12 <<
9514 FLOW_KEY_L4_1_SHIFT));
9517 for (i = 0; i < LDN_MAX + 1; i++)
9518 p->ldg_map[i] = LDG_INVALID;
9523 platform_device_unregister(plat_dev);
9527 static struct niu_parent *niu_get_parent(struct niu *np,
9528 union niu_parent_id *id, u8 ptype)
9530 struct niu_parent *p, *tmp;
9531 int port = np->port;
9533 mutex_lock(&niu_parent_lock);
9535 list_for_each_entry(tmp, &niu_parent_list, list) {
9536 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9542 p = niu_new_parent(np, id, ptype);
9548 sprintf(port_name, "port%d", port);
9549 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9553 p->ports[port] = np;
9554 atomic_inc(&p->refcnt);
9557 mutex_unlock(&niu_parent_lock);
9562 static void niu_put_parent(struct niu *np)
9564 struct niu_parent *p = np->parent;
9568 BUG_ON(!p || p->ports[port] != np);
9570 netif_printk(np, probe, KERN_DEBUG, np->dev,
9571 "%s() port[%u]\n", __func__, port);
9573 sprintf(port_name, "port%d", port);
9575 mutex_lock(&niu_parent_lock);
9577 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9579 p->ports[port] = NULL;
9582 if (atomic_dec_and_test(&p->refcnt)) {
9584 platform_device_unregister(p->plat_dev);
9587 mutex_unlock(&niu_parent_lock);
9590 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9591 u64 *handle, gfp_t flag)
9596 ret = dma_alloc_coherent(dev, size, &dh, flag);
9602 static void niu_pci_free_coherent(struct device *dev, size_t size,
9603 void *cpu_addr, u64 handle)
9605 dma_free_coherent(dev, size, cpu_addr, handle);
9608 static u64 niu_pci_map_page(struct device *dev, struct page *page,
9609 unsigned long offset, size_t size,
9610 enum dma_data_direction direction)
9612 return dma_map_page(dev, page, offset, size, direction);
9615 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9616 size_t size, enum dma_data_direction direction)
9618 dma_unmap_page(dev, dma_address, size, direction);
9621 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9623 enum dma_data_direction direction)
9625 return dma_map_single(dev, cpu_addr, size, direction);
9628 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9630 enum dma_data_direction direction)
9632 dma_unmap_single(dev, dma_address, size, direction);
9635 static const struct niu_ops niu_pci_ops = {
9636 .alloc_coherent = niu_pci_alloc_coherent,
9637 .free_coherent = niu_pci_free_coherent,
9638 .map_page = niu_pci_map_page,
9639 .unmap_page = niu_pci_unmap_page,
9640 .map_single = niu_pci_map_single,
9641 .unmap_single = niu_pci_unmap_single,
9644 static void niu_driver_version(void)
9646 static int niu_version_printed;
9648 if (niu_version_printed++ == 0)
9649 pr_info("%s", version);
9652 static struct net_device *niu_alloc_and_init(struct device *gen_dev,
9653 struct pci_dev *pdev,
9654 struct platform_device *op,
9655 const struct niu_ops *ops, u8 port)
9657 struct net_device *dev;
9660 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
9664 SET_NETDEV_DEV(dev, gen_dev);
9666 np = netdev_priv(dev);
9670 np->device = gen_dev;
9673 np->msg_enable = niu_debug;
9675 spin_lock_init(&np->lock);
9676 INIT_WORK(&np->reset_task, niu_reset_task);
9683 static const struct net_device_ops niu_netdev_ops = {
9684 .ndo_open = niu_open,
9685 .ndo_stop = niu_close,
9686 .ndo_start_xmit = niu_start_xmit,
9687 .ndo_get_stats64 = niu_get_stats,
9688 .ndo_set_rx_mode = niu_set_rx_mode,
9689 .ndo_validate_addr = eth_validate_addr,
9690 .ndo_set_mac_address = niu_set_mac_addr,
9691 .ndo_do_ioctl = niu_ioctl,
9692 .ndo_tx_timeout = niu_tx_timeout,
9693 .ndo_change_mtu = niu_change_mtu,
9696 static void niu_assign_netdev_ops(struct net_device *dev)
9698 dev->netdev_ops = &niu_netdev_ops;
9699 dev->ethtool_ops = &niu_ethtool_ops;
9700 dev->watchdog_timeo = NIU_TX_TIMEOUT;
9703 static void niu_device_announce(struct niu *np)
9705 struct net_device *dev = np->dev;
9707 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
9709 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9710 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9712 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9713 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9714 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9715 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9716 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9719 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9721 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9722 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9723 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9724 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9726 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9727 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9732 static void niu_set_basic_features(struct net_device *dev)
9734 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXHASH;
9735 dev->features |= dev->hw_features | NETIF_F_RXCSUM;
9738 static int niu_pci_init_one(struct pci_dev *pdev,
9739 const struct pci_device_id *ent)
9741 union niu_parent_id parent_id;
9742 struct net_device *dev;
9747 niu_driver_version();
9749 err = pci_enable_device(pdev);
9751 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9755 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9756 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9757 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
9759 goto err_out_disable_pdev;
9762 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9764 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9765 goto err_out_disable_pdev;
9768 if (!pci_is_pcie(pdev)) {
9769 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
9771 goto err_out_free_res;
9774 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9775 &niu_pci_ops, PCI_FUNC(pdev->devfn));
9778 goto err_out_free_res;
9780 np = netdev_priv(dev);
9782 memset(&parent_id, 0, sizeof(parent_id));
9783 parent_id.pci.domain = pci_domain_nr(pdev->bus);
9784 parent_id.pci.bus = pdev->bus->number;
9785 parent_id.pci.device = PCI_SLOT(pdev->devfn);
9787 np->parent = niu_get_parent(np, &parent_id,
9791 goto err_out_free_dev;
9794 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
9795 PCI_EXP_DEVCTL_NOSNOOP_EN,
9796 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
9797 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE |
9798 PCI_EXP_DEVCTL_RELAX_EN);
9800 dma_mask = DMA_BIT_MASK(44);
9801 err = pci_set_dma_mask(pdev, dma_mask);
9803 dev->features |= NETIF_F_HIGHDMA;
9804 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9806 dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
9807 goto err_out_release_parent;
9811 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9813 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
9814 goto err_out_release_parent;
9818 niu_set_basic_features(dev);
9820 dev->priv_flags |= IFF_UNICAST_FLT;
9822 np->regs = pci_ioremap_bar(pdev, 0);
9824 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9826 goto err_out_release_parent;
9829 pci_set_master(pdev);
9830 pci_save_state(pdev);
9832 dev->irq = pdev->irq;
9834 /* MTU range: 68 - 9216 */
9835 dev->min_mtu = ETH_MIN_MTU;
9836 dev->max_mtu = NIU_MAX_MTU;
9838 niu_assign_netdev_ops(dev);
9840 err = niu_get_invariants(np);
9843 dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
9844 goto err_out_iounmap;
9847 err = register_netdev(dev);
9849 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
9850 goto err_out_iounmap;
9853 pci_set_drvdata(pdev, dev);
9855 niu_device_announce(np);
9865 err_out_release_parent:
9872 pci_release_regions(pdev);
9874 err_out_disable_pdev:
9875 pci_disable_device(pdev);
9880 static void niu_pci_remove_one(struct pci_dev *pdev)
9882 struct net_device *dev = pci_get_drvdata(pdev);
9885 struct niu *np = netdev_priv(dev);
9887 unregister_netdev(dev);
9898 pci_release_regions(pdev);
9899 pci_disable_device(pdev);
9903 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9905 struct net_device *dev = pci_get_drvdata(pdev);
9906 struct niu *np = netdev_priv(dev);
9907 unsigned long flags;
9909 if (!netif_running(dev))
9912 flush_work(&np->reset_task);
9915 del_timer_sync(&np->timer);
9917 spin_lock_irqsave(&np->lock, flags);
9918 niu_enable_interrupts(np, 0);
9919 spin_unlock_irqrestore(&np->lock, flags);
9921 netif_device_detach(dev);
9923 spin_lock_irqsave(&np->lock, flags);
9925 spin_unlock_irqrestore(&np->lock, flags);
9927 pci_save_state(pdev);
9932 static int niu_resume(struct pci_dev *pdev)
9934 struct net_device *dev = pci_get_drvdata(pdev);
9935 struct niu *np = netdev_priv(dev);
9936 unsigned long flags;
9939 if (!netif_running(dev))
9942 pci_restore_state(pdev);
9944 netif_device_attach(dev);
9946 spin_lock_irqsave(&np->lock, flags);
9948 err = niu_init_hw(np);
9950 np->timer.expires = jiffies + HZ;
9951 add_timer(&np->timer);
9952 niu_netif_start(np);
9955 spin_unlock_irqrestore(&np->lock, flags);
9960 static struct pci_driver niu_pci_driver = {
9961 .name = DRV_MODULE_NAME,
9962 .id_table = niu_pci_tbl,
9963 .probe = niu_pci_init_one,
9964 .remove = niu_pci_remove_one,
9965 .suspend = niu_suspend,
9966 .resume = niu_resume,
9969 #ifdef CONFIG_SPARC64
9970 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
9971 u64 *dma_addr, gfp_t flag)
9973 unsigned long order = get_order(size);
9974 unsigned long page = __get_free_pages(flag, order);
9978 memset((char *)page, 0, PAGE_SIZE << order);
9979 *dma_addr = __pa(page);
9981 return (void *) page;
9984 static void niu_phys_free_coherent(struct device *dev, size_t size,
9985 void *cpu_addr, u64 handle)
9987 unsigned long order = get_order(size);
9989 free_pages((unsigned long) cpu_addr, order);
9992 static u64 niu_phys_map_page(struct device *dev, struct page *page,
9993 unsigned long offset, size_t size,
9994 enum dma_data_direction direction)
9996 return page_to_phys(page) + offset;
9999 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
10000 size_t size, enum dma_data_direction direction)
10002 /* Nothing to do. */
10005 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
10007 enum dma_data_direction direction)
10009 return __pa(cpu_addr);
10012 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
10014 enum dma_data_direction direction)
10016 /* Nothing to do. */
10019 static const struct niu_ops niu_phys_ops = {
10020 .alloc_coherent = niu_phys_alloc_coherent,
10021 .free_coherent = niu_phys_free_coherent,
10022 .map_page = niu_phys_map_page,
10023 .unmap_page = niu_phys_unmap_page,
10024 .map_single = niu_phys_map_single,
10025 .unmap_single = niu_phys_unmap_single,
10028 static int niu_of_probe(struct platform_device *op)
10030 union niu_parent_id parent_id;
10031 struct net_device *dev;
10036 niu_driver_version();
10038 reg = of_get_property(op->dev.of_node, "reg", NULL);
10040 dev_err(&op->dev, "%pOF: No 'reg' property, aborting\n",
10045 dev = niu_alloc_and_init(&op->dev, NULL, op,
10046 &niu_phys_ops, reg[0] & 0x1);
10051 np = netdev_priv(dev);
10053 memset(&parent_id, 0, sizeof(parent_id));
10054 parent_id.of = of_get_parent(op->dev.of_node);
10056 np->parent = niu_get_parent(np, &parent_id,
10060 goto err_out_free_dev;
10063 niu_set_basic_features(dev);
10065 np->regs = of_ioremap(&op->resource[1], 0,
10066 resource_size(&op->resource[1]),
10069 dev_err(&op->dev, "Cannot map device registers, aborting\n");
10071 goto err_out_release_parent;
10074 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
10075 resource_size(&op->resource[2]),
10077 if (!np->vir_regs_1) {
10078 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
10080 goto err_out_iounmap;
10083 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
10084 resource_size(&op->resource[3]),
10086 if (!np->vir_regs_2) {
10087 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
10089 goto err_out_iounmap;
10092 niu_assign_netdev_ops(dev);
10094 err = niu_get_invariants(np);
10096 if (err != -ENODEV)
10097 dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
10098 goto err_out_iounmap;
10101 err = register_netdev(dev);
10103 dev_err(&op->dev, "Cannot register net device, aborting\n");
10104 goto err_out_iounmap;
10107 platform_set_drvdata(op, dev);
10109 niu_device_announce(np);
10114 if (np->vir_regs_1) {
10115 of_iounmap(&op->resource[2], np->vir_regs_1,
10116 resource_size(&op->resource[2]));
10117 np->vir_regs_1 = NULL;
10120 if (np->vir_regs_2) {
10121 of_iounmap(&op->resource[3], np->vir_regs_2,
10122 resource_size(&op->resource[3]));
10123 np->vir_regs_2 = NULL;
10127 of_iounmap(&op->resource[1], np->regs,
10128 resource_size(&op->resource[1]));
10132 err_out_release_parent:
10133 niu_put_parent(np);
10142 static int niu_of_remove(struct platform_device *op)
10144 struct net_device *dev = platform_get_drvdata(op);
10147 struct niu *np = netdev_priv(dev);
10149 unregister_netdev(dev);
10151 if (np->vir_regs_1) {
10152 of_iounmap(&op->resource[2], np->vir_regs_1,
10153 resource_size(&op->resource[2]));
10154 np->vir_regs_1 = NULL;
10157 if (np->vir_regs_2) {
10158 of_iounmap(&op->resource[3], np->vir_regs_2,
10159 resource_size(&op->resource[3]));
10160 np->vir_regs_2 = NULL;
10164 of_iounmap(&op->resource[1], np->regs,
10165 resource_size(&op->resource[1]));
10171 niu_put_parent(np);
10178 static const struct of_device_id niu_match[] = {
10181 .compatible = "SUNW,niusl",
10185 MODULE_DEVICE_TABLE(of, niu_match);
10187 static struct platform_driver niu_of_driver = {
10190 .of_match_table = niu_match,
10192 .probe = niu_of_probe,
10193 .remove = niu_of_remove,
10196 #endif /* CONFIG_SPARC64 */
10198 static int __init niu_init(void)
10202 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
10204 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10206 #ifdef CONFIG_SPARC64
10207 err = platform_driver_register(&niu_of_driver);
10211 err = pci_register_driver(&niu_pci_driver);
10212 #ifdef CONFIG_SPARC64
10214 platform_driver_unregister(&niu_of_driver);
10221 static void __exit niu_exit(void)
10223 pci_unregister_driver(&niu_pci_driver);
10224 #ifdef CONFIG_SPARC64
10225 platform_driver_unregister(&niu_of_driver);
10229 module_init(niu_init);
10230 module_exit(niu_exit);