1 // SPDX-License-Identifier: GPL-2.0+
2 /* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
4 * Copyright (C) 2004 Sun Microsystems Inc.
5 * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
7 * This driver uses the sungem driver (c) David Miller
8 * (davem@redhat.com) as its basis.
10 * The cassini chip has a number of features that distinguish it from
12 * 4 transmit descriptor rings that are used for either QoS (VLAN) or
13 * load balancing (non-VLAN mode)
14 * batching of multiple packets
15 * multiple CPU dispatching
16 * page-based RX descriptor engine with separate completion rings
17 * Gigabit support (GMII and PCS interface)
18 * MIF link up/down detection works
20 * RX is handled by page sized buffers that are attached as fragments to
21 * the skb. here's what's done:
22 * -- driver allocates pages at a time and keeps reference counts
24 * -- the upper protocol layers assume that the header is in the skb
25 * itself. as a result, cassini will copy a small amount (64 bytes)
27 * -- driver appends the rest of the data pages as frags to skbuffs
28 * and increments the reference count
29 * -- on page reclamation, the driver swaps the page with a spare page.
30 * if that page is still in use, it frees its reference to that page,
31 * and allocates a new page for use. otherwise, it just recycles the
34 * NOTE: cassini can parse the header. however, it's not worth it
35 * as long as the network stack requires a header copy.
37 * TX has 4 queues. currently these queues are used in a round-robin
38 * fashion for load balancing. They can also be used for QoS. for that
39 * to work, however, QoS information needs to be exposed down to the driver
40 * level so that subqueues get targeted to particular transmit rings.
41 * alternatively, the queues can be configured via use of the all-purpose
44 * RX DATA: the rx completion ring has all the info, but the rx desc
45 * ring has all of the data. RX can conceivably come in under multiple
46 * interrupts, but the INT# assignment needs to be set up properly by
47 * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
48 * that. also, the two descriptor rings are designed to distinguish between
49 * encrypted and non-encrypted packets, but we use them for buffering
52 * by default, the selective clear mask is set up to process rx packets.
55 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
57 #include <linux/module.h>
58 #include <linux/kernel.h>
59 #include <linux/types.h>
60 #include <linux/compiler.h>
61 #include <linux/slab.h>
62 #include <linux/delay.h>
63 #include <linux/init.h>
64 #include <linux/interrupt.h>
65 #include <linux/vmalloc.h>
66 #include <linux/ioport.h>
67 #include <linux/pci.h>
69 #include <linux/highmem.h>
70 #include <linux/list.h>
71 #include <linux/dma-mapping.h>
73 #include <linux/netdevice.h>
74 #include <linux/etherdevice.h>
75 #include <linux/skbuff.h>
76 #include <linux/ethtool.h>
77 #include <linux/crc32.h>
78 #include <linux/random.h>
79 #include <linux/mii.h>
81 #include <linux/tcp.h>
82 #include <linux/mutex.h>
83 #include <linux/firmware.h>
85 #include <net/checksum.h>
87 #include <linux/atomic.h>
89 #include <asm/byteorder.h>
90 #include <linux/uaccess.h>
92 #define cas_page_map(x) kmap_atomic((x))
93 #define cas_page_unmap(x) kunmap_atomic((x))
94 #define CAS_NCPUS num_online_cpus()
96 #define cas_skb_release(x) netif_rx(x)
98 /* select which firmware to use */
99 #define USE_HP_WORKAROUND
100 #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
101 #define CAS_HP_ALT_FIRMWARE cas_prog_null /* alternate firmware */
105 #define USE_TX_COMPWB /* use completion writeback registers */
106 #define USE_CSMA_CD_PROTO /* standard CSMA/CD */
107 #define USE_RX_BLANK /* hw interrupt mitigation */
108 #undef USE_ENTROPY_DEV /* don't test for entropy device */
110 /* NOTE: these aren't useable unless PCI interrupts can be assigned.
111 * also, we need to make cp->lock finer-grained.
118 #undef USE_VPD_DEBUG /* debug vpd information if defined */
120 /* rx processing options */
121 #define USE_PAGE_ORDER /* specify to allocate large rx pages */
122 #define RX_DONT_BATCH 0 /* if 1, don't batch flows */
123 #define RX_COPY_ALWAYS 0 /* if 0, use frags */
124 #define RX_COPY_MIN 64 /* copy a little to make upper layers happy */
125 #undef RX_COUNT_BUFFERS /* define to calculate RX buffer stats */
127 #define DRV_MODULE_NAME "cassini"
128 #define DRV_MODULE_VERSION "1.6"
129 #define DRV_MODULE_RELDATE "21 May 2008"
131 #define CAS_DEF_MSG_ENABLE \
141 /* length of time before we decide the hardware is borked,
142 * and dev->tx_timeout() should be called to fix the problem
144 #define CAS_TX_TIMEOUT (HZ)
145 #define CAS_LINK_TIMEOUT (22*HZ/10)
146 #define CAS_LINK_FAST_TIMEOUT (1)
148 /* timeout values for state changing. these specify the number
149 * of 10us delays to be used before giving up.
151 #define STOP_TRIES_PHY 1000
152 #define STOP_TRIES 5000
154 /* specify a minimum frame size to deal with some fifo issues
155 * max mtu == 2 * page size - ethernet header - 64 - swivel =
156 * 2 * page_size - 0x50
158 #define CAS_MIN_FRAME 97
159 #define CAS_1000MB_MIN_FRAME 255
160 #define CAS_MIN_MTU 60
161 #define CAS_MAX_MTU min(((cp->page_size << 1) - 0x50), 9000)
165 * Eliminate these and use separate atomic counters for each, to
166 * avoid a race condition.
169 #define CAS_RESET_MTU 1
170 #define CAS_RESET_ALL 2
171 #define CAS_RESET_SPARE 3
174 static char version[] =
175 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
177 static int cassini_debug = -1; /* -1 == use CAS_DEF_MSG_ENABLE as value */
178 static int link_mode;
180 MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
181 MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
182 MODULE_LICENSE("GPL");
184 module_param(cassini_debug, int, 0);
185 MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
186 module_param(link_mode, int, 0);
187 MODULE_PARM_DESC(link_mode, "default link mode");
190 * Work around for a PCS bug in which the link goes down due to the chip
191 * being confused and never showing a link status of "up."
193 #define DEFAULT_LINKDOWN_TIMEOUT 5
195 * Value in seconds, for user input.
197 static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
198 module_param(linkdown_timeout, int, 0);
199 MODULE_PARM_DESC(linkdown_timeout,
200 "min reset interval in sec. for PCS linkdown issue; disabled if not positive");
203 * value in 'ticks' (units used by jiffies). Set when we init the
204 * module because 'HZ' in actually a function call on some flavors of
205 * Linux. This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
207 static int link_transition_timeout;
211 static u16 link_modes[] = {
212 BMCR_ANENABLE, /* 0 : autoneg */
213 0, /* 1 : 10bt half duplex */
214 BMCR_SPEED100, /* 2 : 100bt half duplex */
215 BMCR_FULLDPLX, /* 3 : 10bt full duplex */
216 BMCR_SPEED100|BMCR_FULLDPLX, /* 4 : 100bt full duplex */
217 CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */
220 static const struct pci_device_id cas_pci_tbl[] = {
221 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
223 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
228 MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
230 static void cas_set_link_modes(struct cas *cp);
232 static inline void cas_lock_tx(struct cas *cp)
236 for (i = 0; i < N_TX_RINGS; i++)
237 spin_lock_nested(&cp->tx_lock[i], i);
240 /* WTZ: QA was finding deadlock problems with the previous
241 * versions after long test runs with multiple cards per machine.
242 * See if replacing cas_lock_all with safer versions helps. The
243 * symptoms QA is reporting match those we'd expect if interrupts
244 * aren't being properly restored, and we fixed a previous deadlock
245 * with similar symptoms by using save/restore versions in other
248 #define cas_lock_all_save(cp, flags) \
250 struct cas *xxxcp = (cp); \
251 spin_lock_irqsave(&xxxcp->lock, flags); \
252 cas_lock_tx(xxxcp); \
255 static inline void cas_unlock_tx(struct cas *cp)
259 for (i = N_TX_RINGS; i > 0; i--)
260 spin_unlock(&cp->tx_lock[i - 1]);
263 #define cas_unlock_all_restore(cp, flags) \
265 struct cas *xxxcp = (cp); \
266 cas_unlock_tx(xxxcp); \
267 spin_unlock_irqrestore(&xxxcp->lock, flags); \
270 static void cas_disable_irq(struct cas *cp, const int ring)
272 /* Make sure we won't get any more interrupts */
274 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
278 /* disable completion interrupts and selectively mask */
279 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
281 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
291 writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
292 cp->regs + REG_PLUS_INTRN_MASK(ring));
296 writel(INTRN_MASK_CLEAR_ALL, cp->regs +
297 REG_PLUS_INTRN_MASK(ring));
303 static inline void cas_mask_intr(struct cas *cp)
307 for (i = 0; i < N_RX_COMP_RINGS; i++)
308 cas_disable_irq(cp, i);
311 static void cas_enable_irq(struct cas *cp, const int ring)
313 if (ring == 0) { /* all but TX_DONE */
314 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
318 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
320 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
330 writel(INTRN_MASK_RX_EN, cp->regs +
331 REG_PLUS_INTRN_MASK(ring));
340 static inline void cas_unmask_intr(struct cas *cp)
344 for (i = 0; i < N_RX_COMP_RINGS; i++)
345 cas_enable_irq(cp, i);
348 static inline void cas_entropy_gather(struct cas *cp)
350 #ifdef USE_ENTROPY_DEV
351 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
354 batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
355 readl(cp->regs + REG_ENTROPY_IV),
360 static inline void cas_entropy_reset(struct cas *cp)
362 #ifdef USE_ENTROPY_DEV
363 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
366 writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
367 cp->regs + REG_BIM_LOCAL_DEV_EN);
368 writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
369 writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
371 /* if we read back 0x0, we don't have an entropy device */
372 if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
373 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
377 /* access to the phy. the following assumes that we've initialized the MIF to
378 * be in frame rather than bit-bang mode
380 static u16 cas_phy_read(struct cas *cp, int reg)
383 int limit = STOP_TRIES_PHY;
385 cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
386 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
387 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
388 cmd |= MIF_FRAME_TURN_AROUND_MSB;
389 writel(cmd, cp->regs + REG_MIF_FRAME);
391 /* poll for completion */
392 while (limit-- > 0) {
394 cmd = readl(cp->regs + REG_MIF_FRAME);
395 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
396 return cmd & MIF_FRAME_DATA_MASK;
398 return 0xFFFF; /* -1 */
401 static int cas_phy_write(struct cas *cp, int reg, u16 val)
403 int limit = STOP_TRIES_PHY;
406 cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
407 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
408 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
409 cmd |= MIF_FRAME_TURN_AROUND_MSB;
410 cmd |= val & MIF_FRAME_DATA_MASK;
411 writel(cmd, cp->regs + REG_MIF_FRAME);
413 /* poll for completion */
414 while (limit-- > 0) {
416 cmd = readl(cp->regs + REG_MIF_FRAME);
417 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
423 static void cas_phy_powerup(struct cas *cp)
425 u16 ctl = cas_phy_read(cp, MII_BMCR);
427 if ((ctl & BMCR_PDOWN) == 0)
430 cas_phy_write(cp, MII_BMCR, ctl);
433 static void cas_phy_powerdown(struct cas *cp)
435 u16 ctl = cas_phy_read(cp, MII_BMCR);
437 if (ctl & BMCR_PDOWN)
440 cas_phy_write(cp, MII_BMCR, ctl);
443 /* cp->lock held. note: the last put_page will free the buffer */
444 static int cas_page_free(struct cas *cp, cas_page_t *page)
446 dma_unmap_page(&cp->pdev->dev, page->dma_addr, cp->page_size,
448 __free_pages(page->buffer, cp->page_order);
453 #ifdef RX_COUNT_BUFFERS
454 #define RX_USED_ADD(x, y) ((x)->used += (y))
455 #define RX_USED_SET(x, y) ((x)->used = (y))
457 #define RX_USED_ADD(x, y) do { } while(0)
458 #define RX_USED_SET(x, y) do { } while(0)
461 /* local page allocation routines for the receive buffers. jumbo pages
462 * require at least 8K contiguous and 8K aligned buffers.
464 static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
468 page = kmalloc(sizeof(cas_page_t), flags);
472 INIT_LIST_HEAD(&page->list);
473 RX_USED_SET(page, 0);
474 page->buffer = alloc_pages(flags, cp->page_order);
477 page->dma_addr = dma_map_page(&cp->pdev->dev, page->buffer, 0,
478 cp->page_size, DMA_FROM_DEVICE);
486 /* initialize spare pool of rx buffers, but allocate during the open */
487 static void cas_spare_init(struct cas *cp)
489 spin_lock(&cp->rx_inuse_lock);
490 INIT_LIST_HEAD(&cp->rx_inuse_list);
491 spin_unlock(&cp->rx_inuse_lock);
493 spin_lock(&cp->rx_spare_lock);
494 INIT_LIST_HEAD(&cp->rx_spare_list);
495 cp->rx_spares_needed = RX_SPARE_COUNT;
496 spin_unlock(&cp->rx_spare_lock);
499 /* used on close. free all the spare buffers. */
500 static void cas_spare_free(struct cas *cp)
502 struct list_head list, *elem, *tmp;
504 /* free spare buffers */
505 INIT_LIST_HEAD(&list);
506 spin_lock(&cp->rx_spare_lock);
507 list_splice_init(&cp->rx_spare_list, &list);
508 spin_unlock(&cp->rx_spare_lock);
509 list_for_each_safe(elem, tmp, &list) {
510 cas_page_free(cp, list_entry(elem, cas_page_t, list));
513 INIT_LIST_HEAD(&list);
516 * Looks like Adrian had protected this with a different
517 * lock than used everywhere else to manipulate this list.
519 spin_lock(&cp->rx_inuse_lock);
520 list_splice_init(&cp->rx_inuse_list, &list);
521 spin_unlock(&cp->rx_inuse_lock);
523 spin_lock(&cp->rx_spare_lock);
524 list_splice_init(&cp->rx_inuse_list, &list);
525 spin_unlock(&cp->rx_spare_lock);
527 list_for_each_safe(elem, tmp, &list) {
528 cas_page_free(cp, list_entry(elem, cas_page_t, list));
532 /* replenish spares if needed */
533 static void cas_spare_recover(struct cas *cp, const gfp_t flags)
535 struct list_head list, *elem, *tmp;
538 /* check inuse list. if we don't need any more free buffers,
542 /* make a local copy of the list */
543 INIT_LIST_HEAD(&list);
544 spin_lock(&cp->rx_inuse_lock);
545 list_splice_init(&cp->rx_inuse_list, &list);
546 spin_unlock(&cp->rx_inuse_lock);
548 list_for_each_safe(elem, tmp, &list) {
549 cas_page_t *page = list_entry(elem, cas_page_t, list);
552 * With the lockless pagecache, cassini buffering scheme gets
553 * slightly less accurate: we might find that a page has an
554 * elevated reference count here, due to a speculative ref,
555 * and skip it as in-use. Ideally we would be able to reclaim
556 * it. However this would be such a rare case, it doesn't
557 * matter too much as we should pick it up the next time round.
559 * Importantly, if we find that the page has a refcount of 1
560 * here (our refcount), then we know it is definitely not inuse
561 * so we can reuse it.
563 if (page_count(page->buffer) > 1)
567 spin_lock(&cp->rx_spare_lock);
568 if (cp->rx_spares_needed > 0) {
569 list_add(elem, &cp->rx_spare_list);
570 cp->rx_spares_needed--;
571 spin_unlock(&cp->rx_spare_lock);
573 spin_unlock(&cp->rx_spare_lock);
574 cas_page_free(cp, page);
578 /* put any inuse buffers back on the list */
579 if (!list_empty(&list)) {
580 spin_lock(&cp->rx_inuse_lock);
581 list_splice(&list, &cp->rx_inuse_list);
582 spin_unlock(&cp->rx_inuse_lock);
585 spin_lock(&cp->rx_spare_lock);
586 needed = cp->rx_spares_needed;
587 spin_unlock(&cp->rx_spare_lock);
591 /* we still need spares, so try to allocate some */
592 INIT_LIST_HEAD(&list);
595 cas_page_t *spare = cas_page_alloc(cp, flags);
598 list_add(&spare->list, &list);
602 spin_lock(&cp->rx_spare_lock);
603 list_splice(&list, &cp->rx_spare_list);
604 cp->rx_spares_needed -= i;
605 spin_unlock(&cp->rx_spare_lock);
608 /* pull a page from the list. */
609 static cas_page_t *cas_page_dequeue(struct cas *cp)
611 struct list_head *entry;
614 spin_lock(&cp->rx_spare_lock);
615 if (list_empty(&cp->rx_spare_list)) {
616 /* try to do a quick recovery */
617 spin_unlock(&cp->rx_spare_lock);
618 cas_spare_recover(cp, GFP_ATOMIC);
619 spin_lock(&cp->rx_spare_lock);
620 if (list_empty(&cp->rx_spare_list)) {
621 netif_err(cp, rx_err, cp->dev,
622 "no spare buffers available\n");
623 spin_unlock(&cp->rx_spare_lock);
628 entry = cp->rx_spare_list.next;
630 recover = ++cp->rx_spares_needed;
631 spin_unlock(&cp->rx_spare_lock);
633 /* trigger the timer to do the recovery */
634 if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
636 atomic_inc(&cp->reset_task_pending);
637 atomic_inc(&cp->reset_task_pending_spare);
638 schedule_work(&cp->reset_task);
640 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
641 schedule_work(&cp->reset_task);
644 return list_entry(entry, cas_page_t, list);
648 static void cas_mif_poll(struct cas *cp, const int enable)
652 cfg = readl(cp->regs + REG_MIF_CFG);
653 cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
655 if (cp->phy_type & CAS_PHY_MII_MDIO1)
656 cfg |= MIF_CFG_PHY_SELECT;
658 /* poll and interrupt on link status change. */
660 cfg |= MIF_CFG_POLL_EN;
661 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
662 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
664 writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
665 cp->regs + REG_MIF_MASK);
666 writel(cfg, cp->regs + REG_MIF_CFG);
669 /* Must be invoked under cp->lock */
670 static void cas_begin_auto_negotiation(struct cas *cp,
671 const struct ethtool_link_ksettings *ep)
677 int oldstate = cp->lstate;
678 int link_was_not_down = !(oldstate == link_down);
680 /* Setup link parameters */
683 lcntl = cp->link_cntl;
684 if (ep->base.autoneg == AUTONEG_ENABLE) {
685 cp->link_cntl = BMCR_ANENABLE;
687 u32 speed = ep->base.speed;
689 if (speed == SPEED_100)
690 cp->link_cntl |= BMCR_SPEED100;
691 else if (speed == SPEED_1000)
692 cp->link_cntl |= CAS_BMCR_SPEED1000;
693 if (ep->base.duplex == DUPLEX_FULL)
694 cp->link_cntl |= BMCR_FULLDPLX;
697 changed = (lcntl != cp->link_cntl);
700 if (cp->lstate == link_up) {
701 netdev_info(cp->dev, "PCS link down\n");
704 netdev_info(cp->dev, "link configuration changed\n");
707 cp->lstate = link_down;
708 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
713 * WTZ: If the old state was link_up, we turn off the carrier
714 * to replicate everything we do elsewhere on a link-down
715 * event when we were already in a link-up state..
717 if (oldstate == link_up)
718 netif_carrier_off(cp->dev);
719 if (changed && link_was_not_down) {
721 * WTZ: This branch will simply schedule a full reset after
722 * we explicitly changed link modes in an ioctl. See if this
723 * fixes the link-problems we were having for forced mode.
725 atomic_inc(&cp->reset_task_pending);
726 atomic_inc(&cp->reset_task_pending_all);
727 schedule_work(&cp->reset_task);
729 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
733 if (cp->phy_type & CAS_PHY_SERDES) {
734 u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
736 if (cp->link_cntl & BMCR_ANENABLE) {
737 val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
738 cp->lstate = link_aneg;
740 if (cp->link_cntl & BMCR_FULLDPLX)
741 val |= PCS_MII_CTRL_DUPLEX;
742 val &= ~PCS_MII_AUTONEG_EN;
743 cp->lstate = link_force_ok;
745 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
746 writel(val, cp->regs + REG_PCS_MII_CTRL);
750 ctl = cas_phy_read(cp, MII_BMCR);
751 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
752 CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
753 ctl |= cp->link_cntl;
754 if (ctl & BMCR_ANENABLE) {
755 ctl |= BMCR_ANRESTART;
756 cp->lstate = link_aneg;
758 cp->lstate = link_force_ok;
760 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
761 cas_phy_write(cp, MII_BMCR, ctl);
766 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
769 /* Must be invoked under cp->lock. */
770 static int cas_reset_mii_phy(struct cas *cp)
772 int limit = STOP_TRIES_PHY;
775 cas_phy_write(cp, MII_BMCR, BMCR_RESET);
778 val = cas_phy_read(cp, MII_BMCR);
779 if ((val & BMCR_RESET) == 0)
786 static void cas_saturn_firmware_init(struct cas *cp)
788 const struct firmware *fw;
789 const char fw_name[] = "/*(DEBLOBBED)*/";
792 if (PHY_NS_DP83065 != cp->phy_id)
795 err = reject_firmware(&fw, fw_name, &cp->pdev->dev);
797 pr_err("Failed to load firmware \"%s\"\n",
802 pr_err("bogus length %zu in \"%s\"\n",
806 cp->fw_load_addr= fw->data[1] << 8 | fw->data[0];
807 cp->fw_size = fw->size - 2;
808 cp->fw_data = vmalloc(cp->fw_size);
811 memcpy(cp->fw_data, &fw->data[2], cp->fw_size);
813 release_firmware(fw);
816 static void cas_saturn_firmware_load(struct cas *cp)
823 cas_phy_powerdown(cp);
825 /* expanded memory access mode */
826 cas_phy_write(cp, DP83065_MII_MEM, 0x0);
828 /* pointer configuration for new firmware */
829 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
830 cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
831 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
832 cas_phy_write(cp, DP83065_MII_REGD, 0x82);
833 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
834 cas_phy_write(cp, DP83065_MII_REGD, 0x0);
835 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
836 cas_phy_write(cp, DP83065_MII_REGD, 0x39);
838 /* download new firmware */
839 cas_phy_write(cp, DP83065_MII_MEM, 0x1);
840 cas_phy_write(cp, DP83065_MII_REGE, cp->fw_load_addr);
841 for (i = 0; i < cp->fw_size; i++)
842 cas_phy_write(cp, DP83065_MII_REGD, cp->fw_data[i]);
844 /* enable firmware */
845 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
846 cas_phy_write(cp, DP83065_MII_REGD, 0x1);
850 /* phy initialization */
851 static void cas_phy_init(struct cas *cp)
855 /* if we're in MII/GMII mode, set up phy */
856 if (CAS_PHY_MII(cp->phy_type)) {
857 writel(PCS_DATAPATH_MODE_MII,
858 cp->regs + REG_PCS_DATAPATH_MODE);
861 cas_reset_mii_phy(cp); /* take out of isolate mode */
863 if (PHY_LUCENT_B0 == cp->phy_id) {
864 /* workaround link up/down issue with lucent */
865 cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
866 cas_phy_write(cp, MII_BMCR, 0x00f1);
867 cas_phy_write(cp, LUCENT_MII_REG, 0x0);
869 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
870 /* workarounds for broadcom phy */
871 cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
872 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
873 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
874 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
875 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
876 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
877 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
878 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
879 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
880 cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
881 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
883 } else if (PHY_BROADCOM_5411 == cp->phy_id) {
884 val = cas_phy_read(cp, BROADCOM_MII_REG4);
885 val = cas_phy_read(cp, BROADCOM_MII_REG4);
887 /* link workaround */
888 cas_phy_write(cp, BROADCOM_MII_REG4,
892 } else if (cp->cas_flags & CAS_FLAG_SATURN) {
893 writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
894 SATURN_PCFG_FSI : 0x0,
895 cp->regs + REG_SATURN_PCFG);
897 /* load firmware to address 10Mbps auto-negotiation
898 * issue. NOTE: this will need to be changed if the
899 * default firmware gets fixed.
901 if (PHY_NS_DP83065 == cp->phy_id) {
902 cas_saturn_firmware_load(cp);
907 /* advertise capabilities */
908 val = cas_phy_read(cp, MII_BMCR);
909 val &= ~BMCR_ANENABLE;
910 cas_phy_write(cp, MII_BMCR, val);
913 cas_phy_write(cp, MII_ADVERTISE,
914 cas_phy_read(cp, MII_ADVERTISE) |
915 (ADVERTISE_10HALF | ADVERTISE_10FULL |
916 ADVERTISE_100HALF | ADVERTISE_100FULL |
917 CAS_ADVERTISE_PAUSE |
918 CAS_ADVERTISE_ASYM_PAUSE));
920 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
921 /* make sure that we don't advertise half
922 * duplex to avoid a chip issue
924 val = cas_phy_read(cp, CAS_MII_1000_CTRL);
925 val &= ~CAS_ADVERTISE_1000HALF;
926 val |= CAS_ADVERTISE_1000FULL;
927 cas_phy_write(cp, CAS_MII_1000_CTRL, val);
931 /* reset pcs for serdes */
935 writel(PCS_DATAPATH_MODE_SERDES,
936 cp->regs + REG_PCS_DATAPATH_MODE);
938 /* enable serdes pins on saturn */
939 if (cp->cas_flags & CAS_FLAG_SATURN)
940 writel(0, cp->regs + REG_SATURN_PCFG);
942 /* Reset PCS unit. */
943 val = readl(cp->regs + REG_PCS_MII_CTRL);
944 val |= PCS_MII_RESET;
945 writel(val, cp->regs + REG_PCS_MII_CTRL);
948 while (--limit > 0) {
950 if ((readl(cp->regs + REG_PCS_MII_CTRL) &
955 netdev_warn(cp->dev, "PCS reset bit would not clear [%08x]\n",
956 readl(cp->regs + REG_PCS_STATE_MACHINE));
958 /* Make sure PCS is disabled while changing advertisement
961 writel(0x0, cp->regs + REG_PCS_CFG);
963 /* Advertise all capabilities except half-duplex. */
964 val = readl(cp->regs + REG_PCS_MII_ADVERT);
965 val &= ~PCS_MII_ADVERT_HD;
966 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
967 PCS_MII_ADVERT_ASYM_PAUSE);
968 writel(val, cp->regs + REG_PCS_MII_ADVERT);
971 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
973 /* pcs workaround: enable sync detect */
974 writel(PCS_SERDES_CTRL_SYNCD_EN,
975 cp->regs + REG_PCS_SERDES_CTRL);
980 static int cas_pcs_link_check(struct cas *cp)
982 u32 stat, state_machine;
985 /* The link status bit latches on zero, so you must
986 * read it twice in such a case to see a transition
987 * to the link being up.
989 stat = readl(cp->regs + REG_PCS_MII_STATUS);
990 if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
991 stat = readl(cp->regs + REG_PCS_MII_STATUS);
993 /* The remote-fault indication is only valid
994 * when autoneg has completed.
996 if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
997 PCS_MII_STATUS_REMOTE_FAULT)) ==
998 (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT))
999 netif_info(cp, link, cp->dev, "PCS RemoteFault\n");
1001 /* work around link detection issue by querying the PCS state
1004 state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
1005 if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
1006 stat &= ~PCS_MII_STATUS_LINK_STATUS;
1007 } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
1008 stat |= PCS_MII_STATUS_LINK_STATUS;
1011 if (stat & PCS_MII_STATUS_LINK_STATUS) {
1012 if (cp->lstate != link_up) {
1014 cp->lstate = link_up;
1015 cp->link_transition = LINK_TRANSITION_LINK_UP;
1017 cas_set_link_modes(cp);
1018 netif_carrier_on(cp->dev);
1021 } else if (cp->lstate == link_up) {
1022 cp->lstate = link_down;
1023 if (link_transition_timeout != 0 &&
1024 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1025 !cp->link_transition_jiffies_valid) {
1027 * force a reset, as a workaround for the
1028 * link-failure problem. May want to move this to a
1029 * point a bit earlier in the sequence. If we had
1030 * generated a reset a short time ago, we'll wait for
1031 * the link timer to check the status until a
1032 * timer expires (link_transistion_jiffies_valid is
1033 * true when the timer is running.) Instead of using
1034 * a system timer, we just do a check whenever the
1035 * link timer is running - this clears the flag after
1039 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1040 cp->link_transition_jiffies = jiffies;
1041 cp->link_transition_jiffies_valid = 1;
1043 cp->link_transition = LINK_TRANSITION_ON_FAILURE;
1045 netif_carrier_off(cp->dev);
1047 netif_info(cp, link, cp->dev, "PCS link down\n");
1049 /* Cassini only: if you force a mode, there can be
1050 * sync problems on link down. to fix that, the following
1051 * things need to be checked:
1052 * 1) read serialink state register
1053 * 2) read pcs status register to verify link down.
1054 * 3) if link down and serial link == 0x03, then you need
1055 * to global reset the chip.
1057 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
1058 /* should check to see if we're in a forced mode */
1059 stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1063 } else if (cp->lstate == link_down) {
1064 if (link_transition_timeout != 0 &&
1065 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1066 !cp->link_transition_jiffies_valid) {
1067 /* force a reset, as a workaround for the
1068 * link-failure problem. May want to move
1069 * this to a point a bit earlier in the
1073 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1074 cp->link_transition_jiffies = jiffies;
1075 cp->link_transition_jiffies_valid = 1;
1077 cp->link_transition = LINK_TRANSITION_STILL_FAILED;
1084 static int cas_pcs_interrupt(struct net_device *dev,
1085 struct cas *cp, u32 status)
1087 u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1089 if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
1091 return cas_pcs_link_check(cp);
1094 static int cas_txmac_interrupt(struct net_device *dev,
1095 struct cas *cp, u32 status)
1097 u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
1102 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1103 "txmac interrupt, txmac_stat: 0x%x\n", txmac_stat);
1105 /* Defer timer expiration is quite normal,
1106 * don't even log the event.
1108 if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
1109 !(txmac_stat & ~MAC_TX_DEFER_TIMER))
1112 spin_lock(&cp->stat_lock[0]);
1113 if (txmac_stat & MAC_TX_UNDERRUN) {
1114 netdev_err(dev, "TX MAC xmit underrun\n");
1115 cp->net_stats[0].tx_fifo_errors++;
1118 if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
1119 netdev_err(dev, "TX MAC max packet size error\n");
1120 cp->net_stats[0].tx_errors++;
1123 /* The rest are all cases of one of the 16-bit TX
1124 * counters expiring.
1126 if (txmac_stat & MAC_TX_COLL_NORMAL)
1127 cp->net_stats[0].collisions += 0x10000;
1129 if (txmac_stat & MAC_TX_COLL_EXCESS) {
1130 cp->net_stats[0].tx_aborted_errors += 0x10000;
1131 cp->net_stats[0].collisions += 0x10000;
1134 if (txmac_stat & MAC_TX_COLL_LATE) {
1135 cp->net_stats[0].tx_aborted_errors += 0x10000;
1136 cp->net_stats[0].collisions += 0x10000;
1138 spin_unlock(&cp->stat_lock[0]);
1140 /* We do not keep track of MAC_TX_COLL_FIRST and
1141 * MAC_TX_PEAK_ATTEMPTS events.
1146 static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware)
1148 cas_hp_inst_t *inst;
1153 while ((inst = firmware) && inst->note) {
1154 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
1156 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
1157 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
1158 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
1160 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
1161 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
1162 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
1163 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
1164 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
1165 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
1166 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
1167 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
1169 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
1170 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
1171 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
1172 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
1173 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
1179 static void cas_init_rx_dma(struct cas *cp)
1181 u64 desc_dma = cp->block_dvma;
1185 /* rx free descriptors */
1186 val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
1187 val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
1188 val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
1189 if ((N_RX_DESC_RINGS > 1) &&
1190 (cp->cas_flags & CAS_FLAG_REG_PLUS)) /* do desc 2 */
1191 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
1192 writel(val, cp->regs + REG_RX_CFG);
1194 val = (unsigned long) cp->init_rxds[0] -
1195 (unsigned long) cp->init_block;
1196 writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
1197 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
1198 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
1200 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1201 /* rx desc 2 is for IPSEC packets. however,
1202 * we don't it that for that purpose.
1204 val = (unsigned long) cp->init_rxds[1] -
1205 (unsigned long) cp->init_block;
1206 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
1207 writel((desc_dma + val) & 0xffffffff, cp->regs +
1208 REG_PLUS_RX_DB1_LOW);
1209 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +
1213 /* rx completion registers */
1214 val = (unsigned long) cp->init_rxcs[0] -
1215 (unsigned long) cp->init_block;
1216 writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
1217 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
1219 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1221 for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
1222 val = (unsigned long) cp->init_rxcs[i] -
1223 (unsigned long) cp->init_block;
1224 writel((desc_dma + val) >> 32, cp->regs +
1225 REG_PLUS_RX_CBN_HI(i));
1226 writel((desc_dma + val) & 0xffffffff, cp->regs +
1227 REG_PLUS_RX_CBN_LOW(i));
1231 /* read selective clear regs to prevent spurious interrupts
1232 * on reset because complete == kick.
1233 * selective clear set up to prevent interrupts on resets
1235 readl(cp->regs + REG_INTR_STATUS_ALIAS);
1236 writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
1237 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1238 for (i = 1; i < N_RX_COMP_RINGS; i++)
1239 readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i));
1241 /* 2 is different from 3 and 4 */
1242 if (N_RX_COMP_RINGS > 1)
1243 writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1,
1244 cp->regs + REG_PLUS_ALIASN_CLEAR(1));
1246 for (i = 2; i < N_RX_COMP_RINGS; i++)
1247 writel(INTR_RX_DONE_ALT,
1248 cp->regs + REG_PLUS_ALIASN_CLEAR(i));
1251 /* set up pause thresholds */
1252 val = CAS_BASE(RX_PAUSE_THRESH_OFF,
1253 cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
1254 val |= CAS_BASE(RX_PAUSE_THRESH_ON,
1255 cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
1256 writel(val, cp->regs + REG_RX_PAUSE_THRESH);
1258 /* zero out dma reassembly buffers */
1259 for (i = 0; i < 64; i++) {
1260 writel(i, cp->regs + REG_RX_TABLE_ADDR);
1261 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
1262 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
1263 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
1266 /* make sure address register is 0 for normal operation */
1267 writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
1268 writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
1270 /* interrupt mitigation */
1272 val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
1273 val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
1274 writel(val, cp->regs + REG_RX_BLANK);
1276 writel(0x0, cp->regs + REG_RX_BLANK);
1279 /* interrupt generation as a function of low water marks for
1280 * free desc and completion entries. these are used to trigger
1281 * housekeeping for rx descs. we don't use the free interrupt
1282 * as it's not very useful
1284 /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
1285 val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
1286 writel(val, cp->regs + REG_RX_AE_THRESH);
1287 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1288 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
1289 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
1292 /* Random early detect registers. useful for congestion avoidance.
1293 * this should be tunable.
1295 writel(0x0, cp->regs + REG_RX_RED);
1297 /* receive page sizes. default == 2K (0x800) */
1299 if (cp->page_size == 0x1000)
1301 else if (cp->page_size == 0x2000)
1303 else if (cp->page_size == 0x4000)
1306 /* round mtu + offset. constrain to page size. */
1307 size = cp->dev->mtu + 64;
1308 if (size > cp->page_size)
1309 size = cp->page_size;
1313 else if (size <= 0x800)
1315 else if (size <= 0x1000)
1320 cp->mtu_stride = 1 << (i + 10);
1321 val = CAS_BASE(RX_PAGE_SIZE, val);
1322 val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
1323 val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
1324 val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
1325 writel(val, cp->regs + REG_RX_PAGE_SIZE);
1327 /* enable the header parser if desired */
1328 if (CAS_HP_FIRMWARE == cas_prog_null)
1331 val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
1332 val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
1333 val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
1334 writel(val, cp->regs + REG_HP_CFG);
1337 static inline void cas_rxc_init(struct cas_rx_comp *rxc)
1339 memset(rxc, 0, sizeof(*rxc));
1340 rxc->word4 = cpu_to_le64(RX_COMP4_ZERO);
1343 /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
1344 * flipping is protected by the fact that the chip will not
1345 * hand back the same page index while it's being processed.
1347 static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
1349 cas_page_t *page = cp->rx_pages[1][index];
1352 if (page_count(page->buffer) == 1)
1355 new = cas_page_dequeue(cp);
1357 spin_lock(&cp->rx_inuse_lock);
1358 list_add(&page->list, &cp->rx_inuse_list);
1359 spin_unlock(&cp->rx_inuse_lock);
1364 /* this needs to be changed if we actually use the ENC RX DESC ring */
1365 static cas_page_t *cas_page_swap(struct cas *cp, const int ring,
1368 cas_page_t **page0 = cp->rx_pages[0];
1369 cas_page_t **page1 = cp->rx_pages[1];
1371 /* swap if buffer is in use */
1372 if (page_count(page0[index]->buffer) > 1) {
1373 cas_page_t *new = cas_page_spare(cp, index);
1375 page1[index] = page0[index];
1379 RX_USED_SET(page0[index], 0);
1380 return page0[index];
1383 static void cas_clean_rxds(struct cas *cp)
1385 /* only clean ring 0 as ring 1 is used for spare buffers */
1386 struct cas_rx_desc *rxd = cp->init_rxds[0];
1389 /* release all rx flows */
1390 for (i = 0; i < N_RX_FLOWS; i++) {
1391 struct sk_buff *skb;
1392 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
1393 cas_skb_release(skb);
1397 /* initialize descriptors */
1398 size = RX_DESC_RINGN_SIZE(0);
1399 for (i = 0; i < size; i++) {
1400 cas_page_t *page = cas_page_swap(cp, 0, i);
1401 rxd[i].buffer = cpu_to_le64(page->dma_addr);
1402 rxd[i].index = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) |
1403 CAS_BASE(RX_INDEX_RING, 0));
1406 cp->rx_old[0] = RX_DESC_RINGN_SIZE(0) - 4;
1408 cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
1411 static void cas_clean_rxcs(struct cas *cp)
1415 /* take ownership of rx comp descriptors */
1416 memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
1417 memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
1418 for (i = 0; i < N_RX_COMP_RINGS; i++) {
1419 struct cas_rx_comp *rxc = cp->init_rxcs[i];
1420 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
1421 cas_rxc_init(rxc + j);
1427 /* When we get a RX fifo overflow, the RX unit is probably hung
1428 * so we do the following.
1430 * If any part of the reset goes wrong, we return 1 and that causes the
1431 * whole chip to be reset.
1433 static int cas_rxmac_reset(struct cas *cp)
1435 struct net_device *dev = cp->dev;
1439 /* First, reset MAC RX. */
1440 writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1441 for (limit = 0; limit < STOP_TRIES; limit++) {
1442 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1446 if (limit == STOP_TRIES) {
1447 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
1451 /* Second, disable RX DMA. */
1452 writel(0, cp->regs + REG_RX_CFG);
1453 for (limit = 0; limit < STOP_TRIES; limit++) {
1454 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1458 if (limit == STOP_TRIES) {
1459 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
1465 /* Execute RX reset command. */
1466 writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1467 for (limit = 0; limit < STOP_TRIES; limit++) {
1468 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1472 if (limit == STOP_TRIES) {
1473 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
1477 /* reset driver rx state */
1481 /* Now, reprogram the rest of RX unit. */
1482 cas_init_rx_dma(cp);
1485 val = readl(cp->regs + REG_RX_CFG);
1486 writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1487 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1488 val = readl(cp->regs + REG_MAC_RX_CFG);
1489 writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1494 static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
1497 u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1502 netif_dbg(cp, intr, cp->dev, "rxmac interrupt, stat: 0x%x\n", stat);
1504 /* these are all rollovers */
1505 spin_lock(&cp->stat_lock[0]);
1506 if (stat & MAC_RX_ALIGN_ERR)
1507 cp->net_stats[0].rx_frame_errors += 0x10000;
1509 if (stat & MAC_RX_CRC_ERR)
1510 cp->net_stats[0].rx_crc_errors += 0x10000;
1512 if (stat & MAC_RX_LEN_ERR)
1513 cp->net_stats[0].rx_length_errors += 0x10000;
1515 if (stat & MAC_RX_OVERFLOW) {
1516 cp->net_stats[0].rx_over_errors++;
1517 cp->net_stats[0].rx_fifo_errors++;
1520 /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR
1523 spin_unlock(&cp->stat_lock[0]);
1527 static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
1530 u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1535 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1536 "mac interrupt, stat: 0x%x\n", stat);
1538 /* This interrupt is just for pause frame and pause
1539 * tracking. It is useful for diagnostics and debug
1540 * but probably by default we will mask these events.
1542 if (stat & MAC_CTRL_PAUSE_STATE)
1543 cp->pause_entered++;
1545 if (stat & MAC_CTRL_PAUSE_RECEIVED)
1546 cp->pause_last_time_recvd = (stat >> 16);
1552 /* Must be invoked under cp->lock. */
1553 static inline int cas_mdio_link_not_up(struct cas *cp)
1557 switch (cp->lstate) {
1558 case link_force_ret:
1559 netif_info(cp, link, cp->dev, "Autoneg failed again, keeping forced mode\n");
1560 cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
1561 cp->timer_ticks = 5;
1562 cp->lstate = link_force_ok;
1563 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1567 val = cas_phy_read(cp, MII_BMCR);
1569 /* Try forced modes. we try things in the following order:
1570 * 1000 full -> 100 full/half -> 10 half
1572 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
1573 val |= BMCR_FULLDPLX;
1574 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
1575 CAS_BMCR_SPEED1000 : BMCR_SPEED100;
1576 cas_phy_write(cp, MII_BMCR, val);
1577 cp->timer_ticks = 5;
1578 cp->lstate = link_force_try;
1579 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1582 case link_force_try:
1583 /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */
1584 val = cas_phy_read(cp, MII_BMCR);
1585 cp->timer_ticks = 5;
1586 if (val & CAS_BMCR_SPEED1000) { /* gigabit */
1587 val &= ~CAS_BMCR_SPEED1000;
1588 val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
1589 cas_phy_write(cp, MII_BMCR, val);
1593 if (val & BMCR_SPEED100) {
1594 if (val & BMCR_FULLDPLX) /* fd failed */
1595 val &= ~BMCR_FULLDPLX;
1596 else { /* 100Mbps failed */
1597 val &= ~BMCR_SPEED100;
1599 cas_phy_write(cp, MII_BMCR, val);
1609 /* must be invoked with cp->lock held */
1610 static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
1614 if (bmsr & BMSR_LSTATUS) {
1615 /* Ok, here we got a link. If we had it due to a forced
1616 * fallback, and we were configured for autoneg, we
1617 * retry a short autoneg pass. If you know your hub is
1618 * broken, use ethtool ;)
1620 if ((cp->lstate == link_force_try) &&
1621 (cp->link_cntl & BMCR_ANENABLE)) {
1622 cp->lstate = link_force_ret;
1623 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1624 cas_mif_poll(cp, 0);
1625 cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
1626 cp->timer_ticks = 5;
1628 netif_info(cp, link, cp->dev,
1629 "Got link after fallback, retrying autoneg once...\n");
1630 cas_phy_write(cp, MII_BMCR,
1631 cp->link_fcntl | BMCR_ANENABLE |
1633 cas_mif_poll(cp, 1);
1635 } else if (cp->lstate != link_up) {
1636 cp->lstate = link_up;
1637 cp->link_transition = LINK_TRANSITION_LINK_UP;
1640 cas_set_link_modes(cp);
1641 netif_carrier_on(cp->dev);
1647 /* link not up. if the link was previously up, we restart the
1651 if (cp->lstate == link_up) {
1652 cp->lstate = link_down;
1653 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
1655 netif_carrier_off(cp->dev);
1657 netif_info(cp, link, cp->dev, "Link down\n");
1660 } else if (++cp->timer_ticks > 10)
1661 cas_mdio_link_not_up(cp);
1666 static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
1669 u32 stat = readl(cp->regs + REG_MIF_STATUS);
1672 /* check for a link change */
1673 if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1676 bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1677 return cas_mii_link_check(cp, bmsr);
1680 static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
1683 u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1688 netdev_err(dev, "PCI error [%04x:%04x]",
1689 stat, readl(cp->regs + REG_BIM_DIAG));
1691 /* cassini+ has this reserved */
1692 if ((stat & PCI_ERR_BADACK) &&
1693 ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
1694 pr_cont(" <No ACK64# during ABS64 cycle>");
1696 if (stat & PCI_ERR_DTRTO)
1697 pr_cont(" <Delayed transaction timeout>");
1698 if (stat & PCI_ERR_OTHER)
1699 pr_cont(" <other>");
1700 if (stat & PCI_ERR_BIM_DMA_WRITE)
1701 pr_cont(" <BIM DMA 0 write req>");
1702 if (stat & PCI_ERR_BIM_DMA_READ)
1703 pr_cont(" <BIM DMA 0 read req>");
1706 if (stat & PCI_ERR_OTHER) {
1709 /* Interrogate PCI config space for the
1712 pci_errs = pci_status_get_and_clear_errors(cp->pdev);
1714 netdev_err(dev, "PCI status errors[%04x]\n", pci_errs);
1715 if (pci_errs & PCI_STATUS_PARITY)
1716 netdev_err(dev, "PCI parity error detected\n");
1717 if (pci_errs & PCI_STATUS_SIG_TARGET_ABORT)
1718 netdev_err(dev, "PCI target abort\n");
1719 if (pci_errs & PCI_STATUS_REC_TARGET_ABORT)
1720 netdev_err(dev, "PCI master acks target abort\n");
1721 if (pci_errs & PCI_STATUS_REC_MASTER_ABORT)
1722 netdev_err(dev, "PCI master abort\n");
1723 if (pci_errs & PCI_STATUS_SIG_SYSTEM_ERROR)
1724 netdev_err(dev, "PCI system error SERR#\n");
1725 if (pci_errs & PCI_STATUS_DETECTED_PARITY)
1726 netdev_err(dev, "PCI parity error\n");
1729 /* For all PCI errors, we should reset the chip. */
1733 /* All non-normal interrupt conditions get serviced here.
1734 * Returns non-zero if we should just exit the interrupt
1735 * handler right now (ie. if we reset the card which invalidates
1736 * all of the other original irq status bits).
1738 static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
1741 if (status & INTR_RX_TAG_ERROR) {
1742 /* corrupt RX tag framing */
1743 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1744 "corrupt rx tag framing\n");
1745 spin_lock(&cp->stat_lock[0]);
1746 cp->net_stats[0].rx_errors++;
1747 spin_unlock(&cp->stat_lock[0]);
1751 if (status & INTR_RX_LEN_MISMATCH) {
1752 /* length mismatch. */
1753 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1754 "length mismatch for rx frame\n");
1755 spin_lock(&cp->stat_lock[0]);
1756 cp->net_stats[0].rx_errors++;
1757 spin_unlock(&cp->stat_lock[0]);
1761 if (status & INTR_PCS_STATUS) {
1762 if (cas_pcs_interrupt(dev, cp, status))
1766 if (status & INTR_TX_MAC_STATUS) {
1767 if (cas_txmac_interrupt(dev, cp, status))
1771 if (status & INTR_RX_MAC_STATUS) {
1772 if (cas_rxmac_interrupt(dev, cp, status))
1776 if (status & INTR_MAC_CTRL_STATUS) {
1777 if (cas_mac_interrupt(dev, cp, status))
1781 if (status & INTR_MIF_STATUS) {
1782 if (cas_mif_interrupt(dev, cp, status))
1786 if (status & INTR_PCI_ERROR_STATUS) {
1787 if (cas_pci_interrupt(dev, cp, status))
1794 atomic_inc(&cp->reset_task_pending);
1795 atomic_inc(&cp->reset_task_pending_all);
1796 netdev_err(dev, "reset called in cas_abnormal_irq [0x%x]\n", status);
1797 schedule_work(&cp->reset_task);
1799 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
1800 netdev_err(dev, "reset called in cas_abnormal_irq\n");
1801 schedule_work(&cp->reset_task);
1806 /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when
1807 * determining whether to do a netif_stop/wakeup
1809 #define CAS_TABORT(x) (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1810 #define CAS_ROUND_PAGE(x) (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1811 static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
1814 unsigned long off = addr + len;
1816 if (CAS_TABORT(cp) == 1)
1818 if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
1820 return TX_TARGET_ABORT_LEN;
1823 static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
1825 struct cas_tx_desc *txds;
1826 struct sk_buff **skbs;
1827 struct net_device *dev = cp->dev;
1830 spin_lock(&cp->tx_lock[ring]);
1831 txds = cp->init_txds[ring];
1832 skbs = cp->tx_skbs[ring];
1833 entry = cp->tx_old[ring];
1835 count = TX_BUFF_COUNT(ring, entry, limit);
1836 while (entry != limit) {
1837 struct sk_buff *skb = skbs[entry];
1843 /* this should never occur */
1844 entry = TX_DESC_NEXT(ring, entry);
1848 /* however, we might get only a partial skb release. */
1849 count -= skb_shinfo(skb)->nr_frags +
1850 + cp->tx_tiny_use[ring][entry].nbufs + 1;
1854 netif_printk(cp, tx_done, KERN_DEBUG, cp->dev,
1855 "tx[%d] done, slot %d\n", ring, entry);
1858 cp->tx_tiny_use[ring][entry].nbufs = 0;
1860 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1861 struct cas_tx_desc *txd = txds + entry;
1863 daddr = le64_to_cpu(txd->buffer);
1864 dlen = CAS_VAL(TX_DESC_BUFLEN,
1865 le64_to_cpu(txd->control));
1866 dma_unmap_page(&cp->pdev->dev, daddr, dlen,
1868 entry = TX_DESC_NEXT(ring, entry);
1870 /* tiny buffer may follow */
1871 if (cp->tx_tiny_use[ring][entry].used) {
1872 cp->tx_tiny_use[ring][entry].used = 0;
1873 entry = TX_DESC_NEXT(ring, entry);
1877 spin_lock(&cp->stat_lock[ring]);
1878 cp->net_stats[ring].tx_packets++;
1879 cp->net_stats[ring].tx_bytes += skb->len;
1880 spin_unlock(&cp->stat_lock[ring]);
1881 dev_consume_skb_irq(skb);
1883 cp->tx_old[ring] = entry;
1885 /* this is wrong for multiple tx rings. the net device needs
1886 * multiple queues for this to do the right thing. we wait
1887 * for 2*packets to be available when using tiny buffers
1889 if (netif_queue_stopped(dev) &&
1890 (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
1891 netif_wake_queue(dev);
1892 spin_unlock(&cp->tx_lock[ring]);
1895 static void cas_tx(struct net_device *dev, struct cas *cp,
1899 #ifdef USE_TX_COMPWB
1900 u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
1902 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1903 "tx interrupt, status: 0x%x, %llx\n",
1904 status, (unsigned long long)compwb);
1905 /* process all the rings */
1906 for (ring = 0; ring < N_TX_RINGS; ring++) {
1907 #ifdef USE_TX_COMPWB
1908 /* use the completion writeback registers */
1909 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
1910 CAS_VAL(TX_COMPWB_LSB, compwb);
1911 compwb = TX_COMPWB_NEXT(compwb);
1913 limit = readl(cp->regs + REG_TX_COMPN(ring));
1915 if (cp->tx_old[ring] != limit)
1916 cas_tx_ringN(cp, ring, limit);
1921 static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
1922 int entry, const u64 *words,
1923 struct sk_buff **skbref)
1925 int dlen, hlen, len, i, alloclen;
1926 int off, swivel = RX_SWIVEL_OFF_VAL;
1927 struct cas_page *page;
1928 struct sk_buff *skb;
1929 void *addr, *crcaddr;
1933 hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
1934 dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
1937 if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT))
1940 alloclen = max(hlen, RX_COPY_MIN);
1942 skb = netdev_alloc_skb(cp->dev, alloclen + swivel + cp->crc_size);
1947 skb_reserve(skb, swivel);
1950 addr = crcaddr = NULL;
1951 if (hlen) { /* always copy header pages */
1952 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
1953 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
1954 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 +
1958 if (!dlen) /* attach FCS */
1960 dma_sync_single_for_cpu(&cp->pdev->dev, page->dma_addr + off,
1961 i, DMA_FROM_DEVICE);
1962 addr = cas_page_map(page->buffer);
1963 memcpy(p, addr + off, i);
1964 dma_sync_single_for_device(&cp->pdev->dev,
1965 page->dma_addr + off, i,
1967 cas_page_unmap(addr);
1968 RX_USED_ADD(page, 0x100);
1974 if (alloclen < (hlen + dlen)) {
1975 skb_frag_t *frag = skb_shinfo(skb)->frags;
1977 /* normal or jumbo packets. we use frags */
1978 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
1979 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
1980 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
1982 hlen = min(cp->page_size - off, dlen);
1984 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1985 "rx page overflow: %d\n", hlen);
1986 dev_kfree_skb_irq(skb);
1990 if (i == dlen) /* attach FCS */
1992 dma_sync_single_for_cpu(&cp->pdev->dev, page->dma_addr + off,
1993 i, DMA_FROM_DEVICE);
1995 /* make sure we always copy a header */
1997 if (p == (char *) skb->data) { /* not split */
1998 addr = cas_page_map(page->buffer);
1999 memcpy(p, addr + off, RX_COPY_MIN);
2000 dma_sync_single_for_device(&cp->pdev->dev,
2001 page->dma_addr + off, i,
2003 cas_page_unmap(addr);
2005 swivel = RX_COPY_MIN;
2006 RX_USED_ADD(page, cp->mtu_stride);
2008 RX_USED_ADD(page, hlen);
2010 skb_put(skb, alloclen);
2012 skb_shinfo(skb)->nr_frags++;
2013 skb->data_len += hlen - swivel;
2014 skb->truesize += hlen - swivel;
2015 skb->len += hlen - swivel;
2017 __skb_frag_set_page(frag, page->buffer);
2018 __skb_frag_ref(frag);
2019 skb_frag_off_set(frag, off);
2020 skb_frag_size_set(frag, hlen - swivel);
2022 /* any more data? */
2023 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2027 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2028 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2029 dma_sync_single_for_cpu(&cp->pdev->dev,
2031 hlen + cp->crc_size,
2033 dma_sync_single_for_device(&cp->pdev->dev,
2035 hlen + cp->crc_size,
2038 skb_shinfo(skb)->nr_frags++;
2039 skb->data_len += hlen;
2043 __skb_frag_set_page(frag, page->buffer);
2044 __skb_frag_ref(frag);
2045 skb_frag_off_set(frag, 0);
2046 skb_frag_size_set(frag, hlen);
2047 RX_USED_ADD(page, hlen + cp->crc_size);
2051 addr = cas_page_map(page->buffer);
2052 crcaddr = addr + off + hlen;
2056 /* copying packet */
2060 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2061 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2062 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2063 hlen = min(cp->page_size - off, dlen);
2065 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
2066 "rx page overflow: %d\n", hlen);
2067 dev_kfree_skb_irq(skb);
2071 if (i == dlen) /* attach FCS */
2073 dma_sync_single_for_cpu(&cp->pdev->dev, page->dma_addr + off,
2074 i, DMA_FROM_DEVICE);
2075 addr = cas_page_map(page->buffer);
2076 memcpy(p, addr + off, i);
2077 dma_sync_single_for_device(&cp->pdev->dev,
2078 page->dma_addr + off, i,
2080 cas_page_unmap(addr);
2081 if (p == (char *) skb->data) /* not split */
2082 RX_USED_ADD(page, cp->mtu_stride);
2084 RX_USED_ADD(page, i);
2086 /* any more data? */
2087 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2089 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2090 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2091 dma_sync_single_for_cpu(&cp->pdev->dev,
2093 dlen + cp->crc_size,
2095 addr = cas_page_map(page->buffer);
2096 memcpy(p, addr, dlen + cp->crc_size);
2097 dma_sync_single_for_device(&cp->pdev->dev,
2099 dlen + cp->crc_size,
2101 cas_page_unmap(addr);
2102 RX_USED_ADD(page, dlen + cp->crc_size);
2107 crcaddr = skb->data + alloclen;
2109 skb_put(skb, alloclen);
2112 csum = (__force __sum16)htons(CAS_VAL(RX_COMP4_TCP_CSUM, words[3]));
2114 /* checksum includes FCS. strip it out. */
2115 csum = csum_fold(csum_partial(crcaddr, cp->crc_size,
2116 csum_unfold(csum)));
2118 cas_page_unmap(addr);
2120 skb->protocol = eth_type_trans(skb, cp->dev);
2121 if (skb->protocol == htons(ETH_P_IP)) {
2122 skb->csum = csum_unfold(~csum);
2123 skb->ip_summed = CHECKSUM_COMPLETE;
2125 skb_checksum_none_assert(skb);
2130 /* we can handle up to 64 rx flows at a time. we do the same thing
2131 * as nonreassm except that we batch up the buffers.
2132 * NOTE: we currently just treat each flow as a bunch of packets that
2133 * we pass up. a better way would be to coalesce the packets
2134 * into a jumbo packet. to do that, we need to do the following:
2135 * 1) the first packet will have a clean split between header and
2137 * 2) each time the next flow packet comes in, extend the
2138 * data length and merge the checksums.
2139 * 3) on flow release, fix up the header.
2140 * 4) make sure the higher layer doesn't care.
2141 * because packets get coalesced, we shouldn't run into fragment count
2144 static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
2145 struct sk_buff *skb)
2147 int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
2148 struct sk_buff_head *flow = &cp->rx_flows[flowid];
2150 /* this is protected at a higher layer, so no need to
2151 * do any additional locking here. stick the buffer
2154 __skb_queue_tail(flow, skb);
2155 if (words[0] & RX_COMP1_RELEASE_FLOW) {
2156 while ((skb = __skb_dequeue(flow))) {
2157 cas_skb_release(skb);
2162 /* put rx descriptor back on ring. if a buffer is in use by a higher
2163 * layer, this will need to put in a replacement.
2165 static void cas_post_page(struct cas *cp, const int ring, const int index)
2170 entry = cp->rx_old[ring];
2172 new = cas_page_swap(cp, ring, index);
2173 cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
2174 cp->init_rxds[ring][entry].index =
2175 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) |
2176 CAS_BASE(RX_INDEX_RING, ring));
2178 entry = RX_DESC_ENTRY(ring, entry + 1);
2179 cp->rx_old[ring] = entry;
2185 writel(entry, cp->regs + REG_RX_KICK);
2186 else if ((N_RX_DESC_RINGS > 1) &&
2187 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2188 writel(entry, cp->regs + REG_PLUS_RX_KICK1);
2192 /* only when things are bad */
2193 static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
2195 unsigned int entry, last, count, released;
2197 cas_page_t **page = cp->rx_pages[ring];
2199 entry = cp->rx_old[ring];
2201 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
2202 "rxd[%d] interrupt, done: %d\n", ring, entry);
2205 count = entry & 0x3;
2206 last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
2208 while (entry != last) {
2209 /* make a new buffer if it's still in use */
2210 if (page_count(page[entry]->buffer) > 1) {
2211 cas_page_t *new = cas_page_dequeue(cp);
2213 /* let the timer know that we need to
2216 cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
2217 if (!timer_pending(&cp->link_timer))
2218 mod_timer(&cp->link_timer, jiffies +
2219 CAS_LINK_FAST_TIMEOUT);
2220 cp->rx_old[ring] = entry;
2221 cp->rx_last[ring] = num ? num - released : 0;
2224 spin_lock(&cp->rx_inuse_lock);
2225 list_add(&page[entry]->list, &cp->rx_inuse_list);
2226 spin_unlock(&cp->rx_inuse_lock);
2227 cp->init_rxds[ring][entry].buffer =
2228 cpu_to_le64(new->dma_addr);
2238 entry = RX_DESC_ENTRY(ring, entry + 1);
2240 cp->rx_old[ring] = entry;
2246 writel(cluster, cp->regs + REG_RX_KICK);
2247 else if ((N_RX_DESC_RINGS > 1) &&
2248 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2249 writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
2254 /* process a completion ring. packets are set up in three basic ways:
2255 * small packets: should be copied header + data in single buffer.
2256 * large packets: header and data in a single buffer.
2257 * split packets: header in a separate buffer from data.
2258 * data may be in multiple pages. data may be > 256
2259 * bytes but in a single page.
2261 * NOTE: RX page posting is done in this routine as well. while there's
2262 * the capability of using multiple RX completion rings, it isn't
2263 * really worthwhile due to the fact that the page posting will
2264 * force serialization on the single descriptor ring.
2266 static int cas_rx_ringN(struct cas *cp, int ring, int budget)
2268 struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
2272 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
2273 "rx[%d] interrupt, done: %d/%d\n",
2275 readl(cp->regs + REG_RX_COMP_HEAD), cp->rx_new[ring]);
2277 entry = cp->rx_new[ring];
2280 struct cas_rx_comp *rxc = rxcs + entry;
2281 struct sk_buff *skb;
2286 words[0] = le64_to_cpu(rxc->word1);
2287 words[1] = le64_to_cpu(rxc->word2);
2288 words[2] = le64_to_cpu(rxc->word3);
2289 words[3] = le64_to_cpu(rxc->word4);
2291 /* don't touch if still owned by hw */
2292 type = CAS_VAL(RX_COMP1_TYPE, words[0]);
2296 /* hw hasn't cleared the zero bit yet */
2297 if (words[3] & RX_COMP4_ZERO) {
2301 /* get info on the packet */
2302 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
2303 spin_lock(&cp->stat_lock[ring]);
2304 cp->net_stats[ring].rx_errors++;
2305 if (words[3] & RX_COMP4_LEN_MISMATCH)
2306 cp->net_stats[ring].rx_length_errors++;
2307 if (words[3] & RX_COMP4_BAD)
2308 cp->net_stats[ring].rx_crc_errors++;
2309 spin_unlock(&cp->stat_lock[ring]);
2311 /* We'll just return it to Cassini. */
2313 spin_lock(&cp->stat_lock[ring]);
2314 ++cp->net_stats[ring].rx_dropped;
2315 spin_unlock(&cp->stat_lock[ring]);
2319 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
2325 /* see if it's a flow re-assembly or not. the driver
2326 * itself handles release back up.
2328 if (RX_DONT_BATCH || (type == 0x2)) {
2329 /* non-reassm: these always get released */
2330 cas_skb_release(skb);
2332 cas_rx_flow_pkt(cp, words, skb);
2335 spin_lock(&cp->stat_lock[ring]);
2336 cp->net_stats[ring].rx_packets++;
2337 cp->net_stats[ring].rx_bytes += len;
2338 spin_unlock(&cp->stat_lock[ring]);
2343 /* should it be released? */
2344 if (words[0] & RX_COMP1_RELEASE_HDR) {
2345 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2346 dring = CAS_VAL(RX_INDEX_RING, i);
2347 i = CAS_VAL(RX_INDEX_NUM, i);
2348 cas_post_page(cp, dring, i);
2351 if (words[0] & RX_COMP1_RELEASE_DATA) {
2352 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2353 dring = CAS_VAL(RX_INDEX_RING, i);
2354 i = CAS_VAL(RX_INDEX_NUM, i);
2355 cas_post_page(cp, dring, i);
2358 if (words[0] & RX_COMP1_RELEASE_NEXT) {
2359 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2360 dring = CAS_VAL(RX_INDEX_RING, i);
2361 i = CAS_VAL(RX_INDEX_NUM, i);
2362 cas_post_page(cp, dring, i);
2365 /* skip to the next entry */
2366 entry = RX_COMP_ENTRY(ring, entry + 1 +
2367 CAS_VAL(RX_COMP1_SKIP, words[0]));
2369 if (budget && (npackets >= budget))
2373 cp->rx_new[ring] = entry;
2376 netdev_info(cp->dev, "Memory squeeze, deferring packet\n");
2381 /* put completion entries back on the ring */
2382 static void cas_post_rxcs_ringN(struct net_device *dev,
2383 struct cas *cp, int ring)
2385 struct cas_rx_comp *rxc = cp->init_rxcs[ring];
2388 last = cp->rx_cur[ring];
2389 entry = cp->rx_new[ring];
2390 netif_printk(cp, intr, KERN_DEBUG, dev,
2391 "rxc[%d] interrupt, done: %d/%d\n",
2392 ring, readl(cp->regs + REG_RX_COMP_HEAD), entry);
2394 /* zero and re-mark descriptors */
2395 while (last != entry) {
2396 cas_rxc_init(rxc + last);
2397 last = RX_COMP_ENTRY(ring, last + 1);
2399 cp->rx_cur[ring] = last;
2402 writel(last, cp->regs + REG_RX_COMP_TAIL);
2403 else if (cp->cas_flags & CAS_FLAG_REG_PLUS)
2404 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
2409 /* cassini can use all four PCI interrupts for the completion ring.
2410 * rings 3 and 4 are identical
2412 #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
2413 static inline void cas_handle_irqN(struct net_device *dev,
2414 struct cas *cp, const u32 status,
2417 if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT))
2418 cas_post_rxcs_ringN(dev, cp, ring);
2421 static irqreturn_t cas_interruptN(int irq, void *dev_id)
2423 struct net_device *dev = dev_id;
2424 struct cas *cp = netdev_priv(dev);
2425 unsigned long flags;
2426 int ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
2427 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
2429 /* check for shared irq */
2433 spin_lock_irqsave(&cp->lock, flags);
2434 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2437 napi_schedule(&cp->napi);
2439 cas_rx_ringN(cp, ring, 0);
2441 status &= ~INTR_RX_DONE_ALT;
2445 cas_handle_irqN(dev, cp, status, ring);
2446 spin_unlock_irqrestore(&cp->lock, flags);
2452 /* everything but rx packets */
2453 static inline void cas_handle_irq1(struct cas *cp, const u32 status)
2455 if (status & INTR_RX_BUF_UNAVAIL_1) {
2456 /* Frame arrived, no free RX buffers available.
2457 * NOTE: we can get this on a link transition. */
2458 cas_post_rxds_ringN(cp, 1, 0);
2459 spin_lock(&cp->stat_lock[1]);
2460 cp->net_stats[1].rx_dropped++;
2461 spin_unlock(&cp->stat_lock[1]);
2464 if (status & INTR_RX_BUF_AE_1)
2465 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) -
2466 RX_AE_FREEN_VAL(1));
2468 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2469 cas_post_rxcs_ringN(cp, 1);
2472 /* ring 2 handles a few more events than 3 and 4 */
2473 static irqreturn_t cas_interrupt1(int irq, void *dev_id)
2475 struct net_device *dev = dev_id;
2476 struct cas *cp = netdev_priv(dev);
2477 unsigned long flags;
2478 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2480 /* check for shared interrupt */
2484 spin_lock_irqsave(&cp->lock, flags);
2485 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2488 napi_schedule(&cp->napi);
2490 cas_rx_ringN(cp, 1, 0);
2492 status &= ~INTR_RX_DONE_ALT;
2495 cas_handle_irq1(cp, status);
2496 spin_unlock_irqrestore(&cp->lock, flags);
2501 static inline void cas_handle_irq(struct net_device *dev,
2502 struct cas *cp, const u32 status)
2504 /* housekeeping interrupts */
2505 if (status & INTR_ERROR_MASK)
2506 cas_abnormal_irq(dev, cp, status);
2508 if (status & INTR_RX_BUF_UNAVAIL) {
2509 /* Frame arrived, no free RX buffers available.
2510 * NOTE: we can get this on a link transition.
2512 cas_post_rxds_ringN(cp, 0, 0);
2513 spin_lock(&cp->stat_lock[0]);
2514 cp->net_stats[0].rx_dropped++;
2515 spin_unlock(&cp->stat_lock[0]);
2516 } else if (status & INTR_RX_BUF_AE) {
2517 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
2518 RX_AE_FREEN_VAL(0));
2521 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2522 cas_post_rxcs_ringN(dev, cp, 0);
2525 static irqreturn_t cas_interrupt(int irq, void *dev_id)
2527 struct net_device *dev = dev_id;
2528 struct cas *cp = netdev_priv(dev);
2529 unsigned long flags;
2530 u32 status = readl(cp->regs + REG_INTR_STATUS);
2535 spin_lock_irqsave(&cp->lock, flags);
2536 if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
2537 cas_tx(dev, cp, status);
2538 status &= ~(INTR_TX_ALL | INTR_TX_INTME);
2541 if (status & INTR_RX_DONE) {
2544 napi_schedule(&cp->napi);
2546 cas_rx_ringN(cp, 0, 0);
2548 status &= ~INTR_RX_DONE;
2552 cas_handle_irq(dev, cp, status);
2553 spin_unlock_irqrestore(&cp->lock, flags);
2559 static int cas_poll(struct napi_struct *napi, int budget)
2561 struct cas *cp = container_of(napi, struct cas, napi);
2562 struct net_device *dev = cp->dev;
2563 int i, enable_intr, credits;
2564 u32 status = readl(cp->regs + REG_INTR_STATUS);
2565 unsigned long flags;
2567 spin_lock_irqsave(&cp->lock, flags);
2568 cas_tx(dev, cp, status);
2569 spin_unlock_irqrestore(&cp->lock, flags);
2571 /* NAPI rx packets. we spread the credits across all of the
2574 * to make sure we're fair with the work we loop through each
2575 * ring N_RX_COMP_RING times with a request of
2576 * budget / N_RX_COMP_RINGS
2580 for (i = 0; i < N_RX_COMP_RINGS; i++) {
2582 for (j = 0; j < N_RX_COMP_RINGS; j++) {
2583 credits += cas_rx_ringN(cp, j, budget / N_RX_COMP_RINGS);
2584 if (credits >= budget) {
2592 /* final rx completion */
2593 spin_lock_irqsave(&cp->lock, flags);
2595 cas_handle_irq(dev, cp, status);
2598 if (N_RX_COMP_RINGS > 1) {
2599 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2601 cas_handle_irq1(dev, cp, status);
2606 if (N_RX_COMP_RINGS > 2) {
2607 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
2609 cas_handle_irqN(dev, cp, status, 2);
2614 if (N_RX_COMP_RINGS > 3) {
2615 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
2617 cas_handle_irqN(dev, cp, status, 3);
2620 spin_unlock_irqrestore(&cp->lock, flags);
2622 napi_complete(napi);
2623 cas_unmask_intr(cp);
2629 #ifdef CONFIG_NET_POLL_CONTROLLER
2630 static void cas_netpoll(struct net_device *dev)
2632 struct cas *cp = netdev_priv(dev);
2634 cas_disable_irq(cp, 0);
2635 cas_interrupt(cp->pdev->irq, dev);
2636 cas_enable_irq(cp, 0);
2639 if (N_RX_COMP_RINGS > 1) {
2640 /* cas_interrupt1(); */
2644 if (N_RX_COMP_RINGS > 2) {
2645 /* cas_interruptN(); */
2649 if (N_RX_COMP_RINGS > 3) {
2650 /* cas_interruptN(); */
2656 static void cas_tx_timeout(struct net_device *dev, unsigned int txqueue)
2658 struct cas *cp = netdev_priv(dev);
2660 netdev_err(dev, "transmit timed out, resetting\n");
2661 if (!cp->hw_running) {
2662 netdev_err(dev, "hrm.. hw not running!\n");
2666 netdev_err(dev, "MIF_STATE[%08x]\n",
2667 readl(cp->regs + REG_MIF_STATE_MACHINE));
2669 netdev_err(dev, "MAC_STATE[%08x]\n",
2670 readl(cp->regs + REG_MAC_STATE_MACHINE));
2672 netdev_err(dev, "TX_STATE[%08x:%08x:%08x] FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
2673 readl(cp->regs + REG_TX_CFG),
2674 readl(cp->regs + REG_MAC_TX_STATUS),
2675 readl(cp->regs + REG_MAC_TX_CFG),
2676 readl(cp->regs + REG_TX_FIFO_PKT_CNT),
2677 readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
2678 readl(cp->regs + REG_TX_FIFO_READ_PTR),
2679 readl(cp->regs + REG_TX_SM_1),
2680 readl(cp->regs + REG_TX_SM_2));
2682 netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
2683 readl(cp->regs + REG_RX_CFG),
2684 readl(cp->regs + REG_MAC_RX_STATUS),
2685 readl(cp->regs + REG_MAC_RX_CFG));
2687 netdev_err(dev, "HP_STATE[%08x:%08x:%08x:%08x]\n",
2688 readl(cp->regs + REG_HP_STATE_MACHINE),
2689 readl(cp->regs + REG_HP_STATUS0),
2690 readl(cp->regs + REG_HP_STATUS1),
2691 readl(cp->regs + REG_HP_STATUS2));
2694 atomic_inc(&cp->reset_task_pending);
2695 atomic_inc(&cp->reset_task_pending_all);
2696 schedule_work(&cp->reset_task);
2698 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
2699 schedule_work(&cp->reset_task);
2703 static inline int cas_intme(int ring, int entry)
2705 /* Algorithm: IRQ every 1/2 of descriptors. */
2706 if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
2712 static void cas_write_txd(struct cas *cp, int ring, int entry,
2713 dma_addr_t mapping, int len, u64 ctrl, int last)
2715 struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
2717 ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
2718 if (cas_intme(ring, entry))
2719 ctrl |= TX_DESC_INTME;
2721 ctrl |= TX_DESC_EOF;
2722 txd->control = cpu_to_le64(ctrl);
2723 txd->buffer = cpu_to_le64(mapping);
2726 static inline void *tx_tiny_buf(struct cas *cp, const int ring,
2729 return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
2732 static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring,
2733 const int entry, const int tentry)
2735 cp->tx_tiny_use[ring][tentry].nbufs++;
2736 cp->tx_tiny_use[ring][entry].used = 1;
2737 return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
2740 static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
2741 struct sk_buff *skb)
2743 struct net_device *dev = cp->dev;
2744 int entry, nr_frags, frag, tabort, tentry;
2746 unsigned long flags;
2750 spin_lock_irqsave(&cp->tx_lock[ring], flags);
2752 /* This is a hard error, log it. */
2753 if (TX_BUFFS_AVAIL(cp, ring) <=
2754 CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
2755 netif_stop_queue(dev);
2756 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2757 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
2762 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2763 const u64 csum_start_off = skb_checksum_start_offset(skb);
2764 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
2766 ctrl = TX_DESC_CSUM_EN |
2767 CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
2768 CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
2771 entry = cp->tx_new[ring];
2772 cp->tx_skbs[ring][entry] = skb;
2774 nr_frags = skb_shinfo(skb)->nr_frags;
2775 len = skb_headlen(skb);
2776 mapping = dma_map_page(&cp->pdev->dev, virt_to_page(skb->data),
2777 offset_in_page(skb->data), len, DMA_TO_DEVICE);
2780 tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
2781 if (unlikely(tabort)) {
2782 /* NOTE: len is always > tabort */
2783 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2784 ctrl | TX_DESC_SOF, 0);
2785 entry = TX_DESC_NEXT(ring, entry);
2787 skb_copy_from_linear_data_offset(skb, len - tabort,
2788 tx_tiny_buf(cp, ring, entry), tabort);
2789 mapping = tx_tiny_map(cp, ring, entry, tentry);
2790 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
2793 cas_write_txd(cp, ring, entry, mapping, len, ctrl |
2794 TX_DESC_SOF, (nr_frags == 0));
2796 entry = TX_DESC_NEXT(ring, entry);
2798 for (frag = 0; frag < nr_frags; frag++) {
2799 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
2801 len = skb_frag_size(fragp);
2802 mapping = skb_frag_dma_map(&cp->pdev->dev, fragp, 0, len,
2805 tabort = cas_calc_tabort(cp, skb_frag_off(fragp), len);
2806 if (unlikely(tabort)) {
2809 /* NOTE: len is always > tabort */
2810 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2812 entry = TX_DESC_NEXT(ring, entry);
2814 addr = cas_page_map(skb_frag_page(fragp));
2815 memcpy(tx_tiny_buf(cp, ring, entry),
2816 addr + skb_frag_off(fragp) + len - tabort,
2818 cas_page_unmap(addr);
2819 mapping = tx_tiny_map(cp, ring, entry, tentry);
2823 cas_write_txd(cp, ring, entry, mapping, len, ctrl,
2824 (frag + 1 == nr_frags));
2825 entry = TX_DESC_NEXT(ring, entry);
2828 cp->tx_new[ring] = entry;
2829 if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
2830 netif_stop_queue(dev);
2832 netif_printk(cp, tx_queued, KERN_DEBUG, dev,
2833 "tx[%d] queued, slot %d, skblen %d, avail %d\n",
2834 ring, entry, skb->len, TX_BUFFS_AVAIL(cp, ring));
2835 writel(entry, cp->regs + REG_TX_KICKN(ring));
2836 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2840 static netdev_tx_t cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
2842 struct cas *cp = netdev_priv(dev);
2844 /* this is only used as a load-balancing hint, so it doesn't
2845 * need to be SMP safe
2849 if (skb_padto(skb, cp->min_frame_size))
2850 return NETDEV_TX_OK;
2852 /* XXX: we need some higher-level QoS hooks to steer packets to
2853 * individual queues.
2855 if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
2856 return NETDEV_TX_BUSY;
2857 return NETDEV_TX_OK;
2860 static void cas_init_tx_dma(struct cas *cp)
2862 u64 desc_dma = cp->block_dvma;
2867 /* set up tx completion writeback registers. must be 8-byte aligned */
2868 #ifdef USE_TX_COMPWB
2869 off = offsetof(struct cas_init_block, tx_compwb);
2870 writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
2871 writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
2874 /* enable completion writebacks, enable paced mode,
2875 * disable read pipe, and disable pre-interrupt compwbs
2877 val = TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |
2878 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
2879 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE |
2880 TX_CFG_INTR_COMPWB_DIS;
2882 /* write out tx ring info and tx desc bases */
2883 for (i = 0; i < MAX_TX_RINGS; i++) {
2884 off = (unsigned long) cp->init_txds[i] -
2885 (unsigned long) cp->init_block;
2887 val |= CAS_TX_RINGN_BASE(i);
2888 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
2889 writel((desc_dma + off) & 0xffffffff, cp->regs +
2891 /* don't zero out the kick register here as the system
2895 writel(val, cp->regs + REG_TX_CFG);
2897 /* program max burst sizes. these numbers should be different
2901 writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2902 writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
2903 writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
2904 writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
2906 writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2907 writel(0x800, cp->regs + REG_TX_MAXBURST_1);
2908 writel(0x800, cp->regs + REG_TX_MAXBURST_2);
2909 writel(0x800, cp->regs + REG_TX_MAXBURST_3);
2913 /* Must be invoked under cp->lock. */
2914 static inline void cas_init_dma(struct cas *cp)
2916 cas_init_tx_dma(cp);
2917 cas_init_rx_dma(cp);
2920 static void cas_process_mc_list(struct cas *cp)
2924 struct netdev_hw_addr *ha;
2927 memset(hash_table, 0, sizeof(hash_table));
2928 netdev_for_each_mc_addr(ha, cp->dev) {
2929 if (i <= CAS_MC_EXACT_MATCH_SIZE) {
2930 /* use the alternate mac address registers for the
2931 * first 15 multicast addresses
2933 writel((ha->addr[4] << 8) | ha->addr[5],
2934 cp->regs + REG_MAC_ADDRN(i*3 + 0));
2935 writel((ha->addr[2] << 8) | ha->addr[3],
2936 cp->regs + REG_MAC_ADDRN(i*3 + 1));
2937 writel((ha->addr[0] << 8) | ha->addr[1],
2938 cp->regs + REG_MAC_ADDRN(i*3 + 2));
2942 /* use hw hash table for the next series of
2943 * multicast addresses
2945 crc = ether_crc_le(ETH_ALEN, ha->addr);
2947 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
2950 for (i = 0; i < 16; i++)
2951 writel(hash_table[i], cp->regs + REG_MAC_HASH_TABLEN(i));
2954 /* Must be invoked under cp->lock. */
2955 static u32 cas_setup_multicast(struct cas *cp)
2960 if (cp->dev->flags & IFF_PROMISC) {
2961 rxcfg |= MAC_RX_CFG_PROMISC_EN;
2963 } else if (cp->dev->flags & IFF_ALLMULTI) {
2964 for (i=0; i < 16; i++)
2965 writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
2966 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2969 cas_process_mc_list(cp);
2970 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2976 /* must be invoked under cp->stat_lock[N_TX_RINGS] */
2977 static void cas_clear_mac_err(struct cas *cp)
2979 writel(0, cp->regs + REG_MAC_COLL_NORMAL);
2980 writel(0, cp->regs + REG_MAC_COLL_FIRST);
2981 writel(0, cp->regs + REG_MAC_COLL_EXCESS);
2982 writel(0, cp->regs + REG_MAC_COLL_LATE);
2983 writel(0, cp->regs + REG_MAC_TIMER_DEFER);
2984 writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
2985 writel(0, cp->regs + REG_MAC_RECV_FRAME);
2986 writel(0, cp->regs + REG_MAC_LEN_ERR);
2987 writel(0, cp->regs + REG_MAC_ALIGN_ERR);
2988 writel(0, cp->regs + REG_MAC_FCS_ERR);
2989 writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
2993 static void cas_mac_reset(struct cas *cp)
2997 /* do both TX and RX reset */
2998 writel(0x1, cp->regs + REG_MAC_TX_RESET);
2999 writel(0x1, cp->regs + REG_MAC_RX_RESET);
3004 if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
3012 if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
3017 if (readl(cp->regs + REG_MAC_TX_RESET) |
3018 readl(cp->regs + REG_MAC_RX_RESET))
3019 netdev_err(cp->dev, "mac tx[%d]/rx[%d] reset failed [%08x]\n",
3020 readl(cp->regs + REG_MAC_TX_RESET),
3021 readl(cp->regs + REG_MAC_RX_RESET),
3022 readl(cp->regs + REG_MAC_STATE_MACHINE));
3026 /* Must be invoked under cp->lock. */
3027 static void cas_init_mac(struct cas *cp)
3029 unsigned char *e = &cp->dev->dev_addr[0];
3033 /* setup core arbitration weight register */
3034 writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
3036 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
3037 /* set the infinite burst register for chips that don't have
3040 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
3041 writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
3044 writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
3046 writel(0x00, cp->regs + REG_MAC_IPG0);
3047 writel(0x08, cp->regs + REG_MAC_IPG1);
3048 writel(0x04, cp->regs + REG_MAC_IPG2);
3050 /* change later for 802.3z */
3051 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3053 /* min frame + FCS */
3054 writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
3056 /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we
3057 * specify the maximum frame size to prevent RX tag errors on
3060 writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
3061 CAS_BASE(MAC_FRAMESIZE_MAX_FRAME,
3062 (CAS_MAX_MTU + ETH_HLEN + 4 + 4)),
3063 cp->regs + REG_MAC_FRAMESIZE_MAX);
3065 /* NOTE: crc_size is used as a surrogate for half-duplex.
3066 * workaround saturn half-duplex issue by increasing preamble
3069 if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
3070 writel(0x41, cp->regs + REG_MAC_PA_SIZE);
3072 writel(0x07, cp->regs + REG_MAC_PA_SIZE);
3073 writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
3074 writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
3075 writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
3077 writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
3079 writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
3080 writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
3081 writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
3082 writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
3083 writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
3085 /* setup mac address in perfect filter array */
3086 for (i = 0; i < 45; i++)
3087 writel(0x0, cp->regs + REG_MAC_ADDRN(i));
3089 writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
3090 writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
3091 writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
3093 writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
3094 writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
3095 writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
3097 cp->mac_rx_cfg = cas_setup_multicast(cp);
3099 spin_lock(&cp->stat_lock[N_TX_RINGS]);
3100 cas_clear_mac_err(cp);
3101 spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3103 /* Setup MAC interrupts. We want to get all of the interesting
3104 * counter expiration events, but we do not want to hear about
3105 * normal rx/tx as the DMA engine tells us that.
3107 writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
3108 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
3110 /* Don't enable even the PAUSE interrupts for now, we
3111 * make no use of those events other than to record them.
3113 writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
3116 /* Must be invoked under cp->lock. */
3117 static void cas_init_pause_thresholds(struct cas *cp)
3119 /* Calculate pause thresholds. Setting the OFF threshold to the
3120 * full RX fifo size effectively disables PAUSE generation
3122 if (cp->rx_fifo_size <= (2 * 1024)) {
3123 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
3125 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
3126 if (max_frame * 3 > cp->rx_fifo_size) {
3127 cp->rx_pause_off = 7104;
3128 cp->rx_pause_on = 960;
3130 int off = (cp->rx_fifo_size - (max_frame * 2));
3131 int on = off - max_frame;
3132 cp->rx_pause_off = off;
3133 cp->rx_pause_on = on;
3138 static int cas_vpd_match(const void __iomem *p, const char *str)
3140 int len = strlen(str) + 1;
3143 for (i = 0; i < len; i++) {
3144 if (readb(p + i) != str[i])
3151 /* get the mac address by reading the vpd information in the rom.
3152 * also get the phy type and determine if there's an entropy generator.
3153 * NOTE: this is a bit convoluted for the following reasons:
3154 * 1) vpd info has order-dependent mac addresses for multinic cards
3155 * 2) the only way to determine the nic order is to use the slot
3157 * 3) fiber cards don't have bridges, so their slot numbers don't
3159 * 4) we don't actually know we have a fiber card until after
3160 * the mac addresses are parsed.
3162 static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
3165 void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
3166 void __iomem *base, *kstart;
3169 #define VPD_FOUND_MAC 0x01
3170 #define VPD_FOUND_PHY 0x02
3172 int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */
3175 #if defined(CONFIG_SPARC)
3176 const unsigned char *addr;
3179 /* give us access to the PROM */
3180 writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
3181 cp->regs + REG_BIM_LOCAL_DEV_EN);
3183 /* check for an expansion rom */
3184 if (readb(p) != 0x55 || readb(p + 1) != 0xaa)
3185 goto use_random_mac_addr;
3187 /* search for beginning of vpd */
3189 for (i = 2; i < EXPANSION_ROM_SIZE; i++) {
3190 /* check for PCIR */
3191 if ((readb(p + i + 0) == 0x50) &&
3192 (readb(p + i + 1) == 0x43) &&
3193 (readb(p + i + 2) == 0x49) &&
3194 (readb(p + i + 3) == 0x52)) {
3195 base = p + (readb(p + i + 8) |
3196 (readb(p + i + 9) << 8));
3201 if (!base || (readb(base) != 0x82))
3202 goto use_random_mac_addr;
3204 i = (readb(base + 1) | (readb(base + 2) << 8)) + 3;
3205 while (i < EXPANSION_ROM_SIZE) {
3206 if (readb(base + i) != 0x90) /* no vpd found */
3207 goto use_random_mac_addr;
3209 /* found a vpd field */
3210 len = readb(base + i + 1) | (readb(base + i + 2) << 8);
3212 /* extract keywords */
3213 kstart = base + i + 3;
3215 while ((p - kstart) < len) {
3216 int klen = readb(p + 2);
3222 /* look for the following things:
3223 * -- correct length == 29
3224 * 3 (type) + 2 (size) +
3225 * 18 (strlen("local-mac-address") + 1) +
3227 * -- VPD Instance 'I'
3228 * -- VPD Type Bytes 'B'
3229 * -- VPD data length == 6
3230 * -- property string == local-mac-address
3232 * -- correct length == 24
3233 * 3 (type) + 2 (size) +
3234 * 12 (strlen("entropy-dev") + 1) +
3235 * 7 (strlen("vms110") + 1)
3236 * -- VPD Instance 'I'
3237 * -- VPD Type String 'B'
3238 * -- VPD data length == 7
3239 * -- property string == entropy-dev
3241 * -- correct length == 18
3242 * 3 (type) + 2 (size) +
3243 * 9 (strlen("phy-type") + 1) +
3244 * 4 (strlen("pcs") + 1)
3245 * -- VPD Instance 'I'
3246 * -- VPD Type String 'S'
3247 * -- VPD data length == 4
3248 * -- property string == phy-type
3250 * -- correct length == 23
3251 * 3 (type) + 2 (size) +
3252 * 14 (strlen("phy-interface") + 1) +
3253 * 4 (strlen("pcs") + 1)
3254 * -- VPD Instance 'I'
3255 * -- VPD Type String 'S'
3256 * -- VPD data length == 4
3257 * -- property string == phy-interface
3259 if (readb(p) != 'I')
3262 /* finally, check string and length */
3263 type = readb(p + 3);
3265 if ((klen == 29) && readb(p + 4) == 6 &&
3266 cas_vpd_match(p + 5,
3267 "local-mac-address")) {
3268 if (mac_off++ > offset)
3271 /* set mac address */
3272 for (j = 0; j < 6; j++)
3282 #ifdef USE_ENTROPY_DEV
3284 cas_vpd_match(p + 5, "entropy-dev") &&
3285 cas_vpd_match(p + 17, "vms110")) {
3286 cp->cas_flags |= CAS_FLAG_ENTROPY_DEV;
3291 if (found & VPD_FOUND_PHY)
3294 if ((klen == 18) && readb(p + 4) == 4 &&
3295 cas_vpd_match(p + 5, "phy-type")) {
3296 if (cas_vpd_match(p + 14, "pcs")) {
3297 phy_type = CAS_PHY_SERDES;
3302 if ((klen == 23) && readb(p + 4) == 4 &&
3303 cas_vpd_match(p + 5, "phy-interface")) {
3304 if (cas_vpd_match(p + 19, "pcs")) {
3305 phy_type = CAS_PHY_SERDES;
3310 found |= VPD_FOUND_MAC;
3314 found |= VPD_FOUND_PHY;
3322 use_random_mac_addr:
3323 if (found & VPD_FOUND_MAC)
3326 #if defined(CONFIG_SPARC)
3327 addr = of_get_property(cp->of_node, "local-mac-address", NULL);
3329 memcpy(dev_addr, addr, ETH_ALEN);
3334 /* Sun MAC prefix then 3 random bytes. */
3335 pr_info("MAC address not found in ROM VPD\n");
3339 get_random_bytes(dev_addr + 3, 3);
3342 writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3346 /* check pci invariants */
3347 static void cas_check_pci_invariants(struct cas *cp)
3349 struct pci_dev *pdev = cp->pdev;
3352 if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
3353 (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
3354 if (pdev->revision >= CAS_ID_REVPLUS)
3355 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3356 if (pdev->revision < CAS_ID_REVPLUS02u)
3357 cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
3359 /* Original Cassini supports HW CSUM, but it's not
3360 * enabled by default as it can trigger TX hangs.
3362 if (pdev->revision < CAS_ID_REV2)
3363 cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
3365 /* Only sun has original cassini chips. */
3366 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3368 /* We use a flag because the same phy might be externally
3371 if ((pdev->vendor == PCI_VENDOR_ID_NS) &&
3372 (pdev->device == PCI_DEVICE_ID_NS_SATURN))
3373 cp->cas_flags |= CAS_FLAG_SATURN;
3378 static int cas_check_invariants(struct cas *cp)
3380 struct pci_dev *pdev = cp->pdev;
3384 /* get page size for rx buffers. */
3386 #ifdef USE_PAGE_ORDER
3387 if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) {
3388 /* see if we can allocate larger pages */
3389 struct page *page = alloc_pages(GFP_ATOMIC,
3390 CAS_JUMBO_PAGE_SHIFT -
3393 __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT);
3394 cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT;
3396 printk("MTU limited to %d bytes\n", CAS_MAX_MTU);
3400 cp->page_size = (PAGE_SIZE << cp->page_order);
3402 /* Fetch the FIFO configurations. */
3403 cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64;
3404 cp->rx_fifo_size = RX_FIFO_SIZE;
3406 /* finish phy determination. MDIO1 takes precedence over MDIO0 if
3407 * they're both connected.
3409 cp->phy_type = cas_get_vpd_info(cp, cp->dev->dev_addr,
3410 PCI_SLOT(pdev->devfn));
3411 if (cp->phy_type & CAS_PHY_SERDES) {
3412 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3413 return 0; /* no more checking needed */
3417 cfg = readl(cp->regs + REG_MIF_CFG);
3418 if (cfg & MIF_CFG_MDIO_1) {
3419 cp->phy_type = CAS_PHY_MII_MDIO1;
3420 } else if (cfg & MIF_CFG_MDIO_0) {
3421 cp->phy_type = CAS_PHY_MII_MDIO0;
3424 cas_mif_poll(cp, 0);
3425 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3427 for (i = 0; i < 32; i++) {
3431 for (j = 0; j < 3; j++) {
3433 phy_id = cas_phy_read(cp, MII_PHYSID1) << 16;
3434 phy_id |= cas_phy_read(cp, MII_PHYSID2);
3435 if (phy_id && (phy_id != 0xFFFFFFFF)) {
3436 cp->phy_id = phy_id;
3441 pr_err("MII phy did not respond [%08x]\n",
3442 readl(cp->regs + REG_MIF_STATE_MACHINE));
3446 /* see if we can do gigabit */
3447 cfg = cas_phy_read(cp, MII_BMSR);
3448 if ((cfg & CAS_BMSR_1000_EXTEND) &&
3449 cas_phy_read(cp, CAS_MII_1000_EXTEND))
3450 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3454 /* Must be invoked under cp->lock. */
3455 static inline void cas_start_dma(struct cas *cp)
3462 val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN;
3463 writel(val, cp->regs + REG_TX_CFG);
3464 val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN;
3465 writel(val, cp->regs + REG_RX_CFG);
3467 /* enable the mac */
3468 val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN;
3469 writel(val, cp->regs + REG_MAC_TX_CFG);
3470 val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN;
3471 writel(val, cp->regs + REG_MAC_RX_CFG);
3475 val = readl(cp->regs + REG_MAC_TX_CFG);
3476 if ((val & MAC_TX_CFG_EN))
3480 if (i < 0) txfailed = 1;
3483 val = readl(cp->regs + REG_MAC_RX_CFG);
3484 if ((val & MAC_RX_CFG_EN)) {
3487 "enabling mac failed [tx:%08x:%08x]\n",
3488 readl(cp->regs + REG_MIF_STATE_MACHINE),
3489 readl(cp->regs + REG_MAC_STATE_MACHINE));
3491 goto enable_rx_done;
3495 netdev_err(cp->dev, "enabling mac failed [%s:%08x:%08x]\n",
3496 (txfailed ? "tx,rx" : "rx"),
3497 readl(cp->regs + REG_MIF_STATE_MACHINE),
3498 readl(cp->regs + REG_MAC_STATE_MACHINE));
3501 cas_unmask_intr(cp); /* enable interrupts */
3502 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
3503 writel(0, cp->regs + REG_RX_COMP_TAIL);
3505 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
3506 if (N_RX_DESC_RINGS > 1)
3507 writel(RX_DESC_RINGN_SIZE(1) - 4,
3508 cp->regs + REG_PLUS_RX_KICK1);
3510 for (i = 1; i < N_RX_COMP_RINGS; i++)
3511 writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i));
3515 /* Must be invoked under cp->lock. */
3516 static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd,
3519 u32 val = readl(cp->regs + REG_PCS_MII_LPA);
3520 *fd = (val & PCS_MII_LPA_FD) ? 1 : 0;
3521 *pause = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00;
3522 if (val & PCS_MII_LPA_ASYM_PAUSE)
3527 /* Must be invoked under cp->lock. */
3528 static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd,
3537 /* use GMII registers */
3538 val = cas_phy_read(cp, MII_LPA);
3539 if (val & CAS_LPA_PAUSE)
3542 if (val & CAS_LPA_ASYM_PAUSE)
3545 if (val & LPA_DUPLEX)
3550 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
3551 val = cas_phy_read(cp, CAS_MII_1000_STATUS);
3552 if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF))
3554 if (val & CAS_LPA_1000FULL)
3559 /* A link-up condition has occurred, initialize and enable the
3562 * Must be invoked under cp->lock.
3564 static void cas_set_link_modes(struct cas *cp)
3567 int full_duplex, speed, pause;
3573 if (CAS_PHY_MII(cp->phy_type)) {
3574 cas_mif_poll(cp, 0);
3575 val = cas_phy_read(cp, MII_BMCR);
3576 if (val & BMCR_ANENABLE) {
3577 cas_read_mii_link_mode(cp, &full_duplex, &speed,
3580 if (val & BMCR_FULLDPLX)
3583 if (val & BMCR_SPEED100)
3585 else if (val & CAS_BMCR_SPEED1000)
3586 speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
3589 cas_mif_poll(cp, 1);
3592 val = readl(cp->regs + REG_PCS_MII_CTRL);
3593 cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause);
3594 if ((val & PCS_MII_AUTONEG_EN) == 0) {
3595 if (val & PCS_MII_CTRL_DUPLEX)
3600 netif_info(cp, link, cp->dev, "Link up at %d Mbps, %s-duplex\n",
3601 speed, full_duplex ? "full" : "half");
3603 val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED;
3604 if (CAS_PHY_MII(cp->phy_type)) {
3605 val |= MAC_XIF_MII_BUFFER_OUTPUT_EN;
3607 val |= MAC_XIF_DISABLE_ECHO;
3610 val |= MAC_XIF_FDPLX_LED;
3612 val |= MAC_XIF_GMII_MODE;
3613 writel(val, cp->regs + REG_MAC_XIF_CFG);
3615 /* deal with carrier and collision detect. */
3616 val = MAC_TX_CFG_IPG_EN;
3618 val |= MAC_TX_CFG_IGNORE_CARRIER;
3619 val |= MAC_TX_CFG_IGNORE_COLL;
3621 #ifndef USE_CSMA_CD_PROTO
3622 val |= MAC_TX_CFG_NEVER_GIVE_UP_EN;
3623 val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM;
3626 /* val now set up for REG_MAC_TX_CFG */
3628 /* If gigabit and half-duplex, enable carrier extension
3629 * mode. increase slot time to 512 bytes as well.
3630 * else, disable it and make sure slot time is 64 bytes.
3631 * also activate checksum bug workaround
3633 if ((speed == 1000) && !full_duplex) {
3634 writel(val | MAC_TX_CFG_CARRIER_EXTEND,
3635 cp->regs + REG_MAC_TX_CFG);
3637 val = readl(cp->regs + REG_MAC_RX_CFG);
3638 val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */
3639 writel(val | MAC_RX_CFG_CARRIER_EXTEND,
3640 cp->regs + REG_MAC_RX_CFG);
3642 writel(0x200, cp->regs + REG_MAC_SLOT_TIME);
3645 /* minimum size gigabit frame at half duplex */
3646 cp->min_frame_size = CAS_1000MB_MIN_FRAME;
3649 writel(val, cp->regs + REG_MAC_TX_CFG);
3651 /* checksum bug workaround. don't strip FCS when in
3654 val = readl(cp->regs + REG_MAC_RX_CFG);
3656 val |= MAC_RX_CFG_STRIP_FCS;
3658 cp->min_frame_size = CAS_MIN_MTU;
3660 val &= ~MAC_RX_CFG_STRIP_FCS;
3662 cp->min_frame_size = CAS_MIN_FRAME;
3664 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,
3665 cp->regs + REG_MAC_RX_CFG);
3666 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3669 if (netif_msg_link(cp)) {
3671 netdev_info(cp->dev, "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
3675 } else if (pause & 0x10) {
3676 netdev_info(cp->dev, "TX pause enabled\n");
3678 netdev_info(cp->dev, "Pause is disabled\n");
3682 val = readl(cp->regs + REG_MAC_CTRL_CFG);
3683 val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN);
3684 if (pause) { /* symmetric or asymmetric pause */
3685 val |= MAC_CTRL_CFG_SEND_PAUSE_EN;
3686 if (pause & 0x01) { /* symmetric pause */
3687 val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
3690 writel(val, cp->regs + REG_MAC_CTRL_CFG);
3694 /* Must be invoked under cp->lock. */
3695 static void cas_init_hw(struct cas *cp, int restart_link)
3700 cas_init_pause_thresholds(cp);
3705 /* Default aneg parameters */
3706 cp->timer_ticks = 0;
3707 cas_begin_auto_negotiation(cp, NULL);
3708 } else if (cp->lstate == link_up) {
3709 cas_set_link_modes(cp);
3710 netif_carrier_on(cp->dev);
3714 /* Must be invoked under cp->lock. on earlier cassini boards,
3715 * SOFT_0 is tied to PCI reset. we use this to force a pci reset,
3716 * let it settle out, and then restore pci state.
3718 static void cas_hard_reset(struct cas *cp)
3720 writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3722 pci_restore_state(cp->pdev);
3726 static void cas_global_reset(struct cas *cp, int blkflag)
3730 /* issue a global reset. don't use RSTOUT. */
3731 if (blkflag && !CAS_PHY_MII(cp->phy_type)) {
3732 /* For PCS, when the blkflag is set, we should set the
3733 * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of
3734 * the last autonegotiation from being cleared. We'll
3735 * need some special handling if the chip is set into a
3738 writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),
3739 cp->regs + REG_SW_RESET);
3741 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);
3744 /* need to wait at least 3ms before polling register */
3748 while (limit-- > 0) {
3749 u32 val = readl(cp->regs + REG_SW_RESET);
3750 if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)
3754 netdev_err(cp->dev, "sw reset failed\n");
3757 /* enable various BIM interrupts */
3758 writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |
3759 BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG);
3761 /* clear out pci error status mask for handled errors.
3762 * we don't deal with DMA counter overflows as they happen
3765 writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |
3766 PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE |
3767 PCI_ERR_BIM_DMA_READ), cp->regs +
3768 REG_PCI_ERR_STATUS_MASK);
3770 /* set up for MII by default to address mac rx reset timeout
3773 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3776 static void cas_reset(struct cas *cp, int blkflag)
3781 cas_global_reset(cp, blkflag);
3783 cas_entropy_reset(cp);
3785 /* disable dma engines. */
3786 val = readl(cp->regs + REG_TX_CFG);
3787 val &= ~TX_CFG_DMA_EN;
3788 writel(val, cp->regs + REG_TX_CFG);
3790 val = readl(cp->regs + REG_RX_CFG);
3791 val &= ~RX_CFG_DMA_EN;
3792 writel(val, cp->regs + REG_RX_CFG);
3794 /* program header parser */
3795 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) ||
3796 (CAS_HP_ALT_FIRMWARE == cas_prog_null)) {
3797 cas_load_firmware(cp, CAS_HP_FIRMWARE);
3799 cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE);
3802 /* clear out error registers */
3803 spin_lock(&cp->stat_lock[N_TX_RINGS]);
3804 cas_clear_mac_err(cp);
3805 spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3808 /* Shut down the chip, must be called with pm_mutex held. */
3809 static void cas_shutdown(struct cas *cp)
3811 unsigned long flags;
3813 /* Make us not-running to avoid timers respawning */
3816 del_timer_sync(&cp->link_timer);
3818 /* Stop the reset task */
3820 while (atomic_read(&cp->reset_task_pending_mtu) ||
3821 atomic_read(&cp->reset_task_pending_spare) ||
3822 atomic_read(&cp->reset_task_pending_all))
3826 while (atomic_read(&cp->reset_task_pending))
3829 /* Actually stop the chip */
3830 cas_lock_all_save(cp, flags);
3832 if (cp->cas_flags & CAS_FLAG_SATURN)
3833 cas_phy_powerdown(cp);
3834 cas_unlock_all_restore(cp, flags);
3837 static int cas_change_mtu(struct net_device *dev, int new_mtu)
3839 struct cas *cp = netdev_priv(dev);
3842 if (!netif_running(dev) || !netif_device_present(dev))
3845 /* let the reset task handle it */
3847 atomic_inc(&cp->reset_task_pending);
3848 if ((cp->phy_type & CAS_PHY_SERDES)) {
3849 atomic_inc(&cp->reset_task_pending_all);
3851 atomic_inc(&cp->reset_task_pending_mtu);
3853 schedule_work(&cp->reset_task);
3855 atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ?
3856 CAS_RESET_ALL : CAS_RESET_MTU);
3857 pr_err("reset called in cas_change_mtu\n");
3858 schedule_work(&cp->reset_task);
3861 flush_work(&cp->reset_task);
3865 static void cas_clean_txd(struct cas *cp, int ring)
3867 struct cas_tx_desc *txd = cp->init_txds[ring];
3868 struct sk_buff *skb, **skbs = cp->tx_skbs[ring];
3872 size = TX_DESC_RINGN_SIZE(ring);
3873 for (i = 0; i < size; i++) {
3876 if (skbs[i] == NULL)
3882 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
3883 int ent = i & (size - 1);
3885 /* first buffer is never a tiny buffer and so
3886 * needs to be unmapped.
3888 daddr = le64_to_cpu(txd[ent].buffer);
3889 dlen = CAS_VAL(TX_DESC_BUFLEN,
3890 le64_to_cpu(txd[ent].control));
3891 dma_unmap_page(&cp->pdev->dev, daddr, dlen,
3894 if (frag != skb_shinfo(skb)->nr_frags) {
3897 /* next buffer might by a tiny buffer.
3900 ent = i & (size - 1);
3901 if (cp->tx_tiny_use[ring][ent].used)
3905 dev_kfree_skb_any(skb);
3908 /* zero out tiny buf usage */
3909 memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring]));
3912 /* freed on close */
3913 static inline void cas_free_rx_desc(struct cas *cp, int ring)
3915 cas_page_t **page = cp->rx_pages[ring];
3918 size = RX_DESC_RINGN_SIZE(ring);
3919 for (i = 0; i < size; i++) {
3921 cas_page_free(cp, page[i]);
3927 static void cas_free_rxds(struct cas *cp)
3931 for (i = 0; i < N_RX_DESC_RINGS; i++)
3932 cas_free_rx_desc(cp, i);
3935 /* Must be invoked under cp->lock. */
3936 static void cas_clean_rings(struct cas *cp)
3940 /* need to clean all tx rings */
3941 memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS);
3942 memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS);
3943 for (i = 0; i < N_TX_RINGS; i++)
3944 cas_clean_txd(cp, i);
3946 /* zero out init block */
3947 memset(cp->init_block, 0, sizeof(struct cas_init_block));
3952 /* allocated on open */
3953 static inline int cas_alloc_rx_desc(struct cas *cp, int ring)
3955 cas_page_t **page = cp->rx_pages[ring];
3958 size = RX_DESC_RINGN_SIZE(ring);
3959 for (i = 0; i < size; i++) {
3960 if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL)
3966 static int cas_alloc_rxds(struct cas *cp)
3970 for (i = 0; i < N_RX_DESC_RINGS; i++) {
3971 if (cas_alloc_rx_desc(cp, i) < 0) {
3979 static void cas_reset_task(struct work_struct *work)
3981 struct cas *cp = container_of(work, struct cas, reset_task);
3983 int pending = atomic_read(&cp->reset_task_pending);
3985 int pending_all = atomic_read(&cp->reset_task_pending_all);
3986 int pending_spare = atomic_read(&cp->reset_task_pending_spare);
3987 int pending_mtu = atomic_read(&cp->reset_task_pending_mtu);
3989 if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) {
3990 /* We can have more tasks scheduled than actually
3993 atomic_dec(&cp->reset_task_pending);
3997 /* The link went down, we reset the ring, but keep
3998 * DMA stopped. Use this function for reset
4001 if (cp->hw_running) {
4002 unsigned long flags;
4004 /* Make sure we don't get interrupts or tx packets */
4005 netif_device_detach(cp->dev);
4006 cas_lock_all_save(cp, flags);
4009 /* We call cas_spare_recover when we call cas_open.
4010 * but we do not initialize the lists cas_spare_recover
4011 * uses until cas_open is called.
4013 cas_spare_recover(cp, GFP_ATOMIC);
4016 /* test => only pending_spare set */
4017 if (!pending_all && !pending_mtu)
4020 if (pending == CAS_RESET_SPARE)
4023 /* when pending == CAS_RESET_ALL, the following
4024 * call to cas_init_hw will restart auto negotiation.
4025 * Setting the second argument of cas_reset to
4026 * !(pending == CAS_RESET_ALL) will set this argument
4027 * to 1 (avoiding reinitializing the PHY for the normal
4028 * PCS case) when auto negotiation is not restarted.
4031 cas_reset(cp, !(pending_all > 0));
4033 cas_clean_rings(cp);
4034 cas_init_hw(cp, (pending_all > 0));
4036 cas_reset(cp, !(pending == CAS_RESET_ALL));
4038 cas_clean_rings(cp);
4039 cas_init_hw(cp, pending == CAS_RESET_ALL);
4043 cas_unlock_all_restore(cp, flags);
4044 netif_device_attach(cp->dev);
4047 atomic_sub(pending_all, &cp->reset_task_pending_all);
4048 atomic_sub(pending_spare, &cp->reset_task_pending_spare);
4049 atomic_sub(pending_mtu, &cp->reset_task_pending_mtu);
4050 atomic_dec(&cp->reset_task_pending);
4052 atomic_set(&cp->reset_task_pending, 0);
4056 static void cas_link_timer(struct timer_list *t)
4058 struct cas *cp = from_timer(cp, t, link_timer);
4059 int mask, pending = 0, reset = 0;
4060 unsigned long flags;
4062 if (link_transition_timeout != 0 &&
4063 cp->link_transition_jiffies_valid &&
4064 ((jiffies - cp->link_transition_jiffies) >
4065 (link_transition_timeout))) {
4066 /* One-second counter so link-down workaround doesn't
4067 * cause resets to occur so fast as to fool the switch
4068 * into thinking the link is down.
4070 cp->link_transition_jiffies_valid = 0;
4073 if (!cp->hw_running)
4076 spin_lock_irqsave(&cp->lock, flags);
4078 cas_entropy_gather(cp);
4080 /* If the link task is still pending, we just
4081 * reschedule the link timer
4084 if (atomic_read(&cp->reset_task_pending_all) ||
4085 atomic_read(&cp->reset_task_pending_spare) ||
4086 atomic_read(&cp->reset_task_pending_mtu))
4089 if (atomic_read(&cp->reset_task_pending))
4093 /* check for rx cleaning */
4094 if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) {
4097 for (i = 0; i < MAX_RX_DESC_RINGS; i++) {
4098 rmask = CAS_FLAG_RXD_POST(i);
4099 if ((mask & rmask) == 0)
4102 /* post_rxds will do a mod_timer */
4103 if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) {
4107 cp->cas_flags &= ~rmask;
4111 if (CAS_PHY_MII(cp->phy_type)) {
4113 cas_mif_poll(cp, 0);
4114 bmsr = cas_phy_read(cp, MII_BMSR);
4115 /* WTZ: Solaris driver reads this twice, but that
4116 * may be due to the PCS case and the use of a
4117 * common implementation. Read it twice here to be
4120 bmsr = cas_phy_read(cp, MII_BMSR);
4121 cas_mif_poll(cp, 1);
4122 readl(cp->regs + REG_MIF_STATUS); /* avoid dups */
4123 reset = cas_mii_link_check(cp, bmsr);
4125 reset = cas_pcs_link_check(cp);
4131 /* check for tx state machine confusion */
4132 if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) {
4133 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE);
4135 int tlm = CAS_VAL(MAC_SM_TLM, val);
4137 if (((tlm == 0x5) || (tlm == 0x3)) &&
4138 (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) {
4139 netif_printk(cp, tx_err, KERN_DEBUG, cp->dev,
4140 "tx err: MAC_STATE[%08x]\n", val);
4145 val = readl(cp->regs + REG_TX_FIFO_PKT_CNT);
4146 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
4147 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR);
4148 if ((val == 0) && (wptr != rptr)) {
4149 netif_printk(cp, tx_err, KERN_DEBUG, cp->dev,
4150 "tx err: TX_FIFO[%08x:%08x:%08x]\n",
4162 atomic_inc(&cp->reset_task_pending);
4163 atomic_inc(&cp->reset_task_pending_all);
4164 schedule_work(&cp->reset_task);
4166 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
4167 pr_err("reset called in cas_link_timer\n");
4168 schedule_work(&cp->reset_task);
4173 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
4175 spin_unlock_irqrestore(&cp->lock, flags);
4178 /* tiny buffers are used to avoid target abort issues with
4181 static void cas_tx_tiny_free(struct cas *cp)
4183 struct pci_dev *pdev = cp->pdev;
4186 for (i = 0; i < N_TX_RINGS; i++) {
4187 if (!cp->tx_tiny_bufs[i])
4190 dma_free_coherent(&pdev->dev, TX_TINY_BUF_BLOCK,
4191 cp->tx_tiny_bufs[i], cp->tx_tiny_dvma[i]);
4192 cp->tx_tiny_bufs[i] = NULL;
4196 static int cas_tx_tiny_alloc(struct cas *cp)
4198 struct pci_dev *pdev = cp->pdev;
4201 for (i = 0; i < N_TX_RINGS; i++) {
4202 cp->tx_tiny_bufs[i] =
4203 dma_alloc_coherent(&pdev->dev, TX_TINY_BUF_BLOCK,
4204 &cp->tx_tiny_dvma[i], GFP_KERNEL);
4205 if (!cp->tx_tiny_bufs[i]) {
4206 cas_tx_tiny_free(cp);
4214 static int cas_open(struct net_device *dev)
4216 struct cas *cp = netdev_priv(dev);
4218 unsigned long flags;
4220 mutex_lock(&cp->pm_mutex);
4222 hw_was_up = cp->hw_running;
4224 /* The power-management mutex protects the hw_running
4225 * etc. state so it is safe to do this bit without cp->lock
4227 if (!cp->hw_running) {
4228 /* Reset the chip */
4229 cas_lock_all_save(cp, flags);
4230 /* We set the second arg to cas_reset to zero
4231 * because cas_init_hw below will have its second
4232 * argument set to non-zero, which will force
4233 * autonegotiation to start.
4237 cas_unlock_all_restore(cp, flags);
4241 if (cas_tx_tiny_alloc(cp) < 0)
4244 /* alloc rx descriptors */
4245 if (cas_alloc_rxds(cp) < 0)
4248 /* allocate spares */
4250 cas_spare_recover(cp, GFP_KERNEL);
4252 /* We can now request the interrupt as we know it's masked
4253 * on the controller. cassini+ has up to 4 interrupts
4254 * that can be used, but you need to do explicit pci interrupt
4255 * mapping to expose them
4257 if (request_irq(cp->pdev->irq, cas_interrupt,
4258 IRQF_SHARED, dev->name, (void *) dev)) {
4259 netdev_err(cp->dev, "failed to request irq !\n");
4265 napi_enable(&cp->napi);
4268 cas_lock_all_save(cp, flags);
4269 cas_clean_rings(cp);
4270 cas_init_hw(cp, !hw_was_up);
4272 cas_unlock_all_restore(cp, flags);
4274 netif_start_queue(dev);
4275 mutex_unlock(&cp->pm_mutex);
4282 cas_tx_tiny_free(cp);
4284 mutex_unlock(&cp->pm_mutex);
4288 static int cas_close(struct net_device *dev)
4290 unsigned long flags;
4291 struct cas *cp = netdev_priv(dev);
4294 napi_disable(&cp->napi);
4296 /* Make sure we don't get distracted by suspend/resume */
4297 mutex_lock(&cp->pm_mutex);
4299 netif_stop_queue(dev);
4301 /* Stop traffic, mark us closed */
4302 cas_lock_all_save(cp, flags);
4306 cas_begin_auto_negotiation(cp, NULL);
4307 cas_clean_rings(cp);
4308 cas_unlock_all_restore(cp, flags);
4310 free_irq(cp->pdev->irq, (void *) dev);
4313 cas_tx_tiny_free(cp);
4314 mutex_unlock(&cp->pm_mutex);
4319 const char name[ETH_GSTRING_LEN];
4320 } ethtool_cassini_statnames[] = {
4327 {"rx_frame_errors"},
4328 {"rx_length_errors"},
4331 {"tx_aborted_errors"},
4338 #define CAS_NUM_STAT_KEYS ARRAY_SIZE(ethtool_cassini_statnames)
4341 const int offsets; /* neg. values for 2nd arg to cas_read_phy */
4342 } ethtool_register_table[] = {
4357 {REG_PCS_MII_STATUS},
4358 {REG_PCS_STATE_MACHINE},
4359 {REG_MAC_COLL_EXCESS},
4362 #define CAS_REG_LEN ARRAY_SIZE(ethtool_register_table)
4363 #define CAS_MAX_REGS (sizeof (u32)*CAS_REG_LEN)
4365 static void cas_read_regs(struct cas *cp, u8 *ptr, int len)
4369 unsigned long flags;
4371 spin_lock_irqsave(&cp->lock, flags);
4372 for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) {
4375 if (ethtool_register_table[i].offsets < 0) {
4376 hval = cas_phy_read(cp,
4377 -ethtool_register_table[i].offsets);
4380 val= readl(cp->regs+ethtool_register_table[i].offsets);
4382 memcpy(p, (u8 *)&val, sizeof(u32));
4384 spin_unlock_irqrestore(&cp->lock, flags);
4387 static struct net_device_stats *cas_get_stats(struct net_device *dev)
4389 struct cas *cp = netdev_priv(dev);
4390 struct net_device_stats *stats = cp->net_stats;
4391 unsigned long flags;
4395 /* we collate all of the stats into net_stats[N_TX_RING] */
4396 if (!cp->hw_running)
4397 return stats + N_TX_RINGS;
4399 /* collect outstanding stats */
4400 /* WTZ: the Cassini spec gives these as 16 bit counters but
4401 * stored in 32-bit words. Added a mask of 0xffff to be safe,
4402 * in case the chip somehow puts any garbage in the other bits.
4403 * Also, counter usage didn't seem to mach what Adrian did
4404 * in the parts of the code that set these quantities. Made
4407 spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags);
4408 stats[N_TX_RINGS].rx_crc_errors +=
4409 readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff;
4410 stats[N_TX_RINGS].rx_frame_errors +=
4411 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff;
4412 stats[N_TX_RINGS].rx_length_errors +=
4413 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff;
4415 tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) +
4416 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff);
4417 stats[N_TX_RINGS].tx_aborted_errors += tmp;
4418 stats[N_TX_RINGS].collisions +=
4419 tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff);
4421 stats[N_TX_RINGS].tx_aborted_errors +=
4422 readl(cp->regs + REG_MAC_COLL_EXCESS);
4423 stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) +
4424 readl(cp->regs + REG_MAC_COLL_LATE);
4426 cas_clear_mac_err(cp);
4428 /* saved bits that are unique to ring 0 */
4429 spin_lock(&cp->stat_lock[0]);
4430 stats[N_TX_RINGS].collisions += stats[0].collisions;
4431 stats[N_TX_RINGS].rx_over_errors += stats[0].rx_over_errors;
4432 stats[N_TX_RINGS].rx_frame_errors += stats[0].rx_frame_errors;
4433 stats[N_TX_RINGS].rx_fifo_errors += stats[0].rx_fifo_errors;
4434 stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors;
4435 stats[N_TX_RINGS].tx_fifo_errors += stats[0].tx_fifo_errors;
4436 spin_unlock(&cp->stat_lock[0]);
4438 for (i = 0; i < N_TX_RINGS; i++) {
4439 spin_lock(&cp->stat_lock[i]);
4440 stats[N_TX_RINGS].rx_length_errors +=
4441 stats[i].rx_length_errors;
4442 stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors;
4443 stats[N_TX_RINGS].rx_packets += stats[i].rx_packets;
4444 stats[N_TX_RINGS].tx_packets += stats[i].tx_packets;
4445 stats[N_TX_RINGS].rx_bytes += stats[i].rx_bytes;
4446 stats[N_TX_RINGS].tx_bytes += stats[i].tx_bytes;
4447 stats[N_TX_RINGS].rx_errors += stats[i].rx_errors;
4448 stats[N_TX_RINGS].tx_errors += stats[i].tx_errors;
4449 stats[N_TX_RINGS].rx_dropped += stats[i].rx_dropped;
4450 stats[N_TX_RINGS].tx_dropped += stats[i].tx_dropped;
4451 memset(stats + i, 0, sizeof(struct net_device_stats));
4452 spin_unlock(&cp->stat_lock[i]);
4454 spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags);
4455 return stats + N_TX_RINGS;
4459 static void cas_set_multicast(struct net_device *dev)
4461 struct cas *cp = netdev_priv(dev);
4462 u32 rxcfg, rxcfg_new;
4463 unsigned long flags;
4464 int limit = STOP_TRIES;
4466 if (!cp->hw_running)
4469 spin_lock_irqsave(&cp->lock, flags);
4470 rxcfg = readl(cp->regs + REG_MAC_RX_CFG);
4472 /* disable RX MAC and wait for completion */
4473 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4474 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) {
4480 /* disable hash filter and wait for completion */
4482 rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN);
4483 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4484 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) {
4490 /* program hash filters */
4491 cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp);
4493 writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
4494 spin_unlock_irqrestore(&cp->lock, flags);
4497 static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4499 struct cas *cp = netdev_priv(dev);
4500 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
4501 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
4502 strlcpy(info->bus_info, pci_name(cp->pdev), sizeof(info->bus_info));
4505 static int cas_get_link_ksettings(struct net_device *dev,
4506 struct ethtool_link_ksettings *cmd)
4508 struct cas *cp = netdev_priv(dev);
4510 int full_duplex, speed, pause;
4511 unsigned long flags;
4512 enum link_state linkstate = link_up;
4513 u32 supported, advertising;
4516 supported = SUPPORTED_Autoneg;
4517 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
4518 supported |= SUPPORTED_1000baseT_Full;
4519 advertising |= ADVERTISED_1000baseT_Full;
4522 /* Record PHY settings if HW is on. */
4523 spin_lock_irqsave(&cp->lock, flags);
4525 linkstate = cp->lstate;
4526 if (CAS_PHY_MII(cp->phy_type)) {
4527 cmd->base.port = PORT_MII;
4528 cmd->base.phy_address = cp->phy_addr;
4529 advertising |= ADVERTISED_TP | ADVERTISED_MII |
4530 ADVERTISED_10baseT_Half |
4531 ADVERTISED_10baseT_Full |
4532 ADVERTISED_100baseT_Half |
4533 ADVERTISED_100baseT_Full;
4536 (SUPPORTED_10baseT_Half |
4537 SUPPORTED_10baseT_Full |
4538 SUPPORTED_100baseT_Half |
4539 SUPPORTED_100baseT_Full |
4540 SUPPORTED_TP | SUPPORTED_MII);
4542 if (cp->hw_running) {
4543 cas_mif_poll(cp, 0);
4544 bmcr = cas_phy_read(cp, MII_BMCR);
4545 cas_read_mii_link_mode(cp, &full_duplex,
4547 cas_mif_poll(cp, 1);
4551 cmd->base.port = PORT_FIBRE;
4552 cmd->base.phy_address = 0;
4553 supported |= SUPPORTED_FIBRE;
4554 advertising |= ADVERTISED_FIBRE;
4556 if (cp->hw_running) {
4557 /* pcs uses the same bits as mii */
4558 bmcr = readl(cp->regs + REG_PCS_MII_CTRL);
4559 cas_read_pcs_link_mode(cp, &full_duplex,
4563 spin_unlock_irqrestore(&cp->lock, flags);
4565 if (bmcr & BMCR_ANENABLE) {
4566 advertising |= ADVERTISED_Autoneg;
4567 cmd->base.autoneg = AUTONEG_ENABLE;
4568 cmd->base.speed = ((speed == 10) ?
4571 SPEED_1000 : SPEED_100));
4572 cmd->base.duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
4574 cmd->base.autoneg = AUTONEG_DISABLE;
4575 cmd->base.speed = ((bmcr & CAS_BMCR_SPEED1000) ?
4577 ((bmcr & BMCR_SPEED100) ?
4578 SPEED_100 : SPEED_10));
4579 cmd->base.duplex = (bmcr & BMCR_FULLDPLX) ?
4580 DUPLEX_FULL : DUPLEX_HALF;
4582 if (linkstate != link_up) {
4583 /* Force these to "unknown" if the link is not up and
4584 * autonogotiation in enabled. We can set the link
4585 * speed to 0, but not cmd->duplex,
4586 * because its legal values are 0 and 1. Ethtool will
4587 * print the value reported in parentheses after the
4588 * word "Unknown" for unrecognized values.
4590 * If in forced mode, we report the speed and duplex
4591 * settings that we configured.
4593 if (cp->link_cntl & BMCR_ANENABLE) {
4594 cmd->base.speed = 0;
4595 cmd->base.duplex = 0xff;
4597 cmd->base.speed = SPEED_10;
4598 if (cp->link_cntl & BMCR_SPEED100) {
4599 cmd->base.speed = SPEED_100;
4600 } else if (cp->link_cntl & CAS_BMCR_SPEED1000) {
4601 cmd->base.speed = SPEED_1000;
4603 cmd->base.duplex = (cp->link_cntl & BMCR_FULLDPLX) ?
4604 DUPLEX_FULL : DUPLEX_HALF;
4608 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
4610 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
4616 static int cas_set_link_ksettings(struct net_device *dev,
4617 const struct ethtool_link_ksettings *cmd)
4619 struct cas *cp = netdev_priv(dev);
4620 unsigned long flags;
4621 u32 speed = cmd->base.speed;
4623 /* Verify the settings we care about. */
4624 if (cmd->base.autoneg != AUTONEG_ENABLE &&
4625 cmd->base.autoneg != AUTONEG_DISABLE)
4628 if (cmd->base.autoneg == AUTONEG_DISABLE &&
4629 ((speed != SPEED_1000 &&
4630 speed != SPEED_100 &&
4631 speed != SPEED_10) ||
4632 (cmd->base.duplex != DUPLEX_HALF &&
4633 cmd->base.duplex != DUPLEX_FULL)))
4636 /* Apply settings and restart link process. */
4637 spin_lock_irqsave(&cp->lock, flags);
4638 cas_begin_auto_negotiation(cp, cmd);
4639 spin_unlock_irqrestore(&cp->lock, flags);
4643 static int cas_nway_reset(struct net_device *dev)
4645 struct cas *cp = netdev_priv(dev);
4646 unsigned long flags;
4648 if ((cp->link_cntl & BMCR_ANENABLE) == 0)
4651 /* Restart link process. */
4652 spin_lock_irqsave(&cp->lock, flags);
4653 cas_begin_auto_negotiation(cp, NULL);
4654 spin_unlock_irqrestore(&cp->lock, flags);
4659 static u32 cas_get_link(struct net_device *dev)
4661 struct cas *cp = netdev_priv(dev);
4662 return cp->lstate == link_up;
4665 static u32 cas_get_msglevel(struct net_device *dev)
4667 struct cas *cp = netdev_priv(dev);
4668 return cp->msg_enable;
4671 static void cas_set_msglevel(struct net_device *dev, u32 value)
4673 struct cas *cp = netdev_priv(dev);
4674 cp->msg_enable = value;
4677 static int cas_get_regs_len(struct net_device *dev)
4679 struct cas *cp = netdev_priv(dev);
4680 return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS;
4683 static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4686 struct cas *cp = netdev_priv(dev);
4688 /* cas_read_regs handles locks (cp->lock). */
4689 cas_read_regs(cp, p, regs->len / sizeof(u32));
4692 static int cas_get_sset_count(struct net_device *dev, int sset)
4696 return CAS_NUM_STAT_KEYS;
4702 static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4704 memcpy(data, ðtool_cassini_statnames,
4705 CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN);
4708 static void cas_get_ethtool_stats(struct net_device *dev,
4709 struct ethtool_stats *estats, u64 *data)
4711 struct cas *cp = netdev_priv(dev);
4712 struct net_device_stats *stats = cas_get_stats(cp->dev);
4714 data[i++] = stats->collisions;
4715 data[i++] = stats->rx_bytes;
4716 data[i++] = stats->rx_crc_errors;
4717 data[i++] = stats->rx_dropped;
4718 data[i++] = stats->rx_errors;
4719 data[i++] = stats->rx_fifo_errors;
4720 data[i++] = stats->rx_frame_errors;
4721 data[i++] = stats->rx_length_errors;
4722 data[i++] = stats->rx_over_errors;
4723 data[i++] = stats->rx_packets;
4724 data[i++] = stats->tx_aborted_errors;
4725 data[i++] = stats->tx_bytes;
4726 data[i++] = stats->tx_dropped;
4727 data[i++] = stats->tx_errors;
4728 data[i++] = stats->tx_fifo_errors;
4729 data[i++] = stats->tx_packets;
4730 BUG_ON(i != CAS_NUM_STAT_KEYS);
4733 static const struct ethtool_ops cas_ethtool_ops = {
4734 .get_drvinfo = cas_get_drvinfo,
4735 .nway_reset = cas_nway_reset,
4736 .get_link = cas_get_link,
4737 .get_msglevel = cas_get_msglevel,
4738 .set_msglevel = cas_set_msglevel,
4739 .get_regs_len = cas_get_regs_len,
4740 .get_regs = cas_get_regs,
4741 .get_sset_count = cas_get_sset_count,
4742 .get_strings = cas_get_strings,
4743 .get_ethtool_stats = cas_get_ethtool_stats,
4744 .get_link_ksettings = cas_get_link_ksettings,
4745 .set_link_ksettings = cas_set_link_ksettings,
4748 static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4750 struct cas *cp = netdev_priv(dev);
4751 struct mii_ioctl_data *data = if_mii(ifr);
4752 unsigned long flags;
4753 int rc = -EOPNOTSUPP;
4755 /* Hold the PM mutex while doing ioctl's or we may collide
4756 * with open/close and power management and oops.
4758 mutex_lock(&cp->pm_mutex);
4760 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
4761 data->phy_id = cp->phy_addr;
4764 case SIOCGMIIREG: /* Read MII PHY register. */
4765 spin_lock_irqsave(&cp->lock, flags);
4766 cas_mif_poll(cp, 0);
4767 data->val_out = cas_phy_read(cp, data->reg_num & 0x1f);
4768 cas_mif_poll(cp, 1);
4769 spin_unlock_irqrestore(&cp->lock, flags);
4773 case SIOCSMIIREG: /* Write MII PHY register. */
4774 spin_lock_irqsave(&cp->lock, flags);
4775 cas_mif_poll(cp, 0);
4776 rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in);
4777 cas_mif_poll(cp, 1);
4778 spin_unlock_irqrestore(&cp->lock, flags);
4784 mutex_unlock(&cp->pm_mutex);
4788 /* When this chip sits underneath an Intel 31154 bridge, it is the
4789 * only subordinate device and we can tweak the bridge settings to
4790 * reflect that fact.
4792 static void cas_program_bridge(struct pci_dev *cas_pdev)
4794 struct pci_dev *pdev = cas_pdev->bus->self;
4800 if (pdev->vendor != 0x8086 || pdev->device != 0x537c)
4803 /* Clear bit 10 (Bus Parking Control) in the Secondary
4804 * Arbiter Control/Status Register which lives at offset
4805 * 0x41. Using a 32-bit word read/modify/write at 0x40
4806 * is much simpler so that's how we do this.
4808 pci_read_config_dword(pdev, 0x40, &val);
4810 pci_write_config_dword(pdev, 0x40, val);
4812 /* Max out the Multi-Transaction Timer settings since
4813 * Cassini is the only device present.
4815 * The register is 16-bit and lives at 0x50. When the
4816 * settings are enabled, it extends the GRANT# signal
4817 * for a requestor after a transaction is complete. This
4818 * allows the next request to run without first needing
4819 * to negotiate the GRANT# signal back.
4821 * Bits 12:10 define the grant duration:
4829 * All other values are illegal.
4831 * Bits 09:00 define which REQ/GNT signal pairs get the
4832 * GRANT# signal treatment. We set them all.
4834 pci_write_config_word(pdev, 0x50, (5 << 10) | 0x3ff);
4836 /* The Read Prefecth Policy register is 16-bit and sits at
4837 * offset 0x52. It enables a "smart" pre-fetch policy. We
4838 * enable it and max out all of the settings since only one
4839 * device is sitting underneath and thus bandwidth sharing is
4842 * The register has several 3 bit fields, which indicates a
4843 * multiplier applied to the base amount of prefetching the
4844 * chip would do. These fields are at:
4846 * 15:13 --- ReRead Primary Bus
4847 * 12:10 --- FirstRead Primary Bus
4848 * 09:07 --- ReRead Secondary Bus
4849 * 06:04 --- FirstRead Secondary Bus
4851 * Bits 03:00 control which REQ/GNT pairs the prefetch settings
4852 * get enabled on. Bit 3 is a grouped enabler which controls
4853 * all of the REQ/GNT pairs from [8:3]. Bits 2 to 0 control
4854 * the individual REQ/GNT pairs [2:0].
4856 pci_write_config_word(pdev, 0x52,
4863 /* Force cacheline size to 0x8 */
4864 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4866 /* Force latency timer to maximum setting so Cassini can
4867 * sit on the bus as long as it likes.
4869 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xff);
4872 static const struct net_device_ops cas_netdev_ops = {
4873 .ndo_open = cas_open,
4874 .ndo_stop = cas_close,
4875 .ndo_start_xmit = cas_start_xmit,
4876 .ndo_get_stats = cas_get_stats,
4877 .ndo_set_rx_mode = cas_set_multicast,
4878 .ndo_do_ioctl = cas_ioctl,
4879 .ndo_tx_timeout = cas_tx_timeout,
4880 .ndo_change_mtu = cas_change_mtu,
4881 .ndo_set_mac_address = eth_mac_addr,
4882 .ndo_validate_addr = eth_validate_addr,
4883 #ifdef CONFIG_NET_POLL_CONTROLLER
4884 .ndo_poll_controller = cas_netpoll,
4888 static int cas_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4890 static int cas_version_printed = 0;
4891 unsigned long casreg_len;
4892 struct net_device *dev;
4894 int i, err, pci_using_dac;
4896 u8 orig_cacheline_size = 0, cas_cacheline_size = 0;
4898 if (cas_version_printed++ == 0)
4899 pr_info("%s", version);
4901 err = pci_enable_device(pdev);
4903 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
4907 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4908 dev_err(&pdev->dev, "Cannot find proper PCI device "
4909 "base address, aborting\n");
4911 goto err_out_disable_pdev;
4914 dev = alloc_etherdev(sizeof(*cp));
4917 goto err_out_disable_pdev;
4919 SET_NETDEV_DEV(dev, &pdev->dev);
4921 err = pci_request_regions(pdev, dev->name);
4923 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
4924 goto err_out_free_netdev;
4926 pci_set_master(pdev);
4928 /* we must always turn on parity response or else parity
4929 * doesn't get generated properly. disable SERR/PERR as well.
4930 * in addition, we want to turn MWI on.
4932 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4933 pci_cmd &= ~PCI_COMMAND_SERR;
4934 pci_cmd |= PCI_COMMAND_PARITY;
4935 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4936 if (pci_try_set_mwi(pdev))
4937 pr_warn("Could not enable MWI for %s\n", pci_name(pdev));
4939 cas_program_bridge(pdev);
4942 * On some architectures, the default cache line size set
4943 * by pci_try_set_mwi reduces perforamnce. We have to increase
4944 * it for this case. To start, we'll print some configuration
4948 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
4949 &orig_cacheline_size);
4950 if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) {
4951 cas_cacheline_size =
4952 (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ?
4953 CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES;
4954 if (pci_write_config_byte(pdev,
4955 PCI_CACHE_LINE_SIZE,
4956 cas_cacheline_size)) {
4957 dev_err(&pdev->dev, "Could not set PCI cache "
4959 goto err_out_free_res;
4965 /* Configure DMA attributes. */
4966 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
4968 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
4970 dev_err(&pdev->dev, "Unable to obtain 64-bit DMA "
4971 "for consistent allocations\n");
4972 goto err_out_free_res;
4976 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
4978 dev_err(&pdev->dev, "No usable DMA configuration, "
4980 goto err_out_free_res;
4985 casreg_len = pci_resource_len(pdev, 0);
4987 cp = netdev_priv(dev);
4990 /* A value of 0 indicates we never explicitly set it */
4991 cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0;
4994 cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE :
4997 #if defined(CONFIG_SPARC)
4998 cp->of_node = pci_device_to_OF_node(pdev);
5001 cp->link_transition = LINK_TRANSITION_UNKNOWN;
5002 cp->link_transition_jiffies_valid = 0;
5004 spin_lock_init(&cp->lock);
5005 spin_lock_init(&cp->rx_inuse_lock);
5006 spin_lock_init(&cp->rx_spare_lock);
5007 for (i = 0; i < N_TX_RINGS; i++) {
5008 spin_lock_init(&cp->stat_lock[i]);
5009 spin_lock_init(&cp->tx_lock[i]);
5011 spin_lock_init(&cp->stat_lock[N_TX_RINGS]);
5012 mutex_init(&cp->pm_mutex);
5014 timer_setup(&cp->link_timer, cas_link_timer, 0);
5017 /* Just in case the implementation of atomic operations
5018 * change so that an explicit initialization is necessary.
5020 atomic_set(&cp->reset_task_pending, 0);
5021 atomic_set(&cp->reset_task_pending_all, 0);
5022 atomic_set(&cp->reset_task_pending_spare, 0);
5023 atomic_set(&cp->reset_task_pending_mtu, 0);
5025 INIT_WORK(&cp->reset_task, cas_reset_task);
5027 /* Default link parameters */
5028 if (link_mode >= 0 && link_mode < 6)
5029 cp->link_cntl = link_modes[link_mode];
5031 cp->link_cntl = BMCR_ANENABLE;
5032 cp->lstate = link_down;
5033 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
5034 netif_carrier_off(cp->dev);
5035 cp->timer_ticks = 0;
5037 /* give us access to cassini registers */
5038 cp->regs = pci_iomap(pdev, 0, casreg_len);
5040 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5041 goto err_out_free_res;
5043 cp->casreg_len = casreg_len;
5045 pci_save_state(pdev);
5046 cas_check_pci_invariants(cp);
5049 if (cas_check_invariants(cp))
5050 goto err_out_iounmap;
5051 if (cp->cas_flags & CAS_FLAG_SATURN)
5052 cas_saturn_firmware_init(cp);
5055 dma_alloc_coherent(&pdev->dev, sizeof(struct cas_init_block),
5056 &cp->block_dvma, GFP_KERNEL);
5057 if (!cp->init_block) {
5058 dev_err(&pdev->dev, "Cannot allocate init block, aborting\n");
5059 goto err_out_iounmap;
5062 for (i = 0; i < N_TX_RINGS; i++)
5063 cp->init_txds[i] = cp->init_block->txds[i];
5065 for (i = 0; i < N_RX_DESC_RINGS; i++)
5066 cp->init_rxds[i] = cp->init_block->rxds[i];
5068 for (i = 0; i < N_RX_COMP_RINGS; i++)
5069 cp->init_rxcs[i] = cp->init_block->rxcs[i];
5071 for (i = 0; i < N_RX_FLOWS; i++)
5072 skb_queue_head_init(&cp->rx_flows[i]);
5074 dev->netdev_ops = &cas_netdev_ops;
5075 dev->ethtool_ops = &cas_ethtool_ops;
5076 dev->watchdog_timeo = CAS_TX_TIMEOUT;
5079 netif_napi_add(dev, &cp->napi, cas_poll, 64);
5081 dev->irq = pdev->irq;
5084 /* Cassini features. */
5085 if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0)
5086 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5089 dev->features |= NETIF_F_HIGHDMA;
5091 /* MTU range: 60 - varies or 9000 */
5092 dev->min_mtu = CAS_MIN_MTU;
5093 dev->max_mtu = CAS_MAX_MTU;
5095 if (register_netdev(dev)) {
5096 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
5097 goto err_out_free_consistent;
5100 i = readl(cp->regs + REG_BIM_CFG);
5101 netdev_info(dev, "Sun Cassini%s (%sbit/%sMHz PCI/%s) Ethernet[%d] %pM\n",
5102 (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "",
5103 (i & BIM_CFG_32BIT) ? "32" : "64",
5104 (i & BIM_CFG_66MHZ) ? "66" : "33",
5105 (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq,
5108 pci_set_drvdata(pdev, dev);
5110 cas_entropy_reset(cp);
5112 cas_begin_auto_negotiation(cp, NULL);
5115 err_out_free_consistent:
5116 dma_free_coherent(&pdev->dev, sizeof(struct cas_init_block),
5117 cp->init_block, cp->block_dvma);
5120 mutex_lock(&cp->pm_mutex);
5123 mutex_unlock(&cp->pm_mutex);
5125 pci_iounmap(pdev, cp->regs);
5129 pci_release_regions(pdev);
5131 /* Try to restore it in case the error occurred after we
5134 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);
5136 err_out_free_netdev:
5139 err_out_disable_pdev:
5140 pci_disable_device(pdev);
5144 static void cas_remove_one(struct pci_dev *pdev)
5146 struct net_device *dev = pci_get_drvdata(pdev);
5151 cp = netdev_priv(dev);
5152 unregister_netdev(dev);
5156 mutex_lock(&cp->pm_mutex);
5157 cancel_work_sync(&cp->reset_task);
5160 mutex_unlock(&cp->pm_mutex);
5163 if (cp->orig_cacheline_size) {
5164 /* Restore the cache line size if we had modified
5167 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
5168 cp->orig_cacheline_size);
5171 dma_free_coherent(&pdev->dev, sizeof(struct cas_init_block),
5172 cp->init_block, cp->block_dvma);
5173 pci_iounmap(pdev, cp->regs);
5175 pci_release_regions(pdev);
5176 pci_disable_device(pdev);
5179 static int __maybe_unused cas_suspend(struct device *dev_d)
5181 struct net_device *dev = dev_get_drvdata(dev_d);
5182 struct cas *cp = netdev_priv(dev);
5183 unsigned long flags;
5185 mutex_lock(&cp->pm_mutex);
5187 /* If the driver is opened, we stop the DMA */
5189 netif_device_detach(dev);
5191 cas_lock_all_save(cp, flags);
5193 /* We can set the second arg of cas_reset to 0
5194 * because on resume, we'll call cas_init_hw with
5195 * its second arg set so that autonegotiation is
5199 cas_clean_rings(cp);
5200 cas_unlock_all_restore(cp, flags);
5205 mutex_unlock(&cp->pm_mutex);
5210 static int __maybe_unused cas_resume(struct device *dev_d)
5212 struct net_device *dev = dev_get_drvdata(dev_d);
5213 struct cas *cp = netdev_priv(dev);
5215 netdev_info(dev, "resuming\n");
5217 mutex_lock(&cp->pm_mutex);
5220 unsigned long flags;
5221 cas_lock_all_save(cp, flags);
5224 cas_clean_rings(cp);
5226 cas_unlock_all_restore(cp, flags);
5228 netif_device_attach(dev);
5230 mutex_unlock(&cp->pm_mutex);
5234 static SIMPLE_DEV_PM_OPS(cas_pm_ops, cas_suspend, cas_resume);
5236 static struct pci_driver cas_driver = {
5237 .name = DRV_MODULE_NAME,
5238 .id_table = cas_pci_tbl,
5239 .probe = cas_init_one,
5240 .remove = cas_remove_one,
5241 .driver.pm = &cas_pm_ops,
5244 static int __init cas_init(void)
5246 if (linkdown_timeout > 0)
5247 link_transition_timeout = linkdown_timeout * HZ;
5249 link_transition_timeout = 0;
5251 return pci_register_driver(&cas_driver);
5254 static void __exit cas_cleanup(void)
5256 pci_unregister_driver(&cas_driver);
5259 module_init(cas_init);
5260 module_exit(cas_cleanup);