drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #include <linux/pinctrl/consumer.h>
  47 #ifdef CONFIG_DEBUG_FS
  48 #include <linux/debugfs.h>
  49 #include <linux/seq_file.h>
  50 #endif /* CONFIG_DEBUG_FS */
  51 #include <linux/net_tstamp.h>
  52 #include "stmmac_ptp.h"
  53 #include "stmmac.h"
  54 #include <linux/reset.h>
  55 #include <linux/of_mdio.h>
  56
  57 #define STMMAC_ALIGN(x)         __ALIGN_KERNEL(x, SMP_CACHE_BYTES)
  58
  59 /* Module parameters */
  60 #define TX_TIMEO        5000
  61 static int watchdog = TX_TIMEO;
  62 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  63 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  64
  65 static int debug = -1;
  66 module_param(debug, int, S_IRUGO | S_IWUSR);
  67 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  68
  69 static int phyaddr = -1;
  70 module_param(phyaddr, int, S_IRUGO);
  71 MODULE_PARM_DESC(phyaddr, "Physical device address");
  72
  73 #define DMA_TX_SIZE 256
  74 static int dma_txsize = DMA_TX_SIZE;
  75 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
  76 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
  77
  78 #define DMA_RX_SIZE 256
  79 static int dma_rxsize = DMA_RX_SIZE;
  80 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
  81 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
  82
  83 static int flow_ctrl = FLOW_OFF;
  84 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
  85 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  86
  87 static int pause = PAUSE_TIME;
  88 module_param(pause, int, S_IRUGO | S_IWUSR);
  89 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  90
  91 #define TC_DEFAULT 64
  92 static int tc = TC_DEFAULT;
  93 module_param(tc, int, S_IRUGO | S_IWUSR);
  94 MODULE_PARM_DESC(tc, "DMA threshold control value");
  95
  96 #define DEFAULT_BUFSIZE 1536
  97 static int buf_sz = DEFAULT_BUFSIZE;
  98 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
  99 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 100
 101 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 102                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 103                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 104
 105 #define STMMAC_DEFAULT_LPI_TIMER        1000
 106 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 107 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 108 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 109 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
 110
 111 /* By default the driver will use the ring mode to manage tx and rx descriptors
 112  * but passing this value so user can force to use the chain instead of the ring
 113  */
 114 static unsigned int chain_mode;
 115 module_param(chain_mode, int, S_IRUGO);
 116 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 117
 118 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 119
 120 #ifdef CONFIG_DEBUG_FS
 121 static int stmmac_init_fs(struct net_device *dev);
 122 static void stmmac_exit_fs(struct net_device *dev);
 123 #endif
 124
 125 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 126
 127 /**
 128  * stmmac_verify_args - verify the driver parameters.
 129  * Description: it checks the driver parameters and set a default in case of
 130  * errors.
 131  */
 132 static void stmmac_verify_args(void)
 133 {
 134         if (unlikely(watchdog < 0))
 135                 watchdog = TX_TIMEO;
 136         if (unlikely(dma_rxsize < 0))
 137                 dma_rxsize = DMA_RX_SIZE;
 138         if (unlikely(dma_txsize < 0))
 139                 dma_txsize = DMA_TX_SIZE;
 140         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 141                 buf_sz = DEFAULT_BUFSIZE;
 142         if (unlikely(flow_ctrl > 1))
 143                 flow_ctrl = FLOW_AUTO;
 144         else if (likely(flow_ctrl < 0))
 145                 flow_ctrl = FLOW_OFF;
 146         if (unlikely((pause < 0) || (pause > 0xffff)))
 147                 pause = PAUSE_TIME;
 148         if (eee_timer < 0)
 149                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 150 }
 151
 152 /**
 153  * stmmac_clk_csr_set - dynamically set the MDC clock
 154  * @priv: driver private structure
 155  * Description: this is to dynamically set the MDC clock according to the csr
 156  * clock input.
 157  * Note:
 158  *      If a specific clk_csr value is passed from the platform
 159  *      this means that the CSR Clock Range selection cannot be
 160  *      changed at run-time and it is fixed (as reported in the driver
 161  *      documentation). Viceversa the driver will try to set the MDC
 162  *      clock dynamically according to the actual clock input.
 163  */
 164 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 165 {
 166         u32 clk_rate;
 167
 168         clk_rate = clk_get_rate(priv->stmmac_clk);
 169
 170         /* Platform provided default clk_csr would be assumed valid
 171          * for all other cases except for the below mentioned ones.
 172          * For values higher than the IEEE 802.3 specified frequency
 173          * we can not estimate the proper divider as it is not known
 174          * the frequency of clk_csr_i. So we do not change the default
 175          * divider.
 176          */
 177         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 178                 if (clk_rate < CSR_F_35M)
 179                         priv->clk_csr = STMMAC_CSR_20_35M;
 180                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 181                         priv->clk_csr = STMMAC_CSR_35_60M;
 182                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 183                         priv->clk_csr = STMMAC_CSR_60_100M;
 184                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 185                         priv->clk_csr = STMMAC_CSR_100_150M;
 186                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 187                         priv->clk_csr = STMMAC_CSR_150_250M;
 188                 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
 189                         priv->clk_csr = STMMAC_CSR_250_300M;
 190         }
 191 }
 192
 193 static void print_pkt(unsigned char *buf, int len)
 194 {
 195         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 196         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 197 }
 198
 199 /* minimum number of free TX descriptors required to wake up TX process */
 200 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 201
 202 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 203 {
 204         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 205 }
 206
 207 /**
 208  * stmmac_hw_fix_mac_speed - callback for speed selection
 209  * @priv: driver private structure
 210  * Description: on some platforms (e.g. ST), some HW system configuraton
 211  * registers have to be set according to the link speed negotiated.
 212  */
 213 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 214 {
 215         struct phy_device *phydev = priv->phydev;
 216
 217         if (likely(priv->plat->fix_mac_speed))
 218                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
 219 }
 220
 221 /**
 222  * stmmac_enable_eee_mode - check and enter in LPI mode
 223  * @priv: driver private structure
 224  * Description: this function is to verify and enter in LPI mode in case of
 225  * EEE.
 226  */
 227 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 228 {
 229         /* Check and enter in LPI mode */
 230         if ((priv->dirty_tx == priv->cur_tx) &&
 231             (priv->tx_path_in_lpi_mode == false))
 232                 priv->hw->mac->set_eee_mode(priv->hw);
 233 }
 234
 235 /**
 236  * stmmac_disable_eee_mode - disable and exit from LPI mode
 237  * @priv: driver private structure
 238  * Description: this function is to exit and disable EEE in case of
 239  * LPI state is true. This is called by the xmit.
 240  */
 241 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 242 {
 243         priv->hw->mac->reset_eee_mode(priv->hw);
 244         del_timer_sync(&priv->eee_ctrl_timer);
 245         priv->tx_path_in_lpi_mode = false;
 246 }
 247
 248 /**
 249  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 250  * @arg : data hook
 251  * Description:
 252  *  if there is no data transfer and if we are not in LPI state,
 253  *  then MAC Transmitter can be moved to LPI state.
 254  */
 255 static void stmmac_eee_ctrl_timer(unsigned long arg)
 256 {
 257         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 258
 259         stmmac_enable_eee_mode(priv);
 260         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 261 }
 262
 263 /**
 264  * stmmac_eee_init - init EEE
 265  * @priv: driver private structure
 266  * Description:
 267  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 268  *  can also manage EEE, this function enable the LPI state and start related
 269  *  timer.
 270  */
 271 bool stmmac_eee_init(struct stmmac_priv *priv)
 272 {
 273         char *phy_bus_name = priv->plat->phy_bus_name;
 274         unsigned long flags;
 275         int interface = priv->plat->interface;
 276         bool ret = false;
 277
 278         if ((interface != PHY_INTERFACE_MODE_MII) &&
 279             (interface != PHY_INTERFACE_MODE_GMII) &&
 280             !phy_interface_mode_is_rgmii(interface))
 281                 goto out;
 282
 283         /* Using PCS we cannot dial with the phy registers at this stage
 284          * so we do not support extra feature like EEE.
 285          */
 286         if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
 287             (priv->pcs == STMMAC_PCS_RTBI))
 288                 goto out;
 289
 290         /* Never init EEE in case of a switch is attached */
 291         if (phy_bus_name && (!strcmp(phy_bus_name, "fixed")))
 292                 goto out;
 293
 294         /* MAC core supports the EEE feature. */
 295         if (priv->dma_cap.eee) {
 296                 int tx_lpi_timer = priv->tx_lpi_timer;
 297
 298                 /* Check if the PHY supports EEE */
 299                 if (phy_init_eee(priv->phydev, 1)) {
 300                         /* To manage at run-time if the EEE cannot be supported
 301                          * anymore (for example because the lp caps have been
 302                          * changed).
 303                          * In that case the driver disable own timers.
 304                          */
 305                         spin_lock_irqsave(&priv->lock, flags);
 306                         if (priv->eee_active) {
 307                                 pr_debug("stmmac: disable EEE\n");
 308                                 del_timer_sync(&priv->eee_ctrl_timer);
 309                                 priv->hw->mac->set_eee_timer(priv->hw, 0,
 310                                                              tx_lpi_timer);
 311                         }
 312                         priv->eee_active = 0;
 313                         spin_unlock_irqrestore(&priv->lock, flags);
 314                         goto out;
 315                 }
 316                 /* Activate the EEE and start timers */
 317                 spin_lock_irqsave(&priv->lock, flags);
 318                 if (!priv->eee_active) {
 319                         priv->eee_active = 1;
 320                         setup_timer(&priv->eee_ctrl_timer,
 321                                     stmmac_eee_ctrl_timer,
 322                                     (unsigned long)priv);
 323                         mod_timer(&priv->eee_ctrl_timer,
 324                                   STMMAC_LPI_T(eee_timer));
 325
 326                         priv->hw->mac->set_eee_timer(priv->hw,
 327                                                      STMMAC_DEFAULT_LIT_LS,
 328                                                      tx_lpi_timer);
 329                 }
 330                 /* Set HW EEE according to the speed */
 331                 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
 332
 333                 ret = true;
 334                 spin_unlock_irqrestore(&priv->lock, flags);
 335
 336                 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
 337         }
 338 out:
 339         return ret;
 340 }
 341
 342 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 343  * @priv: driver private structure
 344  * @entry : descriptor index to be used.
 345  * @skb : the socket buffer
 346  * Description :
 347  * This function will read timestamp from the descriptor & pass it to stack.
 348  * and also perform some sanity checks.
 349  */
 350 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 351                                    unsigned int entry, struct sk_buff *skb)
 352 {
 353         struct skb_shared_hwtstamps shhwtstamp;
 354         u64 ns;
 355         void *desc = NULL;
 356
 357         if (!priv->hwts_tx_en)
 358                 return;
 359
 360         /* exit if skb doesn't support hw tstamp */
 361         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 362                 return;
 363
 364         if (priv->adv_ts)
 365                 desc = (priv->dma_etx + entry);
 366         else
 367                 desc = (priv->dma_tx + entry);
 368
 369         /* check tx tstamp status */
 370         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
 371                 return;
 372
 373         /* get the valid tstamp */
 374         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 375
 376         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 377         shhwtstamp.hwtstamp = ns_to_ktime(ns);
 378         /* pass tstamp to stack */
 379         skb_tstamp_tx(skb, &shhwtstamp);
 380
 381         return;
 382 }
 383
 384 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 385  * @priv: driver private structure
 386  * @entry : descriptor index to be used.
 387  * @skb : the socket buffer
 388  * Description :
 389  * This function will read received packet's timestamp from the descriptor
 390  * and pass it to stack. It also perform some sanity checks.
 391  */
 392 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
 393                                    unsigned int entry, struct sk_buff *skb)
 394 {
 395         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 396         u64 ns;
 397         void *desc = NULL;
 398
 399         if (!priv->hwts_rx_en)
 400                 return;
 401
 402         if (priv->adv_ts)
 403                 desc = (priv->dma_erx + entry);
 404         else
 405                 desc = (priv->dma_rx + entry);
 406
 407         /* exit if rx tstamp is not valid */
 408         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
 409                 return;
 410
 411         /* get valid tstamp */
 412         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 413         shhwtstamp = skb_hwtstamps(skb);
 414         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 415         shhwtstamp->hwtstamp = ns_to_ktime(ns);
 416 }
 417
 418 /**
 419  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 420  *  @dev: device pointer.
 421  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 422  *  a proprietary structure used to pass information to the driver.
 423  *  Description:
 424  *  This function configures the MAC to enable/disable both outgoing(TX)
 425  *  and incoming(RX) packets time stamping based on user input.
 426  *  Return Value:
 427  *  0 on success and an appropriate -ve integer on failure.
 428  */
 429 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
 430 {
 431         struct stmmac_priv *priv = netdev_priv(dev);
 432         struct hwtstamp_config config;
 433         struct timespec64 now;
 434         u64 temp = 0;
 435         u32 ptp_v2 = 0;
 436         u32 tstamp_all = 0;
 437         u32 ptp_over_ipv4_udp = 0;
 438         u32 ptp_over_ipv6_udp = 0;
 439         u32 ptp_over_ethernet = 0;
 440         u32 snap_type_sel = 0;
 441         u32 ts_master_en = 0;
 442         u32 ts_event_en = 0;
 443         u32 value = 0;
 444
 445         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 446                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 447                 priv->hwts_tx_en = 0;
 448                 priv->hwts_rx_en = 0;
 449
 450                 return -EOPNOTSUPP;
 451         }
 452
 453         if (copy_from_user(&config, ifr->ifr_data,
 454                            sizeof(struct hwtstamp_config)))
 455                 return -EFAULT;
 456
 457         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 458                  __func__, config.flags, config.tx_type, config.rx_filter);
 459
 460         /* reserved for future extensions */
 461         if (config.flags)
 462                 return -EINVAL;
 463
 464         if (config.tx_type != HWTSTAMP_TX_OFF &&
 465             config.tx_type != HWTSTAMP_TX_ON)
 466                 return -ERANGE;
 467
 468         if (priv->adv_ts) {
 469                 switch (config.rx_filter) {
 470                 case HWTSTAMP_FILTER_NONE:
 471                         /* time stamp no incoming packet at all */
 472                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 473                         break;
 474
 475                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 476                         /* PTP v1, UDP, any kind of event packet */
 477                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 478                         /* take time stamp for all event messages */
 479                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 480
 481                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 482                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 483                         break;
 484
 485                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 486                         /* PTP v1, UDP, Sync packet */
 487                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 488                         /* take time stamp for SYNC messages only */
 489                         ts_event_en = PTP_TCR_TSEVNTENA;
 490
 491                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 492                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 493                         break;
 494
 495                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 496                         /* PTP v1, UDP, Delay_req packet */
 497                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 498                         /* take time stamp for Delay_Req messages only */
 499                         ts_master_en = PTP_TCR_TSMSTRENA;
 500                         ts_event_en = PTP_TCR_TSEVNTENA;
 501
 502                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 503                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 504                         break;
 505
 506                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 507                         /* PTP v2, UDP, any kind of event packet */
 508                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 509                         ptp_v2 = PTP_TCR_TSVER2ENA;
 510                         /* take time stamp for all event messages */
 511                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 512
 513                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 514                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 515                         break;
 516
 517                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 518                         /* PTP v2, UDP, Sync packet */
 519                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 520                         ptp_v2 = PTP_TCR_TSVER2ENA;
 521                         /* take time stamp for SYNC messages only */
 522                         ts_event_en = PTP_TCR_TSEVNTENA;
 523
 524                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 525                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 526                         break;
 527
 528                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 529                         /* PTP v2, UDP, Delay_req packet */
 530                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 531                         ptp_v2 = PTP_TCR_TSVER2ENA;
 532                         /* take time stamp for Delay_Req messages only */
 533                         ts_master_en = PTP_TCR_TSMSTRENA;
 534                         ts_event_en = PTP_TCR_TSEVNTENA;
 535
 536                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 537                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 538                         break;
 539
 540                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 541                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 542                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 543                         ptp_v2 = PTP_TCR_TSVER2ENA;
 544                         /* take time stamp for all event messages */
 545                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 546
 547                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 548                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 549                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 550                         break;
 551
 552                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 553                         /* PTP v2/802.AS1, any layer, Sync packet */
 554                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 555                         ptp_v2 = PTP_TCR_TSVER2ENA;
 556                         /* take time stamp for SYNC messages only */
 557                         ts_event_en = PTP_TCR_TSEVNTENA;
 558
 559                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 560                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 561                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 562                         break;
 563
 564                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 565                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 566                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 567                         ptp_v2 = PTP_TCR_TSVER2ENA;
 568                         /* take time stamp for Delay_Req messages only */
 569                         ts_master_en = PTP_TCR_TSMSTRENA;
 570                         ts_event_en = PTP_TCR_TSEVNTENA;
 571
 572                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 573                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 574                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 575                         break;
 576
 577                 case HWTSTAMP_FILTER_ALL:
 578                         /* time stamp any incoming packet */
 579                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 580                         tstamp_all = PTP_TCR_TSENALL;
 581                         break;
 582
 583                 default:
 584                         return -ERANGE;
 585                 }
 586         } else {
 587                 switch (config.rx_filter) {
 588                 case HWTSTAMP_FILTER_NONE:
 589                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 590                         break;
 591                 default:
 592                         /* PTP v1, UDP, any kind of event packet */
 593                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 594                         break;
 595                 }
 596         }
 597         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 598         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 599
 600         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 601                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
 602         else {
 603                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 604                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 605                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 606                          ts_master_en | snap_type_sel);
 607
 608                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
 609
 610                 /* program Sub Second Increment reg */
 611                 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
 612
 613                 /* calculate default added value:
 614                  * formula is :
 615                  * addend = (2^32)/freq_div_ratio;
 616                  * where, freq_div_ratio = clk_ptp_ref_i/50MHz
 617                  * hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i;
 618                  * NOTE: clk_ptp_ref_i should be >= 50MHz to
 619                  *       achieve 20ns accuracy.
 620                  *
 621                  * 2^x * y == (y << x), hence
 622                  * 2^32 * 50000000 ==> (50000000 << 32)
 623                  */
 624                 temp = (u64) (50000000ULL << 32);
 625                 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
 626                 priv->hw->ptp->config_addend(priv->ioaddr,
 627                                              priv->default_addend);
 628
 629                 /* initialize system time */
 630                 ktime_get_real_ts64(&now);
 631
 632                 /* lower 32 bits of tv_sec are safe until y2106 */
 633                 priv->hw->ptp->init_systime(priv->ioaddr, (u32)now.tv_sec,
 634                                             now.tv_nsec);
 635         }
 636
 637         return copy_to_user(ifr->ifr_data, &config,
 638                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
 639 }
 640
 641 /**
 642  * stmmac_init_ptp - init PTP
 643  * @priv: driver private structure
 644  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 645  * This is done by looking at the HW cap. register.
 646  * This function also registers the ptp driver.
 647  */
 648 static int stmmac_init_ptp(struct stmmac_priv *priv)
 649 {
 650         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 651                 return -EOPNOTSUPP;
 652
 653         /* Fall-back to main clock in case of no PTP ref is passed */
 654         priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
 655         if (IS_ERR(priv->clk_ptp_ref)) {
 656                 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
 657                 priv->clk_ptp_ref = NULL;
 658         } else {
 659                 clk_prepare_enable(priv->clk_ptp_ref);
 660                 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
 661         }
 662
 663         priv->adv_ts = 0;
 664         if (priv->dma_cap.atime_stamp && priv->extend_desc)
 665                 priv->adv_ts = 1;
 666
 667         if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
 668                 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
 669
 670         if (netif_msg_hw(priv) && priv->adv_ts)
 671                 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
 672
 673         priv->hw->ptp = &stmmac_ptp;
 674         priv->hwts_tx_en = 0;
 675         priv->hwts_rx_en = 0;
 676
 677         return stmmac_ptp_register(priv);
 678 }
 679
 680 static void stmmac_release_ptp(struct stmmac_priv *priv)
 681 {
 682         if (priv->clk_ptp_ref)
 683                 clk_disable_unprepare(priv->clk_ptp_ref);
 684         stmmac_ptp_unregister(priv);
 685 }
 686
 687 /**
 688  * stmmac_adjust_link - adjusts the link parameters
 689  * @dev: net device structure
 690  * Description: this is the helper called by the physical abstraction layer
 691  * drivers to communicate the phy link status. According the speed and duplex
 692  * this driver can invoke registered glue-logic as well.
 693  * It also invoke the eee initialization because it could happen when switch
 694  * on different networks (that are eee capable).
 695  */
 696 static void stmmac_adjust_link(struct net_device *dev)
 697 {
 698         struct stmmac_priv *priv = netdev_priv(dev);
 699         struct phy_device *phydev = priv->phydev;
 700         unsigned long flags;
 701         int new_state = 0;
 702         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 703
 704         if (phydev == NULL)
 705                 return;
 706
 707         spin_lock_irqsave(&priv->lock, flags);
 708
 709         if (phydev->link) {
 710                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 711
 712                 /* Now we make sure that we can be in full duplex mode.
 713                  * If not, we operate in half-duplex mode. */
 714                 if (phydev->duplex != priv->oldduplex) {
 715                         new_state = 1;
 716                         if (!(phydev->duplex))
 717                                 ctrl &= ~priv->hw->link.duplex;
 718                         else
 719                                 ctrl |= priv->hw->link.duplex;
 720                         priv->oldduplex = phydev->duplex;
 721                 }
 722                 /* Flow Control operation */
 723                 if (phydev->pause)
 724                         priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
 725                                                  fc, pause_time);
 726
 727                 if (phydev->speed != priv->speed) {
 728                         new_state = 1;
 729                         switch (phydev->speed) {
 730                         case 1000:
 731                                 if (likely(priv->plat->has_gmac))
 732                                         ctrl &= ~priv->hw->link.port;
 733                                 stmmac_hw_fix_mac_speed(priv);
 734                                 break;
 735                         case 100:
 736                         case 10:
 737                                 if (priv->plat->has_gmac) {
 738                                         ctrl |= priv->hw->link.port;
 739                                         if (phydev->speed == SPEED_100) {
 740                                                 ctrl |= priv->hw->link.speed;
 741                                         } else {
 742                                                 ctrl &= ~(priv->hw->link.speed);
 743                                         }
 744                                 } else {
 745                                         ctrl &= ~priv->hw->link.port;
 746                                 }
 747                                 stmmac_hw_fix_mac_speed(priv);
 748                                 break;
 749                         default:
 750                                 if (netif_msg_link(priv))
 751                                         pr_warn("%s: Speed (%d) not 10/100\n",
 752                                                 dev->name, phydev->speed);
 753                                 break;
 754                         }
 755
 756                         priv->speed = phydev->speed;
 757                 }
 758
 759                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 760
 761                 if (!priv->oldlink) {
 762                         new_state = 1;
 763                         priv->oldlink = 1;
 764                 }
 765         } else if (priv->oldlink) {
 766                 new_state = 1;
 767                 priv->oldlink = 0;
 768                 priv->speed = 0;
 769                 priv->oldduplex = -1;
 770         }
 771
 772         if (new_state && netif_msg_link(priv))
 773                 phy_print_status(phydev);
 774
 775         spin_unlock_irqrestore(&priv->lock, flags);
 776
 777         /* At this stage, it could be needed to setup the EEE or adjust some
 778          * MAC related HW registers.
 779          */
 780         priv->eee_enabled = stmmac_eee_init(priv);
 781 }
 782
 783 /**
 784  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
 785  * @priv: driver private structure
 786  * Description: this is to verify if the HW supports the PCS.
 787  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 788  * configured for the TBI, RTBI, or SGMII PHY interface.
 789  */
 790 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 791 {
 792         int interface = priv->plat->interface;
 793
 794         if (priv->dma_cap.pcs) {
 795                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 796                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 797                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 798                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 799                         pr_debug("STMMAC: PCS RGMII support enable\n");
 800                         priv->pcs = STMMAC_PCS_RGMII;
 801                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 802                         pr_debug("STMMAC: PCS SGMII support enable\n");
 803                         priv->pcs = STMMAC_PCS_SGMII;
 804                 }
 805         }
 806 }
 807
 808 /**
 809  * stmmac_init_phy - PHY initialization
 810  * @dev: net device structure
 811  * Description: it initializes the driver's PHY state, and attaches the PHY
 812  * to the mac driver.
 813  *  Return value:
 814  *  0 on success
 815  */
 816 static int stmmac_init_phy(struct net_device *dev)
 817 {
 818         struct stmmac_priv *priv = netdev_priv(dev);
 819         struct phy_device *phydev;
 820         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 821         char bus_id[MII_BUS_ID_SIZE];
 822         int interface = priv->plat->interface;
 823         int max_speed = priv->plat->max_speed;
 824         priv->oldlink = 0;
 825         priv->speed = 0;
 826         priv->oldduplex = -1;
 827
 828         if (priv->plat->phy_node) {
 829                 phydev = of_phy_connect(dev, priv->plat->phy_node,
 830                                         &stmmac_adjust_link, 0, interface);
 831         } else {
 832                 if (priv->plat->phy_bus_name)
 833                         snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 834                                  priv->plat->phy_bus_name, priv->plat->bus_id);
 835                 else
 836                         snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 837                                  priv->plat->bus_id);
 838
 839                 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 840                          priv->plat->phy_addr);
 841                 pr_debug("stmmac_init_phy:  trying to attach to %s\n",
 842                          phy_id_fmt);
 843
 844                 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
 845                                      interface);
 846         }
 847
 848         if (IS_ERR_OR_NULL(phydev)) {
 849                 pr_err("%s: Could not attach to PHY\n", dev->name);
 850                 if (!phydev)
 851                         return -ENODEV;
 852
 853                 return PTR_ERR(phydev);
 854         }
 855
 856         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 857         if ((interface == PHY_INTERFACE_MODE_MII) ||
 858             (interface == PHY_INTERFACE_MODE_RMII) ||
 859                 (max_speed < 1000 && max_speed > 0))
 860                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 861                                          SUPPORTED_1000baseT_Full);
 862
 863         /*
 864          * Broken HW is sometimes missing the pull-up resistor on the
 865          * MDIO line, which results in reads to non-existent devices returning
 866          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 867          * device as well.
 868          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 869          */
 870         if (!priv->plat->phy_node && phydev->phy_id == 0) {
 871                 phy_disconnect(phydev);
 872                 return -ENODEV;
 873         }
 874         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 875                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 876
 877         priv->phydev = phydev;
 878
 879         return 0;
 880 }
 881
 882 /**
 883  * stmmac_display_ring - display ring
 884  * @head: pointer to the head of the ring passed.
 885  * @size: size of the ring.
 886  * @extend_desc: to verify if extended descriptors are used.
 887  * Description: display the control/status and buffer descriptors.
 888  */
 889 static void stmmac_display_ring(void *head, int size, int extend_desc)
 890 {
 891         int i;
 892         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
 893         struct dma_desc *p = (struct dma_desc *)head;
 894
 895         for (i = 0; i < size; i++) {
 896                 u64 x;
 897                 if (extend_desc) {
 898                         x = *(u64 *) ep;
 899                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
 900                                 i, (unsigned int)virt_to_phys(ep),
 901                                 (unsigned int)x, (unsigned int)(x >> 32),
 902                                 ep->basic.des2, ep->basic.des3);
 903                         ep++;
 904                 } else {
 905                         x = *(u64 *) p;
 906                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
 907                                 i, (unsigned int)virt_to_phys(p),
 908                                 (unsigned int)x, (unsigned int)(x >> 32),
 909                                 p->des2, p->des3);
 910                         p++;
 911                 }
 912                 pr_info("\n");
 913         }
 914 }
 915
 916 static void stmmac_display_rings(struct stmmac_priv *priv)
 917 {
 918         unsigned int txsize = priv->dma_tx_size;
 919         unsigned int rxsize = priv->dma_rx_size;
 920
 921         if (priv->extend_desc) {
 922                 pr_info("Extended RX descriptor ring:\n");
 923                 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
 924                 pr_info("Extended TX descriptor ring:\n");
 925                 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
 926         } else {
 927                 pr_info("RX descriptor ring:\n");
 928                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
 929                 pr_info("TX descriptor ring:\n");
 930                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
 931         }
 932 }
 933
 934 static int stmmac_set_bfsize(int mtu, int bufsize)
 935 {
 936         int ret = bufsize;
 937
 938         if (mtu >= BUF_SIZE_8KiB)
 939                 ret = BUF_SIZE_16KiB;
 940         else if (mtu >= BUF_SIZE_4KiB)
 941                 ret = BUF_SIZE_8KiB;
 942         else if (mtu >= BUF_SIZE_2KiB)
 943                 ret = BUF_SIZE_4KiB;
 944         else if (mtu > DEFAULT_BUFSIZE)
 945                 ret = BUF_SIZE_2KiB;
 946         else
 947                 ret = DEFAULT_BUFSIZE;
 948
 949         return ret;
 950 }
 951
 952 /**
 953  * stmmac_clear_descriptors - clear descriptors
 954  * @priv: driver private structure
 955  * Description: this function is called to clear the tx and rx descriptors
 956  * in case of both basic and extended descriptors are used.
 957  */
 958 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
 959 {
 960         int i;
 961         unsigned int txsize = priv->dma_tx_size;
 962         unsigned int rxsize = priv->dma_rx_size;
 963
 964         /* Clear the Rx/Tx descriptors */
 965         for (i = 0; i < rxsize; i++)
 966                 if (priv->extend_desc)
 967                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
 968                                                      priv->use_riwt, priv->mode,
 969                                                      (i == rxsize - 1), priv->dma_buf_sz);
 970                 else
 971                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
 972                                                      priv->use_riwt, priv->mode,
 973                                                      (i == rxsize - 1), priv->dma_buf_sz);
 974         for (i = 0; i < txsize; i++)
 975                 if (priv->extend_desc)
 976                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 977                                                      priv->mode,
 978                                                      (i == txsize - 1));
 979                 else
 980                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 981                                                      priv->mode,
 982                                                      (i == txsize - 1));
 983 }
 984
 985 /**
 986  * stmmac_init_rx_buffers - init the RX descriptor buffer.
 987  * @priv: driver private structure
 988  * @p: descriptor pointer
 989  * @i: descriptor index
 990  * @flags: gfp flag.
 991  * Description: this function is called to allocate a receive buffer, perform
 992  * the DMA mapping and init the descriptor.
 993  */
 994 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
 995                                   int i, gfp_t flags)
 996 {
 997         struct sk_buff *skb;
 998
 999         skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
1000         if (!skb) {
1001                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
1002                 return -ENOMEM;
1003         }
1004         priv->rx_skbuff[i] = skb;
1005         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
1006                                                 priv->dma_buf_sz,
1007                                                 DMA_FROM_DEVICE);
1008         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
1009                 pr_err("%s: DMA mapping error\n", __func__);
1010                 dev_kfree_skb_any(skb);
1011                 return -EINVAL;
1012         }
1013
1014         p->des2 = priv->rx_skbuff_dma[i];
1015
1016         if ((priv->hw->mode->init_desc3) &&
1017             (priv->dma_buf_sz == BUF_SIZE_16KiB))
1018                 priv->hw->mode->init_desc3(p);
1019
1020         return 0;
1021 }
1022
1023 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
1024 {
1025         if (priv->rx_skbuff[i]) {
1026                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1027                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
1028                 dev_kfree_skb_any(priv->rx_skbuff[i]);
1029         }
1030         priv->rx_skbuff[i] = NULL;
1031 }
1032
1033 /**
1034  * init_dma_desc_rings - init the RX/TX descriptor rings
1035  * @dev: net device structure
1036  * @flags: gfp flag.
1037  * Description: this function initializes the DMA RX/TX descriptors
1038  * and allocates the socket buffers. It suppors the chained and ring
1039  * modes.
1040  */
1041 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1042 {
1043         int i;
1044         struct stmmac_priv *priv = netdev_priv(dev);
1045         unsigned int txsize = priv->dma_tx_size;
1046         unsigned int rxsize = priv->dma_rx_size;
1047         unsigned int bfsize = 0;
1048         int ret = -ENOMEM;
1049
1050         if (priv->hw->mode->set_16kib_bfsize)
1051                 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1052
1053         if (bfsize < BUF_SIZE_16KiB)
1054                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1055
1056         priv->dma_buf_sz = bfsize;
1057
1058         if (netif_msg_probe(priv))
1059                 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
1060                          txsize, rxsize, bfsize);
1061
1062         if (netif_msg_probe(priv)) {
1063                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1064                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1065
1066                 /* RX INITIALIZATION */
1067                 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1068         }
1069         for (i = 0; i < rxsize; i++) {
1070                 struct dma_desc *p;
1071                 if (priv->extend_desc)
1072                         p = &((priv->dma_erx + i)->basic);
1073                 else
1074                         p = priv->dma_rx + i;
1075
1076                 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1077                 if (ret)
1078                         goto err_init_rx_buffers;
1079
1080                 if (netif_msg_probe(priv))
1081                         pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1082                                  priv->rx_skbuff[i]->data,
1083                                  (unsigned int)priv->rx_skbuff_dma[i]);
1084         }
1085         priv->cur_rx = 0;
1086         priv->dirty_rx = (unsigned int)(i - rxsize);
1087         buf_sz = bfsize;
1088
1089         /* Setup the chained descriptor addresses */
1090         if (priv->mode == STMMAC_CHAIN_MODE) {
1091                 if (priv->extend_desc) {
1092                         priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1093                                              rxsize, 1);
1094                         priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1095                                              txsize, 1);
1096                 } else {
1097                         priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1098                                              rxsize, 0);
1099                         priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1100                                              txsize, 0);
1101                 }
1102         }
1103
1104         /* TX INITIALIZATION */
1105         for (i = 0; i < txsize; i++) {
1106                 struct dma_desc *p;
1107                 if (priv->extend_desc)
1108                         p = &((priv->dma_etx + i)->basic);
1109                 else
1110                         p = priv->dma_tx + i;
1111                 p->des2 = 0;
1112                 priv->tx_skbuff_dma[i].buf = 0;
1113                 priv->tx_skbuff_dma[i].map_as_page = false;
1114                 priv->tx_skbuff[i] = NULL;
1115         }
1116
1117         priv->dirty_tx = 0;
1118         priv->cur_tx = 0;
1119         netdev_reset_queue(priv->dev);
1120
1121         stmmac_clear_descriptors(priv);
1122
1123         if (netif_msg_hw(priv))
1124                 stmmac_display_rings(priv);
1125
1126         return 0;
1127 err_init_rx_buffers:
1128         while (--i >= 0)
1129                 stmmac_free_rx_buffers(priv, i);
1130         return ret;
1131 }
1132
1133 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1134 {
1135         int i;
1136
1137         for (i = 0; i < priv->dma_rx_size; i++)
1138                 stmmac_free_rx_buffers(priv, i);
1139 }
1140
1141 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1142 {
1143         int i;
1144
1145         for (i = 0; i < priv->dma_tx_size; i++) {
1146                 struct dma_desc *p;
1147
1148                 if (priv->extend_desc)
1149                         p = &((priv->dma_etx + i)->basic);
1150                 else
1151                         p = priv->dma_tx + i;
1152
1153                 if (priv->tx_skbuff_dma[i].buf) {
1154                         if (priv->tx_skbuff_dma[i].map_as_page)
1155                                 dma_unmap_page(priv->device,
1156                                                priv->tx_skbuff_dma[i].buf,
1157                                                priv->hw->desc->get_tx_len(p),
1158                                                DMA_TO_DEVICE);
1159                         else
1160                                 dma_unmap_single(priv->device,
1161                                                  priv->tx_skbuff_dma[i].buf,
1162                                                  priv->hw->desc->get_tx_len(p),
1163                                                  DMA_TO_DEVICE);
1164                 }
1165
1166                 if (priv->tx_skbuff[i] != NULL) {
1167                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1168                         priv->tx_skbuff[i] = NULL;
1169                         priv->tx_skbuff_dma[i].buf = 0;
1170                         priv->tx_skbuff_dma[i].map_as_page = false;
1171                 }
1172         }
1173 }
1174
1175 /**
1176  * alloc_dma_desc_resources - alloc TX/RX resources.
1177  * @priv: private structure
1178  * Description: according to which descriptor can be used (extend or basic)
1179  * this function allocates the resources for TX and RX paths. In case of
1180  * reception, for example, it pre-allocated the RX socket buffer in order to
1181  * allow zero-copy mechanism.
1182  */
1183 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1184 {
1185         unsigned int txsize = priv->dma_tx_size;
1186         unsigned int rxsize = priv->dma_rx_size;
1187         int ret = -ENOMEM;
1188
1189         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1190                                             GFP_KERNEL);
1191         if (!priv->rx_skbuff_dma)
1192                 return -ENOMEM;
1193
1194         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1195                                         GFP_KERNEL);
1196         if (!priv->rx_skbuff)
1197                 goto err_rx_skbuff;
1198
1199         priv->tx_skbuff_dma = kmalloc_array(txsize,
1200                                             sizeof(*priv->tx_skbuff_dma),
1201                                             GFP_KERNEL);
1202         if (!priv->tx_skbuff_dma)
1203                 goto err_tx_skbuff_dma;
1204
1205         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1206                                         GFP_KERNEL);
1207         if (!priv->tx_skbuff)
1208                 goto err_tx_skbuff;
1209
1210         if (priv->extend_desc) {
1211                 priv->dma_erx = dma_zalloc_coherent(priv->device, rxsize *
1212                                                     sizeof(struct
1213                                                            dma_extended_desc),
1214                                                     &priv->dma_rx_phy,
1215                                                     GFP_KERNEL);
1216                 if (!priv->dma_erx)
1217                         goto err_dma;
1218
1219                 priv->dma_etx = dma_zalloc_coherent(priv->device, txsize *
1220                                                     sizeof(struct
1221                                                            dma_extended_desc),
1222                                                     &priv->dma_tx_phy,
1223                                                     GFP_KERNEL);
1224                 if (!priv->dma_etx) {
1225                         dma_free_coherent(priv->device, priv->dma_rx_size *
1226                                           sizeof(struct dma_extended_desc),
1227                                           priv->dma_erx, priv->dma_rx_phy);
1228                         goto err_dma;
1229                 }
1230         } else {
1231                 priv->dma_rx = dma_zalloc_coherent(priv->device, rxsize *
1232                                                    sizeof(struct dma_desc),
1233                                                    &priv->dma_rx_phy,
1234                                                    GFP_KERNEL);
1235                 if (!priv->dma_rx)
1236                         goto err_dma;
1237
1238                 priv->dma_tx = dma_zalloc_coherent(priv->device, txsize *
1239                                                    sizeof(struct dma_desc),
1240                                                    &priv->dma_tx_phy,
1241                                                    GFP_KERNEL);
1242                 if (!priv->dma_tx) {
1243                         dma_free_coherent(priv->device, priv->dma_rx_size *
1244                                           sizeof(struct dma_desc),
1245                                           priv->dma_rx, priv->dma_rx_phy);
1246                         goto err_dma;
1247                 }
1248         }
1249
1250         return 0;
1251
1252 err_dma:
1253         kfree(priv->tx_skbuff);
1254 err_tx_skbuff:
1255         kfree(priv->tx_skbuff_dma);
1256 err_tx_skbuff_dma:
1257         kfree(priv->rx_skbuff);
1258 err_rx_skbuff:
1259         kfree(priv->rx_skbuff_dma);
1260         return ret;
1261 }
1262
1263 static void free_dma_desc_resources(struct stmmac_priv *priv)
1264 {
1265         /* Release the DMA TX/RX socket buffers */
1266         dma_free_rx_skbufs(priv);
1267         dma_free_tx_skbufs(priv);
1268
1269         /* Free DMA regions of consistent memory previously allocated */
1270         if (!priv->extend_desc) {
1271                 dma_free_coherent(priv->device,
1272                                   priv->dma_tx_size * sizeof(struct dma_desc),
1273                                   priv->dma_tx, priv->dma_tx_phy);
1274                 dma_free_coherent(priv->device,
1275                                   priv->dma_rx_size * sizeof(struct dma_desc),
1276                                   priv->dma_rx, priv->dma_rx_phy);
1277         } else {
1278                 dma_free_coherent(priv->device, priv->dma_tx_size *
1279                                   sizeof(struct dma_extended_desc),
1280                                   priv->dma_etx, priv->dma_tx_phy);
1281                 dma_free_coherent(priv->device, priv->dma_rx_size *
1282                                   sizeof(struct dma_extended_desc),
1283                                   priv->dma_erx, priv->dma_rx_phy);
1284         }
1285         kfree(priv->rx_skbuff_dma);
1286         kfree(priv->rx_skbuff);
1287         kfree(priv->tx_skbuff_dma);
1288         kfree(priv->tx_skbuff);
1289 }
1290
1291 /**
1292  *  stmmac_dma_operation_mode - HW DMA operation mode
1293  *  @priv: driver private structure
1294  *  Description: it is used for configuring the DMA operation mode register in
1295  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1296  */
1297 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1298 {
1299         int rxfifosz = priv->plat->rx_fifo_size;
1300
1301         if (priv->plat->force_thresh_dma_mode)
1302                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
1303         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1304                 /*
1305                  * In case of GMAC, SF mode can be enabled
1306                  * to perform the TX COE in HW. This depends on:
1307                  * 1) TX COE if actually supported
1308                  * 2) There is no bugged Jumbo frame support
1309                  *    that needs to not insert csum in the TDES.
1310                  */
1311                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE,
1312                                         rxfifosz);
1313                 priv->xstats.threshold = SF_DMA_MODE;
1314         } else
1315                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE,
1316                                         rxfifosz);
1317 }
1318
1319 /**
1320  * stmmac_tx_clean - to manage the transmission completion
1321  * @priv: driver private structure
1322  * Description: it reclaims the transmit resources after transmission completes.
1323  */
1324 static void stmmac_tx_clean(struct stmmac_priv *priv)
1325 {
1326         unsigned int txsize = priv->dma_tx_size;
1327         unsigned int bytes_compl = 0, pkts_compl = 0;
1328
1329         spin_lock(&priv->tx_lock);
1330
1331         priv->xstats.tx_clean++;
1332
1333         while (priv->dirty_tx != priv->cur_tx) {
1334                 int last;
1335                 unsigned int entry = priv->dirty_tx % txsize;
1336                 struct sk_buff *skb = priv->tx_skbuff[entry];
1337                 struct dma_desc *p;
1338
1339                 if (priv->extend_desc)
1340                         p = (struct dma_desc *)(priv->dma_etx + entry);
1341                 else
1342                         p = priv->dma_tx + entry;
1343
1344                 /* Check if the descriptor is owned by the DMA. */
1345                 if (priv->hw->desc->get_tx_owner(p))
1346                         break;
1347
1348                 /* Verify tx error by looking at the last segment. */
1349                 last = priv->hw->desc->get_tx_ls(p);
1350                 if (likely(last)) {
1351                         int tx_error =
1352                             priv->hw->desc->tx_status(&priv->dev->stats,
1353                                                       &priv->xstats, p,
1354                                                       priv->ioaddr);
1355                         if (likely(tx_error == 0)) {
1356                                 priv->dev->stats.tx_packets++;
1357                                 priv->xstats.tx_pkt_n++;
1358                         } else
1359                                 priv->dev->stats.tx_errors++;
1360
1361                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1362                 }
1363                 if (netif_msg_tx_done(priv))
1364                         pr_debug("%s: curr %d, dirty %d\n", __func__,
1365                                  priv->cur_tx, priv->dirty_tx);
1366
1367                 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1368                         if (priv->tx_skbuff_dma[entry].map_as_page)
1369                                 dma_unmap_page(priv->device,
1370                                                priv->tx_skbuff_dma[entry].buf,
1371                                                priv->hw->desc->get_tx_len(p),
1372                                                DMA_TO_DEVICE);
1373                         else
1374                                 dma_unmap_single(priv->device,
1375                                                  priv->tx_skbuff_dma[entry].buf,
1376                                                  priv->hw->desc->get_tx_len(p),
1377                                                  DMA_TO_DEVICE);
1378                         priv->tx_skbuff_dma[entry].buf = 0;
1379                         priv->tx_skbuff_dma[entry].map_as_page = false;
1380                 }
1381                 priv->hw->mode->clean_desc3(priv, p);
1382
1383                 if (likely(skb != NULL)) {
1384                         pkts_compl++;
1385                         bytes_compl += skb->len;
1386                         dev_consume_skb_any(skb);
1387                         priv->tx_skbuff[entry] = NULL;
1388                 }
1389
1390                 priv->hw->desc->release_tx_desc(p, priv->mode);
1391
1392                 priv->dirty_tx++;
1393         }
1394
1395         netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1396
1397         if (unlikely(netif_queue_stopped(priv->dev) &&
1398                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1399                 netif_tx_lock(priv->dev);
1400                 if (netif_queue_stopped(priv->dev) &&
1401                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1402                         if (netif_msg_tx_done(priv))
1403                                 pr_debug("%s: restart transmit\n", __func__);
1404                         netif_wake_queue(priv->dev);
1405                 }
1406                 netif_tx_unlock(priv->dev);
1407         }
1408
1409         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1410                 stmmac_enable_eee_mode(priv);
1411                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1412         }
1413         spin_unlock(&priv->tx_lock);
1414 }
1415
1416 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1417 {
1418         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1419 }
1420
1421 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1422 {
1423         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1424 }
1425
1426 /**
1427  * stmmac_tx_err - to manage the tx error
1428  * @priv: driver private structure
1429  * Description: it cleans the descriptors and restarts the transmission
1430  * in case of transmission errors.
1431  */
1432 static void stmmac_tx_err(struct stmmac_priv *priv)
1433 {
1434         int i;
1435         int txsize = priv->dma_tx_size;
1436         netif_stop_queue(priv->dev);
1437
1438         priv->hw->dma->stop_tx(priv->ioaddr);
1439         dma_free_tx_skbufs(priv);
1440         for (i = 0; i < txsize; i++)
1441                 if (priv->extend_desc)
1442                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1443                                                      priv->mode,
1444                                                      (i == txsize - 1));
1445                 else
1446                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1447                                                      priv->mode,
1448                                                      (i == txsize - 1));
1449         priv->dirty_tx = 0;
1450         priv->cur_tx = 0;
1451         netdev_reset_queue(priv->dev);
1452         priv->hw->dma->start_tx(priv->ioaddr);
1453
1454         priv->dev->stats.tx_errors++;
1455         netif_wake_queue(priv->dev);
1456 }
1457
1458 /**
1459  * stmmac_dma_interrupt - DMA ISR
1460  * @priv: driver private structure
1461  * Description: this is the DMA ISR. It is called by the main ISR.
1462  * It calls the dwmac dma routine and schedule poll method in case of some
1463  * work can be done.
1464  */
1465 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1466 {
1467         int status;
1468         int rxfifosz = priv->plat->rx_fifo_size;
1469
1470         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1471         if (likely((status & handle_rx)) || (status & handle_tx)) {
1472                 if (likely(napi_schedule_prep(&priv->napi))) {
1473                         stmmac_disable_dma_irq(priv);
1474                         __napi_schedule(&priv->napi);
1475                 }
1476         }
1477         if (unlikely(status & tx_hard_error_bump_tc)) {
1478                 /* Try to bump up the dma threshold on this failure */
1479                 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1480                     (tc <= 256)) {
1481                         tc += 64;
1482                         if (priv->plat->force_thresh_dma_mode)
1483                                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc,
1484                                                         rxfifosz);
1485                         else
1486                                 priv->hw->dma->dma_mode(priv->ioaddr, tc,
1487                                                         SF_DMA_MODE, rxfifosz);
1488                         priv->xstats.threshold = tc;
1489                 }
1490         } else if (unlikely(status == tx_hard_error))
1491                 stmmac_tx_err(priv);
1492 }
1493
1494 /**
1495  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1496  * @priv: driver private structure
1497  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1498  */
1499 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1500 {
1501         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1502             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1503
1504         dwmac_mmc_intr_all_mask(priv->ioaddr);
1505
1506         if (priv->dma_cap.rmon) {
1507                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1508                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1509         } else
1510                 pr_info(" No MAC Management Counters available\n");
1511 }
1512
1513 /**
1514  * stmmac_get_synopsys_id - return the SYINID.
1515  * @priv: driver private structure
1516  * Description: this simple function is to decode and return the SYINID
1517  * starting from the HW core register.
1518  */
1519 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1520 {
1521         u32 hwid = priv->hw->synopsys_uid;
1522
1523         /* Check Synopsys Id (not available on old chips) */
1524         if (likely(hwid)) {
1525                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1526                 u32 synid = (hwid & 0x000000ff);
1527
1528                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1529                         uid, synid);
1530
1531                 return synid;
1532         }
1533         return 0;
1534 }
1535
1536 /**
1537  * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1538  * @priv: driver private structure
1539  * Description: select the Enhanced/Alternate or Normal descriptors.
1540  * In case of Enhanced/Alternate, it checks if the extended descriptors are
1541  * supported by the HW capability register.
1542  */
1543 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1544 {
1545         if (priv->plat->enh_desc) {
1546                 pr_info(" Enhanced/Alternate descriptors\n");
1547
1548                 /* GMAC older than 3.50 has no extended descriptors */
1549                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1550                         pr_info("\tEnabled extended descriptors\n");
1551                         priv->extend_desc = 1;
1552                 } else
1553                         pr_warn("Extended descriptors not supported\n");
1554
1555                 priv->hw->desc = &enh_desc_ops;
1556         } else {
1557                 pr_info(" Normal descriptors\n");
1558                 priv->hw->desc = &ndesc_ops;
1559         }
1560 }
1561
1562 /**
1563  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1564  * @priv: driver private structure
1565  * Description:
1566  *  new GMAC chip generations have a new register to indicate the
1567  *  presence of the optional feature/functions.
1568  *  This can be also used to override the value passed through the
1569  *  platform and necessary for old MAC10/100 and GMAC chips.
1570  */
1571 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1572 {
1573         u32 hw_cap = 0;
1574
1575         if (priv->hw->dma->get_hw_feature) {
1576                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1577
1578                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1579                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1580                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1581                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1582                 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1583                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1584                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1585                 priv->dma_cap.pmt_remote_wake_up =
1586                     (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1587                 priv->dma_cap.pmt_magic_frame =
1588                     (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1589                 /* MMC */
1590                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1591                 /* IEEE 1588-2002 */
1592                 priv->dma_cap.time_stamp =
1593                     (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1594                 /* IEEE 1588-2008 */
1595                 priv->dma_cap.atime_stamp =
1596                     (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1597                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1598                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1599                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1600                 /* TX and RX csum */
1601                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1602                 priv->dma_cap.rx_coe_type1 =
1603                     (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1604                 priv->dma_cap.rx_coe_type2 =
1605                     (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1606                 priv->dma_cap.rxfifo_over_2048 =
1607                     (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1608                 /* TX and RX number of channels */
1609                 priv->dma_cap.number_rx_channel =
1610                     (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1611                 priv->dma_cap.number_tx_channel =
1612                     (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1613                 /* Alternate (enhanced) DESC mode */
1614                 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1615         }
1616
1617         return hw_cap;
1618 }
1619
1620 /**
1621  * stmmac_check_ether_addr - check if the MAC addr is valid
1622  * @priv: driver private structure
1623  * Description:
1624  * it is to verify if the MAC address is valid, in case of failures it
1625  * generates a random MAC address
1626  */
1627 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1628 {
1629         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1630                 priv->hw->mac->get_umac_addr(priv->hw,
1631                                              priv->dev->dev_addr, 0);
1632                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1633                         eth_hw_addr_random(priv->dev);
1634                 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1635                         priv->dev->dev_addr);
1636         }
1637 }
1638
1639 /**
1640  * stmmac_init_dma_engine - DMA init.
1641  * @priv: driver private structure
1642  * Description:
1643  * It inits the DMA invoking the specific MAC/GMAC callback.
1644  * Some DMA parameters can be passed from the platform;
1645  * in case of these are not passed a default is kept for the MAC or GMAC.
1646  */
1647 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1648 {
1649         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1650         int mixed_burst = 0;
1651         int atds = 0;
1652
1653         if (priv->plat->dma_cfg) {
1654                 pbl = priv->plat->dma_cfg->pbl;
1655                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1656                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1657                 burst_len = priv->plat->dma_cfg->burst_len;
1658         }
1659
1660         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1661                 atds = 1;
1662
1663         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1664                                    burst_len, priv->dma_tx_phy,
1665                                    priv->dma_rx_phy, atds);
1666 }
1667
1668 /**
1669  * stmmac_tx_timer - mitigation sw timer for tx.
1670  * @data: data pointer
1671  * Description:
1672  * This is the timer handler to directly invoke the stmmac_tx_clean.
1673  */
1674 static void stmmac_tx_timer(unsigned long data)
1675 {
1676         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1677
1678         stmmac_tx_clean(priv);
1679 }
1680
1681 /**
1682  * stmmac_init_tx_coalesce - init tx mitigation options.
1683  * @priv: driver private structure
1684  * Description:
1685  * This inits the transmit coalesce parameters: i.e. timer rate,
1686  * timer handler and default threshold used for enabling the
1687  * interrupt on completion bit.
1688  */
1689 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1690 {
1691         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1692         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1693         init_timer(&priv->txtimer);
1694         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1695         priv->txtimer.data = (unsigned long)priv;
1696         priv->txtimer.function = stmmac_tx_timer;
1697         add_timer(&priv->txtimer);
1698 }
1699
1700 /**
1701  * stmmac_hw_setup - setup mac in a usable state.
1702  *  @dev : pointer to the device structure.
1703  *  Description:
1704  *  this is the main function to setup the HW in a usable state because the
1705  *  dma engine is reset, the core registers are configured (e.g. AXI,
1706  *  Checksum features, timers). The DMA is ready to start receiving and
1707  *  transmitting.
1708  *  Return value:
1709  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1710  *  file on failure.
1711  */
1712 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1713 {
1714         struct stmmac_priv *priv = netdev_priv(dev);
1715         int ret;
1716
1717         /* DMA initialization and SW reset */
1718         ret = stmmac_init_dma_engine(priv);
1719         if (ret < 0) {
1720                 pr_err("%s: DMA engine initialization failed\n", __func__);
1721                 return ret;
1722         }
1723
1724         /* Copy the MAC addr into the HW  */
1725         priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1726
1727         /* If required, perform hw setup of the bus. */
1728         if (priv->plat->bus_setup)
1729                 priv->plat->bus_setup(priv->ioaddr);
1730
1731         /* Initialize the MAC Core */
1732         priv->hw->mac->core_init(priv->hw, dev->mtu);
1733
1734         ret = priv->hw->mac->rx_ipc(priv->hw);
1735         if (!ret) {
1736                 pr_warn(" RX IPC Checksum Offload disabled\n");
1737                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1738                 priv->hw->rx_csum = 0;
1739         }
1740
1741         /* Enable the MAC Rx/Tx */
1742         stmmac_set_mac(priv->ioaddr, true);
1743
1744         /* Set the HW DMA mode and the COE */
1745         stmmac_dma_operation_mode(priv);
1746
1747         stmmac_mmc_setup(priv);
1748
1749         if (init_ptp) {
1750                 ret = stmmac_init_ptp(priv);
1751                 if (ret && ret != -EOPNOTSUPP)
1752                         pr_warn("%s: failed PTP initialisation\n", __func__);
1753         }
1754
1755 #ifdef CONFIG_DEBUG_FS
1756         ret = stmmac_init_fs(dev);
1757         if (ret < 0)
1758                 pr_warn("%s: failed debugFS registration\n", __func__);
1759 #endif
1760         /* Start the ball rolling... */
1761         pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1762         priv->hw->dma->start_tx(priv->ioaddr);
1763         priv->hw->dma->start_rx(priv->ioaddr);
1764
1765         /* Dump DMA/MAC registers */
1766         if (netif_msg_hw(priv)) {
1767                 priv->hw->mac->dump_regs(priv->hw);
1768                 priv->hw->dma->dump_regs(priv->ioaddr);
1769         }
1770         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1771
1772         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1773                 priv->rx_riwt = MAX_DMA_RIWT;
1774                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1775         }
1776
1777         if (priv->pcs && priv->hw->mac->ctrl_ane)
1778                 priv->hw->mac->ctrl_ane(priv->hw, 0);
1779
1780         return 0;
1781 }
1782
1783 /**
1784  *  stmmac_open - open entry point of the driver
1785  *  @dev : pointer to the device structure.
1786  *  Description:
1787  *  This function is the open entry point of the driver.
1788  *  Return value:
1789  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1790  *  file on failure.
1791  */
1792 static int stmmac_open(struct net_device *dev)
1793 {
1794         struct stmmac_priv *priv = netdev_priv(dev);
1795         int ret;
1796
1797         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1798             priv->pcs != STMMAC_PCS_RTBI) {
1799                 ret = stmmac_init_phy(dev);
1800                 if (ret) {
1801                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1802                                __func__, ret);
1803                         return ret;
1804                 }
1805         }
1806
1807         /* Extra statistics */
1808         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1809         priv->xstats.threshold = tc;
1810
1811         /* Create and initialize the TX/RX descriptors chains. */
1812         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1813         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1814         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1815
1816         ret = alloc_dma_desc_resources(priv);
1817         if (ret < 0) {
1818                 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1819                 goto dma_desc_error;
1820         }
1821
1822         ret = init_dma_desc_rings(dev, GFP_KERNEL);
1823         if (ret < 0) {
1824                 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1825                 goto init_error;
1826         }
1827
1828         ret = stmmac_hw_setup(dev, true);
1829         if (ret < 0) {
1830                 pr_err("%s: Hw setup failed\n", __func__);
1831                 goto init_error;
1832         }
1833
1834         stmmac_init_tx_coalesce(priv);
1835
1836         if (priv->phydev)
1837                 phy_start(priv->phydev);
1838
1839         /* Request the IRQ lines */
1840         ret = request_irq(dev->irq, stmmac_interrupt,
1841                           IRQF_SHARED, dev->name, dev);
1842         if (unlikely(ret < 0)) {
1843                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1844                        __func__, dev->irq, ret);
1845                 goto init_error;
1846         }
1847
1848         /* Request the Wake IRQ in case of another line is used for WoL */
1849         if (priv->wol_irq != dev->irq) {
1850                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1851                                   IRQF_SHARED, dev->name, dev);
1852                 if (unlikely(ret < 0)) {
1853                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1854                                __func__, priv->wol_irq, ret);
1855                         goto wolirq_error;
1856                 }
1857         }
1858
1859         /* Request the IRQ lines */
1860         if (priv->lpi_irq > 0) {
1861                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1862                                   dev->name, dev);
1863                 if (unlikely(ret < 0)) {
1864                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1865                                __func__, priv->lpi_irq, ret);
1866                         goto lpiirq_error;
1867                 }
1868         }
1869
1870         napi_enable(&priv->napi);
1871         netif_start_queue(dev);
1872
1873         return 0;
1874
1875 lpiirq_error:
1876         if (priv->wol_irq != dev->irq)
1877                 free_irq(priv->wol_irq, dev);
1878 wolirq_error:
1879         free_irq(dev->irq, dev);
1880
1881 init_error:
1882         free_dma_desc_resources(priv);
1883 dma_desc_error:
1884         if (priv->phydev)
1885                 phy_disconnect(priv->phydev);
1886
1887         return ret;
1888 }
1889
1890 /**
1891  *  stmmac_release - close entry point of the driver
1892  *  @dev : device pointer.
1893  *  Description:
1894  *  This is the stop entry point of the driver.
1895  */
1896 static int stmmac_release(struct net_device *dev)
1897 {
1898         struct stmmac_priv *priv = netdev_priv(dev);
1899
1900         /* Stop and disconnect the PHY */
1901         if (priv->phydev) {
1902                 phy_stop(priv->phydev);
1903                 phy_disconnect(priv->phydev);
1904                 priv->phydev = NULL;
1905         }
1906
1907         netif_stop_queue(dev);
1908
1909         napi_disable(&priv->napi);
1910
1911         del_timer_sync(&priv->txtimer);
1912
1913         /* Free the IRQ lines */
1914         free_irq(dev->irq, dev);
1915         if (priv->wol_irq != dev->irq)
1916                 free_irq(priv->wol_irq, dev);
1917         if (priv->lpi_irq > 0)
1918                 free_irq(priv->lpi_irq, dev);
1919
1920         if (priv->eee_enabled) {
1921                 priv->tx_path_in_lpi_mode = false;
1922                 del_timer_sync(&priv->eee_ctrl_timer);
1923         }
1924
1925         /* Stop TX/RX DMA and clear the descriptors */
1926         priv->hw->dma->stop_tx(priv->ioaddr);
1927         priv->hw->dma->stop_rx(priv->ioaddr);
1928
1929         /* Release and free the Rx/Tx resources */
1930         free_dma_desc_resources(priv);
1931
1932         /* Disable the MAC Rx/Tx */
1933         stmmac_set_mac(priv->ioaddr, false);
1934
1935         netif_carrier_off(dev);
1936
1937 #ifdef CONFIG_DEBUG_FS
1938         stmmac_exit_fs(dev);
1939 #endif
1940
1941         stmmac_release_ptp(priv);
1942
1943         return 0;
1944 }
1945
1946 /**
1947  *  stmmac_xmit - Tx entry point of the driver
1948  *  @skb : the socket buffer
1949  *  @dev : device pointer
1950  *  Description : this is the tx entry point of the driver.
1951  *  It programs the chain or the ring and supports oversized frames
1952  *  and SG feature.
1953  */
1954 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1955 {
1956         struct stmmac_priv *priv = netdev_priv(dev);
1957         unsigned int txsize = priv->dma_tx_size;
1958         int entry;
1959         int i, csum_insertion = 0, is_jumbo = 0;
1960         int nfrags = skb_shinfo(skb)->nr_frags;
1961         struct dma_desc *desc, *first;
1962         unsigned int nopaged_len = skb_headlen(skb);
1963         unsigned int enh_desc = priv->plat->enh_desc;
1964
1965         spin_lock(&priv->tx_lock);
1966
1967         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1968                 spin_unlock(&priv->tx_lock);
1969                 if (!netif_queue_stopped(dev)) {
1970                         netif_stop_queue(dev);
1971                         /* This is a hard error, log it. */
1972                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
1973                 }
1974                 return NETDEV_TX_BUSY;
1975         }
1976
1977         if (priv->tx_path_in_lpi_mode)
1978                 stmmac_disable_eee_mode(priv);
1979
1980         entry = priv->cur_tx % txsize;
1981
1982         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1983
1984         if (priv->extend_desc)
1985                 desc = (struct dma_desc *)(priv->dma_etx + entry);
1986         else
1987                 desc = priv->dma_tx + entry;
1988
1989         first = desc;
1990
1991         /* To program the descriptors according to the size of the frame */
1992         if (enh_desc)
1993                 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
1994
1995         if (likely(!is_jumbo)) {
1996                 desc->des2 = dma_map_single(priv->device, skb->data,
1997                                             nopaged_len, DMA_TO_DEVICE);
1998                 if (dma_mapping_error(priv->device, desc->des2))
1999                         goto dma_map_err;
2000                 priv->tx_skbuff_dma[entry].buf = desc->des2;
2001                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
2002                                                 csum_insertion, priv->mode);
2003         } else {
2004                 desc = first;
2005                 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
2006                 if (unlikely(entry < 0))
2007                         goto dma_map_err;
2008         }
2009
2010         for (i = 0; i < nfrags; i++) {
2011                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2012                 int len = skb_frag_size(frag);
2013
2014                 priv->tx_skbuff[entry] = NULL;
2015                 entry = (++priv->cur_tx) % txsize;
2016                 if (priv->extend_desc)
2017                         desc = (struct dma_desc *)(priv->dma_etx + entry);
2018                 else
2019                         desc = priv->dma_tx + entry;
2020
2021                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
2022                                               DMA_TO_DEVICE);
2023                 if (dma_mapping_error(priv->device, desc->des2))
2024                         goto dma_map_err; /* should reuse desc w/o issues */
2025
2026                 priv->tx_skbuff_dma[entry].buf = desc->des2;
2027                 priv->tx_skbuff_dma[entry].map_as_page = true;
2028                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2029                                                 priv->mode);
2030                 wmb();
2031                 priv->hw->desc->set_tx_owner(desc);
2032                 wmb();
2033         }
2034
2035         priv->tx_skbuff[entry] = skb;
2036
2037         /* Finalize the latest segment. */
2038         priv->hw->desc->close_tx_desc(desc);
2039
2040         wmb();
2041         /* According to the coalesce parameter the IC bit for the latest
2042          * segment could be reset and the timer re-started to invoke the
2043          * stmmac_tx function. This approach takes care about the fragments.
2044          */
2045         priv->tx_count_frames += nfrags + 1;
2046         if (priv->tx_coal_frames > priv->tx_count_frames) {
2047                 priv->hw->desc->clear_tx_ic(desc);
2048                 priv->xstats.tx_reset_ic_bit++;
2049                 mod_timer(&priv->txtimer,
2050                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2051         } else
2052                 priv->tx_count_frames = 0;
2053
2054         /* To avoid raise condition */
2055         priv->hw->desc->set_tx_owner(first);
2056         wmb();
2057
2058         priv->cur_tx++;
2059
2060         if (netif_msg_pktdata(priv)) {
2061                 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
2062                         __func__, (priv->cur_tx % txsize),
2063                         (priv->dirty_tx % txsize), entry, first, nfrags);
2064
2065                 if (priv->extend_desc)
2066                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
2067                 else
2068                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
2069
2070                 pr_debug(">>> frame to be transmitted: ");
2071                 print_pkt(skb->data, skb->len);
2072         }
2073         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2074                 if (netif_msg_hw(priv))
2075                         pr_debug("%s: stop transmitted packets\n", __func__);
2076                 netif_stop_queue(dev);
2077         }
2078
2079         dev->stats.tx_bytes += skb->len;
2080
2081         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2082                      priv->hwts_tx_en)) {
2083                 /* declare that device is doing timestamping */
2084                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2085                 priv->hw->desc->enable_tx_timestamp(first);
2086         }
2087
2088         if (!priv->hwts_tx_en)
2089                 skb_tx_timestamp(skb);
2090
2091         netdev_sent_queue(dev, skb->len);
2092         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2093
2094         spin_unlock(&priv->tx_lock);
2095         return NETDEV_TX_OK;
2096
2097 dma_map_err:
2098         spin_unlock(&priv->tx_lock);
2099         dev_err(priv->device, "Tx dma map failed\n");
2100         dev_kfree_skb(skb);
2101         priv->dev->stats.tx_dropped++;
2102         return NETDEV_TX_OK;
2103 }
2104
2105 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2106 {
2107         struct ethhdr *ehdr;
2108         u16 vlanid;
2109
2110         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2111             NETIF_F_HW_VLAN_CTAG_RX &&
2112             !__vlan_get_tag(skb, &vlanid)) {
2113                 /* pop the vlan tag */
2114                 ehdr = (struct ethhdr *)skb->data;
2115                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2116                 skb_pull(skb, VLAN_HLEN);
2117                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2118         }
2119 }
2120
2121
2122 /**
2123  * stmmac_rx_refill - refill used skb preallocated buffers
2124  * @priv: driver private structure
2125  * Description : this is to reallocate the skb for the reception process
2126  * that is based on zero-copy.
2127  */
2128 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2129 {
2130         unsigned int rxsize = priv->dma_rx_size;
2131         int bfsize = priv->dma_buf_sz;
2132
2133         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
2134                 unsigned int entry = priv->dirty_rx % rxsize;
2135                 struct dma_desc *p;
2136
2137                 if (priv->extend_desc)
2138                         p = (struct dma_desc *)(priv->dma_erx + entry);
2139                 else
2140                         p = priv->dma_rx + entry;
2141
2142                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2143                         struct sk_buff *skb;
2144
2145                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2146
2147                         if (unlikely(skb == NULL))
2148                                 break;
2149
2150                         priv->rx_skbuff[entry] = skb;
2151                         priv->rx_skbuff_dma[entry] =
2152                             dma_map_single(priv->device, skb->data, bfsize,
2153                                            DMA_FROM_DEVICE);
2154                         if (dma_mapping_error(priv->device,
2155                                               priv->rx_skbuff_dma[entry])) {
2156                                 dev_err(priv->device, "Rx dma map failed\n");
2157                                 dev_kfree_skb(skb);
2158                                 break;
2159                         }
2160                         p->des2 = priv->rx_skbuff_dma[entry];
2161
2162                         priv->hw->mode->refill_desc3(priv, p);
2163
2164                         if (netif_msg_rx_status(priv))
2165                                 pr_debug("\trefill entry #%d\n", entry);
2166                 }
2167                 wmb();
2168                 priv->hw->desc->set_rx_owner(p);
2169                 wmb();
2170         }
2171 }
2172
2173 /**
2174  * stmmac_rx - manage the receive process
2175  * @priv: driver private structure
2176  * @limit: napi bugget.
2177  * Description :  this the function called by the napi poll method.
2178  * It gets all the frames inside the ring.
2179  */
2180 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2181 {
2182         unsigned int rxsize = priv->dma_rx_size;
2183         unsigned int next_entry = priv->cur_rx % rxsize;
2184         unsigned int count = 0;
2185         int coe = priv->hw->rx_csum;
2186
2187         if (netif_msg_rx_status(priv)) {
2188                 pr_debug("%s: descriptor ring:\n", __func__);
2189                 if (priv->extend_desc)
2190                         stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2191                 else
2192                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2193         }
2194         while (count < limit) {
2195                 int status, entry;
2196                 struct dma_desc *p;
2197
2198                 entry = next_entry;
2199
2200                 if (priv->extend_desc)
2201                         p = (struct dma_desc *)(priv->dma_erx + entry);
2202                 else
2203                         p = priv->dma_rx + entry;
2204
2205                 if (priv->hw->desc->get_rx_owner(p))
2206                         break;
2207
2208                 count++;
2209
2210                 next_entry = (++priv->cur_rx) % rxsize;
2211                 if (priv->extend_desc)
2212                         prefetch(priv->dma_erx + next_entry);
2213                 else
2214                         prefetch(priv->dma_rx + next_entry);
2215
2216                 /* read the status of the incoming frame */
2217                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2218                                                    &priv->xstats, p);
2219                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2220                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2221                                                            &priv->xstats,
2222                                                            priv->dma_erx +
2223                                                            entry);
2224                 if (unlikely(status == discard_frame)) {
2225                         priv->dev->stats.rx_errors++;
2226                         if (priv->hwts_rx_en && !priv->extend_desc) {
2227                                 /* DESC2 & DESC3 will be overwitten by device
2228                                  * with timestamp value, hence reinitialize
2229                                  * them in stmmac_rx_refill() function so that
2230                                  * device can reuse it.
2231                                  */
2232                                 priv->rx_skbuff[entry] = NULL;
2233                                 dma_unmap_single(priv->device,
2234                                                  priv->rx_skbuff_dma[entry],
2235                                                  priv->dma_buf_sz,
2236                                                  DMA_FROM_DEVICE);
2237                         }
2238                 } else {
2239                         struct sk_buff *skb;
2240                         int frame_len;
2241
2242                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2243
2244                         /*  check if frame_len fits the preallocated memory */
2245                         if (frame_len > priv->dma_buf_sz) {
2246                                 priv->dev->stats.rx_length_errors++;
2247                                 continue;
2248                         }
2249
2250                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2251                          * Type frames (LLC/LLC-SNAP)
2252                          */
2253                         if (unlikely(status != llc_snap))
2254                                 frame_len -= ETH_FCS_LEN;
2255
2256                         if (netif_msg_rx_status(priv)) {
2257                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2258                                          p, entry, p->des2);
2259                                 if (frame_len > ETH_FRAME_LEN)
2260                                         pr_debug("\tframe size %d, COE: %d\n",
2261                                                  frame_len, status);
2262                         }
2263                         skb = priv->rx_skbuff[entry];
2264                         if (unlikely(!skb)) {
2265                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
2266                                        priv->dev->name);
2267                                 priv->dev->stats.rx_dropped++;
2268                                 continue;
2269                         }
2270                         prefetch(skb->data - NET_IP_ALIGN);
2271                         priv->rx_skbuff[entry] = NULL;
2272
2273                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2274
2275                         skb_put(skb, frame_len);
2276                         dma_unmap_single(priv->device,
2277                                          priv->rx_skbuff_dma[entry],
2278                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
2279
2280                         if (netif_msg_pktdata(priv)) {
2281                                 pr_debug("frame received (%dbytes)", frame_len);
2282                                 print_pkt(skb->data, frame_len);
2283                         }
2284
2285                         stmmac_rx_vlan(priv->dev, skb);
2286
2287                         skb->protocol = eth_type_trans(skb, priv->dev);
2288
2289                         if (unlikely(!coe))
2290                                 skb_checksum_none_assert(skb);
2291                         else
2292                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2293
2294                         napi_gro_receive(&priv->napi, skb);
2295
2296                         priv->dev->stats.rx_packets++;
2297                         priv->dev->stats.rx_bytes += frame_len;
2298                 }
2299         }
2300
2301         stmmac_rx_refill(priv);
2302
2303         priv->xstats.rx_pkt_n += count;
2304
2305         return count;
2306 }
2307
2308 /**
2309  *  stmmac_poll - stmmac poll method (NAPI)
2310  *  @napi : pointer to the napi structure.
2311  *  @budget : maximum number of packets that the current CPU can receive from
2312  *            all interfaces.
2313  *  Description :
2314  *  To look at the incoming frames and clear the tx resources.
2315  */
2316 static int stmmac_poll(struct napi_struct *napi, int budget)
2317 {
2318         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2319         int work_done = 0;
2320
2321         priv->xstats.napi_poll++;
2322         stmmac_tx_clean(priv);
2323
2324         work_done = stmmac_rx(priv, budget);
2325         if (work_done < budget) {
2326                 napi_complete(napi);
2327                 stmmac_enable_dma_irq(priv);
2328         }
2329         return work_done;
2330 }
2331
2332 /**
2333  *  stmmac_tx_timeout
2334  *  @dev : Pointer to net device structure
2335  *  Description: this function is called when a packet transmission fails to
2336  *   complete within a reasonable time. The driver will mark the error in the
2337  *   netdev structure and arrange for the device to be reset to a sane state
2338  *   in order to transmit a new packet.
2339  */
2340 static void stmmac_tx_timeout(struct net_device *dev)
2341 {
2342         struct stmmac_priv *priv = netdev_priv(dev);
2343
2344         /* Clear Tx resources and restart transmitting again */
2345         stmmac_tx_err(priv);
2346 }
2347
2348 /**
2349  *  stmmac_set_rx_mode - entry point for multicast addressing
2350  *  @dev : pointer to the device structure
2351  *  Description:
2352  *  This function is a driver entry point which gets called by the kernel
2353  *  whenever multicast addresses must be enabled/disabled.
2354  *  Return value:
2355  *  void.
2356  */
2357 static void stmmac_set_rx_mode(struct net_device *dev)
2358 {
2359         struct stmmac_priv *priv = netdev_priv(dev);
2360
2361         priv->hw->mac->set_filter(priv->hw, dev);
2362 }
2363
2364 /**
2365  *  stmmac_change_mtu - entry point to change MTU size for the device.
2366  *  @dev : device pointer.
2367  *  @new_mtu : the new MTU size for the device.
2368  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2369  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2370  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2371  *  Return value:
2372  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2373  *  file on failure.
2374  */
2375 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2376 {
2377         struct stmmac_priv *priv = netdev_priv(dev);
2378         int max_mtu;
2379
2380         if (netif_running(dev)) {
2381                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2382                 return -EBUSY;
2383         }
2384
2385         if (priv->plat->enh_desc)
2386                 max_mtu = JUMBO_LEN;
2387         else
2388                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2389
2390         if (priv->plat->maxmtu < max_mtu)
2391                 max_mtu = priv->plat->maxmtu;
2392
2393         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2394                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2395                 return -EINVAL;
2396         }
2397
2398         dev->mtu = new_mtu;
2399         netdev_update_features(dev);
2400
2401         return 0;
2402 }
2403
2404 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2405                                              netdev_features_t features)
2406 {
2407         struct stmmac_priv *priv = netdev_priv(dev);
2408
2409         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2410                 features &= ~NETIF_F_RXCSUM;
2411
2412         if (!priv->plat->tx_coe)
2413                 features &= ~NETIF_F_ALL_CSUM;
2414
2415         /* Some GMAC devices have a bugged Jumbo frame support that
2416          * needs to have the Tx COE disabled for oversized frames
2417          * (due to limited buffer sizes). In this case we disable
2418          * the TX csum insertionin the TDES and not use SF.
2419          */
2420         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2421                 features &= ~NETIF_F_ALL_CSUM;
2422
2423         return features;
2424 }
2425
2426 static int stmmac_set_features(struct net_device *netdev,
2427                                netdev_features_t features)
2428 {
2429         struct stmmac_priv *priv = netdev_priv(netdev);
2430
2431         /* Keep the COE Type in case of csum is supporting */
2432         if (features & NETIF_F_RXCSUM)
2433                 priv->hw->rx_csum = priv->plat->rx_coe;
2434         else
2435                 priv->hw->rx_csum = 0;
2436         /* No check needed because rx_coe has been set before and it will be
2437          * fixed in case of issue.
2438          */
2439         priv->hw->mac->rx_ipc(priv->hw);
2440
2441         return 0;
2442 }
2443
2444 /**
2445  *  stmmac_interrupt - main ISR
2446  *  @irq: interrupt number.
2447  *  @dev_id: to pass the net device pointer.
2448  *  Description: this is the main driver interrupt service routine.
2449  *  It can call:
2450  *  o DMA service routine (to manage incoming frame reception and transmission
2451  *    status)
2452  *  o Core interrupts to manage: remote wake-up, management counter, LPI
2453  *    interrupts.
2454  */
2455 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2456 {
2457         struct net_device *dev = (struct net_device *)dev_id;
2458         struct stmmac_priv *priv = netdev_priv(dev);
2459
2460         if (priv->irq_wake)
2461                 pm_wakeup_event(priv->device, 0);
2462
2463         if (unlikely(!dev)) {
2464                 pr_err("%s: invalid dev pointer\n", __func__);
2465                 return IRQ_NONE;
2466         }
2467
2468         /* To handle GMAC own interrupts */
2469         if (priv->plat->has_gmac) {
2470                 int status = priv->hw->mac->host_irq_status(priv->hw,
2471                                                             &priv->xstats);
2472                 if (unlikely(status)) {
2473                         /* For LPI we need to save the tx status */
2474                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2475                                 priv->tx_path_in_lpi_mode = true;
2476                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2477                                 priv->tx_path_in_lpi_mode = false;
2478                 }
2479         }
2480
2481         /* To handle DMA interrupts */
2482         stmmac_dma_interrupt(priv);
2483
2484         return IRQ_HANDLED;
2485 }
2486
2487 #ifdef CONFIG_NET_POLL_CONTROLLER
2488 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2489  * to allow network I/O with interrupts disabled.
2490  */
2491 static void stmmac_poll_controller(struct net_device *dev)
2492 {
2493         disable_irq(dev->irq);
2494         stmmac_interrupt(dev->irq, dev);
2495         enable_irq(dev->irq);
2496 }
2497 #endif
2498
2499 /**
2500  *  stmmac_ioctl - Entry point for the Ioctl
2501  *  @dev: Device pointer.
2502  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2503  *  a proprietary structure used to pass information to the driver.
2504  *  @cmd: IOCTL command
2505  *  Description:
2506  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2507  */
2508 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2509 {
2510         struct stmmac_priv *priv = netdev_priv(dev);
2511         int ret = -EOPNOTSUPP;
2512
2513         if (!netif_running(dev))
2514                 return -EINVAL;
2515
2516         switch (cmd) {
2517         case SIOCGMIIPHY:
2518         case SIOCGMIIREG:
2519         case SIOCSMIIREG:
2520                 if (!priv->phydev)
2521                         return -EINVAL;
2522                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2523                 break;
2524         case SIOCSHWTSTAMP:
2525                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2526                 break;
2527         default:
2528                 break;
2529         }
2530
2531         return ret;
2532 }
2533
2534 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
2535 {
2536         struct stmmac_priv *priv = netdev_priv(ndev);
2537         int ret = 0;
2538
2539         ret = eth_mac_addr(ndev, addr);
2540         if (ret)
2541                 return ret;
2542
2543         priv->hw->mac->set_umac_addr(priv->hw, ndev->dev_addr, 0);
2544
2545         return ret;
2546 }
2547
2548 #ifdef CONFIG_DEBUG_FS
2549 static struct dentry *stmmac_fs_dir;
2550
2551 static void sysfs_display_ring(void *head, int size, int extend_desc,
2552                                struct seq_file *seq)
2553 {
2554         int i;
2555         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2556         struct dma_desc *p = (struct dma_desc *)head;
2557
2558         for (i = 0; i < size; i++) {
2559                 u64 x;
2560                 if (extend_desc) {
2561                         x = *(u64 *) ep;
2562                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2563                                    i, (unsigned int)virt_to_phys(ep),
2564                                    (unsigned int)x, (unsigned int)(x >> 32),
2565                                    ep->basic.des2, ep->basic.des3);
2566                         ep++;
2567                 } else {
2568                         x = *(u64 *) p;
2569                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2570                                    i, (unsigned int)virt_to_phys(ep),
2571                                    (unsigned int)x, (unsigned int)(x >> 32),
2572                                    p->des2, p->des3);
2573                         p++;
2574                 }
2575                 seq_printf(seq, "\n");
2576         }
2577 }
2578
2579 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2580 {
2581         struct net_device *dev = seq->private;
2582         struct stmmac_priv *priv = netdev_priv(dev);
2583         unsigned int txsize = priv->dma_tx_size;
2584         unsigned int rxsize = priv->dma_rx_size;
2585
2586         if (priv->extend_desc) {
2587                 seq_printf(seq, "Extended RX descriptor ring:\n");
2588                 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2589                 seq_printf(seq, "Extended TX descriptor ring:\n");
2590                 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2591         } else {
2592                 seq_printf(seq, "RX descriptor ring:\n");
2593                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2594                 seq_printf(seq, "TX descriptor ring:\n");
2595                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2596         }
2597
2598         return 0;
2599 }
2600
2601 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2602 {
2603         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2604 }
2605
2606 static const struct file_operations stmmac_rings_status_fops = {
2607         .owner = THIS_MODULE,
2608         .open = stmmac_sysfs_ring_open,
2609         .read = seq_read,
2610         .llseek = seq_lseek,
2611         .release = single_release,
2612 };
2613
2614 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2615 {
2616         struct net_device *dev = seq->private;
2617         struct stmmac_priv *priv = netdev_priv(dev);
2618
2619         if (!priv->hw_cap_support) {
2620                 seq_printf(seq, "DMA HW features not supported\n");
2621                 return 0;
2622         }
2623
2624         seq_printf(seq, "==============================\n");
2625         seq_printf(seq, "\tDMA HW features\n");
2626         seq_printf(seq, "==============================\n");
2627
2628         seq_printf(seq, "\t10/100 Mbps %s\n",
2629                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2630         seq_printf(seq, "\t1000 Mbps %s\n",
2631                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2632         seq_printf(seq, "\tHalf duple %s\n",
2633                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2634         seq_printf(seq, "\tHash Filter: %s\n",
2635                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2636         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2637                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2638         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2639                    (priv->dma_cap.pcs) ? "Y" : "N");
2640         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2641                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2642         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2643                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2644         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2645                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2646         seq_printf(seq, "\tRMON module: %s\n",
2647                    (priv->dma_cap.rmon) ? "Y" : "N");
2648         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2649                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2650         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2651                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2652         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2653                    (priv->dma_cap.eee) ? "Y" : "N");
2654         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2655         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2656                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2657         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2658                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2659         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2660                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2661         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2662                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2663         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2664                    priv->dma_cap.number_rx_channel);
2665         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2666                    priv->dma_cap.number_tx_channel);
2667         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2668                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2669
2670         return 0;
2671 }
2672
2673 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2674 {
2675         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2676 }
2677
2678 static const struct file_operations stmmac_dma_cap_fops = {
2679         .owner = THIS_MODULE,
2680         .open = stmmac_sysfs_dma_cap_open,
2681         .read = seq_read,
2682         .llseek = seq_lseek,
2683         .release = single_release,
2684 };
2685
2686 static int stmmac_init_fs(struct net_device *dev)
2687 {
2688         struct stmmac_priv *priv = netdev_priv(dev);
2689
2690         /* Create per netdev entries */
2691         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
2692
2693         if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
2694                 pr_err("ERROR %s/%s, debugfs create directory failed\n",
2695                        STMMAC_RESOURCE_NAME, dev->name);
2696
2697                 return -ENOMEM;
2698         }
2699
2700         /* Entry to report DMA RX/TX rings */
2701         priv->dbgfs_rings_status =
2702                 debugfs_create_file("descriptors_status", S_IRUGO,
2703                                     priv->dbgfs_dir, dev,
2704                                     &stmmac_rings_status_fops);
2705
2706         if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
2707                 pr_info("ERROR creating stmmac ring debugfs file\n");
2708                 debugfs_remove_recursive(priv->dbgfs_dir);
2709
2710                 return -ENOMEM;
2711         }
2712
2713         /* Entry to report the DMA HW features */
2714         priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
2715                                             priv->dbgfs_dir,
2716                                             dev, &stmmac_dma_cap_fops);
2717
2718         if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
2719                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2720                 debugfs_remove_recursive(priv->dbgfs_dir);
2721
2722                 return -ENOMEM;
2723         }
2724
2725         return 0;
2726 }
2727
2728 static void stmmac_exit_fs(struct net_device *dev)
2729 {
2730         struct stmmac_priv *priv = netdev_priv(dev);
2731
2732         debugfs_remove_recursive(priv->dbgfs_dir);
2733 }
2734 #endif /* CONFIG_DEBUG_FS */
2735
2736 static const struct net_device_ops stmmac_netdev_ops = {
2737         .ndo_open = stmmac_open,
2738         .ndo_start_xmit = stmmac_xmit,
2739         .ndo_stop = stmmac_release,
2740         .ndo_change_mtu = stmmac_change_mtu,
2741         .ndo_fix_features = stmmac_fix_features,
2742         .ndo_set_features = stmmac_set_features,
2743         .ndo_set_rx_mode = stmmac_set_rx_mode,
2744         .ndo_tx_timeout = stmmac_tx_timeout,
2745         .ndo_do_ioctl = stmmac_ioctl,
2746 #ifdef CONFIG_NET_POLL_CONTROLLER
2747         .ndo_poll_controller = stmmac_poll_controller,
2748 #endif
2749         .ndo_set_mac_address = stmmac_set_mac_address,
2750 };
2751
2752 /**
2753  *  stmmac_hw_init - Init the MAC device
2754  *  @priv: driver private structure
2755  *  Description: this function is to configure the MAC device according to
2756  *  some platform parameters or the HW capability register. It prepares the
2757  *  driver to use either ring or chain modes and to setup either enhanced or
2758  *  normal descriptors.
2759  */
2760 static int stmmac_hw_init(struct stmmac_priv *priv)
2761 {
2762         struct mac_device_info *mac;
2763
2764         /* Identify the MAC HW device */
2765         if (priv->plat->has_gmac) {
2766                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2767                 mac = dwmac1000_setup(priv->ioaddr,
2768                                       priv->plat->multicast_filter_bins,
2769                                       priv->plat->unicast_filter_entries);
2770         } else {
2771                 mac = dwmac100_setup(priv->ioaddr);
2772         }
2773         if (!mac)
2774                 return -ENOMEM;
2775
2776         priv->hw = mac;
2777
2778         /* Get and dump the chip ID */
2779         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2780
2781         /* To use the chained or ring mode */
2782         if (chain_mode) {
2783                 priv->hw->mode = &chain_mode_ops;
2784                 pr_info(" Chain mode enabled\n");
2785                 priv->mode = STMMAC_CHAIN_MODE;
2786         } else {
2787                 priv->hw->mode = &ring_mode_ops;
2788                 pr_info(" Ring mode enabled\n");
2789                 priv->mode = STMMAC_RING_MODE;
2790         }
2791
2792         /* Get the HW capability (new GMAC newer than 3.50a) */
2793         priv->hw_cap_support = stmmac_get_hw_features(priv);
2794         if (priv->hw_cap_support) {
2795                 pr_info(" DMA HW capability register supported");
2796
2797                 /* We can override some gmac/dma configuration fields: e.g.
2798                  * enh_desc, tx_coe (e.g. that are passed through the
2799                  * platform) with the values from the HW capability
2800                  * register (if supported).
2801                  */
2802                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2803                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2804
2805                 /* TXCOE doesn't work in thresh DMA mode */
2806                 if (priv->plat->force_thresh_dma_mode)
2807                         priv->plat->tx_coe = 0;
2808                 else
2809                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
2810
2811                 if (priv->dma_cap.rx_coe_type2)
2812                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2813                 else if (priv->dma_cap.rx_coe_type1)
2814                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2815
2816         } else
2817                 pr_info(" No HW DMA feature register supported");
2818
2819         /* To use alternate (extended) or normal descriptor structures */
2820         stmmac_selec_desc_mode(priv);
2821
2822         if (priv->plat->rx_coe) {
2823                 priv->hw->rx_csum = priv->plat->rx_coe;
2824                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2825                         priv->plat->rx_coe);
2826         }
2827         if (priv->plat->tx_coe)
2828                 pr_info(" TX Checksum insertion supported\n");
2829
2830         if (priv->plat->pmt) {
2831                 pr_info(" Wake-Up On Lan supported\n");
2832                 device_set_wakeup_capable(priv->device, 1);
2833         }
2834
2835         return 0;
2836 }
2837
2838 /**
2839  * stmmac_dvr_probe
2840  * @device: device pointer
2841  * @plat_dat: platform data pointer
2842  * @res: stmmac resource pointer
2843  * Description: this is the main probe function used to
2844  * call the alloc_etherdev, allocate the priv structure.
2845  * Return:
2846  * returns 0 on success, otherwise errno.
2847  */
2848 int stmmac_dvr_probe(struct device *device,
2849                      struct plat_stmmacenet_data *plat_dat,
2850                      struct stmmac_resources *res)
2851 {
2852         int ret = 0;
2853         struct net_device *ndev = NULL;
2854         struct stmmac_priv *priv;
2855
2856         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2857         if (!ndev)
2858                 return -ENOMEM;
2859
2860         SET_NETDEV_DEV(ndev, device);
2861
2862         priv = netdev_priv(ndev);
2863         priv->device = device;
2864         priv->dev = ndev;
2865
2866         stmmac_set_ethtool_ops(ndev);
2867         priv->pause = pause;
2868         priv->plat = plat_dat;
2869         priv->ioaddr = res->addr;
2870         priv->dev->base_addr = (unsigned long)res->addr;
2871
2872         priv->dev->irq = res->irq;
2873         priv->wol_irq = res->wol_irq;
2874         priv->lpi_irq = res->lpi_irq;
2875
2876         if (res->mac)
2877                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
2878
2879         dev_set_drvdata(device, priv->dev);
2880
2881         /* Verify driver arguments */
2882         stmmac_verify_args();
2883
2884         /* Override with kernel parameters if supplied XXX CRS XXX
2885          * this needs to have multiple instances
2886          */
2887         if ((phyaddr >= 0) && (phyaddr <= 31))
2888                 priv->plat->phy_addr = phyaddr;
2889
2890         priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
2891         if (IS_ERR(priv->stmmac_clk)) {
2892                 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
2893                          __func__);
2894                 /* If failed to obtain stmmac_clk and specific clk_csr value
2895                  * is NOT passed from the platform, probe fail.
2896                  */
2897                 if (!priv->plat->clk_csr) {
2898                         ret = PTR_ERR(priv->stmmac_clk);
2899                         goto error_clk_get;
2900                 } else {
2901                         priv->stmmac_clk = NULL;
2902                 }
2903         }
2904         clk_prepare_enable(priv->stmmac_clk);
2905
2906         priv->pclk = devm_clk_get(priv->device, "pclk");
2907         if (IS_ERR(priv->pclk)) {
2908                 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
2909                         ret = -EPROBE_DEFER;
2910                         goto error_pclk_get;
2911                 }
2912                 priv->pclk = NULL;
2913         }
2914         clk_prepare_enable(priv->pclk);
2915
2916         priv->stmmac_rst = devm_reset_control_get(priv->device,
2917                                                   STMMAC_RESOURCE_NAME);
2918         if (IS_ERR(priv->stmmac_rst)) {
2919                 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
2920                         ret = -EPROBE_DEFER;
2921                         goto error_hw_init;
2922                 }
2923                 dev_info(priv->device, "no reset control found\n");
2924                 priv->stmmac_rst = NULL;
2925         }
2926         if (priv->stmmac_rst)
2927                 reset_control_deassert(priv->stmmac_rst);
2928
2929         /* Init MAC and get the capabilities */
2930         ret = stmmac_hw_init(priv);
2931         if (ret)
2932                 goto error_hw_init;
2933
2934         stmmac_check_ether_addr(priv);
2935
2936         ndev->netdev_ops = &stmmac_netdev_ops;
2937
2938         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2939                             NETIF_F_RXCSUM;
2940         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2941         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2942 #ifdef STMMAC_VLAN_TAG_USED
2943         /* Both mac100 and gmac support receive VLAN tag detection */
2944         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2945 #endif
2946         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2947
2948         if (flow_ctrl)
2949                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2950
2951         /* Rx Watchdog is available in the COREs newer than the 3.40.
2952          * In some case, for example on bugged HW this feature
2953          * has to be disable and this can be done by passing the
2954          * riwt_off field from the platform.
2955          */
2956         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2957                 priv->use_riwt = 1;
2958                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2959         }
2960
2961         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2962
2963         spin_lock_init(&priv->lock);
2964         spin_lock_init(&priv->tx_lock);
2965
2966         /* If a specific clk_csr value is passed from the platform
2967          * this means that the CSR Clock Range selection cannot be
2968          * changed at run-time and it is fixed. Viceversa the driver'll try to
2969          * set the MDC clock dynamically according to the csr actual
2970          * clock input.
2971          */
2972         if (!priv->plat->clk_csr)
2973                 stmmac_clk_csr_set(priv);
2974         else
2975                 priv->clk_csr = priv->plat->clk_csr;
2976
2977         stmmac_check_pcs_mode(priv);
2978
2979         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2980             priv->pcs != STMMAC_PCS_RTBI) {
2981                 /* MDIO bus Registration */
2982                 ret = stmmac_mdio_register(ndev);
2983                 if (ret < 0) {
2984                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2985                                  __func__, priv->plat->bus_id);
2986                         goto error_mdio_register;
2987                 }
2988         }
2989
2990         ret = register_netdev(ndev);
2991         if (ret) {
2992                 netdev_err(priv->dev, "%s: ERROR %i registering the device\n",
2993                            __func__, ret);
2994                 goto error_netdev_register;
2995         }
2996
2997         return ret;
2998
2999 error_netdev_register:
3000         if (priv->pcs != STMMAC_PCS_RGMII &&
3001             priv->pcs != STMMAC_PCS_TBI &&
3002             priv->pcs != STMMAC_PCS_RTBI)
3003                 stmmac_mdio_unregister(ndev);
3004 error_mdio_register:
3005         netif_napi_del(&priv->napi);
3006 error_hw_init:
3007         clk_disable_unprepare(priv->pclk);
3008 error_pclk_get:
3009         clk_disable_unprepare(priv->stmmac_clk);
3010 error_clk_get:
3011         free_netdev(ndev);
3012
3013         return ret;
3014 }
3015 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
3016
3017 /**
3018  * stmmac_dvr_remove
3019  * @ndev: net device pointer
3020  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
3021  * changes the link status, releases the DMA descriptor rings.
3022  */
3023 int stmmac_dvr_remove(struct net_device *ndev)
3024 {
3025         struct stmmac_priv *priv = netdev_priv(ndev);
3026
3027         pr_info("%s:\n\tremoving driver", __func__);
3028
3029         priv->hw->dma->stop_rx(priv->ioaddr);
3030         priv->hw->dma->stop_tx(priv->ioaddr);
3031
3032         stmmac_set_mac(priv->ioaddr, false);
3033         netif_carrier_off(ndev);
3034         unregister_netdev(ndev);
3035         if (priv->stmmac_rst)
3036                 reset_control_assert(priv->stmmac_rst);
3037         clk_disable_unprepare(priv->pclk);
3038         clk_disable_unprepare(priv->stmmac_clk);
3039         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
3040             priv->pcs != STMMAC_PCS_RTBI)
3041                 stmmac_mdio_unregister(ndev);
3042         free_netdev(ndev);
3043
3044         return 0;
3045 }
3046 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
3047
3048 /**
3049  * stmmac_suspend - suspend callback
3050  * @ndev: net device pointer
3051  * Description: this is the function to suspend the device and it is called
3052  * by the platform driver to stop the network queue, release the resources,
3053  * program the PMT register (for WoL), clean and release driver resources.
3054  */
3055 int stmmac_suspend(struct net_device *ndev)
3056 {
3057         struct stmmac_priv *priv = netdev_priv(ndev);
3058         unsigned long flags;
3059
3060         if (!ndev || !netif_running(ndev))
3061                 return 0;
3062
3063         if (priv->phydev)
3064                 phy_stop(priv->phydev);
3065
3066         spin_lock_irqsave(&priv->lock, flags);
3067
3068         netif_device_detach(ndev);
3069         netif_stop_queue(ndev);
3070
3071         napi_disable(&priv->napi);
3072
3073         if (priv->eee_enabled) {
3074                 priv->tx_path_in_lpi_mode = false;
3075                 del_timer_sync(&priv->eee_ctrl_timer);
3076         }
3077
3078         /* Stop TX/RX DMA */
3079         priv->hw->dma->stop_tx(priv->ioaddr);
3080         priv->hw->dma->stop_rx(priv->ioaddr);
3081
3082         /* Enable Power down mode by programming the PMT regs */
3083         if (device_may_wakeup(priv->device)) {
3084                 priv->hw->mac->pmt(priv->hw, priv->wolopts);
3085                 priv->irq_wake = 1;
3086         } else {
3087                 stmmac_set_mac(priv->ioaddr, false);
3088                 pinctrl_pm_select_sleep_state(priv->device);
3089                 /* Disable clock in case of PWM is off */
3090                 clk_disable(priv->pclk);
3091                 clk_disable(priv->stmmac_clk);
3092         }
3093         spin_unlock_irqrestore(&priv->lock, flags);
3094
3095         priv->oldlink = 0;
3096         priv->speed = 0;
3097         priv->oldduplex = -1;
3098         return 0;
3099 }
3100 EXPORT_SYMBOL_GPL(stmmac_suspend);
3101
3102 /**
3103  * stmmac_resume - resume callback
3104  * @ndev: net device pointer
3105  * Description: when resume this function is invoked to setup the DMA and CORE
3106  * in a usable state.
3107  */
3108 int stmmac_resume(struct net_device *ndev)
3109 {
3110         struct stmmac_priv *priv = netdev_priv(ndev);
3111         unsigned long flags;
3112
3113         if (!netif_running(ndev))
3114                 return 0;
3115
3116         spin_lock_irqsave(&priv->lock, flags);
3117
3118         /* Power Down bit, into the PM register, is cleared
3119          * automatically as soon as a magic packet or a Wake-up frame
3120          * is received. Anyway, it's better to manually clear
3121          * this bit because it can generate problems while resuming
3122          * from another devices (e.g. serial console).
3123          */
3124         if (device_may_wakeup(priv->device)) {
3125                 priv->hw->mac->pmt(priv->hw, 0);
3126                 priv->irq_wake = 0;
3127         } else {
3128                 pinctrl_pm_select_default_state(priv->device);
3129                 /* enable the clk prevously disabled */
3130                 clk_enable(priv->stmmac_clk);
3131                 clk_enable(priv->pclk);
3132                 /* reset the phy so that it's ready */
3133                 if (priv->mii)
3134                         stmmac_mdio_reset(priv->mii);
3135         }
3136
3137         netif_device_attach(ndev);
3138
3139         priv->cur_rx = 0;
3140         priv->dirty_rx = 0;
3141         priv->dirty_tx = 0;
3142         priv->cur_tx = 0;
3143         stmmac_clear_descriptors(priv);
3144
3145         stmmac_hw_setup(ndev, false);
3146         stmmac_init_tx_coalesce(priv);
3147         stmmac_set_rx_mode(ndev);
3148
3149         napi_enable(&priv->napi);
3150
3151         netif_start_queue(ndev);
3152
3153         spin_unlock_irqrestore(&priv->lock, flags);
3154
3155         if (priv->phydev)
3156                 phy_start(priv->phydev);
3157
3158         return 0;
3159 }
3160 EXPORT_SYMBOL_GPL(stmmac_resume);
3161
3162 #ifndef MODULE
3163 static int __init stmmac_cmdline_opt(char *str)
3164 {
3165         char *opt;
3166
3167         if (!str || !*str)
3168                 return -EINVAL;
3169         while ((opt = strsep(&str, ",")) != NULL) {
3170                 if (!strncmp(opt, "debug:", 6)) {
3171                         if (kstrtoint(opt + 6, 0, &debug))
3172                                 goto err;
3173                 } else if (!strncmp(opt, "phyaddr:", 8)) {
3174                         if (kstrtoint(opt + 8, 0, &phyaddr))
3175                                 goto err;
3176                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
3177                         if (kstrtoint(opt + 11, 0, &dma_txsize))
3178                                 goto err;
3179                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
3180                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
3181                                 goto err;
3182                 } else if (!strncmp(opt, "buf_sz:", 7)) {
3183                         if (kstrtoint(opt + 7, 0, &buf_sz))
3184                                 goto err;
3185                 } else if (!strncmp(opt, "tc:", 3)) {
3186                         if (kstrtoint(opt + 3, 0, &tc))
3187                                 goto err;
3188                 } else if (!strncmp(opt, "watchdog:", 9)) {
3189                         if (kstrtoint(opt + 9, 0, &watchdog))
3190                                 goto err;
3191                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3192                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
3193                                 goto err;
3194                 } else if (!strncmp(opt, "pause:", 6)) {
3195                         if (kstrtoint(opt + 6, 0, &pause))
3196                                 goto err;
3197                 } else if (!strncmp(opt, "eee_timer:", 10)) {
3198                         if (kstrtoint(opt + 10, 0, &eee_timer))
3199                                 goto err;
3200                 } else if (!strncmp(opt, "chain_mode:", 11)) {
3201                         if (kstrtoint(opt + 11, 0, &chain_mode))
3202                                 goto err;
3203                 }
3204         }
3205         return 0;
3206
3207 err:
3208         pr_err("%s: ERROR broken module parameter conversion", __func__);
3209         return -EINVAL;
3210 }
3211
3212 __setup("stmmaceth=", stmmac_cmdline_opt);
3213 #endif /* MODULE */
3214
3215 static int __init stmmac_init(void)
3216 {
3217 #ifdef CONFIG_DEBUG_FS
3218         /* Create debugfs main directory if it doesn't exist yet */
3219         if (!stmmac_fs_dir) {
3220                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
3221
3222                 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
3223                         pr_err("ERROR %s, debugfs create directory failed\n",
3224                                STMMAC_RESOURCE_NAME);
3225
3226                         return -ENOMEM;
3227                 }
3228         }
3229 #endif
3230
3231         return 0;
3232 }
3233
3234 static void __exit stmmac_exit(void)
3235 {
3236 #ifdef CONFIG_DEBUG_FS
3237         debugfs_remove_recursive(stmmac_fs_dir);
3238 #endif
3239 }
3240
3241 module_init(stmmac_init)
3242 module_exit(stmmac_exit)
3243
3244 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3245 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3246 MODULE_LICENSE("GPL");