1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 The full GNU General Public License is included in this distribution in
17 the file called "COPYING".
19 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
21 Documentation available at:
22 http://www.stlinux.com
24 https://bugzilla.stlinux.com/
25 *******************************************************************************/
27 #include <linux/clk.h>
28 #include <linux/kernel.h>
29 #include <linux/interrupt.h>
31 #include <linux/tcp.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/if_ether.h>
35 #include <linux/crc32.h>
36 #include <linux/mii.h>
38 #include <linux/if_vlan.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/prefetch.h>
42 #include <linux/pinctrl/consumer.h>
43 #ifdef CONFIG_DEBUG_FS
44 #include <linux/debugfs.h>
45 #include <linux/seq_file.h>
46 #endif /* CONFIG_DEBUG_FS */
47 #include <linux/net_tstamp.h>
48 #include "stmmac_ptp.h"
50 #include <linux/reset.h>
51 #include <linux/of_mdio.h>
52 #include "dwmac1000.h"
54 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16)
55 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
57 /* Module parameters */
59 static int watchdog = TX_TIMEO;
60 module_param(watchdog, int, S_IRUGO | S_IWUSR);
61 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
63 static int debug = -1;
64 module_param(debug, int, S_IRUGO | S_IWUSR);
65 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
67 static int phyaddr = -1;
68 module_param(phyaddr, int, S_IRUGO);
69 MODULE_PARM_DESC(phyaddr, "Physical device address");
71 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
72 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
74 static int flow_ctrl = FLOW_OFF;
75 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
76 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
78 static int pause = PAUSE_TIME;
79 module_param(pause, int, S_IRUGO | S_IWUSR);
80 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
83 static int tc = TC_DEFAULT;
84 module_param(tc, int, S_IRUGO | S_IWUSR);
85 MODULE_PARM_DESC(tc, "DMA threshold control value");
87 #define DEFAULT_BUFSIZE 1536
88 static int buf_sz = DEFAULT_BUFSIZE;
89 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
90 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
92 #define STMMAC_RX_COPYBREAK 256
94 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
95 NETIF_MSG_LINK | NETIF_MSG_IFUP |
96 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
98 #define STMMAC_DEFAULT_LPI_TIMER 1000
99 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
100 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
101 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
102 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
104 /* By default the driver will use the ring mode to manage tx and rx descriptors,
105 * but allow user to force to use the chain instead of the ring
107 static unsigned int chain_mode;
108 module_param(chain_mode, int, S_IRUGO);
109 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
111 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
113 #ifdef CONFIG_DEBUG_FS
114 static int stmmac_init_fs(struct net_device *dev);
115 static void stmmac_exit_fs(struct net_device *dev);
118 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
121 * stmmac_verify_args - verify the driver parameters.
122 * Description: it checks the driver parameters and set a default in case of
125 static void stmmac_verify_args(void)
127 if (unlikely(watchdog < 0))
129 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
130 buf_sz = DEFAULT_BUFSIZE;
131 if (unlikely(flow_ctrl > 1))
132 flow_ctrl = FLOW_AUTO;
133 else if (likely(flow_ctrl < 0))
134 flow_ctrl = FLOW_OFF;
135 if (unlikely((pause < 0) || (pause > 0xffff)))
138 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
142 * stmmac_disable_all_queues - Disable all queues
143 * @priv: driver private structure
145 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
147 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
150 for (queue = 0; queue < rx_queues_cnt; queue++) {
151 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
153 napi_disable(&rx_q->napi);
158 * stmmac_enable_all_queues - Enable all queues
159 * @priv: driver private structure
161 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
163 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
166 for (queue = 0; queue < rx_queues_cnt; queue++) {
167 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
169 napi_enable(&rx_q->napi);
174 * stmmac_stop_all_queues - Stop all queues
175 * @priv: driver private structure
177 static void stmmac_stop_all_queues(struct stmmac_priv *priv)
179 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
182 for (queue = 0; queue < tx_queues_cnt; queue++)
183 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
187 * stmmac_start_all_queues - Start all queues
188 * @priv: driver private structure
190 static void stmmac_start_all_queues(struct stmmac_priv *priv)
192 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
195 for (queue = 0; queue < tx_queues_cnt; queue++)
196 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
200 * stmmac_clk_csr_set - dynamically set the MDC clock
201 * @priv: driver private structure
202 * Description: this is to dynamically set the MDC clock according to the csr
205 * If a specific clk_csr value is passed from the platform
206 * this means that the CSR Clock Range selection cannot be
207 * changed at run-time and it is fixed (as reported in the driver
208 * documentation). Viceversa the driver will try to set the MDC
209 * clock dynamically according to the actual clock input.
211 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
215 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
217 /* Platform provided default clk_csr would be assumed valid
218 * for all other cases except for the below mentioned ones.
219 * For values higher than the IEEE 802.3 specified frequency
220 * we can not estimate the proper divider as it is not known
221 * the frequency of clk_csr_i. So we do not change the default
224 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
225 if (clk_rate < CSR_F_35M)
226 priv->clk_csr = STMMAC_CSR_20_35M;
227 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
228 priv->clk_csr = STMMAC_CSR_35_60M;
229 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
230 priv->clk_csr = STMMAC_CSR_60_100M;
231 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
232 priv->clk_csr = STMMAC_CSR_100_150M;
233 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
234 priv->clk_csr = STMMAC_CSR_150_250M;
235 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
236 priv->clk_csr = STMMAC_CSR_250_300M;
239 if (priv->plat->has_sun8i) {
240 if (clk_rate > 160000000)
241 priv->clk_csr = 0x03;
242 else if (clk_rate > 80000000)
243 priv->clk_csr = 0x02;
244 else if (clk_rate > 40000000)
245 priv->clk_csr = 0x01;
251 static void print_pkt(unsigned char *buf, int len)
253 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
254 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
257 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
259 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
262 if (tx_q->dirty_tx > tx_q->cur_tx)
263 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
265 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
271 * stmmac_rx_dirty - Get RX queue dirty
272 * @priv: driver private structure
273 * @queue: RX queue index
275 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
277 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
280 if (rx_q->dirty_rx <= rx_q->cur_rx)
281 dirty = rx_q->cur_rx - rx_q->dirty_rx;
283 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
289 * stmmac_hw_fix_mac_speed - callback for speed selection
290 * @priv: driver private structure
291 * Description: on some platforms (e.g. ST), some HW system configuration
292 * registers have to be set according to the link speed negotiated.
294 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
296 struct net_device *ndev = priv->dev;
297 struct phy_device *phydev = ndev->phydev;
299 if (likely(priv->plat->fix_mac_speed))
300 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
304 * stmmac_enable_eee_mode - check and enter in LPI mode
305 * @priv: driver private structure
306 * Description: this function is to verify and enter in LPI mode in case of
309 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
311 u32 tx_cnt = priv->plat->tx_queues_to_use;
314 /* check if all TX queues have the work finished */
315 for (queue = 0; queue < tx_cnt; queue++) {
316 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
318 if (tx_q->dirty_tx != tx_q->cur_tx)
319 return; /* still unfinished work */
322 /* Check and enter in LPI mode */
323 if (!priv->tx_path_in_lpi_mode)
324 priv->hw->mac->set_eee_mode(priv->hw,
325 priv->plat->en_tx_lpi_clockgating);
329 * stmmac_disable_eee_mode - disable and exit from LPI mode
330 * @priv: driver private structure
331 * Description: this function is to exit and disable EEE in case of
332 * LPI state is true. This is called by the xmit.
334 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
336 priv->hw->mac->reset_eee_mode(priv->hw);
337 del_timer_sync(&priv->eee_ctrl_timer);
338 priv->tx_path_in_lpi_mode = false;
342 * stmmac_eee_ctrl_timer - EEE TX SW timer.
345 * if there is no data transfer and if we are not in LPI state,
346 * then MAC Transmitter can be moved to LPI state.
348 static void stmmac_eee_ctrl_timer(unsigned long arg)
350 struct stmmac_priv *priv = (struct stmmac_priv *)arg;
352 stmmac_enable_eee_mode(priv);
353 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
357 * stmmac_eee_init - init EEE
358 * @priv: driver private structure
360 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
361 * can also manage EEE, this function enable the LPI state and start related
364 bool stmmac_eee_init(struct stmmac_priv *priv)
366 struct net_device *ndev = priv->dev;
367 int interface = priv->plat->interface;
370 if ((interface != PHY_INTERFACE_MODE_MII) &&
371 (interface != PHY_INTERFACE_MODE_GMII) &&
372 !phy_interface_mode_is_rgmii(interface))
375 /* Using PCS we cannot dial with the phy registers at this stage
376 * so we do not support extra feature like EEE.
378 if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
379 (priv->hw->pcs == STMMAC_PCS_TBI) ||
380 (priv->hw->pcs == STMMAC_PCS_RTBI))
383 /* MAC core supports the EEE feature. */
384 if (priv->dma_cap.eee) {
385 int tx_lpi_timer = priv->tx_lpi_timer;
387 /* Check if the PHY supports EEE */
388 if (phy_init_eee(ndev->phydev, 1)) {
389 /* To manage at run-time if the EEE cannot be supported
390 * anymore (for example because the lp caps have been
392 * In that case the driver disable own timers.
394 mutex_lock(&priv->lock);
395 if (priv->eee_active) {
396 netdev_dbg(priv->dev, "disable EEE\n");
397 del_timer_sync(&priv->eee_ctrl_timer);
398 priv->hw->mac->set_eee_timer(priv->hw, 0,
401 priv->eee_active = 0;
402 mutex_unlock(&priv->lock);
405 /* Activate the EEE and start timers */
406 mutex_lock(&priv->lock);
407 if (!priv->eee_active) {
408 priv->eee_active = 1;
409 setup_timer(&priv->eee_ctrl_timer,
410 stmmac_eee_ctrl_timer,
411 (unsigned long)priv);
412 mod_timer(&priv->eee_ctrl_timer,
413 STMMAC_LPI_T(eee_timer));
415 priv->hw->mac->set_eee_timer(priv->hw,
416 STMMAC_DEFAULT_LIT_LS,
419 /* Set HW EEE according to the speed */
420 priv->hw->mac->set_eee_pls(priv->hw, ndev->phydev->link);
423 mutex_unlock(&priv->lock);
425 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
431 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
432 * @priv: driver private structure
433 * @p : descriptor pointer
434 * @skb : the socket buffer
436 * This function will read timestamp from the descriptor & pass it to stack.
437 * and also perform some sanity checks.
439 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
440 struct dma_desc *p, struct sk_buff *skb)
442 struct skb_shared_hwtstamps shhwtstamp;
445 if (!priv->hwts_tx_en)
448 /* exit if skb doesn't support hw tstamp */
449 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
452 /* check tx tstamp status */
453 if (priv->hw->desc->get_tx_timestamp_status(p)) {
454 /* get the valid tstamp */
455 ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
457 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
458 shhwtstamp.hwtstamp = ns_to_ktime(ns);
460 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
461 /* pass tstamp to stack */
462 skb_tstamp_tx(skb, &shhwtstamp);
468 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
469 * @priv: driver private structure
470 * @p : descriptor pointer
471 * @np : next descriptor pointer
472 * @skb : the socket buffer
474 * This function will read received packet's timestamp from the descriptor
475 * and pass it to stack. It also perform some sanity checks.
477 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
478 struct dma_desc *np, struct sk_buff *skb)
480 struct skb_shared_hwtstamps *shhwtstamp = NULL;
481 struct dma_desc *desc = p;
484 if (!priv->hwts_rx_en)
486 /* For GMAC4, the valid timestamp is from CTX next desc. */
487 if (priv->plat->has_gmac4)
490 /* Check if timestamp is available */
491 if (priv->hw->desc->get_rx_timestamp_status(p, np, priv->adv_ts)) {
492 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
493 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
494 shhwtstamp = skb_hwtstamps(skb);
495 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
496 shhwtstamp->hwtstamp = ns_to_ktime(ns);
498 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
503 * stmmac_hwtstamp_ioctl - control hardware timestamping.
504 * @dev: device pointer.
505 * @ifr: An IOCTL specific structure, that can contain a pointer to
506 * a proprietary structure used to pass information to the driver.
508 * This function configures the MAC to enable/disable both outgoing(TX)
509 * and incoming(RX) packets time stamping based on user input.
511 * 0 on success and an appropriate -ve integer on failure.
513 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
515 struct stmmac_priv *priv = netdev_priv(dev);
516 struct hwtstamp_config config;
517 struct timespec64 now;
521 u32 ptp_over_ipv4_udp = 0;
522 u32 ptp_over_ipv6_udp = 0;
523 u32 ptp_over_ethernet = 0;
524 u32 snap_type_sel = 0;
525 u32 ts_master_en = 0;
530 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
531 netdev_alert(priv->dev, "No support for HW time stamping\n");
532 priv->hwts_tx_en = 0;
533 priv->hwts_rx_en = 0;
538 if (copy_from_user(&config, ifr->ifr_data,
539 sizeof(struct hwtstamp_config)))
542 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
543 __func__, config.flags, config.tx_type, config.rx_filter);
545 /* reserved for future extensions */
549 if (config.tx_type != HWTSTAMP_TX_OFF &&
550 config.tx_type != HWTSTAMP_TX_ON)
554 switch (config.rx_filter) {
555 case HWTSTAMP_FILTER_NONE:
556 /* time stamp no incoming packet at all */
557 config.rx_filter = HWTSTAMP_FILTER_NONE;
560 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
561 /* PTP v1, UDP, any kind of event packet */
562 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
563 /* take time stamp for all event messages */
564 if (priv->plat->has_gmac4)
565 snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
567 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
569 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
570 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
573 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
574 /* PTP v1, UDP, Sync packet */
575 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
576 /* take time stamp for SYNC messages only */
577 ts_event_en = PTP_TCR_TSEVNTENA;
579 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
580 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
583 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
584 /* PTP v1, UDP, Delay_req packet */
585 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
586 /* take time stamp for Delay_Req messages only */
587 ts_master_en = PTP_TCR_TSMSTRENA;
588 ts_event_en = PTP_TCR_TSEVNTENA;
590 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
591 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
594 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
595 /* PTP v2, UDP, any kind of event packet */
596 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
597 ptp_v2 = PTP_TCR_TSVER2ENA;
598 /* take time stamp for all event messages */
599 if (priv->plat->has_gmac4)
600 snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
602 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
604 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
605 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
608 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
609 /* PTP v2, UDP, Sync packet */
610 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
611 ptp_v2 = PTP_TCR_TSVER2ENA;
612 /* take time stamp for SYNC messages only */
613 ts_event_en = PTP_TCR_TSEVNTENA;
615 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
616 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
619 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
620 /* PTP v2, UDP, Delay_req packet */
621 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
622 ptp_v2 = PTP_TCR_TSVER2ENA;
623 /* take time stamp for Delay_Req messages only */
624 ts_master_en = PTP_TCR_TSMSTRENA;
625 ts_event_en = PTP_TCR_TSEVNTENA;
627 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
628 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
631 case HWTSTAMP_FILTER_PTP_V2_EVENT:
632 /* PTP v2/802.AS1 any layer, any kind of event packet */
633 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
634 ptp_v2 = PTP_TCR_TSVER2ENA;
635 /* take time stamp for all event messages */
636 if (priv->plat->has_gmac4)
637 snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
639 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
641 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
642 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
643 ptp_over_ethernet = PTP_TCR_TSIPENA;
646 case HWTSTAMP_FILTER_PTP_V2_SYNC:
647 /* PTP v2/802.AS1, any layer, Sync packet */
648 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
649 ptp_v2 = PTP_TCR_TSVER2ENA;
650 /* take time stamp for SYNC messages only */
651 ts_event_en = PTP_TCR_TSEVNTENA;
653 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
654 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
655 ptp_over_ethernet = PTP_TCR_TSIPENA;
658 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
659 /* PTP v2/802.AS1, any layer, Delay_req packet */
660 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
661 ptp_v2 = PTP_TCR_TSVER2ENA;
662 /* take time stamp for Delay_Req messages only */
663 ts_master_en = PTP_TCR_TSMSTRENA;
664 ts_event_en = PTP_TCR_TSEVNTENA;
666 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
667 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
668 ptp_over_ethernet = PTP_TCR_TSIPENA;
671 case HWTSTAMP_FILTER_NTP_ALL:
672 case HWTSTAMP_FILTER_ALL:
673 /* time stamp any incoming packet */
674 config.rx_filter = HWTSTAMP_FILTER_ALL;
675 tstamp_all = PTP_TCR_TSENALL;
682 switch (config.rx_filter) {
683 case HWTSTAMP_FILTER_NONE:
684 config.rx_filter = HWTSTAMP_FILTER_NONE;
687 /* PTP v1, UDP, any kind of event packet */
688 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
692 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
693 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
695 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
696 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, 0);
698 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
699 tstamp_all | ptp_v2 | ptp_over_ethernet |
700 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
701 ts_master_en | snap_type_sel);
702 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, value);
704 /* program Sub Second Increment reg */
705 sec_inc = priv->hw->ptp->config_sub_second_increment(
706 priv->ptpaddr, priv->plat->clk_ptp_rate,
707 priv->plat->has_gmac4);
708 temp = div_u64(1000000000ULL, sec_inc);
710 /* calculate default added value:
712 * addend = (2^32)/freq_div_ratio;
713 * where, freq_div_ratio = 1e9ns/sec_inc
715 temp = (u64)(temp << 32);
716 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
717 priv->hw->ptp->config_addend(priv->ptpaddr,
718 priv->default_addend);
720 /* initialize system time */
721 ktime_get_real_ts64(&now);
723 /* lower 32 bits of tv_sec are safe until y2106 */
724 priv->hw->ptp->init_systime(priv->ptpaddr, (u32)now.tv_sec,
728 return copy_to_user(ifr->ifr_data, &config,
729 sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
733 * stmmac_init_ptp - init PTP
734 * @priv: driver private structure
735 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
736 * This is done by looking at the HW cap. register.
737 * This function also registers the ptp driver.
739 static int stmmac_init_ptp(struct stmmac_priv *priv)
741 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
745 /* Check if adv_ts can be enabled for dwmac 4.x core */
746 if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp)
748 /* Dwmac 3.x core with extend_desc can support adv_ts */
749 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
752 if (priv->dma_cap.time_stamp)
753 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
756 netdev_info(priv->dev,
757 "IEEE 1588-2008 Advanced Timestamp supported\n");
759 priv->hw->ptp = &stmmac_ptp;
760 priv->hwts_tx_en = 0;
761 priv->hwts_rx_en = 0;
763 stmmac_ptp_register(priv);
768 static void stmmac_release_ptp(struct stmmac_priv *priv)
770 if (priv->plat->clk_ptp_ref)
771 clk_disable_unprepare(priv->plat->clk_ptp_ref);
772 stmmac_ptp_unregister(priv);
776 * stmmac_mac_flow_ctrl - Configure flow control in all queues
777 * @priv: driver private structure
778 * Description: It is used for configuring the flow control in all queues
780 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
782 u32 tx_cnt = priv->plat->tx_queues_to_use;
784 priv->hw->mac->flow_ctrl(priv->hw, duplex, priv->flow_ctrl,
785 priv->pause, tx_cnt);
789 * stmmac_adjust_link - adjusts the link parameters
790 * @dev: net device structure
791 * Description: this is the helper called by the physical abstraction layer
792 * drivers to communicate the phy link status. According the speed and duplex
793 * this driver can invoke registered glue-logic as well.
794 * It also invoke the eee initialization because it could happen when switch
795 * on different networks (that are eee capable).
797 static void stmmac_adjust_link(struct net_device *dev)
799 struct stmmac_priv *priv = netdev_priv(dev);
800 struct phy_device *phydev = dev->phydev;
801 bool new_state = false;
806 mutex_lock(&priv->lock);
809 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
811 /* Now we make sure that we can be in full duplex mode.
812 * If not, we operate in half-duplex mode. */
813 if (phydev->duplex != priv->oldduplex) {
816 ctrl &= ~priv->hw->link.duplex;
818 ctrl |= priv->hw->link.duplex;
819 priv->oldduplex = phydev->duplex;
821 /* Flow Control operation */
823 stmmac_mac_flow_ctrl(priv, phydev->duplex);
825 if (phydev->speed != priv->speed) {
827 ctrl &= ~priv->hw->link.speed_mask;
828 switch (phydev->speed) {
830 ctrl |= priv->hw->link.speed1000;
833 ctrl |= priv->hw->link.speed100;
836 ctrl |= priv->hw->link.speed10;
839 netif_warn(priv, link, priv->dev,
840 "broken speed: %d\n", phydev->speed);
841 phydev->speed = SPEED_UNKNOWN;
844 if (phydev->speed != SPEED_UNKNOWN)
845 stmmac_hw_fix_mac_speed(priv);
846 priv->speed = phydev->speed;
849 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
851 if (!priv->oldlink) {
853 priv->oldlink = true;
855 } else if (priv->oldlink) {
857 priv->oldlink = false;
858 priv->speed = SPEED_UNKNOWN;
859 priv->oldduplex = DUPLEX_UNKNOWN;
862 if (new_state && netif_msg_link(priv))
863 phy_print_status(phydev);
865 mutex_unlock(&priv->lock);
867 if (phydev->is_pseudo_fixed_link)
868 /* Stop PHY layer to call the hook to adjust the link in case
869 * of a switch is attached to the stmmac driver.
871 phydev->irq = PHY_IGNORE_INTERRUPT;
873 /* At this stage, init the EEE if supported.
874 * Never called in case of fixed_link.
876 priv->eee_enabled = stmmac_eee_init(priv);
880 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
881 * @priv: driver private structure
882 * Description: this is to verify if the HW supports the PCS.
883 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
884 * configured for the TBI, RTBI, or SGMII PHY interface.
886 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
888 int interface = priv->plat->interface;
890 if (priv->dma_cap.pcs) {
891 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
892 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
893 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
894 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
895 netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
896 priv->hw->pcs = STMMAC_PCS_RGMII;
897 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
898 netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
899 priv->hw->pcs = STMMAC_PCS_SGMII;
905 * stmmac_init_phy - PHY initialization
906 * @dev: net device structure
907 * Description: it initializes the driver's PHY state, and attaches the PHY
912 static int stmmac_init_phy(struct net_device *dev)
914 struct stmmac_priv *priv = netdev_priv(dev);
915 u32 tx_cnt = priv->plat->tx_queues_to_use;
916 struct phy_device *phydev;
917 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
918 char bus_id[MII_BUS_ID_SIZE];
919 int interface = priv->plat->interface;
920 int max_speed = priv->plat->max_speed;
921 priv->oldlink = false;
922 priv->speed = SPEED_UNKNOWN;
923 priv->oldduplex = DUPLEX_UNKNOWN;
925 if (priv->plat->phy_node) {
926 phydev = of_phy_connect(dev, priv->plat->phy_node,
927 &stmmac_adjust_link, 0, interface);
929 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
932 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
933 priv->plat->phy_addr);
934 netdev_dbg(priv->dev, "%s: trying to attach to %s\n", __func__,
937 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
941 if (IS_ERR_OR_NULL(phydev)) {
942 netdev_err(priv->dev, "Could not attach to PHY\n");
946 return PTR_ERR(phydev);
949 /* Stop Advertising 1000BASE Capability if interface is not GMII */
950 if ((interface == PHY_INTERFACE_MODE_MII) ||
951 (interface == PHY_INTERFACE_MODE_RMII) ||
952 (max_speed < 1000 && max_speed > 0))
953 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
954 SUPPORTED_1000baseT_Full);
957 * Half-duplex mode not supported with multiqueue
958 * half-duplex can only works with single queue
961 phydev->supported &= ~(SUPPORTED_1000baseT_Half |
962 SUPPORTED_100baseT_Half |
963 SUPPORTED_10baseT_Half);
966 * Broken HW is sometimes missing the pull-up resistor on the
967 * MDIO line, which results in reads to non-existent devices returning
968 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
970 * Note: phydev->phy_id is the result of reading the UID PHY registers.
972 if (!priv->plat->phy_node && phydev->phy_id == 0) {
973 phy_disconnect(phydev);
977 /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid
978 * subsequent PHY polling, make sure we force a link transition if
979 * we have a UP/DOWN/UP transition
981 if (phydev->is_pseudo_fixed_link)
982 phydev->irq = PHY_POLL;
984 phy_attached_info(phydev);
988 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
990 u32 rx_cnt = priv->plat->rx_queues_to_use;
994 /* Display RX rings */
995 for (queue = 0; queue < rx_cnt; queue++) {
996 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
998 pr_info("\tRX Queue %u rings\n", queue);
1000 if (priv->extend_desc)
1001 head_rx = (void *)rx_q->dma_erx;
1003 head_rx = (void *)rx_q->dma_rx;
1005 /* Display RX ring */
1006 priv->hw->desc->display_ring(head_rx, DMA_RX_SIZE, true);
1010 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1012 u32 tx_cnt = priv->plat->tx_queues_to_use;
1016 /* Display TX rings */
1017 for (queue = 0; queue < tx_cnt; queue++) {
1018 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1020 pr_info("\tTX Queue %d rings\n", queue);
1022 if (priv->extend_desc)
1023 head_tx = (void *)tx_q->dma_etx;
1025 head_tx = (void *)tx_q->dma_tx;
1027 priv->hw->desc->display_ring(head_tx, DMA_TX_SIZE, false);
1031 static void stmmac_display_rings(struct stmmac_priv *priv)
1033 /* Display RX ring */
1034 stmmac_display_rx_rings(priv);
1036 /* Display TX ring */
1037 stmmac_display_tx_rings(priv);
1040 static int stmmac_set_bfsize(int mtu, int bufsize)
1044 if (mtu >= BUF_SIZE_8KiB)
1045 ret = BUF_SIZE_16KiB;
1046 else if (mtu >= BUF_SIZE_4KiB)
1047 ret = BUF_SIZE_8KiB;
1048 else if (mtu >= BUF_SIZE_2KiB)
1049 ret = BUF_SIZE_4KiB;
1050 else if (mtu > DEFAULT_BUFSIZE)
1051 ret = BUF_SIZE_2KiB;
1053 ret = DEFAULT_BUFSIZE;
1059 * stmmac_clear_rx_descriptors - clear RX descriptors
1060 * @priv: driver private structure
1061 * @queue: RX queue index
1062 * Description: this function is called to clear the RX descriptors
1063 * in case of both basic and extended descriptors are used.
1065 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1067 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1070 /* Clear the RX descriptors */
1071 for (i = 0; i < DMA_RX_SIZE; i++)
1072 if (priv->extend_desc)
1073 priv->hw->desc->init_rx_desc(&rx_q->dma_erx[i].basic,
1074 priv->use_riwt, priv->mode,
1075 (i == DMA_RX_SIZE - 1),
1078 priv->hw->desc->init_rx_desc(&rx_q->dma_rx[i],
1079 priv->use_riwt, priv->mode,
1080 (i == DMA_RX_SIZE - 1),
1085 * stmmac_clear_tx_descriptors - clear tx descriptors
1086 * @priv: driver private structure
1087 * @queue: TX queue index.
1088 * Description: this function is called to clear the TX descriptors
1089 * in case of both basic and extended descriptors are used.
1091 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1093 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1096 /* Clear the TX descriptors */
1097 for (i = 0; i < DMA_TX_SIZE; i++)
1098 if (priv->extend_desc)
1099 priv->hw->desc->init_tx_desc(&tx_q->dma_etx[i].basic,
1101 (i == DMA_TX_SIZE - 1));
1103 priv->hw->desc->init_tx_desc(&tx_q->dma_tx[i],
1105 (i == DMA_TX_SIZE - 1));
1109 * stmmac_clear_descriptors - clear descriptors
1110 * @priv: driver private structure
1111 * Description: this function is called to clear the TX and RX descriptors
1112 * in case of both basic and extended descriptors are used.
1114 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1116 u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1117 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1120 /* Clear the RX descriptors */
1121 for (queue = 0; queue < rx_queue_cnt; queue++)
1122 stmmac_clear_rx_descriptors(priv, queue);
1124 /* Clear the TX descriptors */
1125 for (queue = 0; queue < tx_queue_cnt; queue++)
1126 stmmac_clear_tx_descriptors(priv, queue);
1130 * stmmac_init_rx_buffers - init the RX descriptor buffer.
1131 * @priv: driver private structure
1132 * @p: descriptor pointer
1133 * @i: descriptor index
1135 * @queue: RX queue index
1136 * Description: this function is called to allocate a receive buffer, perform
1137 * the DMA mapping and init the descriptor.
1139 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1140 int i, gfp_t flags, u32 queue)
1142 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1143 struct sk_buff *skb;
1145 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
1147 netdev_err(priv->dev,
1148 "%s: Rx init fails; skb is NULL\n", __func__);
1151 rx_q->rx_skbuff[i] = skb;
1152 rx_q->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
1155 if (dma_mapping_error(priv->device, rx_q->rx_skbuff_dma[i])) {
1156 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
1157 dev_kfree_skb_any(skb);
1161 if (priv->synopsys_id >= DWMAC_CORE_4_00)
1162 p->des0 = cpu_to_le32(rx_q->rx_skbuff_dma[i]);
1164 p->des2 = cpu_to_le32(rx_q->rx_skbuff_dma[i]);
1166 if ((priv->hw->mode->init_desc3) &&
1167 (priv->dma_buf_sz == BUF_SIZE_16KiB))
1168 priv->hw->mode->init_desc3(p);
1174 * stmmac_free_rx_buffer - free RX dma buffers
1175 * @priv: private structure
1176 * @queue: RX queue index
1179 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1181 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1183 if (rx_q->rx_skbuff[i]) {
1184 dma_unmap_single(priv->device, rx_q->rx_skbuff_dma[i],
1185 priv->dma_buf_sz, DMA_FROM_DEVICE);
1186 dev_kfree_skb_any(rx_q->rx_skbuff[i]);
1188 rx_q->rx_skbuff[i] = NULL;
1192 * stmmac_free_tx_buffer - free RX dma buffers
1193 * @priv: private structure
1194 * @queue: RX queue index
1197 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1199 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1201 if (tx_q->tx_skbuff_dma[i].buf) {
1202 if (tx_q->tx_skbuff_dma[i].map_as_page)
1203 dma_unmap_page(priv->device,
1204 tx_q->tx_skbuff_dma[i].buf,
1205 tx_q->tx_skbuff_dma[i].len,
1208 dma_unmap_single(priv->device,
1209 tx_q->tx_skbuff_dma[i].buf,
1210 tx_q->tx_skbuff_dma[i].len,
1214 if (tx_q->tx_skbuff[i]) {
1215 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1216 tx_q->tx_skbuff[i] = NULL;
1217 tx_q->tx_skbuff_dma[i].buf = 0;
1218 tx_q->tx_skbuff_dma[i].map_as_page = false;
1223 * init_dma_rx_desc_rings - init the RX descriptor rings
1224 * @dev: net device structure
1226 * Description: this function initializes the DMA RX descriptors
1227 * and allocates the socket buffers. It supports the chained and ring
1230 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1232 struct stmmac_priv *priv = netdev_priv(dev);
1233 u32 rx_count = priv->plat->rx_queues_to_use;
1234 unsigned int bfsize = 0;
1239 if (priv->hw->mode->set_16kib_bfsize)
1240 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1242 if (bfsize < BUF_SIZE_16KiB)
1243 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1245 priv->dma_buf_sz = bfsize;
1247 /* RX INITIALIZATION */
1248 netif_dbg(priv, probe, priv->dev,
1249 "SKB addresses:\nskb\t\tskb data\tdma data\n");
1251 for (queue = 0; queue < rx_count; queue++) {
1252 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1254 netif_dbg(priv, probe, priv->dev,
1255 "(%s) dma_rx_phy=0x%08x\n", __func__,
1256 (u32)rx_q->dma_rx_phy);
1258 for (i = 0; i < DMA_RX_SIZE; i++) {
1261 if (priv->extend_desc)
1262 p = &((rx_q->dma_erx + i)->basic);
1264 p = rx_q->dma_rx + i;
1266 ret = stmmac_init_rx_buffers(priv, p, i, flags,
1269 goto err_init_rx_buffers;
1271 netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n",
1272 rx_q->rx_skbuff[i], rx_q->rx_skbuff[i]->data,
1273 (unsigned int)rx_q->rx_skbuff_dma[i]);
1277 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1279 stmmac_clear_rx_descriptors(priv, queue);
1281 /* Setup the chained descriptor addresses */
1282 if (priv->mode == STMMAC_CHAIN_MODE) {
1283 if (priv->extend_desc)
1284 priv->hw->mode->init(rx_q->dma_erx,
1288 priv->hw->mode->init(rx_q->dma_rx,
1298 err_init_rx_buffers:
1299 while (queue >= 0) {
1301 stmmac_free_rx_buffer(priv, queue, i);
1314 * init_dma_tx_desc_rings - init the TX descriptor rings
1315 * @dev: net device structure.
1316 * Description: this function initializes the DMA TX descriptors
1317 * and allocates the socket buffers. It supports the chained and ring
1320 static int init_dma_tx_desc_rings(struct net_device *dev)
1322 struct stmmac_priv *priv = netdev_priv(dev);
1323 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1327 for (queue = 0; queue < tx_queue_cnt; queue++) {
1328 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1330 netif_dbg(priv, probe, priv->dev,
1331 "(%s) dma_tx_phy=0x%08x\n", __func__,
1332 (u32)tx_q->dma_tx_phy);
1334 /* Setup the chained descriptor addresses */
1335 if (priv->mode == STMMAC_CHAIN_MODE) {
1336 if (priv->extend_desc)
1337 priv->hw->mode->init(tx_q->dma_etx,
1341 priv->hw->mode->init(tx_q->dma_tx,
1346 for (i = 0; i < DMA_TX_SIZE; i++) {
1348 if (priv->extend_desc)
1349 p = &((tx_q->dma_etx + i)->basic);
1351 p = tx_q->dma_tx + i;
1353 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1362 tx_q->tx_skbuff_dma[i].buf = 0;
1363 tx_q->tx_skbuff_dma[i].map_as_page = false;
1364 tx_q->tx_skbuff_dma[i].len = 0;
1365 tx_q->tx_skbuff_dma[i].last_segment = false;
1366 tx_q->tx_skbuff[i] = NULL;
1372 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1379 * init_dma_desc_rings - init the RX/TX descriptor rings
1380 * @dev: net device structure
1382 * Description: this function initializes the DMA RX/TX descriptors
1383 * and allocates the socket buffers. It supports the chained and ring
1386 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1388 struct stmmac_priv *priv = netdev_priv(dev);
1391 ret = init_dma_rx_desc_rings(dev, flags);
1395 ret = init_dma_tx_desc_rings(dev);
1397 stmmac_clear_descriptors(priv);
1399 if (netif_msg_hw(priv))
1400 stmmac_display_rings(priv);
1406 * dma_free_rx_skbufs - free RX dma buffers
1407 * @priv: private structure
1408 * @queue: RX queue index
1410 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1414 for (i = 0; i < DMA_RX_SIZE; i++)
1415 stmmac_free_rx_buffer(priv, queue, i);
1419 * dma_free_tx_skbufs - free TX dma buffers
1420 * @priv: private structure
1421 * @queue: TX queue index
1423 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1427 for (i = 0; i < DMA_TX_SIZE; i++)
1428 stmmac_free_tx_buffer(priv, queue, i);
1432 * stmmac_free_tx_skbufs - free TX skb buffers
1433 * @priv: private structure
1435 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv)
1437 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1440 for (queue = 0; queue < tx_queue_cnt; queue++)
1441 dma_free_tx_skbufs(priv, queue);
1445 * free_dma_rx_desc_resources - free RX dma desc resources
1446 * @priv: private structure
1448 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1450 u32 rx_count = priv->plat->rx_queues_to_use;
1453 /* Free RX queue resources */
1454 for (queue = 0; queue < rx_count; queue++) {
1455 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1457 /* Release the DMA RX socket buffers */
1458 dma_free_rx_skbufs(priv, queue);
1460 /* Free DMA regions of consistent memory previously allocated */
1461 if (!priv->extend_desc)
1462 dma_free_coherent(priv->device,
1463 DMA_RX_SIZE * sizeof(struct dma_desc),
1464 rx_q->dma_rx, rx_q->dma_rx_phy);
1466 dma_free_coherent(priv->device, DMA_RX_SIZE *
1467 sizeof(struct dma_extended_desc),
1468 rx_q->dma_erx, rx_q->dma_rx_phy);
1470 kfree(rx_q->rx_skbuff_dma);
1471 kfree(rx_q->rx_skbuff);
1476 * free_dma_tx_desc_resources - free TX dma desc resources
1477 * @priv: private structure
1479 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1481 u32 tx_count = priv->plat->tx_queues_to_use;
1484 /* Free TX queue resources */
1485 for (queue = 0; queue < tx_count; queue++) {
1486 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1488 /* Release the DMA TX socket buffers */
1489 dma_free_tx_skbufs(priv, queue);
1491 /* Free DMA regions of consistent memory previously allocated */
1492 if (!priv->extend_desc)
1493 dma_free_coherent(priv->device,
1494 DMA_TX_SIZE * sizeof(struct dma_desc),
1495 tx_q->dma_tx, tx_q->dma_tx_phy);
1497 dma_free_coherent(priv->device, DMA_TX_SIZE *
1498 sizeof(struct dma_extended_desc),
1499 tx_q->dma_etx, tx_q->dma_tx_phy);
1501 kfree(tx_q->tx_skbuff_dma);
1502 kfree(tx_q->tx_skbuff);
1507 * alloc_dma_rx_desc_resources - alloc RX resources.
1508 * @priv: private structure
1509 * Description: according to which descriptor can be used (extend or basic)
1510 * this function allocates the resources for TX and RX paths. In case of
1511 * reception, for example, it pre-allocated the RX socket buffer in order to
1512 * allow zero-copy mechanism.
1514 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
1516 u32 rx_count = priv->plat->rx_queues_to_use;
1520 /* RX queues buffers and DMA */
1521 for (queue = 0; queue < rx_count; queue++) {
1522 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1524 rx_q->queue_index = queue;
1525 rx_q->priv_data = priv;
1527 rx_q->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE,
1530 if (!rx_q->rx_skbuff_dma)
1533 rx_q->rx_skbuff = kmalloc_array(DMA_RX_SIZE,
1534 sizeof(struct sk_buff *),
1536 if (!rx_q->rx_skbuff)
1539 if (priv->extend_desc) {
1540 rx_q->dma_erx = dma_zalloc_coherent(priv->device,
1550 rx_q->dma_rx = dma_zalloc_coherent(priv->device,
1564 free_dma_rx_desc_resources(priv);
1570 * alloc_dma_tx_desc_resources - alloc TX resources.
1571 * @priv: private structure
1572 * Description: according to which descriptor can be used (extend or basic)
1573 * this function allocates the resources for TX and RX paths. In case of
1574 * reception, for example, it pre-allocated the RX socket buffer in order to
1575 * allow zero-copy mechanism.
1577 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1579 u32 tx_count = priv->plat->tx_queues_to_use;
1583 /* TX queues buffers and DMA */
1584 for (queue = 0; queue < tx_count; queue++) {
1585 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1587 tx_q->queue_index = queue;
1588 tx_q->priv_data = priv;
1590 tx_q->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1591 sizeof(*tx_q->tx_skbuff_dma),
1593 if (!tx_q->tx_skbuff_dma)
1596 tx_q->tx_skbuff = kmalloc_array(DMA_TX_SIZE,
1597 sizeof(struct sk_buff *),
1599 if (!tx_q->tx_skbuff)
1602 if (priv->extend_desc) {
1603 tx_q->dma_etx = dma_zalloc_coherent(priv->device,
1612 tx_q->dma_tx = dma_zalloc_coherent(priv->device,
1626 free_dma_tx_desc_resources(priv);
1632 * alloc_dma_desc_resources - alloc TX/RX resources.
1633 * @priv: private structure
1634 * Description: according to which descriptor can be used (extend or basic)
1635 * this function allocates the resources for TX and RX paths. In case of
1636 * reception, for example, it pre-allocated the RX socket buffer in order to
1637 * allow zero-copy mechanism.
1639 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1642 int ret = alloc_dma_rx_desc_resources(priv);
1647 ret = alloc_dma_tx_desc_resources(priv);
1653 * free_dma_desc_resources - free dma desc resources
1654 * @priv: private structure
1656 static void free_dma_desc_resources(struct stmmac_priv *priv)
1658 /* Release the DMA RX socket buffers */
1659 free_dma_rx_desc_resources(priv);
1661 /* Release the DMA TX socket buffers */
1662 free_dma_tx_desc_resources(priv);
1666 * stmmac_mac_enable_rx_queues - Enable MAC rx queues
1667 * @priv: driver private structure
1668 * Description: It is used for enabling the rx queues in the MAC
1670 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1672 u32 rx_queues_count = priv->plat->rx_queues_to_use;
1676 for (queue = 0; queue < rx_queues_count; queue++) {
1677 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1678 priv->hw->mac->rx_queue_enable(priv->hw, mode, queue);
1683 * stmmac_start_rx_dma - start RX DMA channel
1684 * @priv: driver private structure
1685 * @chan: RX channel index
1687 * This starts a RX DMA channel
1689 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1691 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1692 priv->hw->dma->start_rx(priv->ioaddr, chan);
1696 * stmmac_start_tx_dma - start TX DMA channel
1697 * @priv: driver private structure
1698 * @chan: TX channel index
1700 * This starts a TX DMA channel
1702 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1704 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1705 priv->hw->dma->start_tx(priv->ioaddr, chan);
1709 * stmmac_stop_rx_dma - stop RX DMA channel
1710 * @priv: driver private structure
1711 * @chan: RX channel index
1713 * This stops a RX DMA channel
1715 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1717 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1718 priv->hw->dma->stop_rx(priv->ioaddr, chan);
1722 * stmmac_stop_tx_dma - stop TX DMA channel
1723 * @priv: driver private structure
1724 * @chan: TX channel index
1726 * This stops a TX DMA channel
1728 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1730 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1731 priv->hw->dma->stop_tx(priv->ioaddr, chan);
1735 * stmmac_start_all_dma - start all RX and TX DMA channels
1736 * @priv: driver private structure
1738 * This starts all the RX and TX DMA channels
1740 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1742 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1743 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1746 for (chan = 0; chan < rx_channels_count; chan++)
1747 stmmac_start_rx_dma(priv, chan);
1749 for (chan = 0; chan < tx_channels_count; chan++)
1750 stmmac_start_tx_dma(priv, chan);
1754 * stmmac_stop_all_dma - stop all RX and TX DMA channels
1755 * @priv: driver private structure
1757 * This stops the RX and TX DMA channels
1759 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1761 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1762 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1765 for (chan = 0; chan < rx_channels_count; chan++)
1766 stmmac_stop_rx_dma(priv, chan);
1768 for (chan = 0; chan < tx_channels_count; chan++)
1769 stmmac_stop_tx_dma(priv, chan);
1773 * stmmac_dma_operation_mode - HW DMA operation mode
1774 * @priv: driver private structure
1775 * Description: it is used for configuring the DMA operation mode register in
1776 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1778 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1780 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1781 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1782 int rxfifosz = priv->plat->rx_fifo_size;
1783 int txfifosz = priv->plat->tx_fifo_size;
1789 rxfifosz = priv->dma_cap.rx_fifo_size;
1791 txfifosz = priv->dma_cap.tx_fifo_size;
1793 /* Adjust for real per queue fifo size */
1794 rxfifosz /= rx_channels_count;
1795 txfifosz /= tx_channels_count;
1797 if (priv->plat->force_thresh_dma_mode) {
1800 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1802 * In case of GMAC, SF mode can be enabled
1803 * to perform the TX COE in HW. This depends on:
1804 * 1) TX COE if actually supported
1805 * 2) There is no bugged Jumbo frame support
1806 * that needs to not insert csum in the TDES.
1808 txmode = SF_DMA_MODE;
1809 rxmode = SF_DMA_MODE;
1810 priv->xstats.threshold = SF_DMA_MODE;
1813 rxmode = SF_DMA_MODE;
1816 /* configure all channels */
1817 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1818 for (chan = 0; chan < rx_channels_count; chan++)
1819 priv->hw->dma->dma_rx_mode(priv->ioaddr, rxmode, chan,
1822 for (chan = 0; chan < tx_channels_count; chan++)
1823 priv->hw->dma->dma_tx_mode(priv->ioaddr, txmode, chan,
1826 priv->hw->dma->dma_mode(priv->ioaddr, txmode, rxmode,
1832 * stmmac_tx_clean - to manage the transmission completion
1833 * @priv: driver private structure
1834 * @queue: TX queue index
1835 * Description: it reclaims the transmit resources after transmission completes.
1837 static void stmmac_tx_clean(struct stmmac_priv *priv, u32 queue)
1839 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1840 unsigned int bytes_compl = 0, pkts_compl = 0;
1843 netif_tx_lock(priv->dev);
1845 priv->xstats.tx_clean++;
1847 entry = tx_q->dirty_tx;
1848 while (entry != tx_q->cur_tx) {
1849 struct sk_buff *skb = tx_q->tx_skbuff[entry];
1853 if (priv->extend_desc)
1854 p = (struct dma_desc *)(tx_q->dma_etx + entry);
1856 p = tx_q->dma_tx + entry;
1858 status = priv->hw->desc->tx_status(&priv->dev->stats,
1861 /* Check if the descriptor is owned by the DMA */
1862 if (unlikely(status & tx_dma_own))
1865 /* Make sure descriptor fields are read after reading
1870 /* Just consider the last segment and ...*/
1871 if (likely(!(status & tx_not_ls))) {
1872 /* ... verify the status error condition */
1873 if (unlikely(status & tx_err)) {
1874 priv->dev->stats.tx_errors++;
1876 priv->dev->stats.tx_packets++;
1877 priv->xstats.tx_pkt_n++;
1879 stmmac_get_tx_hwtstamp(priv, p, skb);
1882 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
1883 if (tx_q->tx_skbuff_dma[entry].map_as_page)
1884 dma_unmap_page(priv->device,
1885 tx_q->tx_skbuff_dma[entry].buf,
1886 tx_q->tx_skbuff_dma[entry].len,
1889 dma_unmap_single(priv->device,
1890 tx_q->tx_skbuff_dma[entry].buf,
1891 tx_q->tx_skbuff_dma[entry].len,
1893 tx_q->tx_skbuff_dma[entry].buf = 0;
1894 tx_q->tx_skbuff_dma[entry].len = 0;
1895 tx_q->tx_skbuff_dma[entry].map_as_page = false;
1898 if (priv->hw->mode->clean_desc3)
1899 priv->hw->mode->clean_desc3(tx_q, p);
1901 tx_q->tx_skbuff_dma[entry].last_segment = false;
1902 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
1904 if (likely(skb != NULL)) {
1906 bytes_compl += skb->len;
1907 dev_consume_skb_any(skb);
1908 tx_q->tx_skbuff[entry] = NULL;
1911 priv->hw->desc->release_tx_desc(p, priv->mode);
1913 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1915 tx_q->dirty_tx = entry;
1917 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
1918 pkts_compl, bytes_compl);
1920 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
1922 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
1924 netif_dbg(priv, tx_done, priv->dev,
1925 "%s: restart transmit\n", __func__);
1926 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
1929 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1930 stmmac_enable_eee_mode(priv);
1931 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1933 netif_tx_unlock(priv->dev);
1936 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv, u32 chan)
1938 priv->hw->dma->enable_dma_irq(priv->ioaddr, chan);
1941 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv, u32 chan)
1943 priv->hw->dma->disable_dma_irq(priv->ioaddr, chan);
1947 * stmmac_tx_err - to manage the tx error
1948 * @priv: driver private structure
1949 * @chan: channel index
1950 * Description: it cleans the descriptors and restarts the transmission
1951 * in case of transmission errors.
1953 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
1955 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
1958 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
1960 stmmac_stop_tx_dma(priv, chan);
1961 dma_free_tx_skbufs(priv, chan);
1962 for (i = 0; i < DMA_TX_SIZE; i++)
1963 if (priv->extend_desc)
1964 priv->hw->desc->init_tx_desc(&tx_q->dma_etx[i].basic,
1966 (i == DMA_TX_SIZE - 1));
1968 priv->hw->desc->init_tx_desc(&tx_q->dma_tx[i],
1970 (i == DMA_TX_SIZE - 1));
1973 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
1974 stmmac_start_tx_dma(priv, chan);
1976 priv->dev->stats.tx_errors++;
1977 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
1981 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel
1982 * @priv: driver private structure
1983 * @txmode: TX operating mode
1984 * @rxmode: RX operating mode
1985 * @chan: channel index
1986 * Description: it is used for configuring of the DMA operation mode in
1987 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
1990 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
1991 u32 rxmode, u32 chan)
1993 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1994 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1995 int rxfifosz = priv->plat->rx_fifo_size;
1996 int txfifosz = priv->plat->tx_fifo_size;
1999 rxfifosz = priv->dma_cap.rx_fifo_size;
2001 txfifosz = priv->dma_cap.tx_fifo_size;
2003 /* Adjust for real per queue fifo size */
2004 rxfifosz /= rx_channels_count;
2005 txfifosz /= tx_channels_count;
2007 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
2008 priv->hw->dma->dma_rx_mode(priv->ioaddr, rxmode, chan,
2010 priv->hw->dma->dma_tx_mode(priv->ioaddr, txmode, chan,
2013 priv->hw->dma->dma_mode(priv->ioaddr, txmode, rxmode,
2019 * stmmac_dma_interrupt - DMA ISR
2020 * @priv: driver private structure
2021 * Description: this is the DMA ISR. It is called by the main ISR.
2022 * It calls the dwmac dma routine and schedule poll method in case of some
2025 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2027 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2031 for (chan = 0; chan < tx_channel_count; chan++) {
2032 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
2034 status = priv->hw->dma->dma_interrupt(priv->ioaddr,
2035 &priv->xstats, chan);
2036 if (likely((status & handle_rx)) || (status & handle_tx)) {
2037 if (likely(napi_schedule_prep(&rx_q->napi))) {
2038 stmmac_disable_dma_irq(priv, chan);
2039 __napi_schedule(&rx_q->napi);
2043 if (unlikely(status & tx_hard_error_bump_tc)) {
2044 /* Try to bump up the dma threshold on this failure */
2045 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2048 if (priv->plat->force_thresh_dma_mode)
2049 stmmac_set_dma_operation_mode(priv,
2054 stmmac_set_dma_operation_mode(priv,
2058 priv->xstats.threshold = tc;
2060 } else if (unlikely(status == tx_hard_error)) {
2061 stmmac_tx_err(priv, chan);
2067 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2068 * @priv: driver private structure
2069 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2071 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2073 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2074 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2076 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
2077 priv->ptpaddr = priv->ioaddr + PTP_GMAC4_OFFSET;
2078 priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET;
2080 priv->ptpaddr = priv->ioaddr + PTP_GMAC3_X_OFFSET;
2081 priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET;
2084 dwmac_mmc_intr_all_mask(priv->mmcaddr);
2086 if (priv->dma_cap.rmon) {
2087 dwmac_mmc_ctrl(priv->mmcaddr, mode);
2088 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2090 netdev_info(priv->dev, "No MAC Management Counters available\n");
2094 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
2095 * @priv: driver private structure
2096 * Description: select the Enhanced/Alternate or Normal descriptors.
2097 * In case of Enhanced/Alternate, it checks if the extended descriptors are
2098 * supported by the HW capability register.
2100 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
2102 if (priv->plat->enh_desc) {
2103 dev_info(priv->device, "Enhanced/Alternate descriptors\n");
2105 /* GMAC older than 3.50 has no extended descriptors */
2106 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
2107 dev_info(priv->device, "Enabled extended descriptors\n");
2108 priv->extend_desc = 1;
2110 dev_warn(priv->device, "Extended descriptors not supported\n");
2112 priv->hw->desc = &enh_desc_ops;
2114 dev_info(priv->device, "Normal descriptors\n");
2115 priv->hw->desc = &ndesc_ops;
2120 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2121 * @priv: driver private structure
2123 * new GMAC chip generations have a new register to indicate the
2124 * presence of the optional feature/functions.
2125 * This can be also used to override the value passed through the
2126 * platform and necessary for old MAC10/100 and GMAC chips.
2128 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2132 if (priv->hw->dma->get_hw_feature) {
2133 priv->hw->dma->get_hw_feature(priv->ioaddr,
2142 * stmmac_check_ether_addr - check if the MAC addr is valid
2143 * @priv: driver private structure
2145 * it is to verify if the MAC address is valid, in case of failures it
2146 * generates a random MAC address
2148 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2150 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2151 priv->hw->mac->get_umac_addr(priv->hw,
2152 priv->dev->dev_addr, 0);
2153 if (!is_valid_ether_addr(priv->dev->dev_addr))
2154 eth_hw_addr_random(priv->dev);
2155 netdev_info(priv->dev, "device MAC address %pM\n",
2156 priv->dev->dev_addr);
2161 * stmmac_init_dma_engine - DMA init.
2162 * @priv: driver private structure
2164 * It inits the DMA invoking the specific MAC/GMAC callback.
2165 * Some DMA parameters can be passed from the platform;
2166 * in case of these are not passed a default is kept for the MAC or GMAC.
2168 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2170 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2171 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2172 struct stmmac_rx_queue *rx_q;
2173 struct stmmac_tx_queue *tx_q;
2174 u32 dummy_dma_rx_phy = 0;
2175 u32 dummy_dma_tx_phy = 0;
2180 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2181 dev_err(priv->device, "Invalid DMA configuration\n");
2185 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2188 ret = priv->hw->dma->reset(priv->ioaddr);
2190 dev_err(priv->device, "Failed to reset the dma\n");
2194 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
2195 /* DMA Configuration */
2196 priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg,
2197 dummy_dma_tx_phy, dummy_dma_rx_phy, atds);
2199 /* DMA RX Channel Configuration */
2200 for (chan = 0; chan < rx_channels_count; chan++) {
2201 rx_q = &priv->rx_queue[chan];
2203 priv->hw->dma->init_rx_chan(priv->ioaddr,
2204 priv->plat->dma_cfg,
2205 rx_q->dma_rx_phy, chan);
2207 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2208 (DMA_RX_SIZE * sizeof(struct dma_desc));
2209 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr,
2214 /* DMA TX Channel Configuration */
2215 for (chan = 0; chan < tx_channels_count; chan++) {
2216 tx_q = &priv->tx_queue[chan];
2218 priv->hw->dma->init_chan(priv->ioaddr,
2219 priv->plat->dma_cfg,
2222 priv->hw->dma->init_tx_chan(priv->ioaddr,
2223 priv->plat->dma_cfg,
2224 tx_q->dma_tx_phy, chan);
2226 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2227 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr,
2232 rx_q = &priv->rx_queue[chan];
2233 tx_q = &priv->tx_queue[chan];
2234 priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg,
2235 tx_q->dma_tx_phy, rx_q->dma_rx_phy, atds);
2238 if (priv->plat->axi && priv->hw->dma->axi)
2239 priv->hw->dma->axi(priv->ioaddr, priv->plat->axi);
2245 * stmmac_tx_timer - mitigation sw timer for tx.
2246 * @data: data pointer
2248 * This is the timer handler to directly invoke the stmmac_tx_clean.
2250 static void stmmac_tx_timer(unsigned long data)
2252 struct stmmac_priv *priv = (struct stmmac_priv *)data;
2253 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2256 /* let's scan all the tx queues */
2257 for (queue = 0; queue < tx_queues_count; queue++)
2258 stmmac_tx_clean(priv, queue);
2262 * stmmac_init_tx_coalesce - init tx mitigation options.
2263 * @priv: driver private structure
2265 * This inits the transmit coalesce parameters: i.e. timer rate,
2266 * timer handler and default threshold used for enabling the
2267 * interrupt on completion bit.
2269 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
2271 priv->tx_coal_frames = STMMAC_TX_FRAMES;
2272 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
2273 init_timer(&priv->txtimer);
2274 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
2275 priv->txtimer.data = (unsigned long)priv;
2276 priv->txtimer.function = stmmac_tx_timer;
2277 add_timer(&priv->txtimer);
2280 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2282 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2283 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2286 /* set TX ring length */
2287 if (priv->hw->dma->set_tx_ring_len) {
2288 for (chan = 0; chan < tx_channels_count; chan++)
2289 priv->hw->dma->set_tx_ring_len(priv->ioaddr,
2290 (DMA_TX_SIZE - 1), chan);
2293 /* set RX ring length */
2294 if (priv->hw->dma->set_rx_ring_len) {
2295 for (chan = 0; chan < rx_channels_count; chan++)
2296 priv->hw->dma->set_rx_ring_len(priv->ioaddr,
2297 (DMA_RX_SIZE - 1), chan);
2302 * stmmac_set_tx_queue_weight - Set TX queue weight
2303 * @priv: driver private structure
2304 * Description: It is used for setting TX queues weight
2306 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2308 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2312 for (queue = 0; queue < tx_queues_count; queue++) {
2313 weight = priv->plat->tx_queues_cfg[queue].weight;
2314 priv->hw->mac->set_mtl_tx_queue_weight(priv->hw, weight, queue);
2319 * stmmac_configure_cbs - Configure CBS in TX queue
2320 * @priv: driver private structure
2321 * Description: It is used for configuring CBS in AVB TX queues
2323 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2325 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2329 /* queue 0 is reserved for legacy traffic */
2330 for (queue = 1; queue < tx_queues_count; queue++) {
2331 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2332 if (mode_to_use == MTL_QUEUE_DCB)
2335 priv->hw->mac->config_cbs(priv->hw,
2336 priv->plat->tx_queues_cfg[queue].send_slope,
2337 priv->plat->tx_queues_cfg[queue].idle_slope,
2338 priv->plat->tx_queues_cfg[queue].high_credit,
2339 priv->plat->tx_queues_cfg[queue].low_credit,
2345 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2346 * @priv: driver private structure
2347 * Description: It is used for mapping RX queues to RX dma channels
2349 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2351 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2355 for (queue = 0; queue < rx_queues_count; queue++) {
2356 chan = priv->plat->rx_queues_cfg[queue].chan;
2357 priv->hw->mac->map_mtl_to_dma(priv->hw, queue, chan);
2362 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2363 * @priv: driver private structure
2364 * Description: It is used for configuring the RX Queue Priority
2366 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2368 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2372 for (queue = 0; queue < rx_queues_count; queue++) {
2373 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2376 prio = priv->plat->rx_queues_cfg[queue].prio;
2377 priv->hw->mac->rx_queue_prio(priv->hw, prio, queue);
2382 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2383 * @priv: driver private structure
2384 * Description: It is used for configuring the TX Queue Priority
2386 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2388 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2392 for (queue = 0; queue < tx_queues_count; queue++) {
2393 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2396 prio = priv->plat->tx_queues_cfg[queue].prio;
2397 priv->hw->mac->tx_queue_prio(priv->hw, prio, queue);
2402 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2403 * @priv: driver private structure
2404 * Description: It is used for configuring the RX queue routing
2406 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2408 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2412 for (queue = 0; queue < rx_queues_count; queue++) {
2413 /* no specific packet type routing specified for the queue */
2414 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2417 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2418 priv->hw->mac->rx_queue_routing(priv->hw, packet, queue);
2423 * stmmac_mtl_configuration - Configure MTL
2424 * @priv: driver private structure
2425 * Description: It is used for configurring MTL
2427 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2429 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2430 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2432 if (tx_queues_count > 1 && priv->hw->mac->set_mtl_tx_queue_weight)
2433 stmmac_set_tx_queue_weight(priv);
2435 /* Configure MTL RX algorithms */
2436 if (rx_queues_count > 1 && priv->hw->mac->prog_mtl_rx_algorithms)
2437 priv->hw->mac->prog_mtl_rx_algorithms(priv->hw,
2438 priv->plat->rx_sched_algorithm);
2440 /* Configure MTL TX algorithms */
2441 if (tx_queues_count > 1 && priv->hw->mac->prog_mtl_tx_algorithms)
2442 priv->hw->mac->prog_mtl_tx_algorithms(priv->hw,
2443 priv->plat->tx_sched_algorithm);
2445 /* Configure CBS in AVB TX queues */
2446 if (tx_queues_count > 1 && priv->hw->mac->config_cbs)
2447 stmmac_configure_cbs(priv);
2449 /* Map RX MTL to DMA channels */
2450 if (priv->hw->mac->map_mtl_to_dma)
2451 stmmac_rx_queue_dma_chan_map(priv);
2453 /* Enable MAC RX Queues */
2454 if (priv->hw->mac->rx_queue_enable)
2455 stmmac_mac_enable_rx_queues(priv);
2457 /* Set RX priorities */
2458 if (rx_queues_count > 1 && priv->hw->mac->rx_queue_prio)
2459 stmmac_mac_config_rx_queues_prio(priv);
2461 /* Set TX priorities */
2462 if (tx_queues_count > 1 && priv->hw->mac->tx_queue_prio)
2463 stmmac_mac_config_tx_queues_prio(priv);
2465 /* Set RX routing */
2466 if (rx_queues_count > 1 && priv->hw->mac->rx_queue_routing)
2467 stmmac_mac_config_rx_queues_routing(priv);
2471 * stmmac_hw_setup - setup mac in a usable state.
2472 * @dev : pointer to the device structure.
2474 * this is the main function to setup the HW in a usable state because the
2475 * dma engine is reset, the core registers are configured (e.g. AXI,
2476 * Checksum features, timers). The DMA is ready to start receiving and
2479 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2482 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
2484 struct stmmac_priv *priv = netdev_priv(dev);
2485 u32 rx_cnt = priv->plat->rx_queues_to_use;
2486 u32 tx_cnt = priv->plat->tx_queues_to_use;
2490 /* DMA initialization and SW reset */
2491 ret = stmmac_init_dma_engine(priv);
2493 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2498 /* Copy the MAC addr into the HW */
2499 priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
2501 /* PS and related bits will be programmed according to the speed */
2502 if (priv->hw->pcs) {
2503 int speed = priv->plat->mac_port_sel_speed;
2505 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2506 (speed == SPEED_1000)) {
2507 priv->hw->ps = speed;
2509 dev_warn(priv->device, "invalid port speed\n");
2514 /* Initialize the MAC Core */
2515 priv->hw->mac->core_init(priv->hw, dev);
2518 if (priv->synopsys_id >= DWMAC_CORE_4_00)
2519 stmmac_mtl_configuration(priv);
2521 ret = priv->hw->mac->rx_ipc(priv->hw);
2523 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2524 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2525 priv->hw->rx_csum = 0;
2528 /* Enable the MAC Rx/Tx */
2529 priv->hw->mac->set_mac(priv->ioaddr, true);
2531 /* Set the HW DMA mode and the COE */
2532 stmmac_dma_operation_mode(priv);
2534 stmmac_mmc_setup(priv);
2537 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2539 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2541 ret = stmmac_init_ptp(priv);
2542 if (ret == -EOPNOTSUPP)
2543 netdev_warn(priv->dev, "PTP not supported by HW\n");
2545 netdev_warn(priv->dev, "PTP init failed\n");
2548 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2550 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
2551 priv->rx_riwt = MAX_DMA_RIWT;
2552 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT, rx_cnt);
2555 if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane)
2556 priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0);
2558 /* set TX and RX rings length */
2559 stmmac_set_rings_length(priv);
2563 for (chan = 0; chan < tx_cnt; chan++)
2564 priv->hw->dma->enable_tso(priv->ioaddr, 1, chan);
2567 /* Start the ball rolling... */
2568 stmmac_start_all_dma(priv);
2573 static void stmmac_hw_teardown(struct net_device *dev)
2575 struct stmmac_priv *priv = netdev_priv(dev);
2577 clk_disable_unprepare(priv->plat->clk_ptp_ref);
2581 * stmmac_open - open entry point of the driver
2582 * @dev : pointer to the device structure.
2584 * This function is the open entry point of the driver.
2586 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2589 static int stmmac_open(struct net_device *dev)
2591 struct stmmac_priv *priv = netdev_priv(dev);
2594 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2595 priv->hw->pcs != STMMAC_PCS_TBI &&
2596 priv->hw->pcs != STMMAC_PCS_RTBI) {
2597 ret = stmmac_init_phy(dev);
2599 netdev_err(priv->dev,
2600 "%s: Cannot attach to PHY (error: %d)\n",
2606 /* Extra statistics */
2607 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2608 priv->xstats.threshold = tc;
2610 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
2611 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2614 ret = alloc_dma_desc_resources(priv);
2616 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2618 goto dma_desc_error;
2621 ret = init_dma_desc_rings(dev, GFP_KERNEL);
2623 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2628 ret = stmmac_hw_setup(dev, true);
2630 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2634 stmmac_init_tx_coalesce(priv);
2637 phy_start(dev->phydev);
2639 /* Request the IRQ lines */
2640 ret = request_irq(dev->irq, stmmac_interrupt,
2641 IRQF_SHARED, dev->name, dev);
2642 if (unlikely(ret < 0)) {
2643 netdev_err(priv->dev,
2644 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2645 __func__, dev->irq, ret);
2649 /* Request the Wake IRQ in case of another line is used for WoL */
2650 if (priv->wol_irq != dev->irq) {
2651 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2652 IRQF_SHARED, dev->name, dev);
2653 if (unlikely(ret < 0)) {
2654 netdev_err(priv->dev,
2655 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2656 __func__, priv->wol_irq, ret);
2661 /* Request the IRQ lines */
2662 if (priv->lpi_irq > 0) {
2663 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2665 if (unlikely(ret < 0)) {
2666 netdev_err(priv->dev,
2667 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2668 __func__, priv->lpi_irq, ret);
2673 stmmac_enable_all_queues(priv);
2674 stmmac_start_all_queues(priv);
2679 if (priv->wol_irq != dev->irq)
2680 free_irq(priv->wol_irq, dev);
2682 free_irq(dev->irq, dev);
2685 phy_stop(dev->phydev);
2687 del_timer_sync(&priv->txtimer);
2688 stmmac_hw_teardown(dev);
2690 free_dma_desc_resources(priv);
2693 phy_disconnect(dev->phydev);
2699 * stmmac_release - close entry point of the driver
2700 * @dev : device pointer.
2702 * This is the stop entry point of the driver.
2704 static int stmmac_release(struct net_device *dev)
2706 struct stmmac_priv *priv = netdev_priv(dev);
2708 /* Stop and disconnect the PHY */
2710 phy_stop(dev->phydev);
2711 phy_disconnect(dev->phydev);
2714 stmmac_stop_all_queues(priv);
2716 stmmac_disable_all_queues(priv);
2718 del_timer_sync(&priv->txtimer);
2720 /* Free the IRQ lines */
2721 free_irq(dev->irq, dev);
2722 if (priv->wol_irq != dev->irq)
2723 free_irq(priv->wol_irq, dev);
2724 if (priv->lpi_irq > 0)
2725 free_irq(priv->lpi_irq, dev);
2727 if (priv->eee_enabled) {
2728 priv->tx_path_in_lpi_mode = false;
2729 del_timer_sync(&priv->eee_ctrl_timer);
2732 /* Stop TX/RX DMA and clear the descriptors */
2733 stmmac_stop_all_dma(priv);
2735 /* Release and free the Rx/Tx resources */
2736 free_dma_desc_resources(priv);
2738 /* Disable the MAC Rx/Tx */
2739 priv->hw->mac->set_mac(priv->ioaddr, false);
2741 netif_carrier_off(dev);
2743 stmmac_release_ptp(priv);
2749 * stmmac_tso_allocator - close entry point of the driver
2750 * @priv: driver private structure
2751 * @des: buffer start address
2752 * @total_len: total length to fill in descriptors
2753 * @last_segmant: condition for the last descriptor
2754 * @queue: TX queue index
2756 * This function fills descriptor and request new descriptors according to
2757 * buffer length to fill
2759 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
2760 int total_len, bool last_segment, u32 queue)
2762 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2763 struct dma_desc *desc;
2767 tmp_len = total_len;
2769 while (tmp_len > 0) {
2770 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2771 desc = tx_q->dma_tx + tx_q->cur_tx;
2773 desc->des0 = cpu_to_le32(des + (total_len - tmp_len));
2774 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2775 TSO_MAX_BUFF_SIZE : tmp_len;
2777 priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size,
2779 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2782 tmp_len -= TSO_MAX_BUFF_SIZE;
2787 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2788 * @skb : the socket buffer
2789 * @dev : device pointer
2790 * Description: this is the transmit function that is called on TSO frames
2791 * (support available on GMAC4 and newer chips).
2792 * Diagram below show the ring programming in case of TSO frames:
2796 * | DES0 |---> buffer1 = L2/L3/L4 header
2797 * | DES1 |---> TCP Payload (can continue on next descr...)
2798 * | DES2 |---> buffer 1 and 2 len
2799 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2805 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
2807 * | DES2 | --> buffer 1 and 2 len
2811 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2813 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2815 struct dma_desc *desc, *first, *mss_desc = NULL;
2816 struct stmmac_priv *priv = netdev_priv(dev);
2817 int nfrags = skb_shinfo(skb)->nr_frags;
2818 u32 queue = skb_get_queue_mapping(skb);
2819 unsigned int first_entry, des;
2820 struct stmmac_tx_queue *tx_q;
2821 int tmp_pay_len = 0;
2826 tx_q = &priv->tx_queue[queue];
2828 /* Compute header lengths */
2829 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2831 /* Desc availability based on threshold should be enough safe */
2832 if (unlikely(stmmac_tx_avail(priv, queue) <
2833 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2834 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2835 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2837 /* This is a hard error, log it. */
2838 netdev_err(priv->dev,
2839 "%s: Tx Ring full when queue awake\n",
2842 return NETDEV_TX_BUSY;
2845 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2847 mss = skb_shinfo(skb)->gso_size;
2849 /* set new MSS value if needed */
2850 if (mss != priv->mss) {
2851 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
2852 priv->hw->desc->set_mss(mss_desc, mss);
2854 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2857 if (netif_msg_tx_queued(priv)) {
2858 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2859 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2860 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2864 first_entry = tx_q->cur_tx;
2866 desc = tx_q->dma_tx + first_entry;
2869 /* first descriptor: fill Headers on Buf1 */
2870 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2872 if (dma_mapping_error(priv->device, des))
2875 tx_q->tx_skbuff_dma[first_entry].buf = des;
2876 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2878 first->des0 = cpu_to_le32(des);
2880 /* Fill start of payload in buff2 of first descriptor */
2882 first->des1 = cpu_to_le32(des + proto_hdr_len);
2884 /* If needed take extra descriptors to fill the remaining payload */
2885 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2887 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
2889 /* Prepare fragments */
2890 for (i = 0; i < nfrags; i++) {
2891 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2893 des = skb_frag_dma_map(priv->device, frag, 0,
2894 skb_frag_size(frag),
2896 if (dma_mapping_error(priv->device, des))
2899 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2900 (i == nfrags - 1), queue);
2902 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
2903 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
2904 tx_q->tx_skbuff[tx_q->cur_tx] = NULL;
2905 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
2908 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
2910 /* Only the last descriptor gets to point to the skb. */
2911 tx_q->tx_skbuff[tx_q->cur_tx] = skb;
2913 /* We've used all descriptors we need for this skb, however,
2914 * advance cur_tx so that it references a fresh descriptor.
2915 * ndo_start_xmit will fill this descriptor the next time it's
2916 * called and stmmac_tx_clean may clean up to this descriptor.
2918 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2920 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
2921 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2923 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
2926 dev->stats.tx_bytes += skb->len;
2927 priv->xstats.tx_tso_frames++;
2928 priv->xstats.tx_tso_nfrags += nfrags;
2930 /* Manage tx mitigation */
2931 priv->tx_count_frames += nfrags + 1;
2932 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2933 mod_timer(&priv->txtimer,
2934 STMMAC_COAL_TIMER(priv->tx_coal_timer));
2936 priv->tx_count_frames = 0;
2937 priv->hw->desc->set_tx_ic(desc);
2938 priv->xstats.tx_set_ic_bit++;
2941 skb_tx_timestamp(skb);
2943 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2944 priv->hwts_tx_en)) {
2945 /* declare that device is doing timestamping */
2946 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2947 priv->hw->desc->enable_tx_timestamp(first);
2950 /* Complete the first descriptor before granting the DMA */
2951 priv->hw->desc->prepare_tso_tx_desc(first, 1,
2954 1, tx_q->tx_skbuff_dma[first_entry].last_segment,
2955 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2957 /* If context desc is used to change MSS */
2959 /* Make sure that first descriptor has been completely
2960 * written, including its own bit. This is because MSS is
2961 * actually before first descriptor, so we need to make
2962 * sure that MSS's own bit is the last thing written.
2965 priv->hw->desc->set_tx_owner(mss_desc);
2968 /* The own bit must be the latest setting done when prepare the
2969 * descriptor and then barrier is needed to make sure that
2970 * all is coherent before granting the DMA engine.
2974 if (netif_msg_pktdata(priv)) {
2975 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2976 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
2977 tx_q->cur_tx, first, nfrags);
2979 priv->hw->desc->display_ring((void *)tx_q->dma_tx, DMA_TX_SIZE,
2982 pr_info(">>> frame to be transmitted: ");
2983 print_pkt(skb->data, skb_headlen(skb));
2986 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
2988 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
2989 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, tx_q->tx_tail_addr,
2992 return NETDEV_TX_OK;
2995 dev_err(priv->device, "Tx dma map failed\n");
2997 priv->dev->stats.tx_dropped++;
2998 return NETDEV_TX_OK;
3002 * stmmac_xmit - Tx entry point of the driver
3003 * @skb : the socket buffer
3004 * @dev : device pointer
3005 * Description : this is the tx entry point of the driver.
3006 * It programs the chain or the ring and supports oversized frames
3009 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
3011 struct stmmac_priv *priv = netdev_priv(dev);
3012 unsigned int nopaged_len = skb_headlen(skb);
3013 int i, csum_insertion = 0, is_jumbo = 0;
3014 u32 queue = skb_get_queue_mapping(skb);
3015 int nfrags = skb_shinfo(skb)->nr_frags;
3017 unsigned int first_entry;
3018 struct dma_desc *desc, *first;
3019 struct stmmac_tx_queue *tx_q;
3020 unsigned int enh_desc;
3023 tx_q = &priv->tx_queue[queue];
3025 if (priv->tx_path_in_lpi_mode)
3026 stmmac_disable_eee_mode(priv);
3028 /* Manage oversized TCP frames for GMAC4 device */
3029 if (skb_is_gso(skb) && priv->tso) {
3030 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3032 * There is no way to determine the number of TSO
3033 * capable Queues. Let's use always the Queue 0
3034 * because if TSO is supported then at least this
3035 * one will be capable.
3037 skb_set_queue_mapping(skb, 0);
3039 return stmmac_tso_xmit(skb, dev);
3043 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
3044 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3045 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3047 /* This is a hard error, log it. */
3048 netdev_err(priv->dev,
3049 "%s: Tx Ring full when queue awake\n",
3052 return NETDEV_TX_BUSY;
3055 entry = tx_q->cur_tx;
3056 first_entry = entry;
3058 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
3060 if (likely(priv->extend_desc))
3061 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3063 desc = tx_q->dma_tx + entry;
3067 enh_desc = priv->plat->enh_desc;
3068 /* To program the descriptors according to the size of the frame */
3070 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
3072 if (unlikely(is_jumbo) && likely(priv->synopsys_id <
3074 entry = priv->hw->mode->jumbo_frm(tx_q, skb, csum_insertion);
3075 if (unlikely(entry < 0))
3079 for (i = 0; i < nfrags; i++) {
3080 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3081 int len = skb_frag_size(frag);
3082 bool last_segment = (i == (nfrags - 1));
3084 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3086 if (likely(priv->extend_desc))
3087 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3089 desc = tx_q->dma_tx + entry;
3091 des = skb_frag_dma_map(priv->device, frag, 0, len,
3093 if (dma_mapping_error(priv->device, des))
3094 goto dma_map_err; /* should reuse desc w/o issues */
3096 tx_q->tx_skbuff[entry] = NULL;
3098 tx_q->tx_skbuff_dma[entry].buf = des;
3099 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
3100 desc->des0 = cpu_to_le32(des);
3102 desc->des2 = cpu_to_le32(des);
3104 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3105 tx_q->tx_skbuff_dma[entry].len = len;
3106 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3108 /* Prepare the descriptor and set the own bit too */
3109 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
3110 priv->mode, 1, last_segment,
3114 /* Only the last descriptor gets to point to the skb. */
3115 tx_q->tx_skbuff[entry] = skb;
3117 /* We've used all descriptors we need for this skb, however,
3118 * advance cur_tx so that it references a fresh descriptor.
3119 * ndo_start_xmit will fill this descriptor the next time it's
3120 * called and stmmac_tx_clean may clean up to this descriptor.
3122 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3123 tx_q->cur_tx = entry;
3125 if (netif_msg_pktdata(priv)) {
3128 netdev_dbg(priv->dev,
3129 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3130 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3131 entry, first, nfrags);
3133 if (priv->extend_desc)
3134 tx_head = (void *)tx_q->dma_etx;
3136 tx_head = (void *)tx_q->dma_tx;
3138 priv->hw->desc->display_ring(tx_head, DMA_TX_SIZE, false);
3140 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3141 print_pkt(skb->data, skb->len);
3144 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3145 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3147 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3150 dev->stats.tx_bytes += skb->len;
3152 /* According to the coalesce parameter the IC bit for the latest
3153 * segment is reset and the timer re-started to clean the tx status.
3154 * This approach takes care about the fragments: desc is the first
3155 * element in case of no SG.
3157 priv->tx_count_frames += nfrags + 1;
3158 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
3159 mod_timer(&priv->txtimer,
3160 STMMAC_COAL_TIMER(priv->tx_coal_timer));
3162 priv->tx_count_frames = 0;
3163 priv->hw->desc->set_tx_ic(desc);
3164 priv->xstats.tx_set_ic_bit++;
3167 skb_tx_timestamp(skb);
3169 /* Ready to fill the first descriptor and set the OWN bit w/o any
3170 * problems because all the descriptors are actually ready to be
3171 * passed to the DMA engine.
3173 if (likely(!is_jumbo)) {
3174 bool last_segment = (nfrags == 0);
3176 des = dma_map_single(priv->device, skb->data,
3177 nopaged_len, DMA_TO_DEVICE);
3178 if (dma_mapping_error(priv->device, des))
3181 tx_q->tx_skbuff_dma[first_entry].buf = des;
3182 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
3183 first->des0 = cpu_to_le32(des);
3185 first->des2 = cpu_to_le32(des);
3187 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3188 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
3190 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3191 priv->hwts_tx_en)) {
3192 /* declare that device is doing timestamping */
3193 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3194 priv->hw->desc->enable_tx_timestamp(first);
3197 /* Prepare the first descriptor setting the OWN bit too */
3198 priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len,
3199 csum_insertion, priv->mode, 1,
3200 last_segment, skb->len);
3202 /* The own bit must be the latest setting done when prepare the
3203 * descriptor and then barrier is needed to make sure that
3204 * all is coherent before granting the DMA engine.
3209 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3211 if (priv->synopsys_id < DWMAC_CORE_4_00)
3212 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
3214 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3215 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, tx_q->tx_tail_addr,
3219 return NETDEV_TX_OK;
3222 netdev_err(priv->dev, "Tx DMA map failed\n");
3224 priv->dev->stats.tx_dropped++;
3225 return NETDEV_TX_OK;
3228 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3230 struct ethhdr *ehdr;
3233 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
3234 NETIF_F_HW_VLAN_CTAG_RX &&
3235 !__vlan_get_tag(skb, &vlanid)) {
3236 /* pop the vlan tag */
3237 ehdr = (struct ethhdr *)skb->data;
3238 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
3239 skb_pull(skb, VLAN_HLEN);
3240 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
3245 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q)
3247 if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH)
3254 * stmmac_rx_refill - refill used skb preallocated buffers
3255 * @priv: driver private structure
3256 * @queue: RX queue index
3257 * Description : this is to reallocate the skb for the reception process
3258 * that is based on zero-copy.
3260 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
3262 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3263 int dirty = stmmac_rx_dirty(priv, queue);
3264 unsigned int entry = rx_q->dirty_rx;
3266 int bfsize = priv->dma_buf_sz;
3268 while (dirty-- > 0) {
3271 if (priv->extend_desc)
3272 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3274 p = rx_q->dma_rx + entry;
3276 if (likely(!rx_q->rx_skbuff[entry])) {
3277 struct sk_buff *skb;
3279 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
3280 if (unlikely(!skb)) {
3281 /* so for a while no zero-copy! */
3282 rx_q->rx_zeroc_thresh = STMMAC_RX_THRESH;
3283 if (unlikely(net_ratelimit()))
3284 dev_err(priv->device,
3285 "fail to alloc skb entry %d\n",
3290 rx_q->rx_skbuff[entry] = skb;
3291 rx_q->rx_skbuff_dma[entry] =
3292 dma_map_single(priv->device, skb->data, bfsize,
3294 if (dma_mapping_error(priv->device,
3295 rx_q->rx_skbuff_dma[entry])) {
3296 netdev_err(priv->dev, "Rx DMA map failed\n");
3301 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) {
3302 p->des0 = cpu_to_le32(rx_q->rx_skbuff_dma[entry]);
3305 p->des2 = cpu_to_le32(rx_q->rx_skbuff_dma[entry]);
3307 if (priv->hw->mode->refill_desc3)
3308 priv->hw->mode->refill_desc3(rx_q, p);
3310 if (rx_q->rx_zeroc_thresh > 0)
3311 rx_q->rx_zeroc_thresh--;
3313 netif_dbg(priv, rx_status, priv->dev,
3314 "refill entry #%d\n", entry);
3318 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
3319 priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0, priv->dma_buf_sz);
3321 priv->hw->desc->set_rx_owner(p);
3325 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
3327 rx_q->dirty_rx = entry;
3331 * stmmac_rx - manage the receive process
3332 * @priv: driver private structure
3333 * @limit: napi bugget
3334 * @queue: RX queue index.
3335 * Description : this the function called by the napi poll method.
3336 * It gets all the frames inside the ring.
3338 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
3340 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3341 int coe = priv->hw->rx_csum;
3342 unsigned int next_entry = rx_q->cur_rx;
3343 unsigned int count = 0;
3345 if (netif_msg_rx_status(priv)) {
3348 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
3349 if (priv->extend_desc)
3350 rx_head = (void *)rx_q->dma_erx;
3352 rx_head = (void *)rx_q->dma_rx;
3354 priv->hw->desc->display_ring(rx_head, DMA_RX_SIZE, true);
3356 while (count < limit) {
3359 struct dma_desc *np;
3363 if (priv->extend_desc)
3364 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3366 p = rx_q->dma_rx + entry;
3368 /* read the status of the incoming frame */
3369 status = priv->hw->desc->rx_status(&priv->dev->stats,
3371 /* check if managed by the DMA otherwise go ahead */
3372 if (unlikely(status & dma_own))
3377 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3378 next_entry = rx_q->cur_rx;
3380 if (priv->extend_desc)
3381 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
3383 np = rx_q->dma_rx + next_entry;
3387 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
3388 priv->hw->desc->rx_extended_status(&priv->dev->stats,
3392 if (unlikely(status == discard_frame)) {
3393 priv->dev->stats.rx_errors++;
3394 if (priv->hwts_rx_en && !priv->extend_desc) {
3395 /* DESC2 & DESC3 will be overwritten by device
3396 * with timestamp value, hence reinitialize
3397 * them in stmmac_rx_refill() function so that
3398 * device can reuse it.
3400 dev_kfree_skb_any(rx_q->rx_skbuff[entry]);
3401 rx_q->rx_skbuff[entry] = NULL;
3402 dma_unmap_single(priv->device,
3403 rx_q->rx_skbuff_dma[entry],
3408 struct sk_buff *skb;
3412 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
3413 des = le32_to_cpu(p->des0);
3415 des = le32_to_cpu(p->des2);
3417 frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
3419 /* If frame length is greater than skb buffer size
3420 * (preallocated during init) then the packet is
3423 if (frame_len > priv->dma_buf_sz) {
3424 if (net_ratelimit())
3425 netdev_err(priv->dev,
3426 "len %d larger than size (%d)\n",
3427 frame_len, priv->dma_buf_sz);
3428 priv->dev->stats.rx_length_errors++;
3432 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3433 * Type frames (LLC/LLC-SNAP)
3435 * llc_snap is never checked in GMAC >= 4, so this ACS
3436 * feature is always disabled and packets need to be
3437 * stripped manually.
3439 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
3440 unlikely(status != llc_snap))
3441 frame_len -= ETH_FCS_LEN;
3443 if (netif_msg_rx_status(priv)) {
3444 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n",
3446 if (frame_len > ETH_FRAME_LEN)
3447 netdev_dbg(priv->dev, "frame size %d, COE: %d\n",
3451 /* The zero-copy is always used for all the sizes
3452 * in case of GMAC4 because it needs
3453 * to refill the used descriptors, always.
3455 if (unlikely(!priv->plat->has_gmac4 &&
3456 ((frame_len < priv->rx_copybreak) ||
3457 stmmac_rx_threshold_count(rx_q)))) {
3458 skb = netdev_alloc_skb_ip_align(priv->dev,
3460 if (unlikely(!skb)) {
3461 if (net_ratelimit())
3462 dev_warn(priv->device,
3463 "packet dropped\n");
3464 priv->dev->stats.rx_dropped++;
3468 dma_sync_single_for_cpu(priv->device,
3472 skb_copy_to_linear_data(skb,
3474 rx_skbuff[entry]->data,
3477 skb_put(skb, frame_len);
3478 dma_sync_single_for_device(priv->device,
3483 skb = rx_q->rx_skbuff[entry];
3484 if (unlikely(!skb)) {
3485 if (net_ratelimit())
3486 netdev_err(priv->dev,
3487 "%s: Inconsistent Rx chain\n",
3489 priv->dev->stats.rx_dropped++;
3492 prefetch(skb->data - NET_IP_ALIGN);
3493 rx_q->rx_skbuff[entry] = NULL;
3494 rx_q->rx_zeroc_thresh++;
3496 skb_put(skb, frame_len);
3497 dma_unmap_single(priv->device,
3498 rx_q->rx_skbuff_dma[entry],
3503 if (netif_msg_pktdata(priv)) {
3504 netdev_dbg(priv->dev, "frame received (%dbytes)",
3506 print_pkt(skb->data, frame_len);
3509 stmmac_get_rx_hwtstamp(priv, p, np, skb);
3511 stmmac_rx_vlan(priv->dev, skb);
3513 skb->protocol = eth_type_trans(skb, priv->dev);
3516 skb_checksum_none_assert(skb);
3518 skb->ip_summed = CHECKSUM_UNNECESSARY;
3520 napi_gro_receive(&rx_q->napi, skb);
3522 priv->dev->stats.rx_packets++;
3523 priv->dev->stats.rx_bytes += frame_len;
3527 stmmac_rx_refill(priv, queue);
3529 priv->xstats.rx_pkt_n += count;
3535 * stmmac_poll - stmmac poll method (NAPI)
3536 * @napi : pointer to the napi structure.
3537 * @budget : maximum number of packets that the current CPU can receive from
3540 * To look at the incoming frames and clear the tx resources.
3542 static int stmmac_poll(struct napi_struct *napi, int budget)
3544 struct stmmac_rx_queue *rx_q =
3545 container_of(napi, struct stmmac_rx_queue, napi);
3546 struct stmmac_priv *priv = rx_q->priv_data;
3547 u32 tx_count = priv->plat->tx_queues_to_use;
3548 u32 chan = rx_q->queue_index;
3552 priv->xstats.napi_poll++;
3554 /* check all the queues */
3555 for (queue = 0; queue < tx_count; queue++)
3556 stmmac_tx_clean(priv, queue);
3558 work_done = stmmac_rx(priv, budget, rx_q->queue_index);
3559 if (work_done < budget) {
3560 napi_complete_done(napi, work_done);
3561 stmmac_enable_dma_irq(priv, chan);
3568 * @dev : Pointer to net device structure
3569 * Description: this function is called when a packet transmission fails to
3570 * complete within a reasonable time. The driver will mark the error in the
3571 * netdev structure and arrange for the device to be reset to a sane state
3572 * in order to transmit a new packet.
3574 static void stmmac_tx_timeout(struct net_device *dev)
3576 struct stmmac_priv *priv = netdev_priv(dev);
3577 u32 tx_count = priv->plat->tx_queues_to_use;
3580 /* Clear Tx resources and restart transmitting again */
3581 for (chan = 0; chan < tx_count; chan++)
3582 stmmac_tx_err(priv, chan);
3586 * stmmac_set_rx_mode - entry point for multicast addressing
3587 * @dev : pointer to the device structure
3589 * This function is a driver entry point which gets called by the kernel
3590 * whenever multicast addresses must be enabled/disabled.
3594 static void stmmac_set_rx_mode(struct net_device *dev)
3596 struct stmmac_priv *priv = netdev_priv(dev);
3598 priv->hw->mac->set_filter(priv->hw, dev);
3602 * stmmac_change_mtu - entry point to change MTU size for the device.
3603 * @dev : device pointer.
3604 * @new_mtu : the new MTU size for the device.
3605 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
3606 * to drive packet transmission. Ethernet has an MTU of 1500 octets
3607 * (ETH_DATA_LEN). This value can be changed with ifconfig.
3609 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3612 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3614 struct stmmac_priv *priv = netdev_priv(dev);
3615 int txfifosz = priv->plat->tx_fifo_size;
3616 const int mtu = new_mtu;
3619 txfifosz = priv->dma_cap.tx_fifo_size;
3621 txfifosz /= priv->plat->tx_queues_to_use;
3623 if (netif_running(dev)) {
3624 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3628 new_mtu = STMMAC_ALIGN(new_mtu);
3630 /* If condition true, FIFO is too small or MTU too large */
3631 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
3636 netdev_update_features(dev);
3641 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3642 netdev_features_t features)
3644 struct stmmac_priv *priv = netdev_priv(dev);
3646 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
3647 features &= ~NETIF_F_RXCSUM;
3649 if (!priv->plat->tx_coe)
3650 features &= ~NETIF_F_CSUM_MASK;
3652 /* Some GMAC devices have a bugged Jumbo frame support that
3653 * needs to have the Tx COE disabled for oversized frames
3654 * (due to limited buffer sizes). In this case we disable
3655 * the TX csum insertion in the TDES and not use SF.
3657 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
3658 features &= ~NETIF_F_CSUM_MASK;
3660 /* Disable tso if asked by ethtool */
3661 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3662 if (features & NETIF_F_TSO)
3671 static int stmmac_set_features(struct net_device *netdev,
3672 netdev_features_t features)
3674 struct stmmac_priv *priv = netdev_priv(netdev);
3676 /* Keep the COE Type in case of csum is supporting */
3677 if (features & NETIF_F_RXCSUM)
3678 priv->hw->rx_csum = priv->plat->rx_coe;
3680 priv->hw->rx_csum = 0;
3681 /* No check needed because rx_coe has been set before and it will be
3682 * fixed in case of issue.
3684 priv->hw->mac->rx_ipc(priv->hw);
3690 * stmmac_interrupt - main ISR
3691 * @irq: interrupt number.
3692 * @dev_id: to pass the net device pointer.
3693 * Description: this is the main driver interrupt service routine.
3695 * o DMA service routine (to manage incoming frame reception and transmission
3697 * o Core interrupts to manage: remote wake-up, management counter, LPI
3700 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3702 struct net_device *dev = (struct net_device *)dev_id;
3703 struct stmmac_priv *priv = netdev_priv(dev);
3704 u32 rx_cnt = priv->plat->rx_queues_to_use;
3705 u32 tx_cnt = priv->plat->tx_queues_to_use;
3709 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
3712 pm_wakeup_event(priv->device, 0);
3714 if (unlikely(!dev)) {
3715 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
3719 /* To handle GMAC own interrupts */
3720 if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) {
3721 int status = priv->hw->mac->host_irq_status(priv->hw,
3724 if (unlikely(status)) {
3725 /* For LPI we need to save the tx status */
3726 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
3727 priv->tx_path_in_lpi_mode = true;
3728 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
3729 priv->tx_path_in_lpi_mode = false;
3732 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3733 for (queue = 0; queue < queues_count; queue++) {
3734 struct stmmac_rx_queue *rx_q =
3735 &priv->rx_queue[queue];
3738 priv->hw->mac->host_mtl_irq_status(priv->hw,
3741 if (status & CORE_IRQ_MTL_RX_OVERFLOW &&
3742 priv->hw->dma->set_rx_tail_ptr)
3743 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr,
3749 /* PCS link status */
3750 if (priv->hw->pcs) {
3751 if (priv->xstats.pcs_link)
3752 netif_carrier_on(dev);
3754 netif_carrier_off(dev);
3758 /* To handle DMA interrupts */
3759 stmmac_dma_interrupt(priv);
3764 #ifdef CONFIG_NET_POLL_CONTROLLER
3765 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3766 * to allow network I/O with interrupts disabled.
3768 static void stmmac_poll_controller(struct net_device *dev)
3770 disable_irq(dev->irq);
3771 stmmac_interrupt(dev->irq, dev);
3772 enable_irq(dev->irq);
3777 * stmmac_ioctl - Entry point for the Ioctl
3778 * @dev: Device pointer.
3779 * @rq: An IOCTL specefic structure, that can contain a pointer to
3780 * a proprietary structure used to pass information to the driver.
3781 * @cmd: IOCTL command
3783 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
3785 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3787 int ret = -EOPNOTSUPP;
3789 if (!netif_running(dev))
3798 ret = phy_mii_ioctl(dev->phydev, rq, cmd);
3801 ret = stmmac_hwtstamp_ioctl(dev, rq);
3810 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
3812 struct stmmac_priv *priv = netdev_priv(ndev);
3815 ret = eth_mac_addr(ndev, addr);
3819 priv->hw->mac->set_umac_addr(priv->hw, ndev->dev_addr, 0);
3824 #ifdef CONFIG_DEBUG_FS
3825 static struct dentry *stmmac_fs_dir;
3827 static void sysfs_display_ring(void *head, int size, int extend_desc,
3828 struct seq_file *seq)
3831 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
3832 struct dma_desc *p = (struct dma_desc *)head;
3834 for (i = 0; i < size; i++) {
3836 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3837 i, (unsigned int)virt_to_phys(ep),
3838 le32_to_cpu(ep->basic.des0),
3839 le32_to_cpu(ep->basic.des1),
3840 le32_to_cpu(ep->basic.des2),
3841 le32_to_cpu(ep->basic.des3));
3844 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3845 i, (unsigned int)virt_to_phys(p),
3846 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
3847 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
3850 seq_printf(seq, "\n");
3854 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
3856 struct net_device *dev = seq->private;
3857 struct stmmac_priv *priv = netdev_priv(dev);
3858 u32 rx_count = priv->plat->rx_queues_to_use;
3859 u32 tx_count = priv->plat->tx_queues_to_use;
3862 if ((dev->flags & IFF_UP) == 0)
3865 for (queue = 0; queue < rx_count; queue++) {
3866 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3868 seq_printf(seq, "RX Queue %d:\n", queue);
3870 if (priv->extend_desc) {
3871 seq_printf(seq, "Extended descriptor ring:\n");
3872 sysfs_display_ring((void *)rx_q->dma_erx,
3873 DMA_RX_SIZE, 1, seq);
3875 seq_printf(seq, "Descriptor ring:\n");
3876 sysfs_display_ring((void *)rx_q->dma_rx,
3877 DMA_RX_SIZE, 0, seq);
3881 for (queue = 0; queue < tx_count; queue++) {
3882 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3884 seq_printf(seq, "TX Queue %d:\n", queue);
3886 if (priv->extend_desc) {
3887 seq_printf(seq, "Extended descriptor ring:\n");
3888 sysfs_display_ring((void *)tx_q->dma_etx,
3889 DMA_TX_SIZE, 1, seq);
3891 seq_printf(seq, "Descriptor ring:\n");
3892 sysfs_display_ring((void *)tx_q->dma_tx,
3893 DMA_TX_SIZE, 0, seq);
3900 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
3902 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
3905 /* Debugfs files, should appear in /sys/kernel/debug/stmmaceth/eth0 */
3907 static const struct file_operations stmmac_rings_status_fops = {
3908 .owner = THIS_MODULE,
3909 .open = stmmac_sysfs_ring_open,
3911 .llseek = seq_lseek,
3912 .release = single_release,
3915 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
3917 struct net_device *dev = seq->private;
3918 struct stmmac_priv *priv = netdev_priv(dev);
3920 if (!priv->hw_cap_support) {
3921 seq_printf(seq, "DMA HW features not supported\n");
3925 seq_printf(seq, "==============================\n");
3926 seq_printf(seq, "\tDMA HW features\n");
3927 seq_printf(seq, "==============================\n");
3929 seq_printf(seq, "\t10/100 Mbps: %s\n",
3930 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
3931 seq_printf(seq, "\t1000 Mbps: %s\n",
3932 (priv->dma_cap.mbps_1000) ? "Y" : "N");
3933 seq_printf(seq, "\tHalf duplex: %s\n",
3934 (priv->dma_cap.half_duplex) ? "Y" : "N");
3935 seq_printf(seq, "\tHash Filter: %s\n",
3936 (priv->dma_cap.hash_filter) ? "Y" : "N");
3937 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
3938 (priv->dma_cap.multi_addr) ? "Y" : "N");
3939 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
3940 (priv->dma_cap.pcs) ? "Y" : "N");
3941 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
3942 (priv->dma_cap.sma_mdio) ? "Y" : "N");
3943 seq_printf(seq, "\tPMT Remote wake up: %s\n",
3944 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
3945 seq_printf(seq, "\tPMT Magic Frame: %s\n",
3946 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
3947 seq_printf(seq, "\tRMON module: %s\n",
3948 (priv->dma_cap.rmon) ? "Y" : "N");
3949 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
3950 (priv->dma_cap.time_stamp) ? "Y" : "N");
3951 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
3952 (priv->dma_cap.atime_stamp) ? "Y" : "N");
3953 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
3954 (priv->dma_cap.eee) ? "Y" : "N");
3955 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
3956 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
3957 (priv->dma_cap.tx_coe) ? "Y" : "N");
3958 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3959 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
3960 (priv->dma_cap.rx_coe) ? "Y" : "N");
3962 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
3963 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
3964 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
3965 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
3967 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
3968 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
3969 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
3970 priv->dma_cap.number_rx_channel);
3971 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
3972 priv->dma_cap.number_tx_channel);
3973 seq_printf(seq, "\tEnhanced descriptors: %s\n",
3974 (priv->dma_cap.enh_desc) ? "Y" : "N");
3979 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
3981 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
3984 static const struct file_operations stmmac_dma_cap_fops = {
3985 .owner = THIS_MODULE,
3986 .open = stmmac_sysfs_dma_cap_open,
3988 .llseek = seq_lseek,
3989 .release = single_release,
3992 static int stmmac_init_fs(struct net_device *dev)
3994 struct stmmac_priv *priv = netdev_priv(dev);
3996 /* Create per netdev entries */
3997 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
3999 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
4000 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n");
4005 /* Entry to report DMA RX/TX rings */
4006 priv->dbgfs_rings_status =
4007 debugfs_create_file("descriptors_status", S_IRUGO,
4008 priv->dbgfs_dir, dev,
4009 &stmmac_rings_status_fops);
4011 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
4012 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n");
4013 debugfs_remove_recursive(priv->dbgfs_dir);
4018 /* Entry to report the DMA HW features */
4019 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
4021 dev, &stmmac_dma_cap_fops);
4023 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
4024 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n");
4025 debugfs_remove_recursive(priv->dbgfs_dir);
4033 static void stmmac_exit_fs(struct net_device *dev)
4035 struct stmmac_priv *priv = netdev_priv(dev);
4037 debugfs_remove_recursive(priv->dbgfs_dir);
4039 #endif /* CONFIG_DEBUG_FS */
4041 static const struct net_device_ops stmmac_netdev_ops = {
4042 .ndo_open = stmmac_open,
4043 .ndo_start_xmit = stmmac_xmit,
4044 .ndo_stop = stmmac_release,
4045 .ndo_change_mtu = stmmac_change_mtu,
4046 .ndo_fix_features = stmmac_fix_features,
4047 .ndo_set_features = stmmac_set_features,
4048 .ndo_set_rx_mode = stmmac_set_rx_mode,
4049 .ndo_tx_timeout = stmmac_tx_timeout,
4050 .ndo_do_ioctl = stmmac_ioctl,
4051 #ifdef CONFIG_NET_POLL_CONTROLLER
4052 .ndo_poll_controller = stmmac_poll_controller,
4054 .ndo_set_mac_address = stmmac_set_mac_address,
4058 * stmmac_hw_init - Init the MAC device
4059 * @priv: driver private structure
4060 * Description: this function is to configure the MAC device according to
4061 * some platform parameters or the HW capability register. It prepares the
4062 * driver to use either ring or chain modes and to setup either enhanced or
4063 * normal descriptors.
4065 static int stmmac_hw_init(struct stmmac_priv *priv)
4067 struct mac_device_info *mac;
4069 /* Identify the MAC HW device */
4070 if (priv->plat->setup) {
4071 mac = priv->plat->setup(priv);
4072 } else if (priv->plat->has_gmac) {
4073 priv->dev->priv_flags |= IFF_UNICAST_FLT;
4074 mac = dwmac1000_setup(priv->ioaddr,
4075 priv->plat->multicast_filter_bins,
4076 priv->plat->unicast_filter_entries,
4077 &priv->synopsys_id);
4078 } else if (priv->plat->has_gmac4) {
4079 priv->dev->priv_flags |= IFF_UNICAST_FLT;
4080 mac = dwmac4_setup(priv->ioaddr,
4081 priv->plat->multicast_filter_bins,
4082 priv->plat->unicast_filter_entries,
4083 &priv->synopsys_id);
4085 mac = dwmac100_setup(priv->ioaddr, &priv->synopsys_id);
4092 /* dwmac-sun8i only work in chain mode */
4093 if (priv->plat->has_sun8i)
4096 /* To use the chained or ring mode */
4097 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
4098 priv->hw->mode = &dwmac4_ring_mode_ops;
4101 priv->hw->mode = &chain_mode_ops;
4102 dev_info(priv->device, "Chain mode enabled\n");
4103 priv->mode = STMMAC_CHAIN_MODE;
4105 priv->hw->mode = &ring_mode_ops;
4106 dev_info(priv->device, "Ring mode enabled\n");
4107 priv->mode = STMMAC_RING_MODE;
4111 /* Get the HW capability (new GMAC newer than 3.50a) */
4112 priv->hw_cap_support = stmmac_get_hw_features(priv);
4113 if (priv->hw_cap_support) {
4114 dev_info(priv->device, "DMA HW capability register supported\n");
4116 /* We can override some gmac/dma configuration fields: e.g.
4117 * enh_desc, tx_coe (e.g. that are passed through the
4118 * platform) with the values from the HW capability
4119 * register (if supported).
4121 priv->plat->enh_desc = priv->dma_cap.enh_desc;
4122 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
4123 priv->hw->pmt = priv->plat->pmt;
4125 /* TXCOE doesn't work in thresh DMA mode */
4126 if (priv->plat->force_thresh_dma_mode)
4127 priv->plat->tx_coe = 0;
4129 priv->plat->tx_coe = priv->dma_cap.tx_coe;
4131 /* In case of GMAC4 rx_coe is from HW cap register. */
4132 priv->plat->rx_coe = priv->dma_cap.rx_coe;
4134 if (priv->dma_cap.rx_coe_type2)
4135 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4136 else if (priv->dma_cap.rx_coe_type1)
4137 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4140 dev_info(priv->device, "No HW DMA feature register supported\n");
4143 /* To use alternate (extended), normal or GMAC4 descriptor structures */
4144 if (priv->synopsys_id >= DWMAC_CORE_4_00)
4145 priv->hw->desc = &dwmac4_desc_ops;
4147 stmmac_selec_desc_mode(priv);
4149 if (priv->plat->rx_coe) {
4150 priv->hw->rx_csum = priv->plat->rx_coe;
4151 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
4152 if (priv->synopsys_id < DWMAC_CORE_4_00)
4153 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
4155 if (priv->plat->tx_coe)
4156 dev_info(priv->device, "TX Checksum insertion supported\n");
4158 if (priv->plat->pmt) {
4159 dev_info(priv->device, "Wake-Up On Lan supported\n");
4160 device_set_wakeup_capable(priv->device, 1);
4163 if (priv->dma_cap.tsoen)
4164 dev_info(priv->device, "TSO supported\n");
4171 * @device: device pointer
4172 * @plat_dat: platform data pointer
4173 * @res: stmmac resource pointer
4174 * Description: this is the main probe function used to
4175 * call the alloc_etherdev, allocate the priv structure.
4177 * returns 0 on success, otherwise errno.
4179 int stmmac_dvr_probe(struct device *device,
4180 struct plat_stmmacenet_data *plat_dat,
4181 struct stmmac_resources *res)
4183 struct net_device *ndev = NULL;
4184 struct stmmac_priv *priv;
4188 ndev = alloc_etherdev_mqs(sizeof(struct stmmac_priv),
4194 SET_NETDEV_DEV(ndev, device);
4196 priv = netdev_priv(ndev);
4197 priv->device = device;
4200 stmmac_set_ethtool_ops(ndev);
4201 priv->pause = pause;
4202 priv->plat = plat_dat;
4203 priv->ioaddr = res->addr;
4204 priv->dev->base_addr = (unsigned long)res->addr;
4206 priv->dev->irq = res->irq;
4207 priv->wol_irq = res->wol_irq;
4208 priv->lpi_irq = res->lpi_irq;
4211 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
4213 dev_set_drvdata(device, priv->dev);
4215 /* Verify driver arguments */
4216 stmmac_verify_args();
4218 /* Override with kernel parameters if supplied XXX CRS XXX
4219 * this needs to have multiple instances
4221 if ((phyaddr >= 0) && (phyaddr <= 31))
4222 priv->plat->phy_addr = phyaddr;
4224 if (priv->plat->stmmac_rst) {
4225 ret = reset_control_assert(priv->plat->stmmac_rst);
4226 reset_control_deassert(priv->plat->stmmac_rst);
4227 /* Some reset controllers have only reset callback instead of
4228 * assert + deassert callbacks pair.
4230 if (ret == -ENOTSUPP)
4231 reset_control_reset(priv->plat->stmmac_rst);
4234 /* Init MAC and get the capabilities */
4235 ret = stmmac_hw_init(priv);
4239 stmmac_check_ether_addr(priv);
4241 /* Configure real RX and TX queues */
4242 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4243 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
4245 ndev->netdev_ops = &stmmac_netdev_ops;
4247 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4250 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4251 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
4253 dev_info(priv->device, "TSO feature enabled\n");
4255 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4256 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
4257 #ifdef STMMAC_VLAN_TAG_USED
4258 /* Both mac100 and gmac support receive VLAN tag detection */
4259 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
4261 priv->msg_enable = netif_msg_init(debug, default_msg_level);
4263 /* MTU range: 46 - hw-specific max */
4264 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
4265 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4266 ndev->max_mtu = JUMBO_LEN;
4268 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
4269 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4270 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4272 if ((priv->plat->maxmtu < ndev->max_mtu) &&
4273 (priv->plat->maxmtu >= ndev->min_mtu))
4274 ndev->max_mtu = priv->plat->maxmtu;
4275 else if (priv->plat->maxmtu < ndev->min_mtu)
4276 dev_warn(priv->device,
4277 "%s: warning: maxmtu having invalid value (%d)\n",
4278 __func__, priv->plat->maxmtu);
4281 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
4283 /* Rx Watchdog is available in the COREs newer than the 3.40.
4284 * In some case, for example on bugged HW this feature
4285 * has to be disable and this can be done by passing the
4286 * riwt_off field from the platform.
4288 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
4290 dev_info(priv->device,
4291 "Enable RX Mitigation via HW Watchdog Timer\n");
4294 for (queue = 0; queue < priv->plat->rx_queues_to_use; queue++) {
4295 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4297 netif_napi_add(ndev, &rx_q->napi, stmmac_poll,
4298 (8 * priv->plat->rx_queues_to_use));
4301 mutex_init(&priv->lock);
4303 /* If a specific clk_csr value is passed from the platform
4304 * this means that the CSR Clock Range selection cannot be
4305 * changed at run-time and it is fixed. Viceversa the driver'll try to
4306 * set the MDC clock dynamically according to the csr actual
4309 if (!priv->plat->clk_csr)
4310 stmmac_clk_csr_set(priv);
4312 priv->clk_csr = priv->plat->clk_csr;
4314 stmmac_check_pcs_mode(priv);
4316 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4317 priv->hw->pcs != STMMAC_PCS_TBI &&
4318 priv->hw->pcs != STMMAC_PCS_RTBI) {
4319 /* MDIO bus Registration */
4320 ret = stmmac_mdio_register(ndev);
4322 dev_err(priv->device,
4323 "%s: MDIO bus (id: %d) registration failed",
4324 __func__, priv->plat->bus_id);
4325 goto error_mdio_register;
4329 ret = register_netdev(ndev);
4331 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4333 goto error_netdev_register;
4336 #ifdef CONFIG_DEBUG_FS
4337 ret = stmmac_init_fs(ndev);
4339 netdev_warn(priv->dev, "%s: failed debugFS registration\n",
4345 error_netdev_register:
4346 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4347 priv->hw->pcs != STMMAC_PCS_TBI &&
4348 priv->hw->pcs != STMMAC_PCS_RTBI)
4349 stmmac_mdio_unregister(ndev);
4350 error_mdio_register:
4351 for (queue = 0; queue < priv->plat->rx_queues_to_use; queue++) {
4352 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4354 netif_napi_del(&rx_q->napi);
4361 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
4365 * @dev: device pointer
4366 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
4367 * changes the link status, releases the DMA descriptor rings.
4369 int stmmac_dvr_remove(struct device *dev)
4371 struct net_device *ndev = dev_get_drvdata(dev);
4372 struct stmmac_priv *priv = netdev_priv(ndev);
4374 netdev_info(priv->dev, "%s: removing driver", __func__);
4376 #ifdef CONFIG_DEBUG_FS
4377 stmmac_exit_fs(ndev);
4379 stmmac_stop_all_dma(priv);
4381 priv->hw->mac->set_mac(priv->ioaddr, false);
4382 netif_carrier_off(ndev);
4383 unregister_netdev(ndev);
4384 if (priv->plat->stmmac_rst)
4385 reset_control_assert(priv->plat->stmmac_rst);
4386 clk_disable_unprepare(priv->plat->pclk);
4387 clk_disable_unprepare(priv->plat->stmmac_clk);
4388 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4389 priv->hw->pcs != STMMAC_PCS_TBI &&
4390 priv->hw->pcs != STMMAC_PCS_RTBI)
4391 stmmac_mdio_unregister(ndev);
4392 mutex_destroy(&priv->lock);
4397 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
4400 * stmmac_suspend - suspend callback
4401 * @dev: device pointer
4402 * Description: this is the function to suspend the device and it is called
4403 * by the platform driver to stop the network queue, release the resources,
4404 * program the PMT register (for WoL), clean and release driver resources.
4406 int stmmac_suspend(struct device *dev)
4408 struct net_device *ndev = dev_get_drvdata(dev);
4409 struct stmmac_priv *priv = netdev_priv(ndev);
4411 if (!ndev || !netif_running(ndev))
4415 phy_stop(ndev->phydev);
4417 mutex_lock(&priv->lock);
4419 netif_device_detach(ndev);
4420 stmmac_stop_all_queues(priv);
4422 stmmac_disable_all_queues(priv);
4424 if (priv->eee_enabled) {
4425 priv->tx_path_in_lpi_mode = false;
4426 del_timer_sync(&priv->eee_ctrl_timer);
4429 /* Stop TX/RX DMA */
4430 stmmac_stop_all_dma(priv);
4432 /* Enable Power down mode by programming the PMT regs */
4433 if (device_may_wakeup(priv->device)) {
4434 priv->hw->mac->pmt(priv->hw, priv->wolopts);
4437 priv->hw->mac->set_mac(priv->ioaddr, false);
4438 pinctrl_pm_select_sleep_state(priv->device);
4439 /* Disable clock in case of PWM is off */
4440 if (priv->plat->clk_ptp_ref)
4441 clk_disable_unprepare(priv->plat->clk_ptp_ref);
4442 clk_disable_unprepare(priv->plat->pclk);
4443 clk_disable_unprepare(priv->plat->stmmac_clk);
4445 mutex_unlock(&priv->lock);
4447 priv->oldlink = false;
4448 priv->speed = SPEED_UNKNOWN;
4449 priv->oldduplex = DUPLEX_UNKNOWN;
4452 EXPORT_SYMBOL_GPL(stmmac_suspend);
4455 * stmmac_reset_queues_param - reset queue parameters
4456 * @dev: device pointer
4458 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
4460 u32 rx_cnt = priv->plat->rx_queues_to_use;
4461 u32 tx_cnt = priv->plat->tx_queues_to_use;
4464 for (queue = 0; queue < rx_cnt; queue++) {
4465 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4471 for (queue = 0; queue < tx_cnt; queue++) {
4472 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4480 * stmmac_resume - resume callback
4481 * @dev: device pointer
4482 * Description: when resume this function is invoked to setup the DMA and CORE
4483 * in a usable state.
4485 int stmmac_resume(struct device *dev)
4487 struct net_device *ndev = dev_get_drvdata(dev);
4488 struct stmmac_priv *priv = netdev_priv(ndev);
4490 if (!netif_running(ndev))
4493 /* Power Down bit, into the PM register, is cleared
4494 * automatically as soon as a magic packet or a Wake-up frame
4495 * is received. Anyway, it's better to manually clear
4496 * this bit because it can generate problems while resuming
4497 * from another devices (e.g. serial console).
4499 if (device_may_wakeup(priv->device)) {
4500 mutex_lock(&priv->lock);
4501 priv->hw->mac->pmt(priv->hw, 0);
4502 mutex_unlock(&priv->lock);
4505 pinctrl_pm_select_default_state(priv->device);
4506 /* enable the clk previously disabled */
4507 clk_prepare_enable(priv->plat->stmmac_clk);
4508 clk_prepare_enable(priv->plat->pclk);
4509 if (priv->plat->clk_ptp_ref)
4510 clk_prepare_enable(priv->plat->clk_ptp_ref);
4511 /* reset the phy so that it's ready */
4513 stmmac_mdio_reset(priv->mii);
4516 netif_device_attach(ndev);
4518 mutex_lock(&priv->lock);
4520 stmmac_reset_queues_param(priv);
4522 /* reset private mss value to force mss context settings at
4523 * next tso xmit (only used for gmac4).
4527 stmmac_free_tx_skbufs(priv);
4528 stmmac_clear_descriptors(priv);
4530 stmmac_hw_setup(ndev, false);
4531 stmmac_init_tx_coalesce(priv);
4532 stmmac_set_rx_mode(ndev);
4534 stmmac_enable_all_queues(priv);
4536 stmmac_start_all_queues(priv);
4538 mutex_unlock(&priv->lock);
4541 phy_start(ndev->phydev);
4545 EXPORT_SYMBOL_GPL(stmmac_resume);
4548 static int __init stmmac_cmdline_opt(char *str)
4554 while ((opt = strsep(&str, ",")) != NULL) {
4555 if (!strncmp(opt, "debug:", 6)) {
4556 if (kstrtoint(opt + 6, 0, &debug))
4558 } else if (!strncmp(opt, "phyaddr:", 8)) {
4559 if (kstrtoint(opt + 8, 0, &phyaddr))
4561 } else if (!strncmp(opt, "buf_sz:", 7)) {
4562 if (kstrtoint(opt + 7, 0, &buf_sz))
4564 } else if (!strncmp(opt, "tc:", 3)) {
4565 if (kstrtoint(opt + 3, 0, &tc))
4567 } else if (!strncmp(opt, "watchdog:", 9)) {
4568 if (kstrtoint(opt + 9, 0, &watchdog))
4570 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
4571 if (kstrtoint(opt + 10, 0, &flow_ctrl))
4573 } else if (!strncmp(opt, "pause:", 6)) {
4574 if (kstrtoint(opt + 6, 0, &pause))
4576 } else if (!strncmp(opt, "eee_timer:", 10)) {
4577 if (kstrtoint(opt + 10, 0, &eee_timer))
4579 } else if (!strncmp(opt, "chain_mode:", 11)) {
4580 if (kstrtoint(opt + 11, 0, &chain_mode))
4587 pr_err("%s: ERROR broken module parameter conversion", __func__);
4591 __setup("stmmaceth=", stmmac_cmdline_opt);
4594 static int __init stmmac_init(void)
4596 #ifdef CONFIG_DEBUG_FS
4597 /* Create debugfs main directory if it doesn't exist yet */
4598 if (!stmmac_fs_dir) {
4599 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
4601 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
4602 pr_err("ERROR %s, debugfs create directory failed\n",
4603 STMMAC_RESOURCE_NAME);
4613 static void __exit stmmac_exit(void)
4615 #ifdef CONFIG_DEBUG_FS
4616 debugfs_remove_recursive(stmmac_fs_dir);
4620 module_init(stmmac_init)
4621 module_exit(stmmac_exit)
4623 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
4624 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
4625 MODULE_LICENSE("GPL");