1 /*******************************************************************************
2 This contains the functions to handle the normal descriptors.
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23 *******************************************************************************/
25 #include <linux/stmmac.h>
27 #include "descs_com.h"
29 static int ndesc_get_tx_status(void *data, struct stmmac_extra_stats *x,
30 struct dma_desc *p, void __iomem *ioaddr)
32 struct net_device_stats *stats = (struct net_device_stats *)data;
33 unsigned int tdes0 = le32_to_cpu(p->des0);
34 unsigned int tdes1 = le32_to_cpu(p->des1);
37 /* Get tx owner first */
38 if (unlikely(tdes0 & TDES0_OWN))
41 /* Verify tx error by looking at the last segment. */
42 if (likely(!(tdes1 & TDES1_LAST_SEGMENT)))
45 if (unlikely(tdes0 & TDES0_ERROR_SUMMARY)) {
46 if (unlikely(tdes0 & TDES0_UNDERFLOW_ERROR)) {
48 stats->tx_fifo_errors++;
50 if (unlikely(tdes0 & TDES0_NO_CARRIER)) {
52 stats->tx_carrier_errors++;
54 if (unlikely(tdes0 & TDES0_LOSS_CARRIER)) {
56 stats->tx_carrier_errors++;
58 if (unlikely((tdes0 & TDES0_EXCESSIVE_DEFERRAL) ||
59 (tdes0 & TDES0_EXCESSIVE_COLLISIONS) ||
60 (tdes0 & TDES0_LATE_COLLISION))) {
61 unsigned int collisions;
63 collisions = (tdes0 & TDES0_COLLISION_COUNT_MASK) >> 3;
64 stats->collisions += collisions;
69 if (tdes0 & TDES0_VLAN_FRAME)
72 if (unlikely(tdes0 & TDES0_DEFERRED))
78 static int ndesc_get_tx_len(struct dma_desc *p)
80 return (le32_to_cpu(p->des1) & RDES1_BUFFER1_SIZE_MASK);
83 /* This function verifies if each incoming frame has some errors
84 * and, if required, updates the multicast statistics.
85 * In case of success, it returns good_frame because the GMAC device
86 * is supposed to be able to compute the csum in HW. */
87 static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
91 unsigned int rdes0 = le32_to_cpu(p->des0);
92 struct net_device_stats *stats = (struct net_device_stats *)data;
94 if (unlikely(rdes0 & RDES0_OWN))
97 if (unlikely(!(rdes0 & RDES0_LAST_DESCRIPTOR))) {
98 stats->rx_length_errors++;
102 if (unlikely(rdes0 & RDES0_ERROR_SUMMARY)) {
103 if (unlikely(rdes0 & RDES0_DESCRIPTOR_ERROR))
105 if (unlikely(rdes0 & RDES0_SA_FILTER_FAIL))
107 if (unlikely(rdes0 & RDES0_OVERFLOW_ERROR))
109 if (unlikely(rdes0 & RDES0_IPC_CSUM_ERROR))
111 if (unlikely(rdes0 & RDES0_COLLISION)) {
115 if (unlikely(rdes0 & RDES0_CRC_ERROR)) {
117 stats->rx_crc_errors++;
121 if (unlikely(rdes0 & RDES0_DRIBBLING))
124 if (unlikely(rdes0 & RDES0_LENGTH_ERROR)) {
128 if (unlikely(rdes0 & RDES0_MII_ERROR)) {
132 #ifdef STMMAC_VLAN_TAG_USED
133 if (rdes0 & RDES0_VLAN_TAG)
139 static void ndesc_init_rx_desc(struct dma_desc *p, int disable_rx_ic, int mode,
144 p->des0 |= cpu_to_le32(RDES0_OWN);
146 bfsize1 = min(bfsize, BUF_SIZE_2KiB - 1);
147 p->des1 |= cpu_to_le32(bfsize1 & RDES1_BUFFER1_SIZE_MASK);
149 if (mode == STMMAC_CHAIN_MODE)
150 ndesc_rx_set_on_chain(p, end);
152 ndesc_rx_set_on_ring(p, end, bfsize);
155 p->des1 |= cpu_to_le32(RDES1_DISABLE_IC);
158 static void ndesc_init_tx_desc(struct dma_desc *p, int mode, int end)
160 p->des0 &= cpu_to_le32(~TDES0_OWN);
161 if (mode == STMMAC_CHAIN_MODE)
162 ndesc_tx_set_on_chain(p);
164 ndesc_end_tx_desc_on_ring(p, end);
167 static int ndesc_get_tx_owner(struct dma_desc *p)
169 return (le32_to_cpu(p->des0) & TDES0_OWN) >> 31;
172 static void ndesc_set_tx_owner(struct dma_desc *p)
174 p->des0 |= cpu_to_le32(TDES0_OWN);
177 static void ndesc_set_rx_owner(struct dma_desc *p)
179 p->des0 |= cpu_to_le32(RDES0_OWN);
182 static int ndesc_get_tx_ls(struct dma_desc *p)
184 return (le32_to_cpu(p->des1) & TDES1_LAST_SEGMENT) >> 30;
187 static void ndesc_release_tx_desc(struct dma_desc *p, int mode)
189 int ter = (le32_to_cpu(p->des1) & TDES1_END_RING) >> 25;
191 memset(p, 0, offsetof(struct dma_desc, des2));
192 if (mode == STMMAC_CHAIN_MODE)
193 ndesc_tx_set_on_chain(p);
195 ndesc_end_tx_desc_on_ring(p, ter);
198 static void ndesc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
199 bool csum_flag, int mode, bool tx_own,
202 unsigned int tdes1 = le32_to_cpu(p->des1);
205 tdes1 |= TDES1_FIRST_SEGMENT;
207 tdes1 &= ~TDES1_FIRST_SEGMENT;
209 if (likely(csum_flag))
210 tdes1 |= (TX_CIC_FULL) << TDES1_CHECKSUM_INSERTION_SHIFT;
212 tdes1 &= ~(TX_CIC_FULL << TDES1_CHECKSUM_INSERTION_SHIFT);
215 tdes1 |= TDES1_LAST_SEGMENT;
217 p->des1 = cpu_to_le32(tdes1);
219 if (mode == STMMAC_CHAIN_MODE)
220 norm_set_tx_desc_len_on_chain(p, len);
222 norm_set_tx_desc_len_on_ring(p, len);
225 p->des0 |= cpu_to_le32(TDES0_OWN);
228 static void ndesc_set_tx_ic(struct dma_desc *p)
230 p->des1 |= cpu_to_le32(TDES1_INTERRUPT);
233 static int ndesc_get_rx_frame_len(struct dma_desc *p, int rx_coe_type)
235 unsigned int csum = 0;
237 /* The type-1 checksum offload engines append the checksum at
238 * the end of frame and the two bytes of checksum are added in
240 * Adjust for that in the framelen for type-1 checksum offload
243 if (rx_coe_type == STMMAC_RX_COE_TYPE1)
246 return (((le32_to_cpu(p->des0) & RDES0_FRAME_LEN_MASK)
247 >> RDES0_FRAME_LEN_SHIFT) -
252 static void ndesc_enable_tx_timestamp(struct dma_desc *p)
254 p->des1 |= cpu_to_le32(TDES1_TIME_STAMP_ENABLE);
257 static int ndesc_get_tx_timestamp_status(struct dma_desc *p)
259 return (le32_to_cpu(p->des0) & TDES0_TIME_STAMP_STATUS) >> 17;
262 static u64 ndesc_get_timestamp(void *desc, u32 ats)
264 struct dma_desc *p = (struct dma_desc *)desc;
267 ns = le32_to_cpu(p->des2);
268 /* convert high/sec time stamp value to nanosecond */
269 ns += le32_to_cpu(p->des3) * 1000000000ULL;
274 static int ndesc_get_rx_timestamp_status(void *desc, u32 ats)
276 struct dma_desc *p = (struct dma_desc *)desc;
278 if ((le32_to_cpu(p->des2) == 0xffffffff) &&
279 (le32_to_cpu(p->des3) == 0xffffffff))
280 /* timestamp is corrupted, hence don't store it */
286 static void ndesc_display_ring(void *head, unsigned int size, bool rx)
288 struct dma_desc *p = (struct dma_desc *)head;
291 pr_info("%s descriptor ring:\n", rx ? "RX" : "TX");
293 for (i = 0; i < size; i++) {
297 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
298 i, (unsigned int)virt_to_phys(p),
299 (unsigned int)x, (unsigned int)(x >> 32),
306 const struct stmmac_desc_ops ndesc_ops = {
307 .tx_status = ndesc_get_tx_status,
308 .rx_status = ndesc_get_rx_status,
309 .get_tx_len = ndesc_get_tx_len,
310 .init_rx_desc = ndesc_init_rx_desc,
311 .init_tx_desc = ndesc_init_tx_desc,
312 .get_tx_owner = ndesc_get_tx_owner,
313 .release_tx_desc = ndesc_release_tx_desc,
314 .prepare_tx_desc = ndesc_prepare_tx_desc,
315 .set_tx_ic = ndesc_set_tx_ic,
316 .get_tx_ls = ndesc_get_tx_ls,
317 .set_tx_owner = ndesc_set_tx_owner,
318 .set_rx_owner = ndesc_set_rx_owner,
319 .get_rx_frame_len = ndesc_get_rx_frame_len,
320 .enable_tx_timestamp = ndesc_enable_tx_timestamp,
321 .get_tx_timestamp_status = ndesc_get_tx_timestamp_status,
322 .get_timestamp = ndesc_get_timestamp,
323 .get_rx_timestamp_status = ndesc_get_rx_timestamp_status,
324 .display_ring = ndesc_display_ring,