1 /*******************************************************************************
2 DWMAC Management Counters
4 Copyright (C) 2011 STMicroelectronics Ltd
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23 *******************************************************************************/
25 #include <linux/kernel.h>
29 /* MAC Management Counters register offset */
31 #define MMC_CNTRL 0x00 /* MMC Control */
32 #define MMC_RX_INTR 0x04 /* MMC RX Interrupt */
33 #define MMC_TX_INTR 0x08 /* MMC TX Interrupt */
34 #define MMC_RX_INTR_MASK 0x0c /* MMC Interrupt Mask */
35 #define MMC_TX_INTR_MASK 0x10 /* MMC Interrupt Mask */
36 #define MMC_DEFAULT_MASK 0xffffffff
38 /* MMC TX counter registers */
41 * _GB register stands for good and bad frames
42 * _G is for good only.
44 #define MMC_TX_OCTETCOUNT_GB 0x14
45 #define MMC_TX_FRAMECOUNT_GB 0x18
46 #define MMC_TX_BROADCASTFRAME_G 0x1c
47 #define MMC_TX_MULTICASTFRAME_G 0x20
48 #define MMC_TX_64_OCTETS_GB 0x24
49 #define MMC_TX_65_TO_127_OCTETS_GB 0x28
50 #define MMC_TX_128_TO_255_OCTETS_GB 0x2c
51 #define MMC_TX_256_TO_511_OCTETS_GB 0x30
52 #define MMC_TX_512_TO_1023_OCTETS_GB 0x34
53 #define MMC_TX_1024_TO_MAX_OCTETS_GB 0x38
54 #define MMC_TX_UNICAST_GB 0x3c
55 #define MMC_TX_MULTICAST_GB 0x40
56 #define MMC_TX_BROADCAST_GB 0x44
57 #define MMC_TX_UNDERFLOW_ERROR 0x48
58 #define MMC_TX_SINGLECOL_G 0x4c
59 #define MMC_TX_MULTICOL_G 0x50
60 #define MMC_TX_DEFERRED 0x54
61 #define MMC_TX_LATECOL 0x58
62 #define MMC_TX_EXESSCOL 0x5c
63 #define MMC_TX_CARRIER_ERROR 0x60
64 #define MMC_TX_OCTETCOUNT_G 0x64
65 #define MMC_TX_FRAMECOUNT_G 0x68
66 #define MMC_TX_EXCESSDEF 0x6c
67 #define MMC_TX_PAUSE_FRAME 0x70
68 #define MMC_TX_VLAN_FRAME_G 0x74
70 /* MMC RX counter registers */
71 #define MMC_RX_FRAMECOUNT_GB 0x80
72 #define MMC_RX_OCTETCOUNT_GB 0x84
73 #define MMC_RX_OCTETCOUNT_G 0x88
74 #define MMC_RX_BROADCASTFRAME_G 0x8c
75 #define MMC_RX_MULTICASTFRAME_G 0x90
76 #define MMC_RX_CRC_ERROR 0x94
77 #define MMC_RX_ALIGN_ERROR 0x98
78 #define MMC_RX_RUN_ERROR 0x9C
79 #define MMC_RX_JABBER_ERROR 0xA0
80 #define MMC_RX_UNDERSIZE_G 0xA4
81 #define MMC_RX_OVERSIZE_G 0xA8
82 #define MMC_RX_64_OCTETS_GB 0xAC
83 #define MMC_RX_65_TO_127_OCTETS_GB 0xb0
84 #define MMC_RX_128_TO_255_OCTETS_GB 0xb4
85 #define MMC_RX_256_TO_511_OCTETS_GB 0xb8
86 #define MMC_RX_512_TO_1023_OCTETS_GB 0xbc
87 #define MMC_RX_1024_TO_MAX_OCTETS_GB 0xc0
88 #define MMC_RX_UNICAST_G 0xc4
89 #define MMC_RX_LENGTH_ERROR 0xc8
90 #define MMC_RX_AUTOFRANGETYPE 0xcc
91 #define MMC_RX_PAUSE_FRAMES 0xd0
92 #define MMC_RX_FIFO_OVERFLOW 0xd4
93 #define MMC_RX_VLAN_FRAMES_GB 0xd8
94 #define MMC_RX_WATCHDOG_ERROR 0xdc
96 #define MMC_RX_IPC_INTR_MASK 0x100
97 #define MMC_RX_IPC_INTR 0x108
99 #define MMC_RX_IPV4_GD 0x110
100 #define MMC_RX_IPV4_HDERR 0x114
101 #define MMC_RX_IPV4_NOPAY 0x118
102 #define MMC_RX_IPV4_FRAG 0x11C
103 #define MMC_RX_IPV4_UDSBL 0x120
105 #define MMC_RX_IPV4_GD_OCTETS 0x150
106 #define MMC_RX_IPV4_HDERR_OCTETS 0x154
107 #define MMC_RX_IPV4_NOPAY_OCTETS 0x158
108 #define MMC_RX_IPV4_FRAG_OCTETS 0x15c
109 #define MMC_RX_IPV4_UDSBL_OCTETS 0x160
112 #define MMC_RX_IPV6_GD_OCTETS 0x164
113 #define MMC_RX_IPV6_HDERR_OCTETS 0x168
114 #define MMC_RX_IPV6_NOPAY_OCTETS 0x16c
116 #define MMC_RX_IPV6_GD 0x124
117 #define MMC_RX_IPV6_HDERR 0x128
118 #define MMC_RX_IPV6_NOPAY 0x12c
121 #define MMC_RX_UDP_GD 0x130
122 #define MMC_RX_UDP_ERR 0x134
123 #define MMC_RX_TCP_GD 0x138
124 #define MMC_RX_TCP_ERR 0x13c
125 #define MMC_RX_ICMP_GD 0x140
126 #define MMC_RX_ICMP_ERR 0x144
128 #define MMC_RX_UDP_GD_OCTETS 0x170
129 #define MMC_RX_UDP_ERR_OCTETS 0x174
130 #define MMC_RX_TCP_GD_OCTETS 0x178
131 #define MMC_RX_TCP_ERR_OCTETS 0x17c
132 #define MMC_RX_ICMP_GD_OCTETS 0x180
133 #define MMC_RX_ICMP_ERR_OCTETS 0x184
135 void dwmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)
137 u32 value = readl(mmcaddr + MMC_CNTRL);
139 value |= (mode & 0x3F);
141 writel(value, mmcaddr + MMC_CNTRL);
143 pr_debug("stmmac: MMC ctrl register (offset 0x%x): 0x%08x\n",
147 /* To mask all all interrupts.*/
148 void dwmac_mmc_intr_all_mask(void __iomem *mmcaddr)
150 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_INTR_MASK);
151 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_TX_INTR_MASK);
152 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_IPC_INTR_MASK);
155 /* This reads the MAC core counters (if actaully supported).
156 * by default the MMC core is programmed to reset each
157 * counter after a read. So all the field of the mmc struct
158 * have to be incremented.
160 void dwmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)
162 mmc->mmc_tx_octetcount_gb += readl(mmcaddr + MMC_TX_OCTETCOUNT_GB);
163 mmc->mmc_tx_framecount_gb += readl(mmcaddr + MMC_TX_FRAMECOUNT_GB);
164 mmc->mmc_tx_broadcastframe_g += readl(mmcaddr +
165 MMC_TX_BROADCASTFRAME_G);
166 mmc->mmc_tx_multicastframe_g += readl(mmcaddr +
167 MMC_TX_MULTICASTFRAME_G);
168 mmc->mmc_tx_64_octets_gb += readl(mmcaddr + MMC_TX_64_OCTETS_GB);
169 mmc->mmc_tx_65_to_127_octets_gb +=
170 readl(mmcaddr + MMC_TX_65_TO_127_OCTETS_GB);
171 mmc->mmc_tx_128_to_255_octets_gb +=
172 readl(mmcaddr + MMC_TX_128_TO_255_OCTETS_GB);
173 mmc->mmc_tx_256_to_511_octets_gb +=
174 readl(mmcaddr + MMC_TX_256_TO_511_OCTETS_GB);
175 mmc->mmc_tx_512_to_1023_octets_gb +=
176 readl(mmcaddr + MMC_TX_512_TO_1023_OCTETS_GB);
177 mmc->mmc_tx_1024_to_max_octets_gb +=
178 readl(mmcaddr + MMC_TX_1024_TO_MAX_OCTETS_GB);
179 mmc->mmc_tx_unicast_gb += readl(mmcaddr + MMC_TX_UNICAST_GB);
180 mmc->mmc_tx_multicast_gb += readl(mmcaddr + MMC_TX_MULTICAST_GB);
181 mmc->mmc_tx_broadcast_gb += readl(mmcaddr + MMC_TX_BROADCAST_GB);
182 mmc->mmc_tx_underflow_error += readl(mmcaddr + MMC_TX_UNDERFLOW_ERROR);
183 mmc->mmc_tx_singlecol_g += readl(mmcaddr + MMC_TX_SINGLECOL_G);
184 mmc->mmc_tx_multicol_g += readl(mmcaddr + MMC_TX_MULTICOL_G);
185 mmc->mmc_tx_deferred += readl(mmcaddr + MMC_TX_DEFERRED);
186 mmc->mmc_tx_latecol += readl(mmcaddr + MMC_TX_LATECOL);
187 mmc->mmc_tx_exesscol += readl(mmcaddr + MMC_TX_EXESSCOL);
188 mmc->mmc_tx_carrier_error += readl(mmcaddr + MMC_TX_CARRIER_ERROR);
189 mmc->mmc_tx_octetcount_g += readl(mmcaddr + MMC_TX_OCTETCOUNT_G);
190 mmc->mmc_tx_framecount_g += readl(mmcaddr + MMC_TX_FRAMECOUNT_G);
191 mmc->mmc_tx_excessdef += readl(mmcaddr + MMC_TX_EXCESSDEF);
192 mmc->mmc_tx_pause_frame += readl(mmcaddr + MMC_TX_PAUSE_FRAME);
193 mmc->mmc_tx_vlan_frame_g += readl(mmcaddr + MMC_TX_VLAN_FRAME_G);
195 /* MMC RX counter registers */
196 mmc->mmc_rx_framecount_gb += readl(mmcaddr + MMC_RX_FRAMECOUNT_GB);
197 mmc->mmc_rx_octetcount_gb += readl(mmcaddr + MMC_RX_OCTETCOUNT_GB);
198 mmc->mmc_rx_octetcount_g += readl(mmcaddr + MMC_RX_OCTETCOUNT_G);
199 mmc->mmc_rx_broadcastframe_g += readl(mmcaddr +
200 MMC_RX_BROADCASTFRAME_G);
201 mmc->mmc_rx_multicastframe_g += readl(mmcaddr +
202 MMC_RX_MULTICASTFRAME_G);
203 mmc->mmc_rx_crc_error += readl(mmcaddr + MMC_RX_CRC_ERROR);
204 mmc->mmc_rx_align_error += readl(mmcaddr + MMC_RX_ALIGN_ERROR);
205 mmc->mmc_rx_run_error += readl(mmcaddr + MMC_RX_RUN_ERROR);
206 mmc->mmc_rx_jabber_error += readl(mmcaddr + MMC_RX_JABBER_ERROR);
207 mmc->mmc_rx_undersize_g += readl(mmcaddr + MMC_RX_UNDERSIZE_G);
208 mmc->mmc_rx_oversize_g += readl(mmcaddr + MMC_RX_OVERSIZE_G);
209 mmc->mmc_rx_64_octets_gb += readl(mmcaddr + MMC_RX_64_OCTETS_GB);
210 mmc->mmc_rx_65_to_127_octets_gb +=
211 readl(mmcaddr + MMC_RX_65_TO_127_OCTETS_GB);
212 mmc->mmc_rx_128_to_255_octets_gb +=
213 readl(mmcaddr + MMC_RX_128_TO_255_OCTETS_GB);
214 mmc->mmc_rx_256_to_511_octets_gb +=
215 readl(mmcaddr + MMC_RX_256_TO_511_OCTETS_GB);
216 mmc->mmc_rx_512_to_1023_octets_gb +=
217 readl(mmcaddr + MMC_RX_512_TO_1023_OCTETS_GB);
218 mmc->mmc_rx_1024_to_max_octets_gb +=
219 readl(mmcaddr + MMC_RX_1024_TO_MAX_OCTETS_GB);
220 mmc->mmc_rx_unicast_g += readl(mmcaddr + MMC_RX_UNICAST_G);
221 mmc->mmc_rx_length_error += readl(mmcaddr + MMC_RX_LENGTH_ERROR);
222 mmc->mmc_rx_autofrangetype += readl(mmcaddr + MMC_RX_AUTOFRANGETYPE);
223 mmc->mmc_rx_pause_frames += readl(mmcaddr + MMC_RX_PAUSE_FRAMES);
224 mmc->mmc_rx_fifo_overflow += readl(mmcaddr + MMC_RX_FIFO_OVERFLOW);
225 mmc->mmc_rx_vlan_frames_gb += readl(mmcaddr + MMC_RX_VLAN_FRAMES_GB);
226 mmc->mmc_rx_watchdog_error += readl(mmcaddr + MMC_RX_WATCHDOG_ERROR);
228 mmc->mmc_rx_ipc_intr_mask += readl(mmcaddr + MMC_RX_IPC_INTR_MASK);
229 mmc->mmc_rx_ipc_intr += readl(mmcaddr + MMC_RX_IPC_INTR);
231 mmc->mmc_rx_ipv4_gd += readl(mmcaddr + MMC_RX_IPV4_GD);
232 mmc->mmc_rx_ipv4_hderr += readl(mmcaddr + MMC_RX_IPV4_HDERR);
233 mmc->mmc_rx_ipv4_nopay += readl(mmcaddr + MMC_RX_IPV4_NOPAY);
234 mmc->mmc_rx_ipv4_frag += readl(mmcaddr + MMC_RX_IPV4_FRAG);
235 mmc->mmc_rx_ipv4_udsbl += readl(mmcaddr + MMC_RX_IPV4_UDSBL);
237 mmc->mmc_rx_ipv4_gd_octets += readl(mmcaddr + MMC_RX_IPV4_GD_OCTETS);
238 mmc->mmc_rx_ipv4_hderr_octets +=
239 readl(mmcaddr + MMC_RX_IPV4_HDERR_OCTETS);
240 mmc->mmc_rx_ipv4_nopay_octets +=
241 readl(mmcaddr + MMC_RX_IPV4_NOPAY_OCTETS);
242 mmc->mmc_rx_ipv4_frag_octets += readl(mmcaddr +
243 MMC_RX_IPV4_FRAG_OCTETS);
244 mmc->mmc_rx_ipv4_udsbl_octets +=
245 readl(mmcaddr + MMC_RX_IPV4_UDSBL_OCTETS);
248 mmc->mmc_rx_ipv6_gd_octets += readl(mmcaddr + MMC_RX_IPV6_GD_OCTETS);
249 mmc->mmc_rx_ipv6_hderr_octets +=
250 readl(mmcaddr + MMC_RX_IPV6_HDERR_OCTETS);
251 mmc->mmc_rx_ipv6_nopay_octets +=
252 readl(mmcaddr + MMC_RX_IPV6_NOPAY_OCTETS);
254 mmc->mmc_rx_ipv6_gd += readl(mmcaddr + MMC_RX_IPV6_GD);
255 mmc->mmc_rx_ipv6_hderr += readl(mmcaddr + MMC_RX_IPV6_HDERR);
256 mmc->mmc_rx_ipv6_nopay += readl(mmcaddr + MMC_RX_IPV6_NOPAY);
259 mmc->mmc_rx_udp_gd += readl(mmcaddr + MMC_RX_UDP_GD);
260 mmc->mmc_rx_udp_err += readl(mmcaddr + MMC_RX_UDP_ERR);
261 mmc->mmc_rx_tcp_gd += readl(mmcaddr + MMC_RX_TCP_GD);
262 mmc->mmc_rx_tcp_err += readl(mmcaddr + MMC_RX_TCP_ERR);
263 mmc->mmc_rx_icmp_gd += readl(mmcaddr + MMC_RX_ICMP_GD);
264 mmc->mmc_rx_icmp_err += readl(mmcaddr + MMC_RX_ICMP_ERR);
266 mmc->mmc_rx_udp_gd_octets += readl(mmcaddr + MMC_RX_UDP_GD_OCTETS);
267 mmc->mmc_rx_udp_err_octets += readl(mmcaddr + MMC_RX_UDP_ERR_OCTETS);
268 mmc->mmc_rx_tcp_gd_octets += readl(mmcaddr + MMC_RX_TCP_GD_OCTETS);
269 mmc->mmc_rx_tcp_err_octets += readl(mmcaddr + MMC_RX_TCP_ERR_OCTETS);
270 mmc->mmc_rx_icmp_gd_octets += readl(mmcaddr + MMC_RX_ICMP_GD_OCTETS);
271 mmc->mmc_rx_icmp_err_octets += readl(mmcaddr + MMC_RX_ICMP_ERR_OCTETS);