drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
   4  * stmmac XGMAC support.
   5  */
   6
   7 #include "stmmac.h"
   8 #include "dwxgmac2.h"
   9
  10 static void dwxgmac2_core_init(struct mac_device_info *hw,
  11                                struct net_device *dev)
  12 {
  13         void __iomem *ioaddr = hw->pcsr;
  14         int mtu = dev->mtu;
  15         u32 tx, rx;
  16
  17         tx = readl(ioaddr + XGMAC_TX_CONFIG);
  18         rx = readl(ioaddr + XGMAC_RX_CONFIG);
  19
  20         tx |= XGMAC_CORE_INIT_TX;
  21         rx |= XGMAC_CORE_INIT_RX;
  22
  23         if (mtu >= 9000) {
  24                 rx |= XGMAC_CONFIG_GPSLCE;
  25                 rx |= XGMAC_JUMBO_LEN << XGMAC_CONFIG_GPSL_SHIFT;
  26                 rx |= XGMAC_CONFIG_WD;
  27         } else if (mtu > 2000) {
  28                 rx |= XGMAC_CONFIG_JE;
  29         } else if (mtu > 1500) {
  30                 rx |= XGMAC_CONFIG_S2KP;
  31         }
  32
  33         if (hw->ps) {
  34                 tx |= XGMAC_CONFIG_TE;
  35                 tx &= ~hw->link.speed_mask;
  36
  37                 switch (hw->ps) {
  38                 case SPEED_10000:
  39                         tx |= hw->link.speed10000;
  40                         break;
  41                 case SPEED_2500:
  42                         tx |= hw->link.speed2500;
  43                         break;
  44                 case SPEED_1000:
  45                 default:
  46                         tx |= hw->link.speed1000;
  47                         break;
  48                 }
  49         }
  50
  51         writel(tx, ioaddr + XGMAC_TX_CONFIG);
  52         writel(rx, ioaddr + XGMAC_RX_CONFIG);
  53         writel(XGMAC_INT_DEFAULT_EN, ioaddr + XGMAC_INT_EN);
  54 }
  55
  56 static void dwxgmac2_set_mac(void __iomem *ioaddr, bool enable)
  57 {
  58         u32 tx = readl(ioaddr + XGMAC_TX_CONFIG);
  59         u32 rx = readl(ioaddr + XGMAC_RX_CONFIG);
  60
  61         if (enable) {
  62                 tx |= XGMAC_CONFIG_TE;
  63                 rx |= XGMAC_CONFIG_RE;
  64         } else {
  65                 tx &= ~XGMAC_CONFIG_TE;
  66                 rx &= ~XGMAC_CONFIG_RE;
  67         }
  68
  69         writel(tx, ioaddr + XGMAC_TX_CONFIG);
  70         writel(rx, ioaddr + XGMAC_RX_CONFIG);
  71 }
  72
  73 static int dwxgmac2_rx_ipc(struct mac_device_info *hw)
  74 {
  75         void __iomem *ioaddr = hw->pcsr;
  76         u32 value;
  77
  78         value = readl(ioaddr + XGMAC_RX_CONFIG);
  79         if (hw->rx_csum)
  80                 value |= XGMAC_CONFIG_IPC;
  81         else
  82                 value &= ~XGMAC_CONFIG_IPC;
  83         writel(value, ioaddr + XGMAC_RX_CONFIG);
  84
  85         return !!(readl(ioaddr + XGMAC_RX_CONFIG) & XGMAC_CONFIG_IPC);
  86 }
  87
  88 static void dwxgmac2_rx_queue_enable(struct mac_device_info *hw, u8 mode,
  89                                      u32 queue)
  90 {
  91         void __iomem *ioaddr = hw->pcsr;
  92         u32 value;
  93
  94         value = readl(ioaddr + XGMAC_RXQ_CTRL0) & ~XGMAC_RXQEN(queue);
  95         if (mode == MTL_QUEUE_AVB)
  96                 value |= 0x1 << XGMAC_RXQEN_SHIFT(queue);
  97         else if (mode == MTL_QUEUE_DCB)
  98                 value |= 0x2 << XGMAC_RXQEN_SHIFT(queue);
  99         writel(value, ioaddr + XGMAC_RXQ_CTRL0);
 100 }
 101
 102 static void dwxgmac2_rx_queue_prio(struct mac_device_info *hw, u32 prio,
 103                                    u32 queue)
 104 {
 105         void __iomem *ioaddr = hw->pcsr;
 106         u32 value, reg;
 107
 108         reg = (queue < 4) ? XGMAC_RXQ_CTRL2 : XGMAC_RXQ_CTRL3;
 109         if (queue >= 4)
 110                 queue -= 4;
 111
 112         value = readl(ioaddr + reg);
 113         value &= ~XGMAC_PSRQ(queue);
 114         value |= (prio << XGMAC_PSRQ_SHIFT(queue)) & XGMAC_PSRQ(queue);
 115
 116         writel(value, ioaddr + reg);
 117 }
 118
 119 static void dwxgmac2_prog_mtl_rx_algorithms(struct mac_device_info *hw,
 120                                             u32 rx_alg)
 121 {
 122         void __iomem *ioaddr = hw->pcsr;
 123         u32 value;
 124
 125         value = readl(ioaddr + XGMAC_MTL_OPMODE);
 126         value &= ~XGMAC_RAA;
 127
 128         switch (rx_alg) {
 129         case MTL_RX_ALGORITHM_SP:
 130                 break;
 131         case MTL_RX_ALGORITHM_WSP:
 132                 value |= XGMAC_RAA;
 133                 break;
 134         default:
 135                 break;
 136         }
 137
 138         writel(value, ioaddr + XGMAC_MTL_OPMODE);
 139 }
 140
 141 static void dwxgmac2_prog_mtl_tx_algorithms(struct mac_device_info *hw,
 142                                             u32 tx_alg)
 143 {
 144         void __iomem *ioaddr = hw->pcsr;
 145         u32 value;
 146
 147         value = readl(ioaddr + XGMAC_MTL_OPMODE);
 148         value &= ~XGMAC_ETSALG;
 149
 150         switch (tx_alg) {
 151         case MTL_TX_ALGORITHM_WRR:
 152                 value |= XGMAC_WRR;
 153                 break;
 154         case MTL_TX_ALGORITHM_WFQ:
 155                 value |= XGMAC_WFQ;
 156                 break;
 157         case MTL_TX_ALGORITHM_DWRR:
 158                 value |= XGMAC_DWRR;
 159                 break;
 160         default:
 161                 break;
 162         }
 163
 164         writel(value, ioaddr + XGMAC_MTL_OPMODE);
 165 }
 166
 167 static void dwxgmac2_map_mtl_to_dma(struct mac_device_info *hw, u32 queue,
 168                                     u32 chan)
 169 {
 170         void __iomem *ioaddr = hw->pcsr;
 171         u32 value, reg;
 172
 173         reg = (queue < 4) ? XGMAC_MTL_RXQ_DMA_MAP0 : XGMAC_MTL_RXQ_DMA_MAP1;
 174         if (queue >= 4)
 175                 queue -= 4;
 176
 177         value = readl(ioaddr + reg);
 178         value &= ~XGMAC_QxMDMACH(queue);
 179         value |= (chan << XGMAC_QxMDMACH_SHIFT(queue)) & XGMAC_QxMDMACH(queue);
 180
 181         writel(value, ioaddr + reg);
 182 }
 183
 184 static int dwxgmac2_host_irq_status(struct mac_device_info *hw,
 185                                     struct stmmac_extra_stats *x)
 186 {
 187         void __iomem *ioaddr = hw->pcsr;
 188         u32 stat, en;
 189
 190         en = readl(ioaddr + XGMAC_INT_EN);
 191         stat = readl(ioaddr + XGMAC_INT_STATUS);
 192
 193         stat &= en;
 194
 195         if (stat & XGMAC_PMTIS) {
 196                 x->irq_receive_pmt_irq_n++;
 197                 readl(ioaddr + XGMAC_PMT);
 198         }
 199
 200         return 0;
 201 }
 202
 203 static int dwxgmac2_host_mtl_irq_status(struct mac_device_info *hw, u32 chan)
 204 {
 205         void __iomem *ioaddr = hw->pcsr;
 206         int ret = 0;
 207         u32 status;
 208
 209         status = readl(ioaddr + XGMAC_MTL_INT_STATUS);
 210         if (status & BIT(chan)) {
 211                 u32 chan_status = readl(ioaddr + XGMAC_MTL_QINT_STATUS(chan));
 212
 213                 if (chan_status & XGMAC_RXOVFIS)
 214                         ret |= CORE_IRQ_MTL_RX_OVERFLOW;
 215
 216                 writel(~0x0, ioaddr + XGMAC_MTL_QINT_STATUS(chan));
 217         }
 218
 219         return ret;
 220 }
 221
 222 static void dwxgmac2_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 223                                unsigned int fc, unsigned int pause_time,
 224                                u32 tx_cnt)
 225 {
 226         void __iomem *ioaddr = hw->pcsr;
 227         u32 i;
 228
 229         if (fc & FLOW_RX)
 230                 writel(XGMAC_RFE, ioaddr + XGMAC_RX_FLOW_CTRL);
 231         if (fc & FLOW_TX) {
 232                 for (i = 0; i < tx_cnt; i++) {
 233                         u32 value = XGMAC_TFE;
 234
 235                         if (duplex)
 236                                 value |= pause_time << XGMAC_PT_SHIFT;
 237
 238                         writel(value, ioaddr + XGMAC_Qx_TX_FLOW_CTRL(i));
 239                 }
 240         }
 241 }
 242
 243 static void dwxgmac2_pmt(struct mac_device_info *hw, unsigned long mode)
 244 {
 245         void __iomem *ioaddr = hw->pcsr;
 246         u32 val = 0x0;
 247
 248         if (mode & WAKE_MAGIC)
 249                 val |= XGMAC_PWRDWN | XGMAC_MGKPKTEN;
 250         if (mode & WAKE_UCAST)
 251                 val |= XGMAC_PWRDWN | XGMAC_GLBLUCAST | XGMAC_RWKPKTEN;
 252         if (val) {
 253                 u32 cfg = readl(ioaddr + XGMAC_RX_CONFIG);
 254                 cfg |= XGMAC_CONFIG_RE;
 255                 writel(cfg, ioaddr + XGMAC_RX_CONFIG);
 256         }
 257
 258         writel(val, ioaddr + XGMAC_PMT);
 259 }
 260
 261 static void dwxgmac2_set_umac_addr(struct mac_device_info *hw,
 262                                    unsigned char *addr, unsigned int reg_n)
 263 {
 264         void __iomem *ioaddr = hw->pcsr;
 265         u32 value;
 266
 267         value = (addr[5] << 8) | addr[4];
 268         writel(value | XGMAC_AE, ioaddr + XGMAC_ADDR0_HIGH);
 269
 270         value = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
 271         writel(value, ioaddr + XGMAC_ADDR0_LOW);
 272 }
 273
 274 static void dwxgmac2_get_umac_addr(struct mac_device_info *hw,
 275                                    unsigned char *addr, unsigned int reg_n)
 276 {
 277         void __iomem *ioaddr = hw->pcsr;
 278         u32 hi_addr, lo_addr;
 279
 280         /* Read the MAC address from the hardware */
 281         hi_addr = readl(ioaddr + XGMAC_ADDR0_HIGH);
 282         lo_addr = readl(ioaddr + XGMAC_ADDR0_LOW);
 283
 284         /* Extract the MAC address from the high and low words */
 285         addr[0] = lo_addr & 0xff;
 286         addr[1] = (lo_addr >> 8) & 0xff;
 287         addr[2] = (lo_addr >> 16) & 0xff;
 288         addr[3] = (lo_addr >> 24) & 0xff;
 289         addr[4] = hi_addr & 0xff;
 290         addr[5] = (hi_addr >> 8) & 0xff;
 291 }
 292
 293 static void dwxgmac2_set_filter(struct mac_device_info *hw,
 294                                 struct net_device *dev)
 295 {
 296         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 297         u32 value = XGMAC_FILTER_RA;
 298
 299         if (dev->flags & IFF_PROMISC) {
 300                 value |= XGMAC_FILTER_PR;
 301         } else if ((dev->flags & IFF_ALLMULTI) ||
 302                    (netdev_mc_count(dev) > HASH_TABLE_SIZE)) {
 303                 value |= XGMAC_FILTER_PM;
 304                 writel(~0x0, ioaddr + XGMAC_HASH_TABLE(0));
 305                 writel(~0x0, ioaddr + XGMAC_HASH_TABLE(1));
 306         }
 307
 308         writel(value, ioaddr + XGMAC_PACKET_FILTER);
 309 }
 310
 311 const struct stmmac_ops dwxgmac210_ops = {
 312         .core_init = dwxgmac2_core_init,
 313         .set_mac = dwxgmac2_set_mac,
 314         .rx_ipc = dwxgmac2_rx_ipc,
 315         .rx_queue_enable = dwxgmac2_rx_queue_enable,
 316         .rx_queue_prio = dwxgmac2_rx_queue_prio,
 317         .tx_queue_prio = NULL,
 318         .rx_queue_routing = NULL,
 319         .prog_mtl_rx_algorithms = dwxgmac2_prog_mtl_rx_algorithms,
 320         .prog_mtl_tx_algorithms = dwxgmac2_prog_mtl_tx_algorithms,
 321         .set_mtl_tx_queue_weight = NULL,
 322         .map_mtl_to_dma = dwxgmac2_map_mtl_to_dma,
 323         .config_cbs = NULL,
 324         .dump_regs = NULL,
 325         .host_irq_status = dwxgmac2_host_irq_status,
 326         .host_mtl_irq_status = dwxgmac2_host_mtl_irq_status,
 327         .flow_ctrl = dwxgmac2_flow_ctrl,
 328         .pmt = dwxgmac2_pmt,
 329         .set_umac_addr = dwxgmac2_set_umac_addr,
 330         .get_umac_addr = dwxgmac2_get_umac_addr,
 331         .set_eee_mode = NULL,
 332         .reset_eee_mode = NULL,
 333         .set_eee_timer = NULL,
 334         .set_eee_pls = NULL,
 335         .pcs_ctrl_ane = NULL,
 336         .pcs_rane = NULL,
 337         .pcs_get_adv_lp = NULL,
 338         .debug = NULL,
 339         .set_filter = dwxgmac2_set_filter,
 340 };
 341
 342 int dwxgmac2_setup(struct stmmac_priv *priv)
 343 {
 344         struct mac_device_info *mac = priv->hw;
 345
 346         dev_info(priv->device, "\tXGMAC2\n");
 347
 348         priv->dev->priv_flags |= IFF_UNICAST_FLT;
 349         mac->pcsr = priv->ioaddr;
 350         mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
 351         mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
 352         mac->mcast_bits_log2 = 0;
 353
 354         if (mac->multicast_filter_bins)
 355                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
 356
 357         mac->link.duplex = 0;
 358         mac->link.speed10 = 0;
 359         mac->link.speed100 = 0;
 360         mac->link.speed1000 = XGMAC_CONFIG_SS_1000;
 361         mac->link.speed2500 = XGMAC_CONFIG_SS_2500;
 362         mac->link.speed10000 = XGMAC_CONFIG_SS_10000;
 363         mac->link.speed_mask = XGMAC_CONFIG_SS_MASK;
 364
 365         mac->mii.addr = XGMAC_MDIO_ADDR;
 366         mac->mii.data = XGMAC_MDIO_DATA;
 367         mac->mii.addr_shift = 16;
 368         mac->mii.addr_mask = GENMASK(20, 16);
 369         mac->mii.reg_shift = 0;
 370         mac->mii.reg_mask = GENMASK(15, 0);
 371         mac->mii.clk_csr_shift = 19;
 372         mac->mii.clk_csr_mask = GENMASK(21, 19);
 373
 374         return 0;
 375 }