drivers/net/ethernet/stmicro/stmmac/dwmac5.h

   1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
   2 // Copyright (c) 2017 Synopsys, Inc. and/or its affiliates.
   3 // stmmac Support for 5.xx Ethernet QoS cores
   4
   5 #ifndef __DWMAC5_H__
   6 #define __DWMAC5_H__
   7
   8 #define MAC_DPP_FSM_INT_STATUS          0x00000140
   9 #define MAC_AXI_SLV_DPE_ADDR_STATUS     0x00000144
  10 #define MAC_FSM_CONTROL                 0x00000148
  11 #define PRTYEN                          BIT(1)
  12 #define TMOUTEN                         BIT(0)
  13
  14 #define MAC_FPE_CTRL_STS                0x00000234
  15 #define EFPE                            BIT(0)
  16
  17 #define MAC_PPS_CONTROL                 0x00000b70
  18 #define PPS_MAXIDX(x)                   ((((x) + 1) * 8) - 1)
  19 #define PPS_MINIDX(x)                   ((x) * 8)
  20 #define PPSx_MASK(x)                    GENMASK(PPS_MAXIDX(x), PPS_MINIDX(x))
  21 #define MCGRENx(x)                      BIT(PPS_MAXIDX(x))
  22 #define TRGTMODSELx(x, val)             \
  23         GENMASK(PPS_MAXIDX(x) - 1, PPS_MAXIDX(x) - 2) & \
  24         ((val) << (PPS_MAXIDX(x) - 2))
  25 #define PPSCMDx(x, val)                 \
  26         GENMASK(PPS_MINIDX(x) + 3, PPS_MINIDX(x)) & \
  27         ((val) << PPS_MINIDX(x))
  28 #define PPSEN0                          BIT(4)
  29 #define MAC_PPSx_TARGET_TIME_SEC(x)     (0x00000b80 + ((x) * 0x10))
  30 #define MAC_PPSx_TARGET_TIME_NSEC(x)    (0x00000b84 + ((x) * 0x10))
  31 #define TRGTBUSY0                       BIT(31)
  32 #define TTSL0                           GENMASK(30, 0)
  33 #define MAC_PPSx_INTERVAL(x)            (0x00000b88 + ((x) * 0x10))
  34 #define MAC_PPSx_WIDTH(x)               (0x00000b8c + ((x) * 0x10))
  35
  36 #define MTL_EST_CONTROL                 0x00000c50
  37 #define PTOV                            GENMASK(31, 24)
  38 #define PTOV_SHIFT                      24
  39 #define SSWL                            BIT(1)
  40 #define EEST                            BIT(0)
  41 #define MTL_EST_GCL_CONTROL             0x00000c80
  42 #define BTR_LOW                         0x0
  43 #define BTR_HIGH                        0x1
  44 #define CTR_LOW                         0x2
  45 #define CTR_HIGH                        0x3
  46 #define TER                             0x4
  47 #define LLR                             0x5
  48 #define ADDR_SHIFT                      8
  49 #define GCRR                            BIT(2)
  50 #define SRWO                            BIT(0)
  51 #define MTL_EST_GCL_DATA                0x00000c84
  52
  53 #define MTL_RXP_CONTROL_STATUS          0x00000ca0
  54 #define RXPI                            BIT(31)
  55 #define NPE                             GENMASK(23, 16)
  56 #define NVE                             GENMASK(7, 0)
  57 #define MTL_RXP_IACC_CTRL_STATUS        0x00000cb0
  58 #define STARTBUSY                       BIT(31)
  59 #define RXPEIEC                         GENMASK(22, 21)
  60 #define RXPEIEE                         BIT(20)
  61 #define WRRDN                           BIT(16)
  62 #define ADDR                            GENMASK(15, 0)
  63 #define MTL_RXP_IACC_DATA               0x00000cb4
  64 #define MTL_ECC_CONTROL                 0x00000cc0
  65 #define TSOEE                           BIT(4)
  66 #define MRXPEE                          BIT(3)
  67 #define MESTEE                          BIT(2)
  68 #define MRXEE                           BIT(1)
  69 #define MTXEE                           BIT(0)
  70
  71 #define MTL_SAFETY_INT_STATUS           0x00000cc4
  72 #define MCSIS                           BIT(31)
  73 #define MEUIS                           BIT(1)
  74 #define MECIS                           BIT(0)
  75 #define MTL_ECC_INT_ENABLE              0x00000cc8
  76 #define RPCEIE                          BIT(12)
  77 #define ECEIE                           BIT(8)
  78 #define RXCEIE                          BIT(4)
  79 #define TXCEIE                          BIT(0)
  80 #define MTL_ECC_INT_STATUS              0x00000ccc
  81 #define MTL_DPP_CONTROL                 0x00000ce0
  82 #define EPSI                            BIT(2)
  83 #define OPE                             BIT(1)
  84 #define EDPP                            BIT(0)
  85
  86 #define DMA_SAFETY_INT_STATUS           0x00001080
  87 #define MSUIS                           BIT(29)
  88 #define MSCIS                           BIT(28)
  89 #define DEUIS                           BIT(1)
  90 #define DECIS                           BIT(0)
  91 #define DMA_ECC_INT_ENABLE              0x00001084
  92 #define TCEIE                           BIT(0)
  93 #define DMA_ECC_INT_STATUS              0x00001088
  94
  95 /* EQoS version 5.xx VLAN Tag Filter Fail Packets Queuing */
  96 #define GMAC_RXQ_CTRL4                  0x00000094
  97 #define GMAC_RXQCTRL_VFFQ_MASK          GENMASK(19, 17)
  98 #define GMAC_RXQCTRL_VFFQ_SHIFT         17
  99 #define GMAC_RXQCTRL_VFFQE              BIT(16)
 100
 101 int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp);
 102 int dwmac5_safety_feat_irq_status(struct net_device *ndev,
 103                 void __iomem *ioaddr, unsigned int asp,
 104                 struct stmmac_safety_stats *stats);
 105 int dwmac5_safety_feat_dump(struct stmmac_safety_stats *stats,
 106                         int index, unsigned long *count, const char **desc);
 107 int dwmac5_rxp_config(void __iomem *ioaddr, struct stmmac_tc_entry *entries,
 108                       unsigned int count);
 109 int dwmac5_flex_pps_config(void __iomem *ioaddr, int index,
 110                            struct stmmac_pps_cfg *cfg, bool enable,
 111                            u32 sub_second_inc, u32 systime_flags);
 112 int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,
 113                          unsigned int ptp_rate);
 114 void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,
 115                           bool enable);
 116
 117 #endif /* __DWMAC5_H__ */