2 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
3 * DWC Ether MAC version 4.xx has been used for developing this code.
5 * This contains the functions to handle the dma.
7 * Copyright (C) 2015 STMicroelectronics Ltd
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * Author: Alexandre Torgue <alexandre.torgue@st.com>
18 #include "dwmac4_dma.h"
20 static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
22 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
25 pr_info("dwmac4: Master AXI performs %s burst length\n",
26 (value & DMA_SYS_BUS_FB) ? "fixed" : "any");
29 value |= DMA_AXI_EN_LPI;
31 value |= DMA_AXI_LPI_XIT_FRM;
33 value &= ~DMA_AXI_WR_OSR_LMT;
34 value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) <<
35 DMA_AXI_WR_OSR_LMT_SHIFT;
37 value &= ~DMA_AXI_RD_OSR_LMT;
38 value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) <<
39 DMA_AXI_RD_OSR_LMT_SHIFT;
41 /* Depending on the UNDEF bit the Master AXI will perform any burst
42 * length according to the BLEN programmed (by default all BLEN are
45 for (i = 0; i < AXI_BLEN; i++) {
46 switch (axi->axi_blen[i]) {
48 value |= DMA_AXI_BLEN256;
51 value |= DMA_AXI_BLEN128;
54 value |= DMA_AXI_BLEN64;
57 value |= DMA_AXI_BLEN32;
60 value |= DMA_AXI_BLEN16;
63 value |= DMA_AXI_BLEN8;
66 value |= DMA_AXI_BLEN4;
71 writel(value, ioaddr + DMA_SYS_BUS_MODE);
74 static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr,
75 struct stmmac_dma_cfg *dma_cfg,
76 u32 dma_rx_phy, u32 chan)
79 u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
81 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));
82 value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
83 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
85 writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));
88 static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr,
89 struct stmmac_dma_cfg *dma_cfg,
90 u32 dma_tx_phy, u32 chan)
93 u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
95 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
96 value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT);
97 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
99 writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
102 static void dwmac4_dma_init_channel(void __iomem *ioaddr,
103 struct stmmac_dma_cfg *dma_cfg, u32 chan)
107 /* common channel control register config */
108 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
110 value = value | DMA_BUS_MODE_PBL;
111 writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
113 /* Mask interrupts by writing to CSR7 */
114 writel(DMA_CHAN_INTR_DEFAULT_MASK,
115 ioaddr + DMA_CHAN_INTR_ENA(chan));
118 static void dwmac410_dma_init_channel(void __iomem *ioaddr,
119 struct stmmac_dma_cfg *dma_cfg, u32 chan)
123 /* common channel control register config */
124 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
126 value = value | DMA_BUS_MODE_PBL;
128 writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
130 /* Mask interrupts by writing to CSR7 */
131 writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10,
132 ioaddr + DMA_CHAN_INTR_ENA(chan));
135 static void dwmac4_dma_init(void __iomem *ioaddr,
136 struct stmmac_dma_cfg *dma_cfg,
137 u32 dma_tx, u32 dma_rx, int atds)
139 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
141 /* Set the Fixed burst mode */
142 if (dma_cfg->fixed_burst)
143 value |= DMA_SYS_BUS_FB;
145 /* Mixed Burst has no effect when fb is set */
146 if (dma_cfg->mixed_burst)
147 value |= DMA_SYS_BUS_MB;
150 value |= DMA_SYS_BUS_AAL;
152 writel(value, ioaddr + DMA_SYS_BUS_MODE);
155 static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel,
158 reg_space[DMA_CHAN_CONTROL(channel) / 4] =
159 readl(ioaddr + DMA_CHAN_CONTROL(channel));
160 reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] =
161 readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));
162 reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] =
163 readl(ioaddr + DMA_CHAN_RX_CONTROL(channel));
164 reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] =
165 readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel));
166 reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] =
167 readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));
168 reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] =
169 readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel));
170 reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] =
171 readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel));
172 reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] =
173 readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel));
174 reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] =
175 readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel));
176 reg_space[DMA_CHAN_INTR_ENA(channel) / 4] =
177 readl(ioaddr + DMA_CHAN_INTR_ENA(channel));
178 reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] =
179 readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel));
180 reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] =
181 readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel));
182 reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] =
183 readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel));
184 reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] =
185 readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel));
186 reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] =
187 readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel));
188 reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] =
189 readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel));
190 reg_space[DMA_CHAN_STATUS(channel) / 4] =
191 readl(ioaddr + DMA_CHAN_STATUS(channel));
194 static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
198 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
199 _dwmac4_dump_dma_regs(ioaddr, i, reg_space);
202 static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 number_chan)
206 for (chan = 0; chan < number_chan; chan++)
207 writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(chan));
210 static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode,
211 u32 channel, int fifosz)
213 unsigned int rqs = fifosz / 256 - 1;
214 u32 mtl_rx_op, mtl_rx_int;
216 mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));
218 if (mode == SF_DMA_MODE) {
219 pr_debug("GMAC: enable RX store and forward mode\n");
220 mtl_rx_op |= MTL_OP_MODE_RSF;
222 pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode);
223 mtl_rx_op &= ~MTL_OP_MODE_RSF;
224 mtl_rx_op &= MTL_OP_MODE_RTC_MASK;
226 mtl_rx_op |= MTL_OP_MODE_RTC_32;
228 mtl_rx_op |= MTL_OP_MODE_RTC_64;
230 mtl_rx_op |= MTL_OP_MODE_RTC_96;
232 mtl_rx_op |= MTL_OP_MODE_RTC_128;
235 mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK;
236 mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT;
238 /* enable flow control only if each channel gets 4 KiB or more FIFO */
239 if (fifosz >= 4096) {
240 unsigned int rfd, rfa;
242 mtl_rx_op |= MTL_OP_MODE_EHFC;
244 /* Set Threshold for Activating Flow Control to min 2 frames,
245 * i.e. 1500 * 2 = 3000 bytes.
247 * Set Threshold for Deactivating Flow Control to min 1 frame,
252 /* This violates the above formula because of FIFO size
253 * limit therefore overflow may occur in spite of this.
255 rfd = 0x03; /* Full-2.5K */
256 rfa = 0x01; /* Full-1.5K */
260 rfd = 0x06; /* Full-4K */
261 rfa = 0x0a; /* Full-6K */
265 rfd = 0x06; /* Full-4K */
266 rfa = 0x12; /* Full-10K */
270 rfd = 0x06; /* Full-4K */
271 rfa = 0x1e; /* Full-16K */
275 mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK;
276 mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT;
278 mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK;
279 mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT;
282 writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel));
284 /* Enable MTL RX overflow */
285 mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel));
286 writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN,
287 ioaddr + MTL_CHAN_INT_CTRL(channel));
290 static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode,
291 u32 channel, int fifosz)
293 u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));
294 unsigned int tqs = fifosz / 256 - 1;
296 if (mode == SF_DMA_MODE) {
297 pr_debug("GMAC: enable TX store and forward mode\n");
298 /* Transmit COE type 2 cannot be done in cut-through mode. */
299 mtl_tx_op |= MTL_OP_MODE_TSF;
301 pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode);
302 mtl_tx_op &= ~MTL_OP_MODE_TSF;
303 mtl_tx_op &= MTL_OP_MODE_TTC_MASK;
304 /* Set the transmit threshold */
306 mtl_tx_op |= MTL_OP_MODE_TTC_32;
308 mtl_tx_op |= MTL_OP_MODE_TTC_64;
310 mtl_tx_op |= MTL_OP_MODE_TTC_96;
311 else if (mode <= 128)
312 mtl_tx_op |= MTL_OP_MODE_TTC_128;
313 else if (mode <= 192)
314 mtl_tx_op |= MTL_OP_MODE_TTC_192;
315 else if (mode <= 256)
316 mtl_tx_op |= MTL_OP_MODE_TTC_256;
317 else if (mode <= 384)
318 mtl_tx_op |= MTL_OP_MODE_TTC_384;
320 mtl_tx_op |= MTL_OP_MODE_TTC_512;
322 /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
323 * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
324 * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
325 * with reset values: TXQEN off, TQS 256 bytes.
327 * TXQEN must be written for multi-channel operation and TQS must
328 * reflect the available fifo size per queue (total fifo size / number
329 * of enabled queues).
331 mtl_tx_op |= MTL_OP_MODE_TXQEN;
332 mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK;
333 mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT;
335 writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel));
338 static void dwmac4_get_hw_feature(void __iomem *ioaddr,
339 struct dma_features *dma_cap)
341 u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);
343 /* MAC HW feature0 */
344 dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL);
345 dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1;
346 dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2;
347 dma_cap->hash_filter = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;
348 dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18;
349 dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3;
350 dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5;
351 dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6;
352 dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7;
354 dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8;
356 dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12;
357 /* 802.3az - Energy-Efficient Ethernet (EEE) */
358 dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13;
360 dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;
361 dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;
363 /* MAC HW feature1 */
364 hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);
365 dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
366 dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;
367 /* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by
368 * shifting and store the sizes in bytes.
370 dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6);
371 dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0);
372 /* MAC HW feature2 */
373 hw_cap = readl(ioaddr + GMAC_HW_FEATURE2);
374 /* TX and RX number of channels */
375 dma_cap->number_rx_channel =
376 ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1;
377 dma_cap->number_tx_channel =
378 ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1;
379 /* TX and RX number of queues */
380 dma_cap->number_rx_queues =
381 ((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1;
382 dma_cap->number_tx_queues =
383 ((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1;
386 dma_cap->time_stamp = 0;
389 /* Enable/disable TSO feature and set MSS */
390 static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
396 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
397 writel(value | DMA_CONTROL_TSE,
398 ioaddr + DMA_CHAN_TX_CONTROL(chan));
401 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
402 writel(value & ~DMA_CONTROL_TSE,
403 ioaddr + DMA_CHAN_TX_CONTROL(chan));
407 const struct stmmac_dma_ops dwmac4_dma_ops = {
408 .reset = dwmac4_dma_reset,
409 .init = dwmac4_dma_init,
410 .init_chan = dwmac4_dma_init_channel,
411 .init_rx_chan = dwmac4_dma_init_rx_chan,
412 .init_tx_chan = dwmac4_dma_init_tx_chan,
413 .axi = dwmac4_dma_axi,
414 .dump_regs = dwmac4_dump_dma_regs,
415 .dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
416 .dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
417 .enable_dma_irq = dwmac4_enable_dma_irq,
418 .disable_dma_irq = dwmac4_disable_dma_irq,
419 .start_tx = dwmac4_dma_start_tx,
420 .stop_tx = dwmac4_dma_stop_tx,
421 .start_rx = dwmac4_dma_start_rx,
422 .stop_rx = dwmac4_dma_stop_rx,
423 .dma_interrupt = dwmac4_dma_interrupt,
424 .get_hw_feature = dwmac4_get_hw_feature,
425 .rx_watchdog = dwmac4_rx_watchdog,
426 .set_rx_ring_len = dwmac4_set_rx_ring_len,
427 .set_tx_ring_len = dwmac4_set_tx_ring_len,
428 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
429 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
430 .enable_tso = dwmac4_enable_tso,
433 const struct stmmac_dma_ops dwmac410_dma_ops = {
434 .reset = dwmac4_dma_reset,
435 .init = dwmac4_dma_init,
436 .init_chan = dwmac410_dma_init_channel,
437 .init_rx_chan = dwmac4_dma_init_rx_chan,
438 .init_tx_chan = dwmac4_dma_init_tx_chan,
439 .axi = dwmac4_dma_axi,
440 .dump_regs = dwmac4_dump_dma_regs,
441 .dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
442 .dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
443 .enable_dma_irq = dwmac410_enable_dma_irq,
444 .disable_dma_irq = dwmac4_disable_dma_irq,
445 .start_tx = dwmac4_dma_start_tx,
446 .stop_tx = dwmac4_dma_stop_tx,
447 .start_rx = dwmac4_dma_start_rx,
448 .stop_rx = dwmac4_dma_stop_rx,
449 .dma_interrupt = dwmac4_dma_interrupt,
450 .get_hw_feature = dwmac4_get_hw_feature,
451 .rx_watchdog = dwmac4_rx_watchdog,
452 .set_rx_ring_len = dwmac4_set_rx_ring_len,
453 .set_tx_ring_len = dwmac4_set_tx_ring_len,
454 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
455 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
456 .enable_tso = dwmac4_enable_tso,