drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c

   1 /*
   2  * This contains the functions to handle the descriptors for DesignWare databook
   3  * 4.xx.
   4  *
   5  * Copyright (C) 2015  STMicroelectronics Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * Author: Alexandre Torgue <alexandre.torgue@st.com>
  12  */
  13
  14 #include <linux/stmmac.h>
  15 #include "common.h"
  16 #include "dwmac4_descs.h"
  17
  18 static int dwmac4_wrback_get_tx_status(void *data, struct stmmac_extra_stats *x,
  19                                        struct dma_desc *p,
  20                                        void __iomem *ioaddr)
  21 {
  22         struct net_device_stats *stats = (struct net_device_stats *)data;
  23         unsigned int tdes3;
  24         int ret = tx_done;
  25
  26         tdes3 = le32_to_cpu(p->des3);
  27
  28         /* Get tx owner first */
  29         if (unlikely(tdes3 & TDES3_OWN))
  30                 return tx_dma_own;
  31
  32         /* Verify tx error by looking at the last segment. */
  33         if (likely(!(tdes3 & TDES3_LAST_DESCRIPTOR)))
  34                 return tx_not_ls;
  35
  36         if (unlikely(tdes3 & TDES3_ERROR_SUMMARY)) {
  37                 if (unlikely(tdes3 & TDES3_JABBER_TIMEOUT))
  38                         x->tx_jabber++;
  39                 if (unlikely(tdes3 & TDES3_PACKET_FLUSHED))
  40                         x->tx_frame_flushed++;
  41                 if (unlikely(tdes3 & TDES3_LOSS_CARRIER)) {
  42                         x->tx_losscarrier++;
  43                         stats->tx_carrier_errors++;
  44                 }
  45                 if (unlikely(tdes3 & TDES3_NO_CARRIER)) {
  46                         x->tx_carrier++;
  47                         stats->tx_carrier_errors++;
  48                 }
  49                 if (unlikely((tdes3 & TDES3_LATE_COLLISION) ||
  50                              (tdes3 & TDES3_EXCESSIVE_COLLISION)))
  51                         stats->collisions +=
  52                             (tdes3 & TDES3_COLLISION_COUNT_MASK)
  53                             >> TDES3_COLLISION_COUNT_SHIFT;
  54
  55                 if (unlikely(tdes3 & TDES3_EXCESSIVE_DEFERRAL))
  56                         x->tx_deferred++;
  57
  58                 if (unlikely(tdes3 & TDES3_UNDERFLOW_ERROR))
  59                         x->tx_underflow++;
  60
  61                 if (unlikely(tdes3 & TDES3_IP_HDR_ERROR))
  62                         x->tx_ip_header_error++;
  63
  64                 if (unlikely(tdes3 & TDES3_PAYLOAD_ERROR))
  65                         x->tx_payload_error++;
  66
  67                 ret = tx_err;
  68         }
  69
  70         if (unlikely(tdes3 & TDES3_DEFERRED))
  71                 x->tx_deferred++;
  72
  73         return ret;
  74 }
  75
  76 static int dwmac4_wrback_get_rx_status(void *data, struct stmmac_extra_stats *x,
  77                                        struct dma_desc *p)
  78 {
  79         struct net_device_stats *stats = (struct net_device_stats *)data;
  80         unsigned int rdes1 = le32_to_cpu(p->des1);
  81         unsigned int rdes2 = le32_to_cpu(p->des2);
  82         unsigned int rdes3 = le32_to_cpu(p->des3);
  83         int message_type;
  84         int ret = good_frame;
  85
  86         if (unlikely(rdes3 & RDES3_OWN))
  87                 return dma_own;
  88
  89         /* Verify rx error by looking at the last segment. */
  90         if (likely(!(rdes3 & RDES3_LAST_DESCRIPTOR)))
  91                 return discard_frame;
  92
  93         if (unlikely(rdes3 & RDES3_ERROR_SUMMARY)) {
  94                 if (unlikely(rdes3 & RDES3_GIANT_PACKET))
  95                         stats->rx_length_errors++;
  96                 if (unlikely(rdes3 & RDES3_OVERFLOW_ERROR))
  97                         x->rx_gmac_overflow++;
  98
  99                 if (unlikely(rdes3 & RDES3_RECEIVE_WATCHDOG))
 100                         x->rx_watchdog++;
 101
 102                 if (unlikely(rdes3 & RDES3_RECEIVE_ERROR))
 103                         x->rx_mii++;
 104
 105                 if (unlikely(rdes3 & RDES3_CRC_ERROR)) {
 106                         x->rx_crc_errors++;
 107                         stats->rx_crc_errors++;
 108                 }
 109
 110                 if (unlikely(rdes3 & RDES3_DRIBBLE_ERROR))
 111                         x->dribbling_bit++;
 112
 113                 ret = discard_frame;
 114         }
 115
 116         message_type = (rdes1 & ERDES4_MSG_TYPE_MASK) >> 8;
 117
 118         if (rdes1 & RDES1_IP_HDR_ERROR)
 119                 x->ip_hdr_err++;
 120         if (rdes1 & RDES1_IP_CSUM_BYPASSED)
 121                 x->ip_csum_bypassed++;
 122         if (rdes1 & RDES1_IPV4_HEADER)
 123                 x->ipv4_pkt_rcvd++;
 124         if (rdes1 & RDES1_IPV6_HEADER)
 125                 x->ipv6_pkt_rcvd++;
 126
 127         if (message_type == RDES_EXT_NO_PTP)
 128                 x->no_ptp_rx_msg_type_ext++;
 129         else if (message_type == RDES_EXT_SYNC)
 130                 x->ptp_rx_msg_type_sync++;
 131         else if (message_type == RDES_EXT_FOLLOW_UP)
 132                 x->ptp_rx_msg_type_follow_up++;
 133         else if (message_type == RDES_EXT_DELAY_REQ)
 134                 x->ptp_rx_msg_type_delay_req++;
 135         else if (message_type == RDES_EXT_DELAY_RESP)
 136                 x->ptp_rx_msg_type_delay_resp++;
 137         else if (message_type == RDES_EXT_PDELAY_REQ)
 138                 x->ptp_rx_msg_type_pdelay_req++;
 139         else if (message_type == RDES_EXT_PDELAY_RESP)
 140                 x->ptp_rx_msg_type_pdelay_resp++;
 141         else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
 142                 x->ptp_rx_msg_type_pdelay_follow_up++;
 143         else if (message_type == RDES_PTP_ANNOUNCE)
 144                 x->ptp_rx_msg_type_announce++;
 145         else if (message_type == RDES_PTP_MANAGEMENT)
 146                 x->ptp_rx_msg_type_management++;
 147         else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)
 148                 x->ptp_rx_msg_pkt_reserved_type++;
 149
 150         if (rdes1 & RDES1_PTP_PACKET_TYPE)
 151                 x->ptp_frame_type++;
 152         if (rdes1 & RDES1_PTP_VER)
 153                 x->ptp_ver++;
 154         if (rdes1 & RDES1_TIMESTAMP_DROPPED)
 155                 x->timestamp_dropped++;
 156
 157         if (unlikely(rdes2 & RDES2_SA_FILTER_FAIL)) {
 158                 x->sa_rx_filter_fail++;
 159                 ret = discard_frame;
 160         }
 161         if (unlikely(rdes2 & RDES2_DA_FILTER_FAIL)) {
 162                 x->da_rx_filter_fail++;
 163                 ret = discard_frame;
 164         }
 165
 166         if (rdes2 & RDES2_L3_FILTER_MATCH)
 167                 x->l3_filter_match++;
 168         if (rdes2 & RDES2_L4_FILTER_MATCH)
 169                 x->l4_filter_match++;
 170         if ((rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK)
 171             >> RDES2_L3_L4_FILT_NB_MATCH_SHIFT)
 172                 x->l3_l4_filter_no_match++;
 173
 174         return ret;
 175 }
 176
 177 static int dwmac4_rd_get_tx_len(struct dma_desc *p)
 178 {
 179         return (le32_to_cpu(p->des2) & TDES2_BUFFER1_SIZE_MASK);
 180 }
 181
 182 static int dwmac4_get_tx_owner(struct dma_desc *p)
 183 {
 184         return (le32_to_cpu(p->des3) & TDES3_OWN) >> TDES3_OWN_SHIFT;
 185 }
 186
 187 static void dwmac4_set_tx_owner(struct dma_desc *p)
 188 {
 189         p->des3 |= cpu_to_le32(TDES3_OWN);
 190 }
 191
 192 static void dwmac4_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
 193 {
 194         p->des3 = cpu_to_le32(RDES3_OWN | RDES3_BUFFER1_VALID_ADDR);
 195
 196         if (!disable_rx_ic)
 197                 p->des3 |= cpu_to_le32(RDES3_INT_ON_COMPLETION_EN);
 198 }
 199
 200 static int dwmac4_get_tx_ls(struct dma_desc *p)
 201 {
 202         return (le32_to_cpu(p->des3) & TDES3_LAST_DESCRIPTOR)
 203                 >> TDES3_LAST_DESCRIPTOR_SHIFT;
 204 }
 205
 206 static int dwmac4_wrback_get_rx_frame_len(struct dma_desc *p, int rx_coe)
 207 {
 208         return (le32_to_cpu(p->des3) & RDES3_PACKET_SIZE_MASK);
 209 }
 210
 211 static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p)
 212 {
 213         p->des2 |= cpu_to_le32(TDES2_TIMESTAMP_ENABLE);
 214 }
 215
 216 static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p)
 217 {
 218         /* Context type from W/B descriptor must be zero */
 219         if (le32_to_cpu(p->des3) & TDES3_CONTEXT_TYPE)
 220                 return 0;
 221
 222         /* Tx Timestamp Status is 1 so des0 and des1'll have valid values */
 223         if (le32_to_cpu(p->des3) & TDES3_TIMESTAMP_STATUS)
 224                 return 1;
 225
 226         return 0;
 227 }
 228
 229 static inline void dwmac4_get_timestamp(void *desc, u32 ats, u64 *ts)
 230 {
 231         struct dma_desc *p = (struct dma_desc *)desc;
 232         u64 ns;
 233
 234         ns = le32_to_cpu(p->des0);
 235         /* convert high/sec time stamp value to nanosecond */
 236         ns += le32_to_cpu(p->des1) * 1000000000ULL;
 237
 238         *ts = ns;
 239 }
 240
 241 static int dwmac4_rx_check_timestamp(void *desc)
 242 {
 243         struct dma_desc *p = (struct dma_desc *)desc;
 244         unsigned int rdes0 = le32_to_cpu(p->des0);
 245         unsigned int rdes1 = le32_to_cpu(p->des1);
 246         unsigned int rdes3 = le32_to_cpu(p->des3);
 247         u32 own, ctxt;
 248         int ret = 1;
 249
 250         own = rdes3 & RDES3_OWN;
 251         ctxt = ((rdes3 & RDES3_CONTEXT_DESCRIPTOR)
 252                 >> RDES3_CONTEXT_DESCRIPTOR_SHIFT);
 253
 254         if (likely(!own && ctxt)) {
 255                 if ((rdes0 == 0xffffffff) && (rdes1 == 0xffffffff))
 256                         /* Corrupted value */
 257                         ret = -EINVAL;
 258                 else
 259                         /* A valid Timestamp is ready to be read */
 260                         ret = 0;
 261         }
 262
 263         /* Timestamp not ready */
 264         return ret;
 265 }
 266
 267 static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc,
 268                                                  u32 ats)
 269 {
 270         struct dma_desc *p = (struct dma_desc *)desc;
 271         int ret = -EINVAL;
 272
 273         /* Get the status from normal w/b descriptor */
 274         if (likely(p->des3 & TDES3_RS1V)) {
 275                 if (likely(le32_to_cpu(p->des1) & RDES1_TIMESTAMP_AVAILABLE)) {
 276                         int i = 0;
 277
 278                         /* Check if timestamp is OK from context descriptor */
 279                         do {
 280                                 ret = dwmac4_rx_check_timestamp(next_desc);
 281                                 if (ret < 0)
 282                                         goto exit;
 283                                 i++;
 284
 285                         } while ((ret == 1) && (i < 10));
 286
 287                         if (i == 10)
 288                                 ret = -EBUSY;
 289                 }
 290         }
 291 exit:
 292         if (likely(ret == 0))
 293                 return 1;
 294
 295         return 0;
 296 }
 297
 298 static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
 299                                    int mode, int end, int bfsize)
 300 {
 301         dwmac4_set_rx_owner(p, disable_rx_ic);
 302 }
 303
 304 static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end)
 305 {
 306         p->des0 = 0;
 307         p->des1 = 0;
 308         p->des2 = 0;
 309         p->des3 = 0;
 310 }
 311
 312 static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
 313                                       bool csum_flag, int mode, bool tx_own,
 314                                       bool ls, unsigned int tot_pkt_len)
 315 {
 316         unsigned int tdes3 = le32_to_cpu(p->des3);
 317
 318         p->des2 |= cpu_to_le32(len & TDES2_BUFFER1_SIZE_MASK);
 319
 320         tdes3 |= tot_pkt_len & TDES3_PACKET_SIZE_MASK;
 321         if (is_fs)
 322                 tdes3 |= TDES3_FIRST_DESCRIPTOR;
 323         else
 324                 tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
 325
 326         if (likely(csum_flag))
 327                 tdes3 |= (TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
 328         else
 329                 tdes3 &= ~(TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
 330
 331         if (ls)
 332                 tdes3 |= TDES3_LAST_DESCRIPTOR;
 333         else
 334                 tdes3 &= ~TDES3_LAST_DESCRIPTOR;
 335
 336         /* Finally set the OWN bit. Later the DMA will start! */
 337         if (tx_own)
 338                 tdes3 |= TDES3_OWN;
 339
 340         if (is_fs && tx_own)
 341                 /* When the own bit, for the first frame, has to be set, all
 342                  * descriptors for the same frame has to be set before, to
 343                  * avoid race condition.
 344                  */
 345                 dma_wmb();
 346
 347         p->des3 = cpu_to_le32(tdes3);
 348 }
 349
 350 static void dwmac4_rd_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
 351                                           int len1, int len2, bool tx_own,
 352                                           bool ls, unsigned int tcphdrlen,
 353                                           unsigned int tcppayloadlen)
 354 {
 355         unsigned int tdes3 = le32_to_cpu(p->des3);
 356
 357         if (len1)
 358                 p->des2 |= cpu_to_le32((len1 & TDES2_BUFFER1_SIZE_MASK));
 359
 360         if (len2)
 361                 p->des2 |= cpu_to_le32((len2 << TDES2_BUFFER2_SIZE_MASK_SHIFT)
 362                             & TDES2_BUFFER2_SIZE_MASK);
 363
 364         if (is_fs) {
 365                 tdes3 |= TDES3_FIRST_DESCRIPTOR |
 366                          TDES3_TCP_SEGMENTATION_ENABLE |
 367                          ((tcphdrlen << TDES3_HDR_LEN_SHIFT) &
 368                           TDES3_SLOT_NUMBER_MASK) |
 369                          ((tcppayloadlen & TDES3_TCP_PKT_PAYLOAD_MASK));
 370         } else {
 371                 tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
 372         }
 373
 374         if (ls)
 375                 tdes3 |= TDES3_LAST_DESCRIPTOR;
 376         else
 377                 tdes3 &= ~TDES3_LAST_DESCRIPTOR;
 378
 379         /* Finally set the OWN bit. Later the DMA will start! */
 380         if (tx_own)
 381                 tdes3 |= TDES3_OWN;
 382
 383         if (is_fs && tx_own)
 384                 /* When the own bit, for the first frame, has to be set, all
 385                  * descriptors for the same frame has to be set before, to
 386                  * avoid race condition.
 387                  */
 388                 dma_wmb();
 389
 390         p->des3 = cpu_to_le32(tdes3);
 391 }
 392
 393 static void dwmac4_release_tx_desc(struct dma_desc *p, int mode)
 394 {
 395         p->des0 = 0;
 396         p->des1 = 0;
 397         p->des2 = 0;
 398         p->des3 = 0;
 399 }
 400
 401 static void dwmac4_rd_set_tx_ic(struct dma_desc *p)
 402 {
 403         p->des2 |= cpu_to_le32(TDES2_INTERRUPT_ON_COMPLETION);
 404 }
 405
 406 static void dwmac4_display_ring(void *head, unsigned int size, bool rx)
 407 {
 408         struct dma_desc *p = (struct dma_desc *)head;
 409         int i;
 410
 411         pr_info("%s descriptor ring:\n", rx ? "RX" : "TX");
 412
 413         for (i = 0; i < size; i++) {
 414                 pr_info("%03d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
 415                         i, (unsigned int)virt_to_phys(p),
 416                         le32_to_cpu(p->des0), le32_to_cpu(p->des1),
 417                         le32_to_cpu(p->des2), le32_to_cpu(p->des3));
 418                 p++;
 419         }
 420 }
 421
 422 static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)
 423 {
 424         p->des0 = 0;
 425         p->des1 = 0;
 426         p->des2 = cpu_to_le32(mss);
 427         p->des3 = cpu_to_le32(TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV);
 428 }
 429
 430 static void dwmac4_get_addr(struct dma_desc *p, unsigned int *addr)
 431 {
 432         *addr = le32_to_cpu(p->des0);
 433 }
 434
 435 static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr)
 436 {
 437         p->des0 = cpu_to_le32(addr);
 438         p->des1 = 0;
 439 }
 440
 441 static void dwmac4_clear(struct dma_desc *p)
 442 {
 443         p->des0 = 0;
 444         p->des1 = 0;
 445         p->des2 = 0;
 446         p->des3 = 0;
 447 }
 448
 449 const struct stmmac_desc_ops dwmac4_desc_ops = {
 450         .tx_status = dwmac4_wrback_get_tx_status,
 451         .rx_status = dwmac4_wrback_get_rx_status,
 452         .get_tx_len = dwmac4_rd_get_tx_len,
 453         .get_tx_owner = dwmac4_get_tx_owner,
 454         .set_tx_owner = dwmac4_set_tx_owner,
 455         .set_rx_owner = dwmac4_set_rx_owner,
 456         .get_tx_ls = dwmac4_get_tx_ls,
 457         .get_rx_frame_len = dwmac4_wrback_get_rx_frame_len,
 458         .enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp,
 459         .get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status,
 460         .get_rx_timestamp_status = dwmac4_wrback_get_rx_timestamp_status,
 461         .get_timestamp = dwmac4_get_timestamp,
 462         .set_tx_ic = dwmac4_rd_set_tx_ic,
 463         .prepare_tx_desc = dwmac4_rd_prepare_tx_desc,
 464         .prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc,
 465         .release_tx_desc = dwmac4_release_tx_desc,
 466         .init_rx_desc = dwmac4_rd_init_rx_desc,
 467         .init_tx_desc = dwmac4_rd_init_tx_desc,
 468         .display_ring = dwmac4_display_ring,
 469         .set_mss = dwmac4_set_mss_ctxt,
 470         .get_addr = dwmac4_get_addr,
 471         .set_addr = dwmac4_set_addr,
 472         .clear = dwmac4_clear,
 473 };
 474
 475 const struct stmmac_mode_ops dwmac4_ring_mode_ops = { };