drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

   1 /*
   2  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   3  * DWC Ether MAC version 4.00  has been used for developing this code.
   4  *
   5  * This only implements the mac core functions for this chip.
   6  *
   7  * Copyright (C) 2015  STMicroelectronics Ltd
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms and conditions of the GNU General Public License,
  11  * version 2, as published by the Free Software Foundation.
  12  *
  13  * Author: Alexandre Torgue <alexandre.torgue@st.com>
  14  */
  15
  16 #include <linux/crc32.h>
  17 #include <linux/slab.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/io.h>
  20 #include <net/dsa.h>
  21 #include "stmmac_pcs.h"
  22 #include "dwmac4.h"
  23
  24 static void dwmac4_core_init(struct mac_device_info *hw,
  25                              struct net_device *dev)
  26 {
  27         void __iomem *ioaddr = hw->pcsr;
  28         u32 value = readl(ioaddr + GMAC_CONFIG);
  29         int mtu = dev->mtu;
  30
  31         value |= GMAC_CORE_INIT;
  32
  33         if (mtu > 1500)
  34                 value |= GMAC_CONFIG_2K;
  35         if (mtu > 2000)
  36                 value |= GMAC_CONFIG_JE;
  37
  38         if (hw->ps) {
  39                 value |= GMAC_CONFIG_TE;
  40
  41                 value &= hw->link.speed_mask;
  42                 switch (hw->ps) {
  43                 case SPEED_1000:
  44                         value |= hw->link.speed1000;
  45                         break;
  46                 case SPEED_100:
  47                         value |= hw->link.speed100;
  48                         break;
  49                 case SPEED_10:
  50                         value |= hw->link.speed10;
  51                         break;
  52                 }
  53         }
  54
  55         writel(value, ioaddr + GMAC_CONFIG);
  56
  57         /* Mask GMAC interrupts */
  58         value = GMAC_INT_DEFAULT_MASK;
  59         if (hw->pmt)
  60                 value |= GMAC_INT_PMT_EN;
  61         if (hw->pcs)
  62                 value |= GMAC_PCS_IRQ_DEFAULT;
  63
  64         writel(value, ioaddr + GMAC_INT_EN);
  65 }
  66
  67 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
  68                                    u8 mode, u32 queue)
  69 {
  70         void __iomem *ioaddr = hw->pcsr;
  71         u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
  72
  73         value &= GMAC_RX_QUEUE_CLEAR(queue);
  74         if (mode == MTL_QUEUE_AVB)
  75                 value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
  76         else if (mode == MTL_QUEUE_DCB)
  77                 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
  78
  79         writel(value, ioaddr + GMAC_RXQ_CTRL0);
  80 }
  81
  82 static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
  83                                      u32 prio, u32 queue)
  84 {
  85         void __iomem *ioaddr = hw->pcsr;
  86         u32 base_register;
  87         u32 value;
  88
  89         base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3;
  90
  91         value = readl(ioaddr + base_register);
  92
  93         value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue);
  94         value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
  95                                                 GMAC_RXQCTRL_PSRQX_MASK(queue);
  96         writel(value, ioaddr + base_register);
  97 }
  98
  99 static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
 100                                      u32 prio, u32 queue)
 101 {
 102         void __iomem *ioaddr = hw->pcsr;
 103         u32 base_register;
 104         u32 value;
 105
 106         base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
 107
 108         value = readl(ioaddr + base_register);
 109
 110         value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
 111         value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
 112                                                 GMAC_TXQCTRL_PSTQX_MASK(queue);
 113
 114         writel(value, ioaddr + base_register);
 115 }
 116
 117 static void dwmac4_tx_queue_routing(struct mac_device_info *hw,
 118                                     u8 packet, u32 queue)
 119 {
 120         void __iomem *ioaddr = hw->pcsr;
 121         u32 value;
 122
 123         static const struct stmmac_rx_routing route_possibilities[] = {
 124                 { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
 125                 { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
 126                 { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
 127                 { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
 128                 { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
 129         };
 130
 131         value = readl(ioaddr + GMAC_RXQ_CTRL1);
 132
 133         /* routing configuration */
 134         value &= ~route_possibilities[packet - 1].reg_mask;
 135         value |= (queue << route_possibilities[packet-1].reg_shift) &
 136                  route_possibilities[packet - 1].reg_mask;
 137
 138         /* some packets require extra ops */
 139         if (packet == PACKET_AVCPQ) {
 140                 value &= ~GMAC_RXQCTRL_TACPQE;
 141                 value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
 142         } else if (packet == PACKET_MCBCQ) {
 143                 value &= ~GMAC_RXQCTRL_MCBCQEN;
 144                 value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
 145         }
 146
 147         writel(value, ioaddr + GMAC_RXQ_CTRL1);
 148 }
 149
 150 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
 151                                           u32 rx_alg)
 152 {
 153         void __iomem *ioaddr = hw->pcsr;
 154         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 155
 156         value &= ~MTL_OPERATION_RAA;
 157         switch (rx_alg) {
 158         case MTL_RX_ALGORITHM_SP:
 159                 value |= MTL_OPERATION_RAA_SP;
 160                 break;
 161         case MTL_RX_ALGORITHM_WSP:
 162                 value |= MTL_OPERATION_RAA_WSP;
 163                 break;
 164         default:
 165                 break;
 166         }
 167
 168         writel(value, ioaddr + MTL_OPERATION_MODE);
 169 }
 170
 171 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
 172                                           u32 tx_alg)
 173 {
 174         void __iomem *ioaddr = hw->pcsr;
 175         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 176
 177         value &= ~MTL_OPERATION_SCHALG_MASK;
 178         switch (tx_alg) {
 179         case MTL_TX_ALGORITHM_WRR:
 180                 value |= MTL_OPERATION_SCHALG_WRR;
 181                 break;
 182         case MTL_TX_ALGORITHM_WFQ:
 183                 value |= MTL_OPERATION_SCHALG_WFQ;
 184                 break;
 185         case MTL_TX_ALGORITHM_DWRR:
 186                 value |= MTL_OPERATION_SCHALG_DWRR;
 187                 break;
 188         case MTL_TX_ALGORITHM_SP:
 189                 value |= MTL_OPERATION_SCHALG_SP;
 190                 break;
 191         default:
 192                 break;
 193         }
 194 }
 195
 196 static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
 197                                            u32 weight, u32 queue)
 198 {
 199         void __iomem *ioaddr = hw->pcsr;
 200         u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 201
 202         value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
 203         value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
 204         writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 205 }
 206
 207 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
 208 {
 209         void __iomem *ioaddr = hw->pcsr;
 210         u32 value;
 211
 212         if (queue < 4)
 213                 value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
 214         else
 215                 value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
 216
 217         if (queue == 0 || queue == 4) {
 218                 value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
 219                 value |= MTL_RXQ_DMA_Q04MDMACH(chan);
 220         } else if (queue > 4) {
 221                 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue - 4);
 222                 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue - 4);
 223         } else {
 224                 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
 225                 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
 226         }
 227
 228         if (queue < 4)
 229                 writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
 230         else
 231                 writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
 232 }
 233
 234 static void dwmac4_config_cbs(struct mac_device_info *hw,
 235                               u32 send_slope, u32 idle_slope,
 236                               u32 high_credit, u32 low_credit, u32 queue)
 237 {
 238         void __iomem *ioaddr = hw->pcsr;
 239         u32 value;
 240
 241         pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
 242         pr_debug("\tsend_slope: 0x%08x\n", send_slope);
 243         pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
 244         pr_debug("\thigh_credit: 0x%08x\n", high_credit);
 245         pr_debug("\tlow_credit: 0x%08x\n", low_credit);
 246
 247         /* enable AV algorithm */
 248         value = readl(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
 249         value |= MTL_ETS_CTRL_AVALG;
 250         value |= MTL_ETS_CTRL_CC;
 251         writel(value, ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
 252
 253         /* configure send slope */
 254         value = readl(ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
 255         value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
 256         value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
 257         writel(value, ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
 258
 259         /* configure idle slope (same register as tx weight) */
 260         dwmac4_set_mtl_tx_queue_weight(hw, idle_slope, queue);
 261
 262         /* configure high credit */
 263         value = readl(ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
 264         value &= ~MTL_HIGH_CRED_HC_MASK;
 265         value |= high_credit & MTL_HIGH_CRED_HC_MASK;
 266         writel(value, ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
 267
 268         /* configure high credit */
 269         value = readl(ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
 270         value &= ~MTL_HIGH_CRED_LC_MASK;
 271         value |= low_credit & MTL_HIGH_CRED_LC_MASK;
 272         writel(value, ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
 273 }
 274
 275 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
 276 {
 277         void __iomem *ioaddr = hw->pcsr;
 278         int i;
 279
 280         for (i = 0; i < GMAC_REG_NUM; i++)
 281                 reg_space[i] = readl(ioaddr + i * 4);
 282 }
 283
 284 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
 285 {
 286         void __iomem *ioaddr = hw->pcsr;
 287         u32 value = readl(ioaddr + GMAC_CONFIG);
 288
 289         if (hw->rx_csum)
 290                 value |= GMAC_CONFIG_IPC;
 291         else
 292                 value &= ~GMAC_CONFIG_IPC;
 293
 294         writel(value, ioaddr + GMAC_CONFIG);
 295
 296         value = readl(ioaddr + GMAC_CONFIG);
 297
 298         return !!(value & GMAC_CONFIG_IPC);
 299 }
 300
 301 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
 302 {
 303         void __iomem *ioaddr = hw->pcsr;
 304         unsigned int pmt = 0;
 305         u32 config;
 306
 307         if (mode & WAKE_MAGIC) {
 308                 pr_debug("GMAC: WOL Magic frame\n");
 309                 pmt |= power_down | magic_pkt_en;
 310         }
 311         if (mode & WAKE_UCAST) {
 312                 pr_debug("GMAC: WOL on global unicast\n");
 313                 pmt |= power_down | global_unicast | wake_up_frame_en;
 314         }
 315
 316         if (pmt) {
 317                 /* The receiver must be enabled for WOL before powering down */
 318                 config = readl(ioaddr + GMAC_CONFIG);
 319                 config |= GMAC_CONFIG_RE;
 320                 writel(config, ioaddr + GMAC_CONFIG);
 321         }
 322         writel(pmt, ioaddr + GMAC_PMT);
 323 }
 324
 325 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
 326                                  unsigned char *addr, unsigned int reg_n)
 327 {
 328         void __iomem *ioaddr = hw->pcsr;
 329
 330         stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 331                                    GMAC_ADDR_LOW(reg_n));
 332 }
 333
 334 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
 335                                  unsigned char *addr, unsigned int reg_n)
 336 {
 337         void __iomem *ioaddr = hw->pcsr;
 338
 339         stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 340                                    GMAC_ADDR_LOW(reg_n));
 341 }
 342
 343 static void dwmac4_set_eee_mode(struct mac_device_info *hw,
 344                                 bool en_tx_lpi_clockgating)
 345 {
 346         void __iomem *ioaddr = hw->pcsr;
 347         u32 value;
 348
 349         /* Enable the link status receive on RGMII, SGMII ore SMII
 350          * receive path and instruct the transmit to enter in LPI
 351          * state.
 352          */
 353         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 354         value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
 355
 356         if (en_tx_lpi_clockgating)
 357                 value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
 358
 359         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 360 }
 361
 362 static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
 363 {
 364         void __iomem *ioaddr = hw->pcsr;
 365         u32 value;
 366
 367         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 368         value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
 369         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 370 }
 371
 372 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
 373 {
 374         void __iomem *ioaddr = hw->pcsr;
 375         u32 value;
 376
 377         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 378
 379         if (link)
 380                 value |= GMAC4_LPI_CTRL_STATUS_PLS;
 381         else
 382                 value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
 383
 384         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 385 }
 386
 387 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
 388 {
 389         void __iomem *ioaddr = hw->pcsr;
 390         int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
 391
 392         /* Program the timers in the LPI timer control register:
 393          * LS: minimum time (ms) for which the link
 394          *  status from PHY should be ok before transmitting
 395          *  the LPI pattern.
 396          * TW: minimum time (us) for which the core waits
 397          *  after it has stopped transmitting the LPI pattern.
 398          */
 399         writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
 400 }
 401
 402 static void dwmac4_set_filter(struct mac_device_info *hw,
 403                               struct net_device *dev)
 404 {
 405         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 406         unsigned int value = 0;
 407
 408         if (dev->flags & IFF_PROMISC) {
 409                 value = GMAC_PACKET_FILTER_PR;
 410         } else if ((dev->flags & IFF_ALLMULTI) ||
 411                         (netdev_mc_count(dev) > HASH_TABLE_SIZE)) {
 412                 /* Pass all multi */
 413                 value = GMAC_PACKET_FILTER_PM;
 414                 /* Set the 64 bits of the HASH tab. To be updated if taller
 415                  * hash table is used
 416                  */
 417                 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_0_31);
 418                 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_32_63);
 419         } else if (!netdev_mc_empty(dev)) {
 420                 u32 mc_filter[2];
 421                 struct netdev_hw_addr *ha;
 422
 423                 /* Hash filter for multicast */
 424                 value = GMAC_PACKET_FILTER_HMC;
 425
 426                 memset(mc_filter, 0, sizeof(mc_filter));
 427                 netdev_for_each_mc_addr(ha, dev) {
 428                         /* The upper 6 bits of the calculated CRC are used to
 429                          * index the content of the Hash Table Reg 0 and 1.
 430                          */
 431                         int bit_nr =
 432                                 (bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26);
 433                         /* The most significant bit determines the register
 434                          * to use while the other 5 bits determines the bit
 435                          * within the selected register
 436                          */
 437                         mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1F));
 438                 }
 439                 writel(mc_filter[0], ioaddr + GMAC_HASH_TAB_0_31);
 440                 writel(mc_filter[1], ioaddr + GMAC_HASH_TAB_32_63);
 441         }
 442
 443         /* Handle multiple unicast addresses */
 444         if (netdev_uc_count(dev) > hw->unicast_filter_entries) {
 445                 /* Switch to promiscuous mode if more than 128 addrs
 446                  * are required
 447                  */
 448                 value |= GMAC_PACKET_FILTER_PR;
 449         } else {
 450                 struct netdev_hw_addr *ha;
 451                 int reg = 1;
 452
 453                 netdev_for_each_uc_addr(ha, dev) {
 454                         dwmac4_set_umac_addr(hw, ha->addr, reg);
 455                         reg++;
 456                 }
 457
 458                 while (reg <= GMAC_MAX_PERFECT_ADDRESSES) {
 459                         writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
 460                         writel(0, ioaddr + GMAC_ADDR_LOW(reg));
 461                         reg++;
 462                 }
 463         }
 464
 465         writel(value, ioaddr + GMAC_PACKET_FILTER);
 466 }
 467
 468 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 469                              unsigned int fc, unsigned int pause_time,
 470                              u32 tx_cnt)
 471 {
 472         void __iomem *ioaddr = hw->pcsr;
 473         unsigned int flow = 0;
 474         u32 queue = 0;
 475
 476         pr_debug("GMAC Flow-Control:\n");
 477         if (fc & FLOW_RX) {
 478                 pr_debug("\tReceive Flow-Control ON\n");
 479                 flow |= GMAC_RX_FLOW_CTRL_RFE;
 480         }
 481         writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
 482
 483         if (fc & FLOW_TX) {
 484                 pr_debug("\tTransmit Flow-Control ON\n");
 485
 486                 if (duplex)
 487                         pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
 488
 489                 for (queue = 0; queue < tx_cnt; queue++) {
 490                         flow = GMAC_TX_FLOW_CTRL_TFE;
 491
 492                         if (duplex)
 493                                 flow |=
 494                                 (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
 495
 496                         writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
 497                 }
 498         } else {
 499                 for (queue = 0; queue < tx_cnt; queue++)
 500                         writel(0, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
 501         }
 502 }
 503
 504 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 505                             bool loopback)
 506 {
 507         dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
 508 }
 509
 510 static void dwmac4_rane(void __iomem *ioaddr, bool restart)
 511 {
 512         dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
 513 }
 514
 515 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
 516 {
 517         dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
 518 }
 519
 520 /* RGMII or SMII interface */
 521 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 522 {
 523         u32 status;
 524
 525         status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
 526         x->irq_rgmii_n++;
 527
 528         /* Check the link status */
 529         if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
 530                 int speed_value;
 531
 532                 x->pcs_link = 1;
 533
 534                 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
 535                                GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
 536                 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
 537                         x->pcs_speed = SPEED_1000;
 538                 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
 539                         x->pcs_speed = SPEED_100;
 540                 else
 541                         x->pcs_speed = SPEED_10;
 542
 543                 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
 544
 545                 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
 546                         x->pcs_duplex ? "Full" : "Half");
 547         } else {
 548                 x->pcs_link = 0;
 549                 pr_info("Link is Down\n");
 550         }
 551 }
 552
 553 static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
 554 {
 555         void __iomem *ioaddr = hw->pcsr;
 556         u32 mtl_int_qx_status;
 557         int ret = 0;
 558
 559         mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
 560
 561         /* Check MTL Interrupt */
 562         if (mtl_int_qx_status & MTL_INT_QX(chan)) {
 563                 /* read Queue x Interrupt status */
 564                 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
 565
 566                 if (status & MTL_RX_OVERFLOW_INT) {
 567                         /*  clear Interrupt */
 568                         writel(status | MTL_RX_OVERFLOW_INT,
 569                                ioaddr + MTL_CHAN_INT_CTRL(chan));
 570                         ret = CORE_IRQ_MTL_RX_OVERFLOW;
 571                 }
 572         }
 573
 574         return ret;
 575 }
 576
 577 static int dwmac4_irq_status(struct mac_device_info *hw,
 578                              struct stmmac_extra_stats *x)
 579 {
 580         void __iomem *ioaddr = hw->pcsr;
 581         u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
 582         u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
 583         int ret = 0;
 584
 585         /* Discard disabled bits */
 586         intr_status &= intr_enable;
 587
 588         /* Not used events (e.g. MMC interrupts) are not handled. */
 589         if ((intr_status & mmc_tx_irq))
 590                 x->mmc_tx_irq_n++;
 591         if (unlikely(intr_status & mmc_rx_irq))
 592                 x->mmc_rx_irq_n++;
 593         if (unlikely(intr_status & mmc_rx_csum_offload_irq))
 594                 x->mmc_rx_csum_offload_irq_n++;
 595         /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
 596         if (unlikely(intr_status & pmt_irq)) {
 597                 readl(ioaddr + GMAC_PMT);
 598                 x->irq_receive_pmt_irq_n++;
 599         }
 600
 601         dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
 602         if (intr_status & PCS_RGSMIIIS_IRQ)
 603                 dwmac4_phystatus(ioaddr, x);
 604
 605         return ret;
 606 }
 607
 608 static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
 609                          u32 rx_queues, u32 tx_queues)
 610 {
 611         u32 value;
 612         u32 queue;
 613
 614         for (queue = 0; queue < tx_queues; queue++) {
 615                 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(queue));
 616
 617                 if (value & MTL_DEBUG_TXSTSFSTS)
 618                         x->mtl_tx_status_fifo_full++;
 619                 if (value & MTL_DEBUG_TXFSTS)
 620                         x->mtl_tx_fifo_not_empty++;
 621                 if (value & MTL_DEBUG_TWCSTS)
 622                         x->mmtl_fifo_ctrl++;
 623                 if (value & MTL_DEBUG_TRCSTS_MASK) {
 624                         u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
 625                                      >> MTL_DEBUG_TRCSTS_SHIFT;
 626                         if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
 627                                 x->mtl_tx_fifo_read_ctrl_write++;
 628                         else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
 629                                 x->mtl_tx_fifo_read_ctrl_wait++;
 630                         else if (trcsts == MTL_DEBUG_TRCSTS_READ)
 631                                 x->mtl_tx_fifo_read_ctrl_read++;
 632                         else
 633                                 x->mtl_tx_fifo_read_ctrl_idle++;
 634                 }
 635                 if (value & MTL_DEBUG_TXPAUSED)
 636                         x->mac_tx_in_pause++;
 637         }
 638
 639         for (queue = 0; queue < rx_queues; queue++) {
 640                 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(queue));
 641
 642                 if (value & MTL_DEBUG_RXFSTS_MASK) {
 643                         u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
 644                                      >> MTL_DEBUG_RRCSTS_SHIFT;
 645
 646                         if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
 647                                 x->mtl_rx_fifo_fill_level_full++;
 648                         else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
 649                                 x->mtl_rx_fifo_fill_above_thresh++;
 650                         else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
 651                                 x->mtl_rx_fifo_fill_below_thresh++;
 652                         else
 653                                 x->mtl_rx_fifo_fill_level_empty++;
 654                 }
 655                 if (value & MTL_DEBUG_RRCSTS_MASK) {
 656                         u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
 657                                      MTL_DEBUG_RRCSTS_SHIFT;
 658
 659                         if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
 660                                 x->mtl_rx_fifo_read_ctrl_flush++;
 661                         else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
 662                                 x->mtl_rx_fifo_read_ctrl_read_data++;
 663                         else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
 664                                 x->mtl_rx_fifo_read_ctrl_status++;
 665                         else
 666                                 x->mtl_rx_fifo_read_ctrl_idle++;
 667                 }
 668                 if (value & MTL_DEBUG_RWCSTS)
 669                         x->mtl_rx_fifo_ctrl_active++;
 670         }
 671
 672         /* GMAC debug */
 673         value = readl(ioaddr + GMAC_DEBUG);
 674
 675         if (value & GMAC_DEBUG_TFCSTS_MASK) {
 676                 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
 677                               >> GMAC_DEBUG_TFCSTS_SHIFT;
 678
 679                 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
 680                         x->mac_tx_frame_ctrl_xfer++;
 681                 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
 682                         x->mac_tx_frame_ctrl_pause++;
 683                 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
 684                         x->mac_tx_frame_ctrl_wait++;
 685                 else
 686                         x->mac_tx_frame_ctrl_idle++;
 687         }
 688         if (value & GMAC_DEBUG_TPESTS)
 689                 x->mac_gmii_tx_proto_engine++;
 690         if (value & GMAC_DEBUG_RFCFCSTS_MASK)
 691                 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
 692                                             >> GMAC_DEBUG_RFCFCSTS_SHIFT;
 693         if (value & GMAC_DEBUG_RPESTS)
 694                 x->mac_gmii_rx_proto_engine++;
 695 }
 696
 697 static const struct stmmac_ops dwmac4_ops = {
 698         .core_init = dwmac4_core_init,
 699         .set_mac = stmmac_set_mac,
 700         .rx_ipc = dwmac4_rx_ipc_enable,
 701         .rx_queue_enable = dwmac4_rx_queue_enable,
 702         .rx_queue_prio = dwmac4_rx_queue_priority,
 703         .tx_queue_prio = dwmac4_tx_queue_priority,
 704         .rx_queue_routing = dwmac4_tx_queue_routing,
 705         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
 706         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
 707         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
 708         .map_mtl_to_dma = dwmac4_map_mtl_dma,
 709         .config_cbs = dwmac4_config_cbs,
 710         .dump_regs = dwmac4_dump_regs,
 711         .host_irq_status = dwmac4_irq_status,
 712         .host_mtl_irq_status = dwmac4_irq_mtl_status,
 713         .flow_ctrl = dwmac4_flow_ctrl,
 714         .pmt = dwmac4_pmt,
 715         .set_umac_addr = dwmac4_set_umac_addr,
 716         .get_umac_addr = dwmac4_get_umac_addr,
 717         .set_eee_mode = dwmac4_set_eee_mode,
 718         .reset_eee_mode = dwmac4_reset_eee_mode,
 719         .set_eee_timer = dwmac4_set_eee_timer,
 720         .set_eee_pls = dwmac4_set_eee_pls,
 721         .pcs_ctrl_ane = dwmac4_ctrl_ane,
 722         .pcs_rane = dwmac4_rane,
 723         .pcs_get_adv_lp = dwmac4_get_adv_lp,
 724         .debug = dwmac4_debug,
 725         .set_filter = dwmac4_set_filter,
 726 };
 727
 728 static const struct stmmac_ops dwmac410_ops = {
 729         .core_init = dwmac4_core_init,
 730         .set_mac = stmmac_dwmac4_set_mac,
 731         .rx_ipc = dwmac4_rx_ipc_enable,
 732         .rx_queue_enable = dwmac4_rx_queue_enable,
 733         .rx_queue_prio = dwmac4_rx_queue_priority,
 734         .tx_queue_prio = dwmac4_tx_queue_priority,
 735         .rx_queue_routing = dwmac4_tx_queue_routing,
 736         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
 737         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
 738         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
 739         .map_mtl_to_dma = dwmac4_map_mtl_dma,
 740         .config_cbs = dwmac4_config_cbs,
 741         .dump_regs = dwmac4_dump_regs,
 742         .host_irq_status = dwmac4_irq_status,
 743         .host_mtl_irq_status = dwmac4_irq_mtl_status,
 744         .flow_ctrl = dwmac4_flow_ctrl,
 745         .pmt = dwmac4_pmt,
 746         .set_umac_addr = dwmac4_set_umac_addr,
 747         .get_umac_addr = dwmac4_get_umac_addr,
 748         .set_eee_mode = dwmac4_set_eee_mode,
 749         .reset_eee_mode = dwmac4_reset_eee_mode,
 750         .set_eee_timer = dwmac4_set_eee_timer,
 751         .set_eee_pls = dwmac4_set_eee_pls,
 752         .pcs_ctrl_ane = dwmac4_ctrl_ane,
 753         .pcs_rane = dwmac4_rane,
 754         .pcs_get_adv_lp = dwmac4_get_adv_lp,
 755         .debug = dwmac4_debug,
 756         .set_filter = dwmac4_set_filter,
 757 };
 758
 759 struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
 760                                      int perfect_uc_entries, int *synopsys_id)
 761 {
 762         struct mac_device_info *mac;
 763         u32 hwid = readl(ioaddr + GMAC_VERSION);
 764
 765         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 766         if (!mac)
 767                 return NULL;
 768
 769         mac->pcsr = ioaddr;
 770         mac->multicast_filter_bins = mcbins;
 771         mac->unicast_filter_entries = perfect_uc_entries;
 772         mac->mcast_bits_log2 = 0;
 773
 774         if (mac->multicast_filter_bins)
 775                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
 776
 777         mac->link.duplex = GMAC_CONFIG_DM;
 778         mac->link.speed10 = GMAC_CONFIG_PS;
 779         mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
 780         mac->link.speed1000 = 0;
 781         mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
 782         mac->mii.addr = GMAC_MDIO_ADDR;
 783         mac->mii.data = GMAC_MDIO_DATA;
 784         mac->mii.addr_shift = 21;
 785         mac->mii.addr_mask = GENMASK(25, 21);
 786         mac->mii.reg_shift = 16;
 787         mac->mii.reg_mask = GENMASK(20, 16);
 788         mac->mii.clk_csr_shift = 8;
 789         mac->mii.clk_csr_mask = GENMASK(11, 8);
 790
 791         /* Get and dump the chip ID */
 792         *synopsys_id = stmmac_get_synopsys_id(hwid);
 793
 794         if (*synopsys_id > DWMAC_CORE_4_00)
 795                 mac->dma = &dwmac410_dma_ops;
 796         else
 797                 mac->dma = &dwmac4_dma_ops;
 798
 799         if (*synopsys_id >= DWMAC_CORE_4_00)
 800                 mac->mac = &dwmac410_ops;
 801         else
 802                 mac->mac = &dwmac4_ops;
 803
 804         return mac;
 805 }