drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   4  * DWC Ether MAC version 4.00  has been used for developing this code.
   5  *
   6  * This only implements the mac core functions for this chip.
   7  *
   8  * Copyright (C) 2015  STMicroelectronics Ltd
   9  *
  10  * Author: Alexandre Torgue <alexandre.torgue@st.com>
  11  */
  12
  13 #include <linux/crc32.h>
  14 #include <linux/slab.h>
  15 #include <linux/ethtool.h>
  16 #include <linux/io.h>
  17 #include <net/dsa.h>
  18 #include "stmmac.h"
  19 #include "stmmac_pcs.h"
  20 #include "dwmac4.h"
  21 #include "dwmac5.h"
  22
  23 static void dwmac4_core_init(struct mac_device_info *hw,
  24                              struct net_device *dev)
  25 {
  26         void __iomem *ioaddr = hw->pcsr;
  27         u32 value = readl(ioaddr + GMAC_CONFIG);
  28
  29         value |= GMAC_CORE_INIT;
  30
  31         if (hw->ps) {
  32                 value |= GMAC_CONFIG_TE;
  33
  34                 value &= hw->link.speed_mask;
  35                 switch (hw->ps) {
  36                 case SPEED_1000:
  37                         value |= hw->link.speed1000;
  38                         break;
  39                 case SPEED_100:
  40                         value |= hw->link.speed100;
  41                         break;
  42                 case SPEED_10:
  43                         value |= hw->link.speed10;
  44                         break;
  45                 }
  46         }
  47
  48         writel(value, ioaddr + GMAC_CONFIG);
  49
  50         /* Enable GMAC interrupts */
  51         value = GMAC_INT_DEFAULT_ENABLE;
  52
  53         if (hw->pcs)
  54                 value |= GMAC_PCS_IRQ_DEFAULT;
  55
  56         writel(value, ioaddr + GMAC_INT_EN);
  57 }
  58
  59 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
  60                                    u8 mode, u32 queue)
  61 {
  62         void __iomem *ioaddr = hw->pcsr;
  63         u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
  64
  65         value &= GMAC_RX_QUEUE_CLEAR(queue);
  66         if (mode == MTL_QUEUE_AVB)
  67                 value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
  68         else if (mode == MTL_QUEUE_DCB)
  69                 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
  70
  71         writel(value, ioaddr + GMAC_RXQ_CTRL0);
  72 }
  73
  74 static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
  75                                      u32 prio, u32 queue)
  76 {
  77         void __iomem *ioaddr = hw->pcsr;
  78         u32 clear_mask = 0;
  79         u32 ctrl2, ctrl3;
  80         int i;
  81
  82         ctrl2 = readl(ioaddr + GMAC_RXQ_CTRL2);
  83         ctrl3 = readl(ioaddr + GMAC_RXQ_CTRL3);
  84
  85         /* The software must ensure that the same priority
  86          * is not mapped to multiple Rx queues
  87          */
  88         for (i = 0; i < 4; i++)
  89                 clear_mask |= ((prio << GMAC_RXQCTRL_PSRQX_SHIFT(i)) &
  90                                                 GMAC_RXQCTRL_PSRQX_MASK(i));
  91
  92         ctrl2 &= ~clear_mask;
  93         ctrl3 &= ~clear_mask;
  94
  95         /* First assign new priorities to a queue, then
  96          * clear them from others queues
  97          */
  98         if (queue < 4) {
  99                 ctrl2 |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
 100                                                 GMAC_RXQCTRL_PSRQX_MASK(queue);
 101
 102                 writel(ctrl2, ioaddr + GMAC_RXQ_CTRL2);
 103                 writel(ctrl3, ioaddr + GMAC_RXQ_CTRL3);
 104         } else {
 105                 queue -= 4;
 106
 107                 ctrl3 |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
 108                                                 GMAC_RXQCTRL_PSRQX_MASK(queue);
 109
 110                 writel(ctrl3, ioaddr + GMAC_RXQ_CTRL3);
 111                 writel(ctrl2, ioaddr + GMAC_RXQ_CTRL2);
 112         }
 113 }
 114
 115 static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
 116                                      u32 prio, u32 queue)
 117 {
 118         void __iomem *ioaddr = hw->pcsr;
 119         u32 base_register;
 120         u32 value;
 121
 122         base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
 123         if (queue >= 4)
 124                 queue -= 4;
 125
 126         value = readl(ioaddr + base_register);
 127
 128         value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
 129         value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
 130                                                 GMAC_TXQCTRL_PSTQX_MASK(queue);
 131
 132         writel(value, ioaddr + base_register);
 133 }
 134
 135 static void dwmac4_rx_queue_routing(struct mac_device_info *hw,
 136                                     u8 packet, u32 queue)
 137 {
 138         void __iomem *ioaddr = hw->pcsr;
 139         u32 value;
 140
 141         static const struct stmmac_rx_routing route_possibilities[] = {
 142                 { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
 143                 { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
 144                 { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
 145                 { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
 146                 { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
 147         };
 148
 149         value = readl(ioaddr + GMAC_RXQ_CTRL1);
 150
 151         /* routing configuration */
 152         value &= ~route_possibilities[packet - 1].reg_mask;
 153         value |= (queue << route_possibilities[packet-1].reg_shift) &
 154                  route_possibilities[packet - 1].reg_mask;
 155
 156         /* some packets require extra ops */
 157         if (packet == PACKET_AVCPQ) {
 158                 value &= ~GMAC_RXQCTRL_TACPQE;
 159                 value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
 160         } else if (packet == PACKET_MCBCQ) {
 161                 value &= ~GMAC_RXQCTRL_MCBCQEN;
 162                 value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
 163         }
 164
 165         writel(value, ioaddr + GMAC_RXQ_CTRL1);
 166 }
 167
 168 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
 169                                           u32 rx_alg)
 170 {
 171         void __iomem *ioaddr = hw->pcsr;
 172         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 173
 174         value &= ~MTL_OPERATION_RAA;
 175         switch (rx_alg) {
 176         case MTL_RX_ALGORITHM_SP:
 177                 value |= MTL_OPERATION_RAA_SP;
 178                 break;
 179         case MTL_RX_ALGORITHM_WSP:
 180                 value |= MTL_OPERATION_RAA_WSP;
 181                 break;
 182         default:
 183                 break;
 184         }
 185
 186         writel(value, ioaddr + MTL_OPERATION_MODE);
 187 }
 188
 189 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
 190                                           u32 tx_alg)
 191 {
 192         void __iomem *ioaddr = hw->pcsr;
 193         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 194
 195         value &= ~MTL_OPERATION_SCHALG_MASK;
 196         switch (tx_alg) {
 197         case MTL_TX_ALGORITHM_WRR:
 198                 value |= MTL_OPERATION_SCHALG_WRR;
 199                 break;
 200         case MTL_TX_ALGORITHM_WFQ:
 201                 value |= MTL_OPERATION_SCHALG_WFQ;
 202                 break;
 203         case MTL_TX_ALGORITHM_DWRR:
 204                 value |= MTL_OPERATION_SCHALG_DWRR;
 205                 break;
 206         case MTL_TX_ALGORITHM_SP:
 207                 value |= MTL_OPERATION_SCHALG_SP;
 208                 break;
 209         default:
 210                 break;
 211         }
 212
 213         writel(value, ioaddr + MTL_OPERATION_MODE);
 214 }
 215
 216 static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
 217                                            u32 weight, u32 queue)
 218 {
 219         void __iomem *ioaddr = hw->pcsr;
 220         u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 221
 222         value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
 223         value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
 224         writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 225 }
 226
 227 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
 228 {
 229         void __iomem *ioaddr = hw->pcsr;
 230         u32 value;
 231
 232         if (queue < 4)
 233                 value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
 234         else
 235                 value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
 236
 237         if (queue == 0 || queue == 4) {
 238                 value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
 239                 value |= MTL_RXQ_DMA_Q04MDMACH(chan);
 240         } else if (queue > 4) {
 241                 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue - 4);
 242                 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue - 4);
 243         } else {
 244                 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
 245                 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
 246         }
 247
 248         if (queue < 4)
 249                 writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
 250         else
 251                 writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
 252 }
 253
 254 static void dwmac4_config_cbs(struct mac_device_info *hw,
 255                               u32 send_slope, u32 idle_slope,
 256                               u32 high_credit, u32 low_credit, u32 queue)
 257 {
 258         void __iomem *ioaddr = hw->pcsr;
 259         u32 value;
 260
 261         pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
 262         pr_debug("\tsend_slope: 0x%08x\n", send_slope);
 263         pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
 264         pr_debug("\thigh_credit: 0x%08x\n", high_credit);
 265         pr_debug("\tlow_credit: 0x%08x\n", low_credit);
 266
 267         /* enable AV algorithm */
 268         value = readl(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
 269         value |= MTL_ETS_CTRL_AVALG;
 270         value |= MTL_ETS_CTRL_CC;
 271         writel(value, ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
 272
 273         /* configure send slope */
 274         value = readl(ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
 275         value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
 276         value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
 277         writel(value, ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
 278
 279         /* configure idle slope (same register as tx weight) */
 280         dwmac4_set_mtl_tx_queue_weight(hw, idle_slope, queue);
 281
 282         /* configure high credit */
 283         value = readl(ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
 284         value &= ~MTL_HIGH_CRED_HC_MASK;
 285         value |= high_credit & MTL_HIGH_CRED_HC_MASK;
 286         writel(value, ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
 287
 288         /* configure high credit */
 289         value = readl(ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
 290         value &= ~MTL_HIGH_CRED_LC_MASK;
 291         value |= low_credit & MTL_HIGH_CRED_LC_MASK;
 292         writel(value, ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
 293 }
 294
 295 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
 296 {
 297         void __iomem *ioaddr = hw->pcsr;
 298         int i;
 299
 300         for (i = 0; i < GMAC_REG_NUM; i++)
 301                 reg_space[i] = readl(ioaddr + i * 4);
 302 }
 303
 304 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
 305 {
 306         void __iomem *ioaddr = hw->pcsr;
 307         u32 value = readl(ioaddr + GMAC_CONFIG);
 308
 309         if (hw->rx_csum)
 310                 value |= GMAC_CONFIG_IPC;
 311         else
 312                 value &= ~GMAC_CONFIG_IPC;
 313
 314         writel(value, ioaddr + GMAC_CONFIG);
 315
 316         value = readl(ioaddr + GMAC_CONFIG);
 317
 318         return !!(value & GMAC_CONFIG_IPC);
 319 }
 320
 321 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
 322 {
 323         void __iomem *ioaddr = hw->pcsr;
 324         unsigned int pmt = 0;
 325         u32 config;
 326
 327         if (mode & WAKE_MAGIC) {
 328                 pr_debug("GMAC: WOL Magic frame\n");
 329                 pmt |= power_down | magic_pkt_en;
 330         }
 331         if (mode & WAKE_UCAST) {
 332                 pr_debug("GMAC: WOL on global unicast\n");
 333                 pmt |= power_down | global_unicast | wake_up_frame_en;
 334         }
 335
 336         if (pmt) {
 337                 /* The receiver must be enabled for WOL before powering down */
 338                 config = readl(ioaddr + GMAC_CONFIG);
 339                 config |= GMAC_CONFIG_RE;
 340                 writel(config, ioaddr + GMAC_CONFIG);
 341         }
 342         writel(pmt, ioaddr + GMAC_PMT);
 343 }
 344
 345 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
 346                                  unsigned char *addr, unsigned int reg_n)
 347 {
 348         void __iomem *ioaddr = hw->pcsr;
 349
 350         stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 351                                    GMAC_ADDR_LOW(reg_n));
 352 }
 353
 354 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
 355                                  unsigned char *addr, unsigned int reg_n)
 356 {
 357         void __iomem *ioaddr = hw->pcsr;
 358
 359         stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 360                                    GMAC_ADDR_LOW(reg_n));
 361 }
 362
 363 static void dwmac4_set_eee_mode(struct mac_device_info *hw,
 364                                 bool en_tx_lpi_clockgating)
 365 {
 366         void __iomem *ioaddr = hw->pcsr;
 367         u32 value;
 368
 369         /* Enable the link status receive on RGMII, SGMII ore SMII
 370          * receive path and instruct the transmit to enter in LPI
 371          * state.
 372          */
 373         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 374         value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
 375
 376         if (en_tx_lpi_clockgating)
 377                 value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
 378
 379         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 380 }
 381
 382 static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
 383 {
 384         void __iomem *ioaddr = hw->pcsr;
 385         u32 value;
 386
 387         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 388         value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
 389         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 390 }
 391
 392 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
 393 {
 394         void __iomem *ioaddr = hw->pcsr;
 395         u32 value;
 396
 397         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 398
 399         if (link)
 400                 value |= GMAC4_LPI_CTRL_STATUS_PLS;
 401         else
 402                 value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
 403
 404         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 405 }
 406
 407 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
 408 {
 409         void __iomem *ioaddr = hw->pcsr;
 410         int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
 411
 412         /* Program the timers in the LPI timer control register:
 413          * LS: minimum time (ms) for which the link
 414          *  status from PHY should be ok before transmitting
 415          *  the LPI pattern.
 416          * TW: minimum time (us) for which the core waits
 417          *  after it has stopped transmitting the LPI pattern.
 418          */
 419         writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
 420 }
 421
 422 static void dwmac4_write_single_vlan(struct net_device *dev, u16 vid)
 423 {
 424         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 425         u32 val;
 426
 427         val = readl(ioaddr + GMAC_VLAN_TAG);
 428         val &= ~GMAC_VLAN_TAG_VID;
 429         val |= GMAC_VLAN_TAG_ETV | vid;
 430
 431         writel(val, ioaddr + GMAC_VLAN_TAG);
 432 }
 433
 434 static int dwmac4_write_vlan_filter(struct net_device *dev,
 435                                     struct mac_device_info *hw,
 436                                     u8 index, u32 data)
 437 {
 438         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 439         int i, timeout = 10;
 440         u32 val;
 441
 442         if (index >= hw->num_vlan)
 443                 return -EINVAL;
 444
 445         writel(data, ioaddr + GMAC_VLAN_TAG_DATA);
 446
 447         val = readl(ioaddr + GMAC_VLAN_TAG);
 448         val &= ~(GMAC_VLAN_TAG_CTRL_OFS_MASK |
 449                 GMAC_VLAN_TAG_CTRL_CT |
 450                 GMAC_VLAN_TAG_CTRL_OB);
 451         val |= (index << GMAC_VLAN_TAG_CTRL_OFS_SHIFT) | GMAC_VLAN_TAG_CTRL_OB;
 452
 453         writel(val, ioaddr + GMAC_VLAN_TAG);
 454
 455         for (i = 0; i < timeout; i++) {
 456                 val = readl(ioaddr + GMAC_VLAN_TAG);
 457                 if (!(val & GMAC_VLAN_TAG_CTRL_OB))
 458                         return 0;
 459                 udelay(1);
 460         }
 461
 462         netdev_err(dev, "Timeout accessing MAC_VLAN_Tag_Filter\n");
 463
 464         return -EBUSY;
 465 }
 466
 467 static int dwmac4_add_hw_vlan_rx_fltr(struct net_device *dev,
 468                                       struct mac_device_info *hw,
 469                                       __be16 proto, u16 vid)
 470 {
 471         int index = -1;
 472         u32 val = 0;
 473         int i, ret;
 474
 475         if (vid > 4095)
 476                 return -EINVAL;
 477
 478         /* Single Rx VLAN Filter */
 479         if (hw->num_vlan == 1) {
 480                 /* For single VLAN filter, VID 0 means VLAN promiscuous */
 481                 if (vid == 0) {
 482                         netdev_warn(dev, "Adding VLAN ID 0 is not supported\n");
 483                         return -EPERM;
 484                 }
 485
 486                 if (hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) {
 487                         netdev_err(dev, "Only single VLAN ID supported\n");
 488                         return -EPERM;
 489                 }
 490
 491                 hw->vlan_filter[0] = vid;
 492                 dwmac4_write_single_vlan(dev, vid);
 493
 494                 return 0;
 495         }
 496
 497         /* Extended Rx VLAN Filter Enable */
 498         val |= GMAC_VLAN_TAG_DATA_ETV | GMAC_VLAN_TAG_DATA_VEN | vid;
 499
 500         for (i = 0; i < hw->num_vlan; i++) {
 501                 if (hw->vlan_filter[i] == val)
 502                         return 0;
 503                 else if (!(hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN))
 504                         index = i;
 505         }
 506
 507         if (index == -1) {
 508                 netdev_err(dev, "MAC_VLAN_Tag_Filter full (size: %0u)\n",
 509                            hw->num_vlan);
 510                 return -EPERM;
 511         }
 512
 513         ret = dwmac4_write_vlan_filter(dev, hw, index, val);
 514
 515         if (!ret)
 516                 hw->vlan_filter[index] = val;
 517
 518         return ret;
 519 }
 520
 521 static int dwmac4_del_hw_vlan_rx_fltr(struct net_device *dev,
 522                                       struct mac_device_info *hw,
 523                                       __be16 proto, u16 vid)
 524 {
 525         int i, ret = 0;
 526
 527         /* Single Rx VLAN Filter */
 528         if (hw->num_vlan == 1) {
 529                 if ((hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) == vid) {
 530                         hw->vlan_filter[0] = 0;
 531                         dwmac4_write_single_vlan(dev, 0);
 532                 }
 533                 return 0;
 534         }
 535
 536         /* Extended Rx VLAN Filter Enable */
 537         for (i = 0; i < hw->num_vlan; i++) {
 538                 if ((hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VID) == vid) {
 539                         ret = dwmac4_write_vlan_filter(dev, hw, i, 0);
 540
 541                         if (!ret)
 542                                 hw->vlan_filter[i] = 0;
 543                         else
 544                                 return ret;
 545                 }
 546         }
 547
 548         return ret;
 549 }
 550
 551 static void dwmac4_restore_hw_vlan_rx_fltr(struct net_device *dev,
 552                                            struct mac_device_info *hw)
 553 {
 554         void __iomem *ioaddr = hw->pcsr;
 555         u32 value;
 556         u32 hash;
 557         u32 val;
 558         int i;
 559
 560         /* Single Rx VLAN Filter */
 561         if (hw->num_vlan == 1) {
 562                 dwmac4_write_single_vlan(dev, hw->vlan_filter[0]);
 563                 return;
 564         }
 565
 566         /* Extended Rx VLAN Filter Enable */
 567         for (i = 0; i < hw->num_vlan; i++) {
 568                 if (hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN) {
 569                         val = hw->vlan_filter[i];
 570                         dwmac4_write_vlan_filter(dev, hw, i, val);
 571                 }
 572         }
 573
 574         hash = readl(ioaddr + GMAC_VLAN_HASH_TABLE);
 575         if (hash & GMAC_VLAN_VLHT) {
 576                 value = readl(ioaddr + GMAC_VLAN_TAG);
 577                 value |= GMAC_VLAN_VTHM;
 578                 writel(value, ioaddr + GMAC_VLAN_TAG);
 579         }
 580 }
 581
 582 static void dwmac4_set_filter(struct mac_device_info *hw,
 583                               struct net_device *dev)
 584 {
 585         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 586         int numhashregs = (hw->multicast_filter_bins >> 5);
 587         int mcbitslog2 = hw->mcast_bits_log2;
 588         unsigned int value;
 589         u32 mc_filter[8];
 590         int i;
 591
 592         memset(mc_filter, 0, sizeof(mc_filter));
 593
 594         value = readl(ioaddr + GMAC_PACKET_FILTER);
 595         value &= ~GMAC_PACKET_FILTER_HMC;
 596         value &= ~GMAC_PACKET_FILTER_HPF;
 597         value &= ~GMAC_PACKET_FILTER_PCF;
 598         value &= ~GMAC_PACKET_FILTER_PM;
 599         value &= ~GMAC_PACKET_FILTER_PR;
 600         value &= ~GMAC_PACKET_FILTER_RA;
 601         if (dev->flags & IFF_PROMISC) {
 602                 /* VLAN Tag Filter Fail Packets Queuing */
 603                 if (hw->vlan_fail_q_en) {
 604                         value = readl(ioaddr + GMAC_RXQ_CTRL4);
 605                         value &= ~GMAC_RXQCTRL_VFFQ_MASK;
 606                         value |= GMAC_RXQCTRL_VFFQE |
 607                                  (hw->vlan_fail_q << GMAC_RXQCTRL_VFFQ_SHIFT);
 608                         writel(value, ioaddr + GMAC_RXQ_CTRL4);
 609                         value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_RA;
 610                 } else {
 611                         value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_PCF;
 612                 }
 613
 614         } else if ((dev->flags & IFF_ALLMULTI) ||
 615                    (netdev_mc_count(dev) > hw->multicast_filter_bins)) {
 616                 /* Pass all multi */
 617                 value |= GMAC_PACKET_FILTER_PM;
 618                 /* Set all the bits of the HASH tab */
 619                 memset(mc_filter, 0xff, sizeof(mc_filter));
 620         } else if (!netdev_mc_empty(dev) && (dev->flags & IFF_MULTICAST)) {
 621                 struct netdev_hw_addr *ha;
 622
 623                 /* Hash filter for multicast */
 624                 value |= GMAC_PACKET_FILTER_HMC;
 625
 626                 netdev_for_each_mc_addr(ha, dev) {
 627                         /* The upper n bits of the calculated CRC are used to
 628                          * index the contents of the hash table. The number of
 629                          * bits used depends on the hardware configuration
 630                          * selected at core configuration time.
 631                          */
 632                         u32 bit_nr = bitrev32(~crc32_le(~0, ha->addr,
 633                                         ETH_ALEN)) >> (32 - mcbitslog2);
 634                         /* The most significant bit determines the register to
 635                          * use (H/L) while the other 5 bits determine the bit
 636                          * within the register.
 637                          */
 638                         mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1f));
 639                 }
 640         }
 641
 642         for (i = 0; i < numhashregs; i++)
 643                 writel(mc_filter[i], ioaddr + GMAC_HASH_TAB(i));
 644
 645         value |= GMAC_PACKET_FILTER_HPF;
 646
 647         /* Handle multiple unicast addresses */
 648         if (netdev_uc_count(dev) > hw->unicast_filter_entries) {
 649                 /* Switch to promiscuous mode if more than 128 addrs
 650                  * are required
 651                  */
 652                 value |= GMAC_PACKET_FILTER_PR;
 653         } else {
 654                 struct netdev_hw_addr *ha;
 655                 int reg = 1;
 656
 657                 netdev_for_each_uc_addr(ha, dev) {
 658                         dwmac4_set_umac_addr(hw, ha->addr, reg);
 659                         reg++;
 660                 }
 661
 662                 while (reg < GMAC_MAX_PERFECT_ADDRESSES) {
 663                         writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
 664                         writel(0, ioaddr + GMAC_ADDR_LOW(reg));
 665                         reg++;
 666                 }
 667         }
 668
 669         /* VLAN filtering */
 670         if (dev->flags & IFF_PROMISC && !hw->vlan_fail_q_en)
 671                 value &= ~GMAC_PACKET_FILTER_VTFE;
 672         else if (dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
 673                 value |= GMAC_PACKET_FILTER_VTFE;
 674
 675         writel(value, ioaddr + GMAC_PACKET_FILTER);
 676 }
 677
 678 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 679                              unsigned int fc, unsigned int pause_time,
 680                              u32 tx_cnt)
 681 {
 682         void __iomem *ioaddr = hw->pcsr;
 683         unsigned int flow = 0;
 684         u32 queue = 0;
 685
 686         pr_debug("GMAC Flow-Control:\n");
 687         if (fc & FLOW_RX) {
 688                 pr_debug("\tReceive Flow-Control ON\n");
 689                 flow |= GMAC_RX_FLOW_CTRL_RFE;
 690         } else {
 691                 pr_debug("\tReceive Flow-Control OFF\n");
 692         }
 693         writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
 694
 695         if (fc & FLOW_TX) {
 696                 pr_debug("\tTransmit Flow-Control ON\n");
 697
 698                 if (duplex)
 699                         pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
 700
 701                 for (queue = 0; queue < tx_cnt; queue++) {
 702                         flow = GMAC_TX_FLOW_CTRL_TFE;
 703
 704                         if (duplex)
 705                                 flow |=
 706                                 (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
 707
 708                         writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
 709                 }
 710         } else {
 711                 for (queue = 0; queue < tx_cnt; queue++)
 712                         writel(0, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
 713         }
 714 }
 715
 716 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 717                             bool loopback)
 718 {
 719         dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
 720 }
 721
 722 static void dwmac4_rane(void __iomem *ioaddr, bool restart)
 723 {
 724         dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
 725 }
 726
 727 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
 728 {
 729         dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
 730 }
 731
 732 /* RGMII or SMII interface */
 733 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 734 {
 735         u32 status;
 736
 737         status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
 738         x->irq_rgmii_n++;
 739
 740         /* Check the link status */
 741         if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
 742                 int speed_value;
 743
 744                 x->pcs_link = 1;
 745
 746                 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
 747                                GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
 748                 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
 749                         x->pcs_speed = SPEED_1000;
 750                 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
 751                         x->pcs_speed = SPEED_100;
 752                 else
 753                         x->pcs_speed = SPEED_10;
 754
 755                 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
 756
 757                 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
 758                         x->pcs_duplex ? "Full" : "Half");
 759         } else {
 760                 x->pcs_link = 0;
 761                 pr_info("Link is Down\n");
 762         }
 763 }
 764
 765 static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
 766 {
 767         void __iomem *ioaddr = hw->pcsr;
 768         u32 mtl_int_qx_status;
 769         int ret = 0;
 770
 771         mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
 772
 773         /* Check MTL Interrupt */
 774         if (mtl_int_qx_status & MTL_INT_QX(chan)) {
 775                 /* read Queue x Interrupt status */
 776                 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
 777
 778                 if (status & MTL_RX_OVERFLOW_INT) {
 779                         /*  clear Interrupt */
 780                         writel(status | MTL_RX_OVERFLOW_INT,
 781                                ioaddr + MTL_CHAN_INT_CTRL(chan));
 782                         ret = CORE_IRQ_MTL_RX_OVERFLOW;
 783                 }
 784         }
 785
 786         return ret;
 787 }
 788
 789 static int dwmac4_irq_status(struct mac_device_info *hw,
 790                              struct stmmac_extra_stats *x)
 791 {
 792         void __iomem *ioaddr = hw->pcsr;
 793         u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
 794         u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
 795         int ret = 0;
 796
 797         /* Discard disabled bits */
 798         intr_status &= intr_enable;
 799
 800         /* Not used events (e.g. MMC interrupts) are not handled. */
 801         if ((intr_status & mmc_tx_irq))
 802                 x->mmc_tx_irq_n++;
 803         if (unlikely(intr_status & mmc_rx_irq))
 804                 x->mmc_rx_irq_n++;
 805         if (unlikely(intr_status & mmc_rx_csum_offload_irq))
 806                 x->mmc_rx_csum_offload_irq_n++;
 807         /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
 808         if (unlikely(intr_status & pmt_irq)) {
 809                 readl(ioaddr + GMAC_PMT);
 810                 x->irq_receive_pmt_irq_n++;
 811         }
 812
 813         /* MAC tx/rx EEE LPI entry/exit interrupts */
 814         if (intr_status & lpi_irq) {
 815                 /* Clear LPI interrupt by reading MAC_LPI_Control_Status */
 816                 u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 817
 818                 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
 819                         ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
 820                         x->irq_tx_path_in_lpi_mode_n++;
 821                 }
 822                 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
 823                         ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
 824                         x->irq_tx_path_exit_lpi_mode_n++;
 825                 }
 826                 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
 827                         x->irq_rx_path_in_lpi_mode_n++;
 828                 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
 829                         x->irq_rx_path_exit_lpi_mode_n++;
 830         }
 831
 832         dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
 833         if (intr_status & PCS_RGSMIIIS_IRQ)
 834                 dwmac4_phystatus(ioaddr, x);
 835
 836         return ret;
 837 }
 838
 839 static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
 840                          u32 rx_queues, u32 tx_queues)
 841 {
 842         u32 value;
 843         u32 queue;
 844
 845         for (queue = 0; queue < tx_queues; queue++) {
 846                 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(queue));
 847
 848                 if (value & MTL_DEBUG_TXSTSFSTS)
 849                         x->mtl_tx_status_fifo_full++;
 850                 if (value & MTL_DEBUG_TXFSTS)
 851                         x->mtl_tx_fifo_not_empty++;
 852                 if (value & MTL_DEBUG_TWCSTS)
 853                         x->mmtl_fifo_ctrl++;
 854                 if (value & MTL_DEBUG_TRCSTS_MASK) {
 855                         u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
 856                                      >> MTL_DEBUG_TRCSTS_SHIFT;
 857                         if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
 858                                 x->mtl_tx_fifo_read_ctrl_write++;
 859                         else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
 860                                 x->mtl_tx_fifo_read_ctrl_wait++;
 861                         else if (trcsts == MTL_DEBUG_TRCSTS_READ)
 862                                 x->mtl_tx_fifo_read_ctrl_read++;
 863                         else
 864                                 x->mtl_tx_fifo_read_ctrl_idle++;
 865                 }
 866                 if (value & MTL_DEBUG_TXPAUSED)
 867                         x->mac_tx_in_pause++;
 868         }
 869
 870         for (queue = 0; queue < rx_queues; queue++) {
 871                 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(queue));
 872
 873                 if (value & MTL_DEBUG_RXFSTS_MASK) {
 874                         u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
 875                                      >> MTL_DEBUG_RRCSTS_SHIFT;
 876
 877                         if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
 878                                 x->mtl_rx_fifo_fill_level_full++;
 879                         else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
 880                                 x->mtl_rx_fifo_fill_above_thresh++;
 881                         else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
 882                                 x->mtl_rx_fifo_fill_below_thresh++;
 883                         else
 884                                 x->mtl_rx_fifo_fill_level_empty++;
 885                 }
 886                 if (value & MTL_DEBUG_RRCSTS_MASK) {
 887                         u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
 888                                      MTL_DEBUG_RRCSTS_SHIFT;
 889
 890                         if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
 891                                 x->mtl_rx_fifo_read_ctrl_flush++;
 892                         else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
 893                                 x->mtl_rx_fifo_read_ctrl_read_data++;
 894                         else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
 895                                 x->mtl_rx_fifo_read_ctrl_status++;
 896                         else
 897                                 x->mtl_rx_fifo_read_ctrl_idle++;
 898                 }
 899                 if (value & MTL_DEBUG_RWCSTS)
 900                         x->mtl_rx_fifo_ctrl_active++;
 901         }
 902
 903         /* GMAC debug */
 904         value = readl(ioaddr + GMAC_DEBUG);
 905
 906         if (value & GMAC_DEBUG_TFCSTS_MASK) {
 907                 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
 908                               >> GMAC_DEBUG_TFCSTS_SHIFT;
 909
 910                 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
 911                         x->mac_tx_frame_ctrl_xfer++;
 912                 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
 913                         x->mac_tx_frame_ctrl_pause++;
 914                 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
 915                         x->mac_tx_frame_ctrl_wait++;
 916                 else
 917                         x->mac_tx_frame_ctrl_idle++;
 918         }
 919         if (value & GMAC_DEBUG_TPESTS)
 920                 x->mac_gmii_tx_proto_engine++;
 921         if (value & GMAC_DEBUG_RFCFCSTS_MASK)
 922                 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
 923                                             >> GMAC_DEBUG_RFCFCSTS_SHIFT;
 924         if (value & GMAC_DEBUG_RPESTS)
 925                 x->mac_gmii_rx_proto_engine++;
 926 }
 927
 928 static void dwmac4_set_mac_loopback(void __iomem *ioaddr, bool enable)
 929 {
 930         u32 value = readl(ioaddr + GMAC_CONFIG);
 931
 932         if (enable)
 933                 value |= GMAC_CONFIG_LM;
 934         else
 935                 value &= ~GMAC_CONFIG_LM;
 936
 937         writel(value, ioaddr + GMAC_CONFIG);
 938 }
 939
 940 static void dwmac4_update_vlan_hash(struct mac_device_info *hw, u32 hash,
 941                                     __le16 perfect_match, bool is_double)
 942 {
 943         void __iomem *ioaddr = hw->pcsr;
 944         u32 value;
 945
 946         writel(hash, ioaddr + GMAC_VLAN_HASH_TABLE);
 947
 948         value = readl(ioaddr + GMAC_VLAN_TAG);
 949
 950         if (hash) {
 951                 value |= GMAC_VLAN_VTHM | GMAC_VLAN_ETV;
 952                 if (is_double) {
 953                         value |= GMAC_VLAN_EDVLP;
 954                         value |= GMAC_VLAN_ESVL;
 955                         value |= GMAC_VLAN_DOVLTC;
 956                 }
 957
 958                 writel(value, ioaddr + GMAC_VLAN_TAG);
 959         } else if (perfect_match) {
 960                 u32 value = GMAC_VLAN_ETV;
 961
 962                 if (is_double) {
 963                         value |= GMAC_VLAN_EDVLP;
 964                         value |= GMAC_VLAN_ESVL;
 965                         value |= GMAC_VLAN_DOVLTC;
 966                 }
 967
 968                 writel(value | perfect_match, ioaddr + GMAC_VLAN_TAG);
 969         } else {
 970                 value &= ~(GMAC_VLAN_VTHM | GMAC_VLAN_ETV);
 971                 value &= ~(GMAC_VLAN_EDVLP | GMAC_VLAN_ESVL);
 972                 value &= ~GMAC_VLAN_DOVLTC;
 973                 value &= ~GMAC_VLAN_VID;
 974
 975                 writel(value, ioaddr + GMAC_VLAN_TAG);
 976         }
 977 }
 978
 979 static void dwmac4_sarc_configure(void __iomem *ioaddr, int val)
 980 {
 981         u32 value = readl(ioaddr + GMAC_CONFIG);
 982
 983         value &= ~GMAC_CONFIG_SARC;
 984         value |= val << GMAC_CONFIG_SARC_SHIFT;
 985
 986         writel(value, ioaddr + GMAC_CONFIG);
 987 }
 988
 989 static void dwmac4_enable_vlan(struct mac_device_info *hw, u32 type)
 990 {
 991         void __iomem *ioaddr = hw->pcsr;
 992         u32 value;
 993
 994         value = readl(ioaddr + GMAC_VLAN_INCL);
 995         value |= GMAC_VLAN_VLTI;
 996         value |= GMAC_VLAN_CSVL; /* Only use SVLAN */
 997         value &= ~GMAC_VLAN_VLC;
 998         value |= (type << GMAC_VLAN_VLC_SHIFT) & GMAC_VLAN_VLC;
 999         writel(value, ioaddr + GMAC_VLAN_INCL);
1000 }
1001
1002 static void dwmac4_set_arp_offload(struct mac_device_info *hw, bool en,
1003                                    u32 addr)
1004 {
1005         void __iomem *ioaddr = hw->pcsr;
1006         u32 value;
1007
1008         writel(addr, ioaddr + GMAC_ARP_ADDR);
1009
1010         value = readl(ioaddr + GMAC_CONFIG);
1011         if (en)
1012                 value |= GMAC_CONFIG_ARPEN;
1013         else
1014                 value &= ~GMAC_CONFIG_ARPEN;
1015         writel(value, ioaddr + GMAC_CONFIG);
1016 }
1017
1018 static int dwmac4_config_l3_filter(struct mac_device_info *hw, u32 filter_no,
1019                                    bool en, bool ipv6, bool sa, bool inv,
1020                                    u32 match)
1021 {
1022         void __iomem *ioaddr = hw->pcsr;
1023         u32 value;
1024
1025         value = readl(ioaddr + GMAC_PACKET_FILTER);
1026         value |= GMAC_PACKET_FILTER_IPFE;
1027         writel(value, ioaddr + GMAC_PACKET_FILTER);
1028
1029         value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
1030
1031         /* For IPv6 not both SA/DA filters can be active */
1032         if (ipv6) {
1033                 value |= GMAC_L3PEN0;
1034                 value &= ~(GMAC_L3SAM0 | GMAC_L3SAIM0);
1035                 value &= ~(GMAC_L3DAM0 | GMAC_L3DAIM0);
1036                 if (sa) {
1037                         value |= GMAC_L3SAM0;
1038                         if (inv)
1039                                 value |= GMAC_L3SAIM0;
1040                 } else {
1041                         value |= GMAC_L3DAM0;
1042                         if (inv)
1043                                 value |= GMAC_L3DAIM0;
1044                 }
1045         } else {
1046                 value &= ~GMAC_L3PEN0;
1047                 if (sa) {
1048                         value |= GMAC_L3SAM0;
1049                         if (inv)
1050                                 value |= GMAC_L3SAIM0;
1051                 } else {
1052                         value |= GMAC_L3DAM0;
1053                         if (inv)
1054                                 value |= GMAC_L3DAIM0;
1055                 }
1056         }
1057
1058         writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
1059
1060         if (sa) {
1061                 writel(match, ioaddr + GMAC_L3_ADDR0(filter_no));
1062         } else {
1063                 writel(match, ioaddr + GMAC_L3_ADDR1(filter_no));
1064         }
1065
1066         if (!en)
1067                 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
1068
1069         return 0;
1070 }
1071
1072 static int dwmac4_config_l4_filter(struct mac_device_info *hw, u32 filter_no,
1073                                    bool en, bool udp, bool sa, bool inv,
1074                                    u32 match)
1075 {
1076         void __iomem *ioaddr = hw->pcsr;
1077         u32 value;
1078
1079         value = readl(ioaddr + GMAC_PACKET_FILTER);
1080         value |= GMAC_PACKET_FILTER_IPFE;
1081         writel(value, ioaddr + GMAC_PACKET_FILTER);
1082
1083         value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
1084         if (udp) {
1085                 value |= GMAC_L4PEN0;
1086         } else {
1087                 value &= ~GMAC_L4PEN0;
1088         }
1089
1090         value &= ~(GMAC_L4SPM0 | GMAC_L4SPIM0);
1091         value &= ~(GMAC_L4DPM0 | GMAC_L4DPIM0);
1092         if (sa) {
1093                 value |= GMAC_L4SPM0;
1094                 if (inv)
1095                         value |= GMAC_L4SPIM0;
1096         } else {
1097                 value |= GMAC_L4DPM0;
1098                 if (inv)
1099                         value |= GMAC_L4DPIM0;
1100         }
1101
1102         writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
1103
1104         if (sa) {
1105                 value = match & GMAC_L4SP0;
1106         } else {
1107                 value = (match << GMAC_L4DP0_SHIFT) & GMAC_L4DP0;
1108         }
1109
1110         writel(value, ioaddr + GMAC_L4_ADDR(filter_no));
1111
1112         if (!en)
1113                 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
1114
1115         return 0;
1116 }
1117
1118 const struct stmmac_ops dwmac4_ops = {
1119         .core_init = dwmac4_core_init,
1120         .set_mac = stmmac_set_mac,
1121         .rx_ipc = dwmac4_rx_ipc_enable,
1122         .rx_queue_enable = dwmac4_rx_queue_enable,
1123         .rx_queue_prio = dwmac4_rx_queue_priority,
1124         .tx_queue_prio = dwmac4_tx_queue_priority,
1125         .rx_queue_routing = dwmac4_rx_queue_routing,
1126         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1127         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1128         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1129         .map_mtl_to_dma = dwmac4_map_mtl_dma,
1130         .config_cbs = dwmac4_config_cbs,
1131         .dump_regs = dwmac4_dump_regs,
1132         .host_irq_status = dwmac4_irq_status,
1133         .host_mtl_irq_status = dwmac4_irq_mtl_status,
1134         .flow_ctrl = dwmac4_flow_ctrl,
1135         .pmt = dwmac4_pmt,
1136         .set_umac_addr = dwmac4_set_umac_addr,
1137         .get_umac_addr = dwmac4_get_umac_addr,
1138         .set_eee_mode = dwmac4_set_eee_mode,
1139         .reset_eee_mode = dwmac4_reset_eee_mode,
1140         .set_eee_timer = dwmac4_set_eee_timer,
1141         .set_eee_pls = dwmac4_set_eee_pls,
1142         .pcs_ctrl_ane = dwmac4_ctrl_ane,
1143         .pcs_rane = dwmac4_rane,
1144         .pcs_get_adv_lp = dwmac4_get_adv_lp,
1145         .debug = dwmac4_debug,
1146         .set_filter = dwmac4_set_filter,
1147         .set_mac_loopback = dwmac4_set_mac_loopback,
1148         .update_vlan_hash = dwmac4_update_vlan_hash,
1149         .sarc_configure = dwmac4_sarc_configure,
1150         .enable_vlan = dwmac4_enable_vlan,
1151         .set_arp_offload = dwmac4_set_arp_offload,
1152         .config_l3_filter = dwmac4_config_l3_filter,
1153         .config_l4_filter = dwmac4_config_l4_filter,
1154         .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1155         .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1156         .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1157 };
1158
1159 const struct stmmac_ops dwmac410_ops = {
1160         .core_init = dwmac4_core_init,
1161         .set_mac = stmmac_dwmac4_set_mac,
1162         .rx_ipc = dwmac4_rx_ipc_enable,
1163         .rx_queue_enable = dwmac4_rx_queue_enable,
1164         .rx_queue_prio = dwmac4_rx_queue_priority,
1165         .tx_queue_prio = dwmac4_tx_queue_priority,
1166         .rx_queue_routing = dwmac4_rx_queue_routing,
1167         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1168         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1169         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1170         .map_mtl_to_dma = dwmac4_map_mtl_dma,
1171         .config_cbs = dwmac4_config_cbs,
1172         .dump_regs = dwmac4_dump_regs,
1173         .host_irq_status = dwmac4_irq_status,
1174         .host_mtl_irq_status = dwmac4_irq_mtl_status,
1175         .flow_ctrl = dwmac4_flow_ctrl,
1176         .pmt = dwmac4_pmt,
1177         .set_umac_addr = dwmac4_set_umac_addr,
1178         .get_umac_addr = dwmac4_get_umac_addr,
1179         .set_eee_mode = dwmac4_set_eee_mode,
1180         .reset_eee_mode = dwmac4_reset_eee_mode,
1181         .set_eee_timer = dwmac4_set_eee_timer,
1182         .set_eee_pls = dwmac4_set_eee_pls,
1183         .pcs_ctrl_ane = dwmac4_ctrl_ane,
1184         .pcs_rane = dwmac4_rane,
1185         .pcs_get_adv_lp = dwmac4_get_adv_lp,
1186         .debug = dwmac4_debug,
1187         .set_filter = dwmac4_set_filter,
1188         .flex_pps_config = dwmac5_flex_pps_config,
1189         .set_mac_loopback = dwmac4_set_mac_loopback,
1190         .update_vlan_hash = dwmac4_update_vlan_hash,
1191         .sarc_configure = dwmac4_sarc_configure,
1192         .enable_vlan = dwmac4_enable_vlan,
1193         .set_arp_offload = dwmac4_set_arp_offload,
1194         .config_l3_filter = dwmac4_config_l3_filter,
1195         .config_l4_filter = dwmac4_config_l4_filter,
1196         .est_configure = dwmac5_est_configure,
1197         .fpe_configure = dwmac5_fpe_configure,
1198         .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1199         .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1200         .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1201 };
1202
1203 const struct stmmac_ops dwmac510_ops = {
1204         .core_init = dwmac4_core_init,
1205         .set_mac = stmmac_dwmac4_set_mac,
1206         .rx_ipc = dwmac4_rx_ipc_enable,
1207         .rx_queue_enable = dwmac4_rx_queue_enable,
1208         .rx_queue_prio = dwmac4_rx_queue_priority,
1209         .tx_queue_prio = dwmac4_tx_queue_priority,
1210         .rx_queue_routing = dwmac4_rx_queue_routing,
1211         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1212         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1213         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1214         .map_mtl_to_dma = dwmac4_map_mtl_dma,
1215         .config_cbs = dwmac4_config_cbs,
1216         .dump_regs = dwmac4_dump_regs,
1217         .host_irq_status = dwmac4_irq_status,
1218         .host_mtl_irq_status = dwmac4_irq_mtl_status,
1219         .flow_ctrl = dwmac4_flow_ctrl,
1220         .pmt = dwmac4_pmt,
1221         .set_umac_addr = dwmac4_set_umac_addr,
1222         .get_umac_addr = dwmac4_get_umac_addr,
1223         .set_eee_mode = dwmac4_set_eee_mode,
1224         .reset_eee_mode = dwmac4_reset_eee_mode,
1225         .set_eee_timer = dwmac4_set_eee_timer,
1226         .set_eee_pls = dwmac4_set_eee_pls,
1227         .pcs_ctrl_ane = dwmac4_ctrl_ane,
1228         .pcs_rane = dwmac4_rane,
1229         .pcs_get_adv_lp = dwmac4_get_adv_lp,
1230         .debug = dwmac4_debug,
1231         .set_filter = dwmac4_set_filter,
1232         .safety_feat_config = dwmac5_safety_feat_config,
1233         .safety_feat_irq_status = dwmac5_safety_feat_irq_status,
1234         .safety_feat_dump = dwmac5_safety_feat_dump,
1235         .rxp_config = dwmac5_rxp_config,
1236         .flex_pps_config = dwmac5_flex_pps_config,
1237         .set_mac_loopback = dwmac4_set_mac_loopback,
1238         .update_vlan_hash = dwmac4_update_vlan_hash,
1239         .sarc_configure = dwmac4_sarc_configure,
1240         .enable_vlan = dwmac4_enable_vlan,
1241         .set_arp_offload = dwmac4_set_arp_offload,
1242         .config_l3_filter = dwmac4_config_l3_filter,
1243         .config_l4_filter = dwmac4_config_l4_filter,
1244         .est_configure = dwmac5_est_configure,
1245         .fpe_configure = dwmac5_fpe_configure,
1246         .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1247         .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1248         .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1249 };
1250
1251 static u32 dwmac4_get_num_vlan(void __iomem *ioaddr)
1252 {
1253         u32 val, num_vlan;
1254
1255         val = readl(ioaddr + GMAC_HW_FEATURE3);
1256         switch (val & GMAC_HW_FEAT_NRVF) {
1257         case 0:
1258                 num_vlan = 1;
1259                 break;
1260         case 1:
1261                 num_vlan = 4;
1262                 break;
1263         case 2:
1264                 num_vlan = 8;
1265                 break;
1266         case 3:
1267                 num_vlan = 16;
1268                 break;
1269         case 4:
1270                 num_vlan = 24;
1271                 break;
1272         case 5:
1273                 num_vlan = 32;
1274                 break;
1275         default:
1276                 num_vlan = 1;
1277         }
1278
1279         return num_vlan;
1280 }
1281
1282 int dwmac4_setup(struct stmmac_priv *priv)
1283 {
1284         struct mac_device_info *mac = priv->hw;
1285
1286         dev_info(priv->device, "\tDWMAC4/5\n");
1287
1288         priv->dev->priv_flags |= IFF_UNICAST_FLT;
1289         mac->pcsr = priv->ioaddr;
1290         mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
1291         mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
1292         mac->mcast_bits_log2 = 0;
1293
1294         if (mac->multicast_filter_bins)
1295                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
1296
1297         mac->link.duplex = GMAC_CONFIG_DM;
1298         mac->link.speed10 = GMAC_CONFIG_PS;
1299         mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1300         mac->link.speed1000 = 0;
1301         mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1302         mac->mii.addr = GMAC_MDIO_ADDR;
1303         mac->mii.data = GMAC_MDIO_DATA;
1304         mac->mii.addr_shift = 21;
1305         mac->mii.addr_mask = GENMASK(25, 21);
1306         mac->mii.reg_shift = 16;
1307         mac->mii.reg_mask = GENMASK(20, 16);
1308         mac->mii.clk_csr_shift = 8;
1309         mac->mii.clk_csr_mask = GENMASK(11, 8);
1310         mac->num_vlan = dwmac4_get_num_vlan(priv->ioaddr);
1311
1312         return 0;
1313 }