1 // SPDX-License-Identifier: GPL-2.0-only
3 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
4 * DWC Ether MAC version 4.00 has been used for developing this code.
6 * This only implements the mac core functions for this chip.
8 * Copyright (C) 2015 STMicroelectronics Ltd
10 * Author: Alexandre Torgue <alexandre.torgue@st.com>
13 #include <linux/crc32.h>
14 #include <linux/slab.h>
15 #include <linux/ethtool.h>
19 #include "stmmac_pcs.h"
23 static void dwmac4_core_init(struct mac_device_info *hw,
24 struct net_device *dev)
26 void __iomem *ioaddr = hw->pcsr;
27 u32 value = readl(ioaddr + GMAC_CONFIG);
29 value |= GMAC_CORE_INIT;
32 value |= GMAC_CONFIG_TE;
34 value &= hw->link.speed_mask;
37 value |= hw->link.speed1000;
40 value |= hw->link.speed100;
43 value |= hw->link.speed10;
48 writel(value, ioaddr + GMAC_CONFIG);
50 /* Enable GMAC interrupts */
51 value = GMAC_INT_DEFAULT_ENABLE;
54 value |= GMAC_PCS_IRQ_DEFAULT;
56 writel(value, ioaddr + GMAC_INT_EN);
59 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
62 void __iomem *ioaddr = hw->pcsr;
63 u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
65 value &= GMAC_RX_QUEUE_CLEAR(queue);
66 if (mode == MTL_QUEUE_AVB)
67 value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
68 else if (mode == MTL_QUEUE_DCB)
69 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
71 writel(value, ioaddr + GMAC_RXQ_CTRL0);
74 static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
77 void __iomem *ioaddr = hw->pcsr;
82 ctrl2 = readl(ioaddr + GMAC_RXQ_CTRL2);
83 ctrl3 = readl(ioaddr + GMAC_RXQ_CTRL3);
85 /* The software must ensure that the same priority
86 * is not mapped to multiple Rx queues
88 for (i = 0; i < 4; i++)
89 clear_mask |= ((prio << GMAC_RXQCTRL_PSRQX_SHIFT(i)) &
90 GMAC_RXQCTRL_PSRQX_MASK(i));
95 /* First assign new priorities to a queue, then
96 * clear them from others queues
99 ctrl2 |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
100 GMAC_RXQCTRL_PSRQX_MASK(queue);
102 writel(ctrl2, ioaddr + GMAC_RXQ_CTRL2);
103 writel(ctrl3, ioaddr + GMAC_RXQ_CTRL3);
107 ctrl3 |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
108 GMAC_RXQCTRL_PSRQX_MASK(queue);
110 writel(ctrl3, ioaddr + GMAC_RXQ_CTRL3);
111 writel(ctrl2, ioaddr + GMAC_RXQ_CTRL2);
115 static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
118 void __iomem *ioaddr = hw->pcsr;
122 base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
126 value = readl(ioaddr + base_register);
128 value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
129 value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
130 GMAC_TXQCTRL_PSTQX_MASK(queue);
132 writel(value, ioaddr + base_register);
135 static void dwmac4_rx_queue_routing(struct mac_device_info *hw,
136 u8 packet, u32 queue)
138 void __iomem *ioaddr = hw->pcsr;
141 static const struct stmmac_rx_routing route_possibilities[] = {
142 { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
143 { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
144 { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
145 { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
146 { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
149 value = readl(ioaddr + GMAC_RXQ_CTRL1);
151 /* routing configuration */
152 value &= ~route_possibilities[packet - 1].reg_mask;
153 value |= (queue << route_possibilities[packet-1].reg_shift) &
154 route_possibilities[packet - 1].reg_mask;
156 /* some packets require extra ops */
157 if (packet == PACKET_AVCPQ) {
158 value &= ~GMAC_RXQCTRL_TACPQE;
159 value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
160 } else if (packet == PACKET_MCBCQ) {
161 value &= ~GMAC_RXQCTRL_MCBCQEN;
162 value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
165 writel(value, ioaddr + GMAC_RXQ_CTRL1);
168 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
171 void __iomem *ioaddr = hw->pcsr;
172 u32 value = readl(ioaddr + MTL_OPERATION_MODE);
174 value &= ~MTL_OPERATION_RAA;
176 case MTL_RX_ALGORITHM_SP:
177 value |= MTL_OPERATION_RAA_SP;
179 case MTL_RX_ALGORITHM_WSP:
180 value |= MTL_OPERATION_RAA_WSP;
186 writel(value, ioaddr + MTL_OPERATION_MODE);
189 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
192 void __iomem *ioaddr = hw->pcsr;
193 u32 value = readl(ioaddr + MTL_OPERATION_MODE);
195 value &= ~MTL_OPERATION_SCHALG_MASK;
197 case MTL_TX_ALGORITHM_WRR:
198 value |= MTL_OPERATION_SCHALG_WRR;
200 case MTL_TX_ALGORITHM_WFQ:
201 value |= MTL_OPERATION_SCHALG_WFQ;
203 case MTL_TX_ALGORITHM_DWRR:
204 value |= MTL_OPERATION_SCHALG_DWRR;
206 case MTL_TX_ALGORITHM_SP:
207 value |= MTL_OPERATION_SCHALG_SP;
213 writel(value, ioaddr + MTL_OPERATION_MODE);
216 static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
217 u32 weight, u32 queue)
219 void __iomem *ioaddr = hw->pcsr;
220 u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
222 value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
223 value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
224 writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
227 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
229 void __iomem *ioaddr = hw->pcsr;
233 value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
235 value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
237 if (queue == 0 || queue == 4) {
238 value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
239 value |= MTL_RXQ_DMA_Q04MDMACH(chan);
240 } else if (queue > 4) {
241 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue - 4);
242 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue - 4);
244 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
245 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
249 writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
251 writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
254 static void dwmac4_config_cbs(struct mac_device_info *hw,
255 u32 send_slope, u32 idle_slope,
256 u32 high_credit, u32 low_credit, u32 queue)
258 void __iomem *ioaddr = hw->pcsr;
261 pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
262 pr_debug("\tsend_slope: 0x%08x\n", send_slope);
263 pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
264 pr_debug("\thigh_credit: 0x%08x\n", high_credit);
265 pr_debug("\tlow_credit: 0x%08x\n", low_credit);
267 /* enable AV algorithm */
268 value = readl(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
269 value |= MTL_ETS_CTRL_AVALG;
270 value |= MTL_ETS_CTRL_CC;
271 writel(value, ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
273 /* configure send slope */
274 value = readl(ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
275 value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
276 value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
277 writel(value, ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
279 /* configure idle slope (same register as tx weight) */
280 dwmac4_set_mtl_tx_queue_weight(hw, idle_slope, queue);
282 /* configure high credit */
283 value = readl(ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
284 value &= ~MTL_HIGH_CRED_HC_MASK;
285 value |= high_credit & MTL_HIGH_CRED_HC_MASK;
286 writel(value, ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
288 /* configure high credit */
289 value = readl(ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
290 value &= ~MTL_HIGH_CRED_LC_MASK;
291 value |= low_credit & MTL_HIGH_CRED_LC_MASK;
292 writel(value, ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
295 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
297 void __iomem *ioaddr = hw->pcsr;
300 for (i = 0; i < GMAC_REG_NUM; i++)
301 reg_space[i] = readl(ioaddr + i * 4);
304 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
306 void __iomem *ioaddr = hw->pcsr;
307 u32 value = readl(ioaddr + GMAC_CONFIG);
310 value |= GMAC_CONFIG_IPC;
312 value &= ~GMAC_CONFIG_IPC;
314 writel(value, ioaddr + GMAC_CONFIG);
316 value = readl(ioaddr + GMAC_CONFIG);
318 return !!(value & GMAC_CONFIG_IPC);
321 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
323 void __iomem *ioaddr = hw->pcsr;
324 unsigned int pmt = 0;
327 if (mode & WAKE_MAGIC) {
328 pr_debug("GMAC: WOL Magic frame\n");
329 pmt |= power_down | magic_pkt_en;
331 if (mode & WAKE_UCAST) {
332 pr_debug("GMAC: WOL on global unicast\n");
333 pmt |= power_down | global_unicast | wake_up_frame_en;
337 /* The receiver must be enabled for WOL before powering down */
338 config = readl(ioaddr + GMAC_CONFIG);
339 config |= GMAC_CONFIG_RE;
340 writel(config, ioaddr + GMAC_CONFIG);
342 writel(pmt, ioaddr + GMAC_PMT);
345 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
346 unsigned char *addr, unsigned int reg_n)
348 void __iomem *ioaddr = hw->pcsr;
350 stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
351 GMAC_ADDR_LOW(reg_n));
354 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
355 unsigned char *addr, unsigned int reg_n)
357 void __iomem *ioaddr = hw->pcsr;
359 stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
360 GMAC_ADDR_LOW(reg_n));
363 static void dwmac4_set_eee_mode(struct mac_device_info *hw,
364 bool en_tx_lpi_clockgating)
366 void __iomem *ioaddr = hw->pcsr;
369 /* Enable the link status receive on RGMII, SGMII ore SMII
370 * receive path and instruct the transmit to enter in LPI
373 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
374 value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
376 if (en_tx_lpi_clockgating)
377 value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
379 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
382 static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
384 void __iomem *ioaddr = hw->pcsr;
387 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
388 value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
389 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
392 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
394 void __iomem *ioaddr = hw->pcsr;
397 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
400 value |= GMAC4_LPI_CTRL_STATUS_PLS;
402 value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
404 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
407 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
409 void __iomem *ioaddr = hw->pcsr;
410 int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
412 /* Program the timers in the LPI timer control register:
413 * LS: minimum time (ms) for which the link
414 * status from PHY should be ok before transmitting
416 * TW: minimum time (us) for which the core waits
417 * after it has stopped transmitting the LPI pattern.
419 writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
422 static void dwmac4_write_single_vlan(struct net_device *dev, u16 vid)
424 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
427 val = readl(ioaddr + GMAC_VLAN_TAG);
428 val &= ~GMAC_VLAN_TAG_VID;
429 val |= GMAC_VLAN_TAG_ETV | vid;
431 writel(val, ioaddr + GMAC_VLAN_TAG);
434 static int dwmac4_write_vlan_filter(struct net_device *dev,
435 struct mac_device_info *hw,
438 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
442 if (index >= hw->num_vlan)
445 writel(data, ioaddr + GMAC_VLAN_TAG_DATA);
447 val = readl(ioaddr + GMAC_VLAN_TAG);
448 val &= ~(GMAC_VLAN_TAG_CTRL_OFS_MASK |
449 GMAC_VLAN_TAG_CTRL_CT |
450 GMAC_VLAN_TAG_CTRL_OB);
451 val |= (index << GMAC_VLAN_TAG_CTRL_OFS_SHIFT) | GMAC_VLAN_TAG_CTRL_OB;
453 writel(val, ioaddr + GMAC_VLAN_TAG);
455 for (i = 0; i < timeout; i++) {
456 val = readl(ioaddr + GMAC_VLAN_TAG);
457 if (!(val & GMAC_VLAN_TAG_CTRL_OB))
462 netdev_err(dev, "Timeout accessing MAC_VLAN_Tag_Filter\n");
467 static int dwmac4_add_hw_vlan_rx_fltr(struct net_device *dev,
468 struct mac_device_info *hw,
469 __be16 proto, u16 vid)
478 /* Single Rx VLAN Filter */
479 if (hw->num_vlan == 1) {
480 /* For single VLAN filter, VID 0 means VLAN promiscuous */
482 netdev_warn(dev, "Adding VLAN ID 0 is not supported\n");
486 if (hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) {
487 netdev_err(dev, "Only single VLAN ID supported\n");
491 hw->vlan_filter[0] = vid;
492 dwmac4_write_single_vlan(dev, vid);
497 /* Extended Rx VLAN Filter Enable */
498 val |= GMAC_VLAN_TAG_DATA_ETV | GMAC_VLAN_TAG_DATA_VEN | vid;
500 for (i = 0; i < hw->num_vlan; i++) {
501 if (hw->vlan_filter[i] == val)
503 else if (!(hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN))
508 netdev_err(dev, "MAC_VLAN_Tag_Filter full (size: %0u)\n",
513 ret = dwmac4_write_vlan_filter(dev, hw, index, val);
516 hw->vlan_filter[index] = val;
521 static int dwmac4_del_hw_vlan_rx_fltr(struct net_device *dev,
522 struct mac_device_info *hw,
523 __be16 proto, u16 vid)
527 /* Single Rx VLAN Filter */
528 if (hw->num_vlan == 1) {
529 if ((hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) == vid) {
530 hw->vlan_filter[0] = 0;
531 dwmac4_write_single_vlan(dev, 0);
536 /* Extended Rx VLAN Filter Enable */
537 for (i = 0; i < hw->num_vlan; i++) {
538 if ((hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VID) == vid) {
539 ret = dwmac4_write_vlan_filter(dev, hw, i, 0);
542 hw->vlan_filter[i] = 0;
551 static void dwmac4_restore_hw_vlan_rx_fltr(struct net_device *dev,
552 struct mac_device_info *hw)
554 void __iomem *ioaddr = hw->pcsr;
560 /* Single Rx VLAN Filter */
561 if (hw->num_vlan == 1) {
562 dwmac4_write_single_vlan(dev, hw->vlan_filter[0]);
566 /* Extended Rx VLAN Filter Enable */
567 for (i = 0; i < hw->num_vlan; i++) {
568 if (hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN) {
569 val = hw->vlan_filter[i];
570 dwmac4_write_vlan_filter(dev, hw, i, val);
574 hash = readl(ioaddr + GMAC_VLAN_HASH_TABLE);
575 if (hash & GMAC_VLAN_VLHT) {
576 value = readl(ioaddr + GMAC_VLAN_TAG);
577 value |= GMAC_VLAN_VTHM;
578 writel(value, ioaddr + GMAC_VLAN_TAG);
582 static void dwmac4_set_filter(struct mac_device_info *hw,
583 struct net_device *dev)
585 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
586 int numhashregs = (hw->multicast_filter_bins >> 5);
587 int mcbitslog2 = hw->mcast_bits_log2;
592 memset(mc_filter, 0, sizeof(mc_filter));
594 value = readl(ioaddr + GMAC_PACKET_FILTER);
595 value &= ~GMAC_PACKET_FILTER_HMC;
596 value &= ~GMAC_PACKET_FILTER_HPF;
597 value &= ~GMAC_PACKET_FILTER_PCF;
598 value &= ~GMAC_PACKET_FILTER_PM;
599 value &= ~GMAC_PACKET_FILTER_PR;
600 value &= ~GMAC_PACKET_FILTER_RA;
601 if (dev->flags & IFF_PROMISC) {
602 /* VLAN Tag Filter Fail Packets Queuing */
603 if (hw->vlan_fail_q_en) {
604 value = readl(ioaddr + GMAC_RXQ_CTRL4);
605 value &= ~GMAC_RXQCTRL_VFFQ_MASK;
606 value |= GMAC_RXQCTRL_VFFQE |
607 (hw->vlan_fail_q << GMAC_RXQCTRL_VFFQ_SHIFT);
608 writel(value, ioaddr + GMAC_RXQ_CTRL4);
609 value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_RA;
611 value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_PCF;
614 } else if ((dev->flags & IFF_ALLMULTI) ||
615 (netdev_mc_count(dev) > hw->multicast_filter_bins)) {
617 value |= GMAC_PACKET_FILTER_PM;
618 /* Set all the bits of the HASH tab */
619 memset(mc_filter, 0xff, sizeof(mc_filter));
620 } else if (!netdev_mc_empty(dev) && (dev->flags & IFF_MULTICAST)) {
621 struct netdev_hw_addr *ha;
623 /* Hash filter for multicast */
624 value |= GMAC_PACKET_FILTER_HMC;
626 netdev_for_each_mc_addr(ha, dev) {
627 /* The upper n bits of the calculated CRC are used to
628 * index the contents of the hash table. The number of
629 * bits used depends on the hardware configuration
630 * selected at core configuration time.
632 u32 bit_nr = bitrev32(~crc32_le(~0, ha->addr,
633 ETH_ALEN)) >> (32 - mcbitslog2);
634 /* The most significant bit determines the register to
635 * use (H/L) while the other 5 bits determine the bit
636 * within the register.
638 mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1f));
642 for (i = 0; i < numhashregs; i++)
643 writel(mc_filter[i], ioaddr + GMAC_HASH_TAB(i));
645 value |= GMAC_PACKET_FILTER_HPF;
647 /* Handle multiple unicast addresses */
648 if (netdev_uc_count(dev) > hw->unicast_filter_entries) {
649 /* Switch to promiscuous mode if more than 128 addrs
652 value |= GMAC_PACKET_FILTER_PR;
654 struct netdev_hw_addr *ha;
657 netdev_for_each_uc_addr(ha, dev) {
658 dwmac4_set_umac_addr(hw, ha->addr, reg);
662 while (reg < GMAC_MAX_PERFECT_ADDRESSES) {
663 writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
664 writel(0, ioaddr + GMAC_ADDR_LOW(reg));
670 if (dev->flags & IFF_PROMISC && !hw->vlan_fail_q_en)
671 value &= ~GMAC_PACKET_FILTER_VTFE;
672 else if (dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
673 value |= GMAC_PACKET_FILTER_VTFE;
675 writel(value, ioaddr + GMAC_PACKET_FILTER);
678 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
679 unsigned int fc, unsigned int pause_time,
682 void __iomem *ioaddr = hw->pcsr;
683 unsigned int flow = 0;
686 pr_debug("GMAC Flow-Control:\n");
688 pr_debug("\tReceive Flow-Control ON\n");
689 flow |= GMAC_RX_FLOW_CTRL_RFE;
691 pr_debug("\tReceive Flow-Control OFF\n");
693 writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
696 pr_debug("\tTransmit Flow-Control ON\n");
699 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
701 for (queue = 0; queue < tx_cnt; queue++) {
702 flow = GMAC_TX_FLOW_CTRL_TFE;
706 (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
708 writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
711 for (queue = 0; queue < tx_cnt; queue++)
712 writel(0, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
716 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
719 dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
722 static void dwmac4_rane(void __iomem *ioaddr, bool restart)
724 dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
727 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
729 dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
732 /* RGMII or SMII interface */
733 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
737 status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
740 /* Check the link status */
741 if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
746 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
747 GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
748 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
749 x->pcs_speed = SPEED_1000;
750 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
751 x->pcs_speed = SPEED_100;
753 x->pcs_speed = SPEED_10;
755 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
757 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
758 x->pcs_duplex ? "Full" : "Half");
761 pr_info("Link is Down\n");
765 static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
767 void __iomem *ioaddr = hw->pcsr;
768 u32 mtl_int_qx_status;
771 mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
773 /* Check MTL Interrupt */
774 if (mtl_int_qx_status & MTL_INT_QX(chan)) {
775 /* read Queue x Interrupt status */
776 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
778 if (status & MTL_RX_OVERFLOW_INT) {
779 /* clear Interrupt */
780 writel(status | MTL_RX_OVERFLOW_INT,
781 ioaddr + MTL_CHAN_INT_CTRL(chan));
782 ret = CORE_IRQ_MTL_RX_OVERFLOW;
789 static int dwmac4_irq_status(struct mac_device_info *hw,
790 struct stmmac_extra_stats *x)
792 void __iomem *ioaddr = hw->pcsr;
793 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
794 u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
797 /* Discard disabled bits */
798 intr_status &= intr_enable;
800 /* Not used events (e.g. MMC interrupts) are not handled. */
801 if ((intr_status & mmc_tx_irq))
803 if (unlikely(intr_status & mmc_rx_irq))
805 if (unlikely(intr_status & mmc_rx_csum_offload_irq))
806 x->mmc_rx_csum_offload_irq_n++;
807 /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
808 if (unlikely(intr_status & pmt_irq)) {
809 readl(ioaddr + GMAC_PMT);
810 x->irq_receive_pmt_irq_n++;
813 /* MAC tx/rx EEE LPI entry/exit interrupts */
814 if (intr_status & lpi_irq) {
815 /* Clear LPI interrupt by reading MAC_LPI_Control_Status */
816 u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
818 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
819 ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
820 x->irq_tx_path_in_lpi_mode_n++;
822 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
823 ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
824 x->irq_tx_path_exit_lpi_mode_n++;
826 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
827 x->irq_rx_path_in_lpi_mode_n++;
828 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
829 x->irq_rx_path_exit_lpi_mode_n++;
832 dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
833 if (intr_status & PCS_RGSMIIIS_IRQ)
834 dwmac4_phystatus(ioaddr, x);
839 static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
840 u32 rx_queues, u32 tx_queues)
845 for (queue = 0; queue < tx_queues; queue++) {
846 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(queue));
848 if (value & MTL_DEBUG_TXSTSFSTS)
849 x->mtl_tx_status_fifo_full++;
850 if (value & MTL_DEBUG_TXFSTS)
851 x->mtl_tx_fifo_not_empty++;
852 if (value & MTL_DEBUG_TWCSTS)
854 if (value & MTL_DEBUG_TRCSTS_MASK) {
855 u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
856 >> MTL_DEBUG_TRCSTS_SHIFT;
857 if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
858 x->mtl_tx_fifo_read_ctrl_write++;
859 else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
860 x->mtl_tx_fifo_read_ctrl_wait++;
861 else if (trcsts == MTL_DEBUG_TRCSTS_READ)
862 x->mtl_tx_fifo_read_ctrl_read++;
864 x->mtl_tx_fifo_read_ctrl_idle++;
866 if (value & MTL_DEBUG_TXPAUSED)
867 x->mac_tx_in_pause++;
870 for (queue = 0; queue < rx_queues; queue++) {
871 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(queue));
873 if (value & MTL_DEBUG_RXFSTS_MASK) {
874 u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
875 >> MTL_DEBUG_RRCSTS_SHIFT;
877 if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
878 x->mtl_rx_fifo_fill_level_full++;
879 else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
880 x->mtl_rx_fifo_fill_above_thresh++;
881 else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
882 x->mtl_rx_fifo_fill_below_thresh++;
884 x->mtl_rx_fifo_fill_level_empty++;
886 if (value & MTL_DEBUG_RRCSTS_MASK) {
887 u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
888 MTL_DEBUG_RRCSTS_SHIFT;
890 if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
891 x->mtl_rx_fifo_read_ctrl_flush++;
892 else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
893 x->mtl_rx_fifo_read_ctrl_read_data++;
894 else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
895 x->mtl_rx_fifo_read_ctrl_status++;
897 x->mtl_rx_fifo_read_ctrl_idle++;
899 if (value & MTL_DEBUG_RWCSTS)
900 x->mtl_rx_fifo_ctrl_active++;
904 value = readl(ioaddr + GMAC_DEBUG);
906 if (value & GMAC_DEBUG_TFCSTS_MASK) {
907 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
908 >> GMAC_DEBUG_TFCSTS_SHIFT;
910 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
911 x->mac_tx_frame_ctrl_xfer++;
912 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
913 x->mac_tx_frame_ctrl_pause++;
914 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
915 x->mac_tx_frame_ctrl_wait++;
917 x->mac_tx_frame_ctrl_idle++;
919 if (value & GMAC_DEBUG_TPESTS)
920 x->mac_gmii_tx_proto_engine++;
921 if (value & GMAC_DEBUG_RFCFCSTS_MASK)
922 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
923 >> GMAC_DEBUG_RFCFCSTS_SHIFT;
924 if (value & GMAC_DEBUG_RPESTS)
925 x->mac_gmii_rx_proto_engine++;
928 static void dwmac4_set_mac_loopback(void __iomem *ioaddr, bool enable)
930 u32 value = readl(ioaddr + GMAC_CONFIG);
933 value |= GMAC_CONFIG_LM;
935 value &= ~GMAC_CONFIG_LM;
937 writel(value, ioaddr + GMAC_CONFIG);
940 static void dwmac4_update_vlan_hash(struct mac_device_info *hw, u32 hash,
941 __le16 perfect_match, bool is_double)
943 void __iomem *ioaddr = hw->pcsr;
946 writel(hash, ioaddr + GMAC_VLAN_HASH_TABLE);
948 value = readl(ioaddr + GMAC_VLAN_TAG);
951 value |= GMAC_VLAN_VTHM | GMAC_VLAN_ETV;
953 value |= GMAC_VLAN_EDVLP;
954 value |= GMAC_VLAN_ESVL;
955 value |= GMAC_VLAN_DOVLTC;
958 writel(value, ioaddr + GMAC_VLAN_TAG);
959 } else if (perfect_match) {
960 u32 value = GMAC_VLAN_ETV;
963 value |= GMAC_VLAN_EDVLP;
964 value |= GMAC_VLAN_ESVL;
965 value |= GMAC_VLAN_DOVLTC;
968 writel(value | perfect_match, ioaddr + GMAC_VLAN_TAG);
970 value &= ~(GMAC_VLAN_VTHM | GMAC_VLAN_ETV);
971 value &= ~(GMAC_VLAN_EDVLP | GMAC_VLAN_ESVL);
972 value &= ~GMAC_VLAN_DOVLTC;
973 value &= ~GMAC_VLAN_VID;
975 writel(value, ioaddr + GMAC_VLAN_TAG);
979 static void dwmac4_sarc_configure(void __iomem *ioaddr, int val)
981 u32 value = readl(ioaddr + GMAC_CONFIG);
983 value &= ~GMAC_CONFIG_SARC;
984 value |= val << GMAC_CONFIG_SARC_SHIFT;
986 writel(value, ioaddr + GMAC_CONFIG);
989 static void dwmac4_enable_vlan(struct mac_device_info *hw, u32 type)
991 void __iomem *ioaddr = hw->pcsr;
994 value = readl(ioaddr + GMAC_VLAN_INCL);
995 value |= GMAC_VLAN_VLTI;
996 value |= GMAC_VLAN_CSVL; /* Only use SVLAN */
997 value &= ~GMAC_VLAN_VLC;
998 value |= (type << GMAC_VLAN_VLC_SHIFT) & GMAC_VLAN_VLC;
999 writel(value, ioaddr + GMAC_VLAN_INCL);
1002 static void dwmac4_set_arp_offload(struct mac_device_info *hw, bool en,
1005 void __iomem *ioaddr = hw->pcsr;
1008 writel(addr, ioaddr + GMAC_ARP_ADDR);
1010 value = readl(ioaddr + GMAC_CONFIG);
1012 value |= GMAC_CONFIG_ARPEN;
1014 value &= ~GMAC_CONFIG_ARPEN;
1015 writel(value, ioaddr + GMAC_CONFIG);
1018 static int dwmac4_config_l3_filter(struct mac_device_info *hw, u32 filter_no,
1019 bool en, bool ipv6, bool sa, bool inv,
1022 void __iomem *ioaddr = hw->pcsr;
1025 value = readl(ioaddr + GMAC_PACKET_FILTER);
1026 value |= GMAC_PACKET_FILTER_IPFE;
1027 writel(value, ioaddr + GMAC_PACKET_FILTER);
1029 value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
1031 /* For IPv6 not both SA/DA filters can be active */
1033 value |= GMAC_L3PEN0;
1034 value &= ~(GMAC_L3SAM0 | GMAC_L3SAIM0);
1035 value &= ~(GMAC_L3DAM0 | GMAC_L3DAIM0);
1037 value |= GMAC_L3SAM0;
1039 value |= GMAC_L3SAIM0;
1041 value |= GMAC_L3DAM0;
1043 value |= GMAC_L3DAIM0;
1046 value &= ~GMAC_L3PEN0;
1048 value |= GMAC_L3SAM0;
1050 value |= GMAC_L3SAIM0;
1052 value |= GMAC_L3DAM0;
1054 value |= GMAC_L3DAIM0;
1058 writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
1061 writel(match, ioaddr + GMAC_L3_ADDR0(filter_no));
1063 writel(match, ioaddr + GMAC_L3_ADDR1(filter_no));
1067 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
1072 static int dwmac4_config_l4_filter(struct mac_device_info *hw, u32 filter_no,
1073 bool en, bool udp, bool sa, bool inv,
1076 void __iomem *ioaddr = hw->pcsr;
1079 value = readl(ioaddr + GMAC_PACKET_FILTER);
1080 value |= GMAC_PACKET_FILTER_IPFE;
1081 writel(value, ioaddr + GMAC_PACKET_FILTER);
1083 value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
1085 value |= GMAC_L4PEN0;
1087 value &= ~GMAC_L4PEN0;
1090 value &= ~(GMAC_L4SPM0 | GMAC_L4SPIM0);
1091 value &= ~(GMAC_L4DPM0 | GMAC_L4DPIM0);
1093 value |= GMAC_L4SPM0;
1095 value |= GMAC_L4SPIM0;
1097 value |= GMAC_L4DPM0;
1099 value |= GMAC_L4DPIM0;
1102 writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
1105 value = match & GMAC_L4SP0;
1107 value = (match << GMAC_L4DP0_SHIFT) & GMAC_L4DP0;
1110 writel(value, ioaddr + GMAC_L4_ADDR(filter_no));
1113 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
1118 const struct stmmac_ops dwmac4_ops = {
1119 .core_init = dwmac4_core_init,
1120 .set_mac = stmmac_set_mac,
1121 .rx_ipc = dwmac4_rx_ipc_enable,
1122 .rx_queue_enable = dwmac4_rx_queue_enable,
1123 .rx_queue_prio = dwmac4_rx_queue_priority,
1124 .tx_queue_prio = dwmac4_tx_queue_priority,
1125 .rx_queue_routing = dwmac4_rx_queue_routing,
1126 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1127 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1128 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1129 .map_mtl_to_dma = dwmac4_map_mtl_dma,
1130 .config_cbs = dwmac4_config_cbs,
1131 .dump_regs = dwmac4_dump_regs,
1132 .host_irq_status = dwmac4_irq_status,
1133 .host_mtl_irq_status = dwmac4_irq_mtl_status,
1134 .flow_ctrl = dwmac4_flow_ctrl,
1136 .set_umac_addr = dwmac4_set_umac_addr,
1137 .get_umac_addr = dwmac4_get_umac_addr,
1138 .set_eee_mode = dwmac4_set_eee_mode,
1139 .reset_eee_mode = dwmac4_reset_eee_mode,
1140 .set_eee_timer = dwmac4_set_eee_timer,
1141 .set_eee_pls = dwmac4_set_eee_pls,
1142 .pcs_ctrl_ane = dwmac4_ctrl_ane,
1143 .pcs_rane = dwmac4_rane,
1144 .pcs_get_adv_lp = dwmac4_get_adv_lp,
1145 .debug = dwmac4_debug,
1146 .set_filter = dwmac4_set_filter,
1147 .set_mac_loopback = dwmac4_set_mac_loopback,
1148 .update_vlan_hash = dwmac4_update_vlan_hash,
1149 .sarc_configure = dwmac4_sarc_configure,
1150 .enable_vlan = dwmac4_enable_vlan,
1151 .set_arp_offload = dwmac4_set_arp_offload,
1152 .config_l3_filter = dwmac4_config_l3_filter,
1153 .config_l4_filter = dwmac4_config_l4_filter,
1154 .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1155 .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1156 .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1159 const struct stmmac_ops dwmac410_ops = {
1160 .core_init = dwmac4_core_init,
1161 .set_mac = stmmac_dwmac4_set_mac,
1162 .rx_ipc = dwmac4_rx_ipc_enable,
1163 .rx_queue_enable = dwmac4_rx_queue_enable,
1164 .rx_queue_prio = dwmac4_rx_queue_priority,
1165 .tx_queue_prio = dwmac4_tx_queue_priority,
1166 .rx_queue_routing = dwmac4_rx_queue_routing,
1167 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1168 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1169 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1170 .map_mtl_to_dma = dwmac4_map_mtl_dma,
1171 .config_cbs = dwmac4_config_cbs,
1172 .dump_regs = dwmac4_dump_regs,
1173 .host_irq_status = dwmac4_irq_status,
1174 .host_mtl_irq_status = dwmac4_irq_mtl_status,
1175 .flow_ctrl = dwmac4_flow_ctrl,
1177 .set_umac_addr = dwmac4_set_umac_addr,
1178 .get_umac_addr = dwmac4_get_umac_addr,
1179 .set_eee_mode = dwmac4_set_eee_mode,
1180 .reset_eee_mode = dwmac4_reset_eee_mode,
1181 .set_eee_timer = dwmac4_set_eee_timer,
1182 .set_eee_pls = dwmac4_set_eee_pls,
1183 .pcs_ctrl_ane = dwmac4_ctrl_ane,
1184 .pcs_rane = dwmac4_rane,
1185 .pcs_get_adv_lp = dwmac4_get_adv_lp,
1186 .debug = dwmac4_debug,
1187 .set_filter = dwmac4_set_filter,
1188 .flex_pps_config = dwmac5_flex_pps_config,
1189 .set_mac_loopback = dwmac4_set_mac_loopback,
1190 .update_vlan_hash = dwmac4_update_vlan_hash,
1191 .sarc_configure = dwmac4_sarc_configure,
1192 .enable_vlan = dwmac4_enable_vlan,
1193 .set_arp_offload = dwmac4_set_arp_offload,
1194 .config_l3_filter = dwmac4_config_l3_filter,
1195 .config_l4_filter = dwmac4_config_l4_filter,
1196 .est_configure = dwmac5_est_configure,
1197 .fpe_configure = dwmac5_fpe_configure,
1198 .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1199 .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1200 .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1203 const struct stmmac_ops dwmac510_ops = {
1204 .core_init = dwmac4_core_init,
1205 .set_mac = stmmac_dwmac4_set_mac,
1206 .rx_ipc = dwmac4_rx_ipc_enable,
1207 .rx_queue_enable = dwmac4_rx_queue_enable,
1208 .rx_queue_prio = dwmac4_rx_queue_priority,
1209 .tx_queue_prio = dwmac4_tx_queue_priority,
1210 .rx_queue_routing = dwmac4_rx_queue_routing,
1211 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1212 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1213 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1214 .map_mtl_to_dma = dwmac4_map_mtl_dma,
1215 .config_cbs = dwmac4_config_cbs,
1216 .dump_regs = dwmac4_dump_regs,
1217 .host_irq_status = dwmac4_irq_status,
1218 .host_mtl_irq_status = dwmac4_irq_mtl_status,
1219 .flow_ctrl = dwmac4_flow_ctrl,
1221 .set_umac_addr = dwmac4_set_umac_addr,
1222 .get_umac_addr = dwmac4_get_umac_addr,
1223 .set_eee_mode = dwmac4_set_eee_mode,
1224 .reset_eee_mode = dwmac4_reset_eee_mode,
1225 .set_eee_timer = dwmac4_set_eee_timer,
1226 .set_eee_pls = dwmac4_set_eee_pls,
1227 .pcs_ctrl_ane = dwmac4_ctrl_ane,
1228 .pcs_rane = dwmac4_rane,
1229 .pcs_get_adv_lp = dwmac4_get_adv_lp,
1230 .debug = dwmac4_debug,
1231 .set_filter = dwmac4_set_filter,
1232 .safety_feat_config = dwmac5_safety_feat_config,
1233 .safety_feat_irq_status = dwmac5_safety_feat_irq_status,
1234 .safety_feat_dump = dwmac5_safety_feat_dump,
1235 .rxp_config = dwmac5_rxp_config,
1236 .flex_pps_config = dwmac5_flex_pps_config,
1237 .set_mac_loopback = dwmac4_set_mac_loopback,
1238 .update_vlan_hash = dwmac4_update_vlan_hash,
1239 .sarc_configure = dwmac4_sarc_configure,
1240 .enable_vlan = dwmac4_enable_vlan,
1241 .set_arp_offload = dwmac4_set_arp_offload,
1242 .config_l3_filter = dwmac4_config_l3_filter,
1243 .config_l4_filter = dwmac4_config_l4_filter,
1244 .est_configure = dwmac5_est_configure,
1245 .fpe_configure = dwmac5_fpe_configure,
1246 .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1247 .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1248 .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1251 static u32 dwmac4_get_num_vlan(void __iomem *ioaddr)
1255 val = readl(ioaddr + GMAC_HW_FEATURE3);
1256 switch (val & GMAC_HW_FEAT_NRVF) {
1282 int dwmac4_setup(struct stmmac_priv *priv)
1284 struct mac_device_info *mac = priv->hw;
1286 dev_info(priv->device, "\tDWMAC4/5\n");
1288 priv->dev->priv_flags |= IFF_UNICAST_FLT;
1289 mac->pcsr = priv->ioaddr;
1290 mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
1291 mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
1292 mac->mcast_bits_log2 = 0;
1294 if (mac->multicast_filter_bins)
1295 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
1297 mac->link.duplex = GMAC_CONFIG_DM;
1298 mac->link.speed10 = GMAC_CONFIG_PS;
1299 mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1300 mac->link.speed1000 = 0;
1301 mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1302 mac->mii.addr = GMAC_MDIO_ADDR;
1303 mac->mii.data = GMAC_MDIO_DATA;
1304 mac->mii.addr_shift = 21;
1305 mac->mii.addr_mask = GENMASK(25, 21);
1306 mac->mii.reg_shift = 16;
1307 mac->mii.reg_mask = GENMASK(20, 16);
1308 mac->mii.clk_csr_shift = 8;
1309 mac->mii.clk_csr_mask = GENMASK(11, 8);
1310 mac->num_vlan = dwmac4_get_num_vlan(priv->ioaddr);