drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

   1 /*
   2  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   3  * DWC Ether MAC version 4.00  has been used for developing this code.
   4  *
   5  * This only implements the mac core functions for this chip.
   6  *
   7  * Copyright (C) 2015  STMicroelectronics Ltd
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms and conditions of the GNU General Public License,
  11  * version 2, as published by the Free Software Foundation.
  12  *
  13  * Author: Alexandre Torgue <alexandre.torgue@st.com>
  14  */
  15
  16 #include <linux/crc32.h>
  17 #include <linux/slab.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/io.h>
  20 #include "stmmac_pcs.h"
  21 #include "dwmac4.h"
  22
  23 static void dwmac4_core_init(struct mac_device_info *hw, int mtu)
  24 {
  25         void __iomem *ioaddr = hw->pcsr;
  26         u32 value = readl(ioaddr + GMAC_CONFIG);
  27
  28         value |= GMAC_CORE_INIT;
  29
  30         if (mtu > 1500)
  31                 value |= GMAC_CONFIG_2K;
  32         if (mtu > 2000)
  33                 value |= GMAC_CONFIG_JE;
  34
  35         if (hw->ps) {
  36                 value |= GMAC_CONFIG_TE;
  37
  38                 if (hw->ps == SPEED_1000) {
  39                         value &= ~GMAC_CONFIG_PS;
  40                 } else {
  41                         value |= GMAC_CONFIG_PS;
  42
  43                         if (hw->ps == SPEED_10)
  44                                 value &= ~GMAC_CONFIG_FES;
  45                         else
  46                                 value |= GMAC_CONFIG_FES;
  47                 }
  48         }
  49
  50         writel(value, ioaddr + GMAC_CONFIG);
  51
  52         /* Mask GMAC interrupts */
  53         value = GMAC_INT_DEFAULT_MASK;
  54         if (hw->pmt)
  55                 value |= GMAC_INT_PMT_EN;
  56         if (hw->pcs)
  57                 value |= GMAC_PCS_IRQ_DEFAULT;
  58
  59         writel(value, ioaddr + GMAC_INT_EN);
  60 }
  61
  62 static void dwmac4_dump_regs(struct mac_device_info *hw)
  63 {
  64         void __iomem *ioaddr = hw->pcsr;
  65         int i;
  66
  67         pr_debug("\tDWMAC4 regs (base addr = 0x%p)\n", ioaddr);
  68
  69         for (i = 0; i < GMAC_REG_NUM; i++) {
  70                 int offset = i * 4;
  71
  72                 pr_debug("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
  73                          offset, readl(ioaddr + offset));
  74         }
  75 }
  76
  77 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
  78 {
  79         void __iomem *ioaddr = hw->pcsr;
  80         u32 value = readl(ioaddr + GMAC_CONFIG);
  81
  82         if (hw->rx_csum)
  83                 value |= GMAC_CONFIG_IPC;
  84         else
  85                 value &= ~GMAC_CONFIG_IPC;
  86
  87         writel(value, ioaddr + GMAC_CONFIG);
  88
  89         value = readl(ioaddr + GMAC_CONFIG);
  90
  91         return !!(value & GMAC_CONFIG_IPC);
  92 }
  93
  94 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
  95 {
  96         void __iomem *ioaddr = hw->pcsr;
  97         unsigned int pmt = 0;
  98
  99         if (mode & WAKE_MAGIC) {
 100                 pr_debug("GMAC: WOL Magic frame\n");
 101                 pmt |= power_down | magic_pkt_en;
 102         }
 103         if (mode & WAKE_UCAST) {
 104                 pr_debug("GMAC: WOL on global unicast\n");
 105                 pmt |= power_down | global_unicast | wake_up_frame_en;
 106         }
 107
 108         writel(pmt, ioaddr + GMAC_PMT);
 109 }
 110
 111 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
 112                                  unsigned char *addr, unsigned int reg_n)
 113 {
 114         void __iomem *ioaddr = hw->pcsr;
 115
 116         stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 117                                    GMAC_ADDR_LOW(reg_n));
 118 }
 119
 120 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
 121                                  unsigned char *addr, unsigned int reg_n)
 122 {
 123         void __iomem *ioaddr = hw->pcsr;
 124
 125         stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 126                                    GMAC_ADDR_LOW(reg_n));
 127 }
 128
 129 static void dwmac4_set_filter(struct mac_device_info *hw,
 130                               struct net_device *dev)
 131 {
 132         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 133         unsigned int value = 0;
 134
 135         if (dev->flags & IFF_PROMISC) {
 136                 value = GMAC_PACKET_FILTER_PR;
 137         } else if ((dev->flags & IFF_ALLMULTI) ||
 138                         (netdev_mc_count(dev) > HASH_TABLE_SIZE)) {
 139                 /* Pass all multi */
 140                 value = GMAC_PACKET_FILTER_PM;
 141                 /* Set the 64 bits of the HASH tab. To be updated if taller
 142                  * hash table is used
 143                  */
 144                 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_0_31);
 145                 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_32_63);
 146         } else if (!netdev_mc_empty(dev)) {
 147                 u32 mc_filter[2];
 148                 struct netdev_hw_addr *ha;
 149
 150                 /* Hash filter for multicast */
 151                 value = GMAC_PACKET_FILTER_HMC;
 152
 153                 memset(mc_filter, 0, sizeof(mc_filter));
 154                 netdev_for_each_mc_addr(ha, dev) {
 155                         /* The upper 6 bits of the calculated CRC are used to
 156                          * index the content of the Hash Table Reg 0 and 1.
 157                          */
 158                         int bit_nr =
 159                                 (bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26);
 160                         /* The most significant bit determines the register
 161                          * to use while the other 5 bits determines the bit
 162                          * within the selected register
 163                          */
 164                         mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1F));
 165                 }
 166                 writel(mc_filter[0], ioaddr + GMAC_HASH_TAB_0_31);
 167                 writel(mc_filter[1], ioaddr + GMAC_HASH_TAB_32_63);
 168         }
 169
 170         /* Handle multiple unicast addresses */
 171         if (netdev_uc_count(dev) > hw->unicast_filter_entries) {
 172                 /* Switch to promiscuous mode if more than 128 addrs
 173                  * are required
 174                  */
 175                 value |= GMAC_PACKET_FILTER_PR;
 176         } else {
 177                 struct netdev_hw_addr *ha;
 178                 int reg = 1;
 179
 180                 netdev_for_each_uc_addr(ha, dev) {
 181                         dwmac4_set_umac_addr(hw, ha->addr, reg);
 182                         reg++;
 183                 }
 184
 185                 while (reg <= GMAC_MAX_PERFECT_ADDRESSES) {
 186                         writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
 187                         writel(0, ioaddr + GMAC_ADDR_LOW(reg));
 188                         reg++;
 189                 }
 190         }
 191
 192         writel(value, ioaddr + GMAC_PACKET_FILTER);
 193 }
 194
 195 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 196                              unsigned int fc, unsigned int pause_time)
 197 {
 198         void __iomem *ioaddr = hw->pcsr;
 199         u32 channel = STMMAC_CHAN0;     /* FIXME */
 200         unsigned int flow = 0;
 201
 202         pr_debug("GMAC Flow-Control:\n");
 203         if (fc & FLOW_RX) {
 204                 pr_debug("\tReceive Flow-Control ON\n");
 205                 flow |= GMAC_RX_FLOW_CTRL_RFE;
 206                 writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
 207         }
 208         if (fc & FLOW_TX) {
 209                 pr_debug("\tTransmit Flow-Control ON\n");
 210                 flow |= GMAC_TX_FLOW_CTRL_TFE;
 211                 writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(channel));
 212
 213                 if (duplex) {
 214                         pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
 215                         flow |= (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
 216                         writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(channel));
 217                 }
 218         }
 219 }
 220
 221 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 222                             bool loopback)
 223 {
 224         dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
 225 }
 226
 227 static void dwmac4_rane(void __iomem *ioaddr, bool restart)
 228 {
 229         dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
 230 }
 231
 232 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
 233 {
 234         dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
 235 }
 236
 237 /* RGMII or SMII interface */
 238 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 239 {
 240         u32 status;
 241
 242         status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
 243         x->irq_rgmii_n++;
 244
 245         /* Check the link status */
 246         if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
 247                 int speed_value;
 248
 249                 x->pcs_link = 1;
 250
 251                 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
 252                                GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
 253                 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
 254                         x->pcs_speed = SPEED_1000;
 255                 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
 256                         x->pcs_speed = SPEED_100;
 257                 else
 258                         x->pcs_speed = SPEED_10;
 259
 260                 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
 261
 262                 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
 263                         x->pcs_duplex ? "Full" : "Half");
 264         } else {
 265                 x->pcs_link = 0;
 266                 pr_info("Link is Down\n");
 267         }
 268 }
 269
 270 static int dwmac4_irq_status(struct mac_device_info *hw,
 271                              struct stmmac_extra_stats *x)
 272 {
 273         void __iomem *ioaddr = hw->pcsr;
 274         u32 mtl_int_qx_status;
 275         u32 intr_status;
 276         int ret = 0;
 277
 278         intr_status = readl(ioaddr + GMAC_INT_STATUS);
 279
 280         /* Not used events (e.g. MMC interrupts) are not handled. */
 281         if ((intr_status & mmc_tx_irq))
 282                 x->mmc_tx_irq_n++;
 283         if (unlikely(intr_status & mmc_rx_irq))
 284                 x->mmc_rx_irq_n++;
 285         if (unlikely(intr_status & mmc_rx_csum_offload_irq))
 286                 x->mmc_rx_csum_offload_irq_n++;
 287         /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
 288         if (unlikely(intr_status & pmt_irq)) {
 289                 readl(ioaddr + GMAC_PMT);
 290                 x->irq_receive_pmt_irq_n++;
 291         }
 292
 293         mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
 294         /* Check MTL Interrupt: Currently only one queue is used: Q0. */
 295         if (mtl_int_qx_status & MTL_INT_Q0) {
 296                 /* read Queue 0 Interrupt status */
 297                 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(STMMAC_CHAN0));
 298
 299                 if (status & MTL_RX_OVERFLOW_INT) {
 300                         /*  clear Interrupt */
 301                         writel(status | MTL_RX_OVERFLOW_INT,
 302                                ioaddr + MTL_CHAN_INT_CTRL(STMMAC_CHAN0));
 303                         ret = CORE_IRQ_MTL_RX_OVERFLOW;
 304                 }
 305         }
 306
 307         dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
 308         if (intr_status & PCS_RGSMIIIS_IRQ)
 309                 dwmac4_phystatus(ioaddr, x);
 310
 311         return ret;
 312 }
 313
 314 static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 315 {
 316         u32 value;
 317
 318         /*  Currently only channel 0 is supported */
 319         value = readl(ioaddr + MTL_CHAN_TX_DEBUG(STMMAC_CHAN0));
 320
 321         if (value & MTL_DEBUG_TXSTSFSTS)
 322                 x->mtl_tx_status_fifo_full++;
 323         if (value & MTL_DEBUG_TXFSTS)
 324                 x->mtl_tx_fifo_not_empty++;
 325         if (value & MTL_DEBUG_TWCSTS)
 326                 x->mmtl_fifo_ctrl++;
 327         if (value & MTL_DEBUG_TRCSTS_MASK) {
 328                 u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
 329                              >> MTL_DEBUG_TRCSTS_SHIFT;
 330                 if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
 331                         x->mtl_tx_fifo_read_ctrl_write++;
 332                 else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
 333                         x->mtl_tx_fifo_read_ctrl_wait++;
 334                 else if (trcsts == MTL_DEBUG_TRCSTS_READ)
 335                         x->mtl_tx_fifo_read_ctrl_read++;
 336                 else
 337                         x->mtl_tx_fifo_read_ctrl_idle++;
 338         }
 339         if (value & MTL_DEBUG_TXPAUSED)
 340                 x->mac_tx_in_pause++;
 341
 342         value = readl(ioaddr + MTL_CHAN_RX_DEBUG(STMMAC_CHAN0));
 343
 344         if (value & MTL_DEBUG_RXFSTS_MASK) {
 345                 u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
 346                              >> MTL_DEBUG_RRCSTS_SHIFT;
 347
 348                 if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
 349                         x->mtl_rx_fifo_fill_level_full++;
 350                 else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
 351                         x->mtl_rx_fifo_fill_above_thresh++;
 352                 else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
 353                         x->mtl_rx_fifo_fill_below_thresh++;
 354                 else
 355                         x->mtl_rx_fifo_fill_level_empty++;
 356         }
 357         if (value & MTL_DEBUG_RRCSTS_MASK) {
 358                 u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
 359                              MTL_DEBUG_RRCSTS_SHIFT;
 360
 361                 if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
 362                         x->mtl_rx_fifo_read_ctrl_flush++;
 363                 else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
 364                         x->mtl_rx_fifo_read_ctrl_read_data++;
 365                 else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
 366                         x->mtl_rx_fifo_read_ctrl_status++;
 367                 else
 368                         x->mtl_rx_fifo_read_ctrl_idle++;
 369         }
 370         if (value & MTL_DEBUG_RWCSTS)
 371                 x->mtl_rx_fifo_ctrl_active++;
 372
 373         /* GMAC debug */
 374         value = readl(ioaddr + GMAC_DEBUG);
 375
 376         if (value & GMAC_DEBUG_TFCSTS_MASK) {
 377                 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
 378                               >> GMAC_DEBUG_TFCSTS_SHIFT;
 379
 380                 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
 381                         x->mac_tx_frame_ctrl_xfer++;
 382                 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
 383                         x->mac_tx_frame_ctrl_pause++;
 384                 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
 385                         x->mac_tx_frame_ctrl_wait++;
 386                 else
 387                         x->mac_tx_frame_ctrl_idle++;
 388         }
 389         if (value & GMAC_DEBUG_TPESTS)
 390                 x->mac_gmii_tx_proto_engine++;
 391         if (value & GMAC_DEBUG_RFCFCSTS_MASK)
 392                 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
 393                                             >> GMAC_DEBUG_RFCFCSTS_SHIFT;
 394         if (value & GMAC_DEBUG_RPESTS)
 395                 x->mac_gmii_rx_proto_engine++;
 396 }
 397
 398 static const struct stmmac_ops dwmac4_ops = {
 399         .core_init = dwmac4_core_init,
 400         .rx_ipc = dwmac4_rx_ipc_enable,
 401         .dump_regs = dwmac4_dump_regs,
 402         .host_irq_status = dwmac4_irq_status,
 403         .flow_ctrl = dwmac4_flow_ctrl,
 404         .pmt = dwmac4_pmt,
 405         .set_umac_addr = dwmac4_set_umac_addr,
 406         .get_umac_addr = dwmac4_get_umac_addr,
 407         .pcs_ctrl_ane = dwmac4_ctrl_ane,
 408         .pcs_rane = dwmac4_rane,
 409         .pcs_get_adv_lp = dwmac4_get_adv_lp,
 410         .debug = dwmac4_debug,
 411         .set_filter = dwmac4_set_filter,
 412 };
 413
 414 struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
 415                                      int perfect_uc_entries, int *synopsys_id)
 416 {
 417         struct mac_device_info *mac;
 418         u32 hwid = readl(ioaddr + GMAC_VERSION);
 419
 420         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 421         if (!mac)
 422                 return NULL;
 423
 424         mac->pcsr = ioaddr;
 425         mac->multicast_filter_bins = mcbins;
 426         mac->unicast_filter_entries = perfect_uc_entries;
 427         mac->mcast_bits_log2 = 0;
 428
 429         if (mac->multicast_filter_bins)
 430                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
 431
 432         mac->mac = &dwmac4_ops;
 433
 434         mac->link.port = GMAC_CONFIG_PS;
 435         mac->link.duplex = GMAC_CONFIG_DM;
 436         mac->link.speed = GMAC_CONFIG_FES;
 437         mac->mii.addr = GMAC_MDIO_ADDR;
 438         mac->mii.data = GMAC_MDIO_DATA;
 439
 440         /* Get and dump the chip ID */
 441         *synopsys_id = stmmac_get_synopsys_id(hwid);
 442
 443         if (*synopsys_id > DWMAC_CORE_4_00)
 444                 mac->dma = &dwmac410_dma_ops;
 445         else
 446                 mac->dma = &dwmac4_dma_ops;
 447
 448         return mac;
 449 }