drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

   1 /*******************************************************************************
   2   This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   3   DWC Ether MAC 10/100/1000 Universal version 3.41a  has been used for
   4   developing this code.
   5
   6   This only implements the mac core functions for this chip.
   7
   8   Copyright (C) 2007-2009  STMicroelectronics Ltd
   9
  10   This program is free software; you can redistribute it and/or modify it
  11   under the terms and conditions of the GNU General Public License,
  12   version 2, as published by the Free Software Foundation.
  13
  14   This program is distributed in the hope it will be useful, but WITHOUT
  15   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17   more details.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  23 *******************************************************************************/
  24
  25 #include <linux/crc32.h>
  26 #include <linux/slab.h>
  27 #include <linux/ethtool.h>
  28 #include <net/dsa.h>
  29 #include <asm/io.h>
  30 #include "stmmac_pcs.h"
  31 #include "dwmac1000.h"
  32
  33 static void dwmac1000_core_init(struct mac_device_info *hw,
  34                                 struct net_device *dev)
  35 {
  36         void __iomem *ioaddr = hw->pcsr;
  37         u32 value = readl(ioaddr + GMAC_CONTROL);
  38         int mtu = dev->mtu;
  39
  40         /* Configure GMAC core */
  41         value |= GMAC_CORE_INIT;
  42
  43         /* Clear ACS bit because Ethernet switch tagging formats such as
  44          * Broadcom tags can look like invalid LLC/SNAP packets and cause the
  45          * hardware to truncate packets on reception.
  46          */
  47         if (netdev_uses_dsa(dev))
  48                 value &= ~GMAC_CONTROL_ACS;
  49
  50         if (mtu > 1500)
  51                 value |= GMAC_CONTROL_2K;
  52         if (mtu > 2000)
  53                 value |= GMAC_CONTROL_JE;
  54
  55         if (hw->ps) {
  56                 value |= GMAC_CONTROL_TE;
  57
  58                 value &= ~hw->link.speed_mask;
  59                 switch (hw->ps) {
  60                 case SPEED_1000:
  61                         value |= hw->link.speed1000;
  62                         break;
  63                 case SPEED_100:
  64                         value |= hw->link.speed100;
  65                         break;
  66                 case SPEED_10:
  67                         value |= hw->link.speed10;
  68                         break;
  69                 }
  70         }
  71
  72         writel(value, ioaddr + GMAC_CONTROL);
  73
  74         /* Mask GMAC interrupts */
  75         value = GMAC_INT_DEFAULT_MASK;
  76
  77         if (hw->pmt)
  78                 value &= ~GMAC_INT_DISABLE_PMT;
  79         if (hw->pcs)
  80                 value &= ~GMAC_INT_DISABLE_PCS;
  81
  82         writel(value, ioaddr + GMAC_INT_MASK);
  83
  84 #ifdef STMMAC_VLAN_TAG_USED
  85         /* Tag detection without filtering */
  86         writel(0x0, ioaddr + GMAC_VLAN_TAG);
  87 #endif
  88 }
  89
  90 static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)
  91 {
  92         void __iomem *ioaddr = hw->pcsr;
  93         u32 value = readl(ioaddr + GMAC_CONTROL);
  94
  95         if (hw->rx_csum)
  96                 value |= GMAC_CONTROL_IPC;
  97         else
  98                 value &= ~GMAC_CONTROL_IPC;
  99
 100         writel(value, ioaddr + GMAC_CONTROL);
 101
 102         value = readl(ioaddr + GMAC_CONTROL);
 103
 104         return !!(value & GMAC_CONTROL_IPC);
 105 }
 106
 107 static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)
 108 {
 109         void __iomem *ioaddr = hw->pcsr;
 110         int i;
 111
 112         for (i = 0; i < 55; i++)
 113                 reg_space[i] = readl(ioaddr + i * 4);
 114 }
 115
 116 static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
 117                                     unsigned char *addr,
 118                                     unsigned int reg_n)
 119 {
 120         void __iomem *ioaddr = hw->pcsr;
 121         stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 122                             GMAC_ADDR_LOW(reg_n));
 123 }
 124
 125 static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
 126                                     unsigned char *addr,
 127                                     unsigned int reg_n)
 128 {
 129         void __iomem *ioaddr = hw->pcsr;
 130         stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 131                             GMAC_ADDR_LOW(reg_n));
 132 }
 133
 134 static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
 135                                  int mcbitslog2)
 136 {
 137         int numhashregs, regs;
 138
 139         switch (mcbitslog2) {
 140         case 6:
 141                 writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
 142                 writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
 143                 return;
 144                 break;
 145         case 7:
 146                 numhashregs = 4;
 147                 break;
 148         case 8:
 149                 numhashregs = 8;
 150                 break;
 151         default:
 152                 pr_debug("STMMAC: err in setting multicast filter\n");
 153                 return;
 154                 break;
 155         }
 156         for (regs = 0; regs < numhashregs; regs++)
 157                 writel(mcfilterbits[regs],
 158                        ioaddr + GMAC_EXTHASH_BASE + regs * 4);
 159 }
 160
 161 static void dwmac1000_set_filter(struct mac_device_info *hw,
 162                                  struct net_device *dev)
 163 {
 164         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 165         unsigned int value = 0;
 166         unsigned int perfect_addr_number = hw->unicast_filter_entries;
 167         u32 mc_filter[8];
 168         int mcbitslog2 = hw->mcast_bits_log2;
 169
 170         pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,
 171                  netdev_mc_count(dev), netdev_uc_count(dev));
 172
 173         memset(mc_filter, 0, sizeof(mc_filter));
 174
 175         if (dev->flags & IFF_PROMISC) {
 176                 value = GMAC_FRAME_FILTER_PR;
 177         } else if (dev->flags & IFF_ALLMULTI) {
 178                 value = GMAC_FRAME_FILTER_PM;   /* pass all multi */
 179         } else if (!netdev_mc_empty(dev) && (mcbitslog2 == 0)) {
 180                 /* Fall back to all multicast if we've no filter */
 181                 value = GMAC_FRAME_FILTER_PM;
 182         } else if (!netdev_mc_empty(dev)) {
 183                 struct netdev_hw_addr *ha;
 184
 185                 /* Hash filter for multicast */
 186                 value = GMAC_FRAME_FILTER_HMC;
 187
 188                 netdev_for_each_mc_addr(ha, dev) {
 189                         /* The upper n bits of the calculated CRC are used to
 190                          * index the contents of the hash table. The number of
 191                          * bits used depends on the hardware configuration
 192                          * selected at core configuration time.
 193                          */
 194                         int bit_nr = bitrev32(~crc32_le(~0, ha->addr,
 195                                               ETH_ALEN)) >>
 196                                               (32 - mcbitslog2);
 197                         /* The most significant bit determines the register to
 198                          * use (H/L) while the other 5 bits determine the bit
 199                          * within the register.
 200                          */
 201                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
 202                 }
 203         }
 204
 205         dwmac1000_set_mchash(ioaddr, mc_filter, mcbitslog2);
 206
 207         /* Handle multiple unicast addresses (perfect filtering) */
 208         if (netdev_uc_count(dev) > perfect_addr_number)
 209                 /* Switch to promiscuous mode if more than unicast
 210                  * addresses are requested than supported by hardware.
 211                  */
 212                 value |= GMAC_FRAME_FILTER_PR;
 213         else {
 214                 int reg = 1;
 215                 struct netdev_hw_addr *ha;
 216
 217                 netdev_for_each_uc_addr(ha, dev) {
 218                         stmmac_set_mac_addr(ioaddr, ha->addr,
 219                                             GMAC_ADDR_HIGH(reg),
 220                                             GMAC_ADDR_LOW(reg));
 221                         reg++;
 222                 }
 223
 224                 while (reg < perfect_addr_number) {
 225                         writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
 226                         writel(0, ioaddr + GMAC_ADDR_LOW(reg));
 227                         reg++;
 228                 }
 229         }
 230
 231 #ifdef FRAME_FILTER_DEBUG
 232         /* Enable Receive all mode (to debug filtering_fail errors) */
 233         value |= GMAC_FRAME_FILTER_RA;
 234 #endif
 235         writel(value, ioaddr + GMAC_FRAME_FILTER);
 236 }
 237
 238
 239 static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 240                                 unsigned int fc, unsigned int pause_time,
 241                                 u32 tx_cnt)
 242 {
 243         void __iomem *ioaddr = hw->pcsr;
 244         /* Set flow such that DZPQ in Mac Register 6 is 0,
 245          * and unicast pause detect is enabled.
 246          */
 247         unsigned int flow = GMAC_FLOW_CTRL_UP;
 248
 249         pr_debug("GMAC Flow-Control:\n");
 250         if (fc & FLOW_RX) {
 251                 pr_debug("\tReceive Flow-Control ON\n");
 252                 flow |= GMAC_FLOW_CTRL_RFE;
 253         }
 254         if (fc & FLOW_TX) {
 255                 pr_debug("\tTransmit Flow-Control ON\n");
 256                 flow |= GMAC_FLOW_CTRL_TFE;
 257         }
 258
 259         if (duplex) {
 260                 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
 261                 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
 262         }
 263
 264         writel(flow, ioaddr + GMAC_FLOW_CTRL);
 265 }
 266
 267 static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)
 268 {
 269         void __iomem *ioaddr = hw->pcsr;
 270         unsigned int pmt = 0;
 271
 272         if (mode & WAKE_MAGIC) {
 273                 pr_debug("GMAC: WOL Magic frame\n");
 274                 pmt |= power_down | magic_pkt_en;
 275         }
 276         if (mode & WAKE_UCAST) {
 277                 pr_debug("GMAC: WOL on global unicast\n");
 278                 pmt |= power_down | global_unicast | wake_up_frame_en;
 279         }
 280
 281         writel(pmt, ioaddr + GMAC_PMT);
 282 }
 283
 284 /* RGMII or SMII interface */
 285 static void dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 286 {
 287         u32 status;
 288
 289         status = readl(ioaddr + GMAC_RGSMIIIS);
 290         x->irq_rgmii_n++;
 291
 292         /* Check the link status */
 293         if (status & GMAC_RGSMIIIS_LNKSTS) {
 294                 int speed_value;
 295
 296                 x->pcs_link = 1;
 297
 298                 speed_value = ((status & GMAC_RGSMIIIS_SPEED) >>
 299                                GMAC_RGSMIIIS_SPEED_SHIFT);
 300                 if (speed_value == GMAC_RGSMIIIS_SPEED_125)
 301                         x->pcs_speed = SPEED_1000;
 302                 else if (speed_value == GMAC_RGSMIIIS_SPEED_25)
 303                         x->pcs_speed = SPEED_100;
 304                 else
 305                         x->pcs_speed = SPEED_10;
 306
 307                 x->pcs_duplex = (status & GMAC_RGSMIIIS_LNKMOD_MASK);
 308
 309                 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
 310                         x->pcs_duplex ? "Full" : "Half");
 311         } else {
 312                 x->pcs_link = 0;
 313                 pr_info("Link is Down\n");
 314         }
 315 }
 316
 317 static int dwmac1000_irq_status(struct mac_device_info *hw,
 318                                 struct stmmac_extra_stats *x)
 319 {
 320         void __iomem *ioaddr = hw->pcsr;
 321         u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
 322         u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
 323         int ret = 0;
 324
 325         /* Discard masked bits */
 326         intr_status &= ~intr_mask;
 327
 328         /* Not used events (e.g. MMC interrupts) are not handled. */
 329         if ((intr_status & GMAC_INT_STATUS_MMCTIS))
 330                 x->mmc_tx_irq_n++;
 331         if (unlikely(intr_status & GMAC_INT_STATUS_MMCRIS))
 332                 x->mmc_rx_irq_n++;
 333         if (unlikely(intr_status & GMAC_INT_STATUS_MMCCSUM))
 334                 x->mmc_rx_csum_offload_irq_n++;
 335         if (unlikely(intr_status & GMAC_INT_DISABLE_PMT)) {
 336                 /* clear the PMT bits 5 and 6 by reading the PMT status reg */
 337                 readl(ioaddr + GMAC_PMT);
 338                 x->irq_receive_pmt_irq_n++;
 339         }
 340
 341         /* MAC tx/rx EEE LPI entry/exit interrupts */
 342         if (intr_status & GMAC_INT_STATUS_LPIIS) {
 343                 /* Clean LPI interrupt by reading the Reg 12 */
 344                 ret = readl(ioaddr + LPI_CTRL_STATUS);
 345
 346                 if (ret & LPI_CTRL_STATUS_TLPIEN)
 347                         x->irq_tx_path_in_lpi_mode_n++;
 348                 if (ret & LPI_CTRL_STATUS_TLPIEX)
 349                         x->irq_tx_path_exit_lpi_mode_n++;
 350                 if (ret & LPI_CTRL_STATUS_RLPIEN)
 351                         x->irq_rx_path_in_lpi_mode_n++;
 352                 if (ret & LPI_CTRL_STATUS_RLPIEX)
 353                         x->irq_rx_path_exit_lpi_mode_n++;
 354         }
 355
 356         dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
 357
 358         if (intr_status & PCS_RGSMIIIS_IRQ)
 359                 dwmac1000_rgsmii(ioaddr, x);
 360
 361         return ret;
 362 }
 363
 364 static void dwmac1000_set_eee_mode(struct mac_device_info *hw,
 365                                    bool en_tx_lpi_clockgating)
 366 {
 367         void __iomem *ioaddr = hw->pcsr;
 368         u32 value;
 369
 370         /*TODO - en_tx_lpi_clockgating treatment */
 371
 372         /* Enable the link status receive on RGMII, SGMII ore SMII
 373          * receive path and instruct the transmit to enter in LPI
 374          * state.
 375          */
 376         value = readl(ioaddr + LPI_CTRL_STATUS);
 377         value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
 378         writel(value, ioaddr + LPI_CTRL_STATUS);
 379 }
 380
 381 static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)
 382 {
 383         void __iomem *ioaddr = hw->pcsr;
 384         u32 value;
 385
 386         value = readl(ioaddr + LPI_CTRL_STATUS);
 387         value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
 388         writel(value, ioaddr + LPI_CTRL_STATUS);
 389 }
 390
 391 static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)
 392 {
 393         void __iomem *ioaddr = hw->pcsr;
 394         u32 value;
 395
 396         value = readl(ioaddr + LPI_CTRL_STATUS);
 397
 398         if (link)
 399                 value |= LPI_CTRL_STATUS_PLS;
 400         else
 401                 value &= ~LPI_CTRL_STATUS_PLS;
 402
 403         writel(value, ioaddr + LPI_CTRL_STATUS);
 404 }
 405
 406 static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
 407 {
 408         void __iomem *ioaddr = hw->pcsr;
 409         int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
 410
 411         /* Program the timers in the LPI timer control register:
 412          * LS: minimum time (ms) for which the link
 413          *  status from PHY should be ok before transmitting
 414          *  the LPI pattern.
 415          * TW: minimum time (us) for which the core waits
 416          *  after it has stopped transmitting the LPI pattern.
 417          */
 418         writel(value, ioaddr + LPI_TIMER_CTRL);
 419 }
 420
 421 static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 422                                bool loopback)
 423 {
 424         dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
 425 }
 426
 427 static void dwmac1000_rane(void __iomem *ioaddr, bool restart)
 428 {
 429         dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
 430 }
 431
 432 static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
 433 {
 434         dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
 435 }
 436
 437 static void dwmac1000_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
 438                             u32 rx_queues, u32 tx_queues)
 439 {
 440         u32 value = readl(ioaddr + GMAC_DEBUG);
 441
 442         if (value & GMAC_DEBUG_TXSTSFSTS)
 443                 x->mtl_tx_status_fifo_full++;
 444         if (value & GMAC_DEBUG_TXFSTS)
 445                 x->mtl_tx_fifo_not_empty++;
 446         if (value & GMAC_DEBUG_TWCSTS)
 447                 x->mmtl_fifo_ctrl++;
 448         if (value & GMAC_DEBUG_TRCSTS_MASK) {
 449                 u32 trcsts = (value & GMAC_DEBUG_TRCSTS_MASK)
 450                              >> GMAC_DEBUG_TRCSTS_SHIFT;
 451                 if (trcsts == GMAC_DEBUG_TRCSTS_WRITE)
 452                         x->mtl_tx_fifo_read_ctrl_write++;
 453                 else if (trcsts == GMAC_DEBUG_TRCSTS_TXW)
 454                         x->mtl_tx_fifo_read_ctrl_wait++;
 455                 else if (trcsts == GMAC_DEBUG_TRCSTS_READ)
 456                         x->mtl_tx_fifo_read_ctrl_read++;
 457                 else
 458                         x->mtl_tx_fifo_read_ctrl_idle++;
 459         }
 460         if (value & GMAC_DEBUG_TXPAUSED)
 461                 x->mac_tx_in_pause++;
 462         if (value & GMAC_DEBUG_TFCSTS_MASK) {
 463                 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
 464                               >> GMAC_DEBUG_TFCSTS_SHIFT;
 465
 466                 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
 467                         x->mac_tx_frame_ctrl_xfer++;
 468                 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
 469                         x->mac_tx_frame_ctrl_pause++;
 470                 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
 471                         x->mac_tx_frame_ctrl_wait++;
 472                 else
 473                         x->mac_tx_frame_ctrl_idle++;
 474         }
 475         if (value & GMAC_DEBUG_TPESTS)
 476                 x->mac_gmii_tx_proto_engine++;
 477         if (value & GMAC_DEBUG_RXFSTS_MASK) {
 478                 u32 rxfsts = (value & GMAC_DEBUG_RXFSTS_MASK)
 479                              >> GMAC_DEBUG_RRCSTS_SHIFT;
 480
 481                 if (rxfsts == GMAC_DEBUG_RXFSTS_FULL)
 482                         x->mtl_rx_fifo_fill_level_full++;
 483                 else if (rxfsts == GMAC_DEBUG_RXFSTS_AT)
 484                         x->mtl_rx_fifo_fill_above_thresh++;
 485                 else if (rxfsts == GMAC_DEBUG_RXFSTS_BT)
 486                         x->mtl_rx_fifo_fill_below_thresh++;
 487                 else
 488                         x->mtl_rx_fifo_fill_level_empty++;
 489         }
 490         if (value & GMAC_DEBUG_RRCSTS_MASK) {
 491                 u32 rrcsts = (value & GMAC_DEBUG_RRCSTS_MASK) >>
 492                              GMAC_DEBUG_RRCSTS_SHIFT;
 493
 494                 if (rrcsts == GMAC_DEBUG_RRCSTS_FLUSH)
 495                         x->mtl_rx_fifo_read_ctrl_flush++;
 496                 else if (rrcsts == GMAC_DEBUG_RRCSTS_RSTAT)
 497                         x->mtl_rx_fifo_read_ctrl_read_data++;
 498                 else if (rrcsts == GMAC_DEBUG_RRCSTS_RDATA)
 499                         x->mtl_rx_fifo_read_ctrl_status++;
 500                 else
 501                         x->mtl_rx_fifo_read_ctrl_idle++;
 502         }
 503         if (value & GMAC_DEBUG_RWCSTS)
 504                 x->mtl_rx_fifo_ctrl_active++;
 505         if (value & GMAC_DEBUG_RFCFCSTS_MASK)
 506                 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
 507                                             >> GMAC_DEBUG_RFCFCSTS_SHIFT;
 508         if (value & GMAC_DEBUG_RPESTS)
 509                 x->mac_gmii_rx_proto_engine++;
 510 }
 511
 512 static const struct stmmac_ops dwmac1000_ops = {
 513         .core_init = dwmac1000_core_init,
 514         .set_mac = stmmac_set_mac,
 515         .rx_ipc = dwmac1000_rx_ipc_enable,
 516         .dump_regs = dwmac1000_dump_regs,
 517         .host_irq_status = dwmac1000_irq_status,
 518         .set_filter = dwmac1000_set_filter,
 519         .flow_ctrl = dwmac1000_flow_ctrl,
 520         .pmt = dwmac1000_pmt,
 521         .set_umac_addr = dwmac1000_set_umac_addr,
 522         .get_umac_addr = dwmac1000_get_umac_addr,
 523         .set_eee_mode = dwmac1000_set_eee_mode,
 524         .reset_eee_mode = dwmac1000_reset_eee_mode,
 525         .set_eee_timer = dwmac1000_set_eee_timer,
 526         .set_eee_pls = dwmac1000_set_eee_pls,
 527         .debug = dwmac1000_debug,
 528         .pcs_ctrl_ane = dwmac1000_ctrl_ane,
 529         .pcs_rane = dwmac1000_rane,
 530         .pcs_get_adv_lp = dwmac1000_get_adv_lp,
 531 };
 532
 533 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
 534                                         int perfect_uc_entries,
 535                                         int *synopsys_id)
 536 {
 537         struct mac_device_info *mac;
 538         u32 hwid = readl(ioaddr + GMAC_VERSION);
 539
 540         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 541         if (!mac)
 542                 return NULL;
 543
 544         mac->pcsr = ioaddr;
 545         mac->multicast_filter_bins = mcbins;
 546         mac->unicast_filter_entries = perfect_uc_entries;
 547         mac->mcast_bits_log2 = 0;
 548
 549         if (mac->multicast_filter_bins)
 550                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
 551
 552         mac->mac = &dwmac1000_ops;
 553         mac->dma = &dwmac1000_dma_ops;
 554
 555         mac->link.duplex = GMAC_CONTROL_DM;
 556         mac->link.speed10 = GMAC_CONTROL_PS;
 557         mac->link.speed100 = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
 558         mac->link.speed1000 = 0;
 559         mac->link.speed_mask = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
 560         mac->mii.addr = GMAC_MII_ADDR;
 561         mac->mii.data = GMAC_MII_DATA;
 562         mac->mii.addr_shift = 11;
 563         mac->mii.addr_mask = 0x0000F800;
 564         mac->mii.reg_shift = 6;
 565         mac->mii.reg_mask = 0x000007C0;
 566         mac->mii.clk_csr_shift = 2;
 567         mac->mii.clk_csr_mask = GENMASK(5, 2);
 568
 569         /* Get and dump the chip ID */
 570         *synopsys_id = stmmac_get_synopsys_id(hwid);
 571
 572         return mac;
 573 }