1 /*******************************************************************************
2 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
3 DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
6 This only implements the mac core functions for this chip.
8 Copyright (C) 2007-2009 STMicroelectronics Ltd
10 This program is free software; you can redistribute it and/or modify it
11 under the terms and conditions of the GNU General Public License,
12 version 2, as published by the Free Software Foundation.
14 This program is distributed in the hope it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 You should have received a copy of the GNU General Public License along with
20 this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
23 The full GNU General Public License is included in this distribution in
24 the file called "COPYING".
26 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
27 *******************************************************************************/
29 #include <linux/crc32.h>
30 #include <linux/slab.h>
31 #include <linux/ethtool.h>
33 #include "stmmac_pcs.h"
34 #include "dwmac1000.h"
36 static void dwmac1000_core_init(struct mac_device_info *hw, int mtu)
38 void __iomem *ioaddr = hw->pcsr;
39 u32 value = readl(ioaddr + GMAC_CONTROL);
41 /* Configure GMAC core */
42 value |= GMAC_CORE_INIT;
45 value |= GMAC_CONTROL_2K;
47 value |= GMAC_CONTROL_JE;
50 value |= GMAC_CONTROL_TE;
52 if (hw->ps == SPEED_1000) {
53 value &= ~GMAC_CONTROL_PS;
55 value |= GMAC_CONTROL_PS;
57 if (hw->ps == SPEED_10)
58 value &= ~GMAC_CONTROL_FES;
60 value |= GMAC_CONTROL_FES;
64 writel(value, ioaddr + GMAC_CONTROL);
66 /* Mask GMAC interrupts */
67 value = GMAC_INT_DEFAULT_MASK;
70 value &= ~GMAC_INT_DISABLE_PMT;
72 value &= ~GMAC_INT_DISABLE_PCS;
74 writel(value, ioaddr + GMAC_INT_MASK);
76 #ifdef STMMAC_VLAN_TAG_USED
77 /* Tag detection without filtering */
78 writel(0x0, ioaddr + GMAC_VLAN_TAG);
82 static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)
84 void __iomem *ioaddr = hw->pcsr;
85 u32 value = readl(ioaddr + GMAC_CONTROL);
88 value |= GMAC_CONTROL_IPC;
90 value &= ~GMAC_CONTROL_IPC;
92 writel(value, ioaddr + GMAC_CONTROL);
94 value = readl(ioaddr + GMAC_CONTROL);
96 return !!(value & GMAC_CONTROL_IPC);
99 static void dwmac1000_dump_regs(struct mac_device_info *hw)
101 void __iomem *ioaddr = hw->pcsr;
103 pr_info("\tDWMAC1000 regs (base addr = 0x%p)\n", ioaddr);
105 for (i = 0; i < 55; i++) {
107 pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
108 offset, readl(ioaddr + offset));
112 static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
116 void __iomem *ioaddr = hw->pcsr;
117 stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
118 GMAC_ADDR_LOW(reg_n));
121 static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
125 void __iomem *ioaddr = hw->pcsr;
126 stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
127 GMAC_ADDR_LOW(reg_n));
130 static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
133 int numhashregs, regs;
135 switch (mcbitslog2) {
137 writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
138 writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
148 pr_debug("STMMAC: err in setting multicast filter\n");
152 for (regs = 0; regs < numhashregs; regs++)
153 writel(mcfilterbits[regs],
154 ioaddr + GMAC_EXTHASH_BASE + regs * 4);
157 static void dwmac1000_set_filter(struct mac_device_info *hw,
158 struct net_device *dev)
160 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
161 unsigned int value = 0;
162 unsigned int perfect_addr_number = hw->unicast_filter_entries;
164 int mcbitslog2 = hw->mcast_bits_log2;
166 pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,
167 netdev_mc_count(dev), netdev_uc_count(dev));
169 memset(mc_filter, 0, sizeof(mc_filter));
171 if (dev->flags & IFF_PROMISC) {
172 value = GMAC_FRAME_FILTER_PR;
173 } else if (dev->flags & IFF_ALLMULTI) {
174 value = GMAC_FRAME_FILTER_PM; /* pass all multi */
175 } else if (!netdev_mc_empty(dev) && (mcbitslog2 == 0)) {
176 /* Fall back to all multicast if we've no filter */
177 value = GMAC_FRAME_FILTER_PM;
178 } else if (!netdev_mc_empty(dev)) {
179 struct netdev_hw_addr *ha;
181 /* Hash filter for multicast */
182 value = GMAC_FRAME_FILTER_HMC;
184 netdev_for_each_mc_addr(ha, dev) {
185 /* The upper n bits of the calculated CRC are used to
186 * index the contents of the hash table. The number of
187 * bits used depends on the hardware configuration
188 * selected at core configuration time.
190 int bit_nr = bitrev32(~crc32_le(~0, ha->addr,
193 /* The most significant bit determines the register to
194 * use (H/L) while the other 5 bits determine the bit
195 * within the register.
197 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
201 dwmac1000_set_mchash(ioaddr, mc_filter, mcbitslog2);
203 /* Handle multiple unicast addresses (perfect filtering) */
204 if (netdev_uc_count(dev) > perfect_addr_number)
205 /* Switch to promiscuous mode if more than unicast
206 * addresses are requested than supported by hardware.
208 value |= GMAC_FRAME_FILTER_PR;
211 struct netdev_hw_addr *ha;
213 netdev_for_each_uc_addr(ha, dev) {
214 stmmac_set_mac_addr(ioaddr, ha->addr,
220 while (reg < perfect_addr_number) {
221 writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
222 writel(0, ioaddr + GMAC_ADDR_LOW(reg));
227 #ifdef FRAME_FILTER_DEBUG
228 /* Enable Receive all mode (to debug filtering_fail errors) */
229 value |= GMAC_FRAME_FILTER_RA;
231 writel(value, ioaddr + GMAC_FRAME_FILTER);
235 static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
236 unsigned int fc, unsigned int pause_time)
238 void __iomem *ioaddr = hw->pcsr;
239 /* Set flow such that DZPQ in Mac Register 6 is 0,
240 * and unicast pause detect is enabled.
242 unsigned int flow = GMAC_FLOW_CTRL_UP;
244 pr_debug("GMAC Flow-Control:\n");
246 pr_debug("\tReceive Flow-Control ON\n");
247 flow |= GMAC_FLOW_CTRL_RFE;
250 pr_debug("\tTransmit Flow-Control ON\n");
251 flow |= GMAC_FLOW_CTRL_TFE;
255 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
256 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
259 writel(flow, ioaddr + GMAC_FLOW_CTRL);
262 static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)
264 void __iomem *ioaddr = hw->pcsr;
265 unsigned int pmt = 0;
267 if (mode & WAKE_MAGIC) {
268 pr_debug("GMAC: WOL Magic frame\n");
269 pmt |= power_down | magic_pkt_en;
271 if (mode & WAKE_UCAST) {
272 pr_debug("GMAC: WOL on global unicast\n");
273 pmt |= power_down | global_unicast | wake_up_frame_en;
276 writel(pmt, ioaddr + GMAC_PMT);
279 /* RGMII or SMII interface */
280 static void dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x)
284 status = readl(ioaddr + GMAC_RGSMIIIS);
287 /* Check the link status */
288 if (status & GMAC_RGSMIIIS_LNKSTS) {
293 speed_value = ((status & GMAC_RGSMIIIS_SPEED) >>
294 GMAC_RGSMIIIS_SPEED_SHIFT);
295 if (speed_value == GMAC_RGSMIIIS_SPEED_125)
296 x->pcs_speed = SPEED_1000;
297 else if (speed_value == GMAC_RGSMIIIS_SPEED_25)
298 x->pcs_speed = SPEED_100;
300 x->pcs_speed = SPEED_10;
302 x->pcs_duplex = (status & GMAC_RGSMIIIS_LNKMOD_MASK);
304 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
305 x->pcs_duplex ? "Full" : "Half");
308 pr_info("Link is Down\n");
312 static int dwmac1000_irq_status(struct mac_device_info *hw,
313 struct stmmac_extra_stats *x)
315 void __iomem *ioaddr = hw->pcsr;
316 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
317 u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
320 /* Discard masked bits */
321 intr_status &= ~intr_mask;
323 /* Not used events (e.g. MMC interrupts) are not handled. */
324 if ((intr_status & GMAC_INT_STATUS_MMCTIS))
326 if (unlikely(intr_status & GMAC_INT_STATUS_MMCRIS))
328 if (unlikely(intr_status & GMAC_INT_STATUS_MMCCSUM))
329 x->mmc_rx_csum_offload_irq_n++;
330 if (unlikely(intr_status & GMAC_INT_DISABLE_PMT)) {
331 /* clear the PMT bits 5 and 6 by reading the PMT status reg */
332 readl(ioaddr + GMAC_PMT);
333 x->irq_receive_pmt_irq_n++;
336 /* MAC tx/rx EEE LPI entry/exit interrupts */
337 if (intr_status & GMAC_INT_STATUS_LPIIS) {
338 /* Clean LPI interrupt by reading the Reg 12 */
339 ret = readl(ioaddr + LPI_CTRL_STATUS);
341 if (ret & LPI_CTRL_STATUS_TLPIEN)
342 x->irq_tx_path_in_lpi_mode_n++;
343 if (ret & LPI_CTRL_STATUS_TLPIEX)
344 x->irq_tx_path_exit_lpi_mode_n++;
345 if (ret & LPI_CTRL_STATUS_RLPIEN)
346 x->irq_rx_path_in_lpi_mode_n++;
347 if (ret & LPI_CTRL_STATUS_RLPIEX)
348 x->irq_rx_path_exit_lpi_mode_n++;
351 dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
353 if (intr_status & PCS_RGSMIIIS_IRQ)
354 dwmac1000_rgsmii(ioaddr, x);
359 static void dwmac1000_set_eee_mode(struct mac_device_info *hw)
361 void __iomem *ioaddr = hw->pcsr;
364 /* Enable the link status receive on RGMII, SGMII ore SMII
365 * receive path and instruct the transmit to enter in LPI
368 value = readl(ioaddr + LPI_CTRL_STATUS);
369 value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
370 writel(value, ioaddr + LPI_CTRL_STATUS);
373 static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)
375 void __iomem *ioaddr = hw->pcsr;
378 value = readl(ioaddr + LPI_CTRL_STATUS);
379 value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
380 writel(value, ioaddr + LPI_CTRL_STATUS);
383 static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)
385 void __iomem *ioaddr = hw->pcsr;
388 value = readl(ioaddr + LPI_CTRL_STATUS);
391 value |= LPI_CTRL_STATUS_PLS;
393 value &= ~LPI_CTRL_STATUS_PLS;
395 writel(value, ioaddr + LPI_CTRL_STATUS);
398 static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
400 void __iomem *ioaddr = hw->pcsr;
401 int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
403 /* Program the timers in the LPI timer control register:
404 * LS: minimum time (ms) for which the link
405 * status from PHY should be ok before transmitting
407 * TW: minimum time (us) for which the core waits
408 * after it has stopped transmitting the LPI pattern.
410 writel(value, ioaddr + LPI_TIMER_CTRL);
413 static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
416 dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
419 static void dwmac1000_rane(void __iomem *ioaddr, bool restart)
421 dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
424 static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
426 dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
429 static void dwmac1000_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x)
431 u32 value = readl(ioaddr + GMAC_DEBUG);
433 if (value & GMAC_DEBUG_TXSTSFSTS)
434 x->mtl_tx_status_fifo_full++;
435 if (value & GMAC_DEBUG_TXFSTS)
436 x->mtl_tx_fifo_not_empty++;
437 if (value & GMAC_DEBUG_TWCSTS)
439 if (value & GMAC_DEBUG_TRCSTS_MASK) {
440 u32 trcsts = (value & GMAC_DEBUG_TRCSTS_MASK)
441 >> GMAC_DEBUG_TRCSTS_SHIFT;
442 if (trcsts == GMAC_DEBUG_TRCSTS_WRITE)
443 x->mtl_tx_fifo_read_ctrl_write++;
444 else if (trcsts == GMAC_DEBUG_TRCSTS_TXW)
445 x->mtl_tx_fifo_read_ctrl_wait++;
446 else if (trcsts == GMAC_DEBUG_TRCSTS_READ)
447 x->mtl_tx_fifo_read_ctrl_read++;
449 x->mtl_tx_fifo_read_ctrl_idle++;
451 if (value & GMAC_DEBUG_TXPAUSED)
452 x->mac_tx_in_pause++;
453 if (value & GMAC_DEBUG_TFCSTS_MASK) {
454 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
455 >> GMAC_DEBUG_TFCSTS_SHIFT;
457 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
458 x->mac_tx_frame_ctrl_xfer++;
459 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
460 x->mac_tx_frame_ctrl_pause++;
461 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
462 x->mac_tx_frame_ctrl_wait++;
464 x->mac_tx_frame_ctrl_idle++;
466 if (value & GMAC_DEBUG_TPESTS)
467 x->mac_gmii_tx_proto_engine++;
468 if (value & GMAC_DEBUG_RXFSTS_MASK) {
469 u32 rxfsts = (value & GMAC_DEBUG_RXFSTS_MASK)
470 >> GMAC_DEBUG_RRCSTS_SHIFT;
472 if (rxfsts == GMAC_DEBUG_RXFSTS_FULL)
473 x->mtl_rx_fifo_fill_level_full++;
474 else if (rxfsts == GMAC_DEBUG_RXFSTS_AT)
475 x->mtl_rx_fifo_fill_above_thresh++;
476 else if (rxfsts == GMAC_DEBUG_RXFSTS_BT)
477 x->mtl_rx_fifo_fill_below_thresh++;
479 x->mtl_rx_fifo_fill_level_empty++;
481 if (value & GMAC_DEBUG_RRCSTS_MASK) {
482 u32 rrcsts = (value & GMAC_DEBUG_RRCSTS_MASK) >>
483 GMAC_DEBUG_RRCSTS_SHIFT;
485 if (rrcsts == GMAC_DEBUG_RRCSTS_FLUSH)
486 x->mtl_rx_fifo_read_ctrl_flush++;
487 else if (rrcsts == GMAC_DEBUG_RRCSTS_RSTAT)
488 x->mtl_rx_fifo_read_ctrl_read_data++;
489 else if (rrcsts == GMAC_DEBUG_RRCSTS_RDATA)
490 x->mtl_rx_fifo_read_ctrl_status++;
492 x->mtl_rx_fifo_read_ctrl_idle++;
494 if (value & GMAC_DEBUG_RWCSTS)
495 x->mtl_rx_fifo_ctrl_active++;
496 if (value & GMAC_DEBUG_RFCFCSTS_MASK)
497 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
498 >> GMAC_DEBUG_RFCFCSTS_SHIFT;
499 if (value & GMAC_DEBUG_RPESTS)
500 x->mac_gmii_rx_proto_engine++;
503 static const struct stmmac_ops dwmac1000_ops = {
504 .core_init = dwmac1000_core_init,
505 .rx_ipc = dwmac1000_rx_ipc_enable,
506 .dump_regs = dwmac1000_dump_regs,
507 .host_irq_status = dwmac1000_irq_status,
508 .set_filter = dwmac1000_set_filter,
509 .flow_ctrl = dwmac1000_flow_ctrl,
510 .pmt = dwmac1000_pmt,
511 .set_umac_addr = dwmac1000_set_umac_addr,
512 .get_umac_addr = dwmac1000_get_umac_addr,
513 .set_eee_mode = dwmac1000_set_eee_mode,
514 .reset_eee_mode = dwmac1000_reset_eee_mode,
515 .set_eee_timer = dwmac1000_set_eee_timer,
516 .set_eee_pls = dwmac1000_set_eee_pls,
517 .debug = dwmac1000_debug,
518 .pcs_ctrl_ane = dwmac1000_ctrl_ane,
519 .pcs_rane = dwmac1000_rane,
520 .pcs_get_adv_lp = dwmac1000_get_adv_lp,
523 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
524 int perfect_uc_entries,
527 struct mac_device_info *mac;
528 u32 hwid = readl(ioaddr + GMAC_VERSION);
530 mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
535 mac->multicast_filter_bins = mcbins;
536 mac->unicast_filter_entries = perfect_uc_entries;
537 mac->mcast_bits_log2 = 0;
539 if (mac->multicast_filter_bins)
540 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
542 mac->mac = &dwmac1000_ops;
543 mac->dma = &dwmac1000_dma_ops;
545 mac->link.port = GMAC_CONTROL_PS;
546 mac->link.duplex = GMAC_CONTROL_DM;
547 mac->link.speed = GMAC_CONTROL_FES;
548 mac->mii.addr = GMAC_MII_ADDR;
549 mac->mii.data = GMAC_MII_DATA;
551 /* Get and dump the chip ID */
552 *synopsys_id = stmmac_get_synopsys_id(hwid);