1 /* Copyright Altera Corporation (C) 2014. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License, version 2,
5 * as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 * Adopted from dwmac-sti.c
18 #include <linux/mfd/syscon.h>
20 #include <linux/of_address.h>
21 #include <linux/of_net.h>
22 #include <linux/phy.h>
23 #include <linux/regmap.h>
24 #include <linux/reset.h>
25 #include <linux/stmmac.h>
28 #include "stmmac_platform.h"
30 #include "altr_tse_pcs.h"
32 #define SGMII_ADAPTER_CTRL_REG 0x00
33 #define SGMII_ADAPTER_DISABLE 0x0001
35 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
36 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
37 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
38 #define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
39 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
40 #define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010
42 #define SYSMGR_FPGAGRP_MODULE_REG 0x00000028
43 #define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004
45 #define EMAC_SPLITTER_CTRL_REG 0x0
46 #define EMAC_SPLITTER_CTRL_SPEED_MASK 0x3
47 #define EMAC_SPLITTER_CTRL_SPEED_10 0x2
48 #define EMAC_SPLITTER_CTRL_SPEED_100 0x3
49 #define EMAC_SPLITTER_CTRL_SPEED_1000 0x0
51 struct socfpga_dwmac {
56 struct regmap *sys_mgr_base_addr;
57 struct reset_control *stmmac_rst;
58 struct reset_control *stmmac_ocp_rst;
59 void __iomem *splitter_base;
64 static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed)
66 struct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)priv;
67 void __iomem *splitter_base = dwmac->splitter_base;
68 void __iomem *tse_pcs_base = dwmac->pcs.tse_pcs_base;
69 void __iomem *sgmii_adapter_base = dwmac->pcs.sgmii_adapter_base;
70 struct device *dev = dwmac->dev;
71 struct net_device *ndev = dev_get_drvdata(dev);
72 struct phy_device *phy_dev = ndev->phydev;
75 if ((tse_pcs_base) && (sgmii_adapter_base))
76 writew(SGMII_ADAPTER_DISABLE,
77 sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
80 val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG);
81 val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK;
85 val |= EMAC_SPLITTER_CTRL_SPEED_1000;
88 val |= EMAC_SPLITTER_CTRL_SPEED_100;
91 val |= EMAC_SPLITTER_CTRL_SPEED_10;
96 writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG);
99 if (tse_pcs_base && sgmii_adapter_base)
100 tse_pcs_fix_mac_speed(&dwmac->pcs, phy_dev, speed);
103 static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev)
105 struct device_node *np = dev->of_node;
106 struct regmap *sys_mgr_base_addr;
107 u32 reg_offset, reg_shift;
109 struct device_node *np_splitter = NULL;
110 struct device_node *np_sgmii_adapter = NULL;
111 struct resource res_splitter;
112 struct resource res_tse_pcs;
113 struct resource res_sgmii_adapter;
115 dwmac->interface = of_get_phy_mode(np);
117 sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
118 if (IS_ERR(sys_mgr_base_addr)) {
119 dev_info(dev, "No sysmgr-syscon node found\n");
120 return PTR_ERR(sys_mgr_base_addr);
123 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset);
125 dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n");
129 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift);
131 dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n");
135 dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk");
137 np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0);
139 ret = of_address_to_resource(np_splitter, 0, &res_splitter);
140 of_node_put(np_splitter);
142 dev_info(dev, "Missing emac splitter address\n");
146 dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter);
147 if (IS_ERR(dwmac->splitter_base)) {
148 dev_info(dev, "Failed to mapping emac splitter\n");
149 return PTR_ERR(dwmac->splitter_base);
153 np_sgmii_adapter = of_parse_phandle(np,
154 "altr,gmii-to-sgmii-converter", 0);
155 if (np_sgmii_adapter) {
156 index = of_property_match_string(np_sgmii_adapter, "reg-names",
157 "hps_emac_interface_splitter_avalon_slave");
160 if (of_address_to_resource(np_sgmii_adapter, index,
163 "%s: ERROR: missing emac splitter address\n",
169 dwmac->splitter_base =
170 devm_ioremap_resource(dev, &res_splitter);
172 if (IS_ERR(dwmac->splitter_base)) {
173 ret = PTR_ERR(dwmac->splitter_base);
178 index = of_property_match_string(np_sgmii_adapter, "reg-names",
179 "gmii_to_sgmii_adapter_avalon_slave");
182 if (of_address_to_resource(np_sgmii_adapter, index,
183 &res_sgmii_adapter)) {
185 "%s: ERROR: failed mapping adapter\n",
191 dwmac->pcs.sgmii_adapter_base =
192 devm_ioremap_resource(dev, &res_sgmii_adapter);
194 if (IS_ERR(dwmac->pcs.sgmii_adapter_base)) {
195 ret = PTR_ERR(dwmac->pcs.sgmii_adapter_base);
200 index = of_property_match_string(np_sgmii_adapter, "reg-names",
201 "eth_tse_control_port");
204 if (of_address_to_resource(np_sgmii_adapter, index,
207 "%s: ERROR: failed mapping tse control port\n",
213 dwmac->pcs.tse_pcs_base =
214 devm_ioremap_resource(dev, &res_tse_pcs);
216 if (IS_ERR(dwmac->pcs.tse_pcs_base)) {
217 ret = PTR_ERR(dwmac->pcs.tse_pcs_base);
222 dwmac->reg_offset = reg_offset;
223 dwmac->reg_shift = reg_shift;
224 dwmac->sys_mgr_base_addr = sys_mgr_base_addr;
226 of_node_put(np_sgmii_adapter);
231 of_node_put(np_sgmii_adapter);
235 static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac)
237 struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
238 int phymode = dwmac->interface;
239 u32 reg_offset = dwmac->reg_offset;
240 u32 reg_shift = dwmac->reg_shift;
241 u32 ctrl, val, module;
244 case PHY_INTERFACE_MODE_RGMII:
245 case PHY_INTERFACE_MODE_RGMII_ID:
246 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
248 case PHY_INTERFACE_MODE_MII:
249 case PHY_INTERFACE_MODE_GMII:
250 case PHY_INTERFACE_MODE_SGMII:
251 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
254 dev_err(dwmac->dev, "bad phy mode %d\n", phymode);
258 /* Overwrite val to GMII if splitter core is enabled. The phymode here
259 * is the actual phy mode on phy hardware, but phy interface from
262 if (dwmac->splitter_base)
263 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
265 /* Assert reset to the enet controller before changing the phy mode */
266 reset_control_assert(dwmac->stmmac_ocp_rst);
267 reset_control_assert(dwmac->stmmac_rst);
269 regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
270 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
271 ctrl |= val << reg_shift;
273 if (dwmac->f2h_ptp_ref_clk) {
274 ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
275 regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
277 module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2));
278 regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
281 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2));
284 regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
286 /* Deassert reset for the phy configuration to be sampled by
287 * the enet controller, and operation to start in requested mode
289 reset_control_deassert(dwmac->stmmac_ocp_rst);
290 reset_control_deassert(dwmac->stmmac_rst);
291 if (phymode == PHY_INTERFACE_MODE_SGMII) {
292 if (tse_pcs_init(dwmac->pcs.tse_pcs_base, &dwmac->pcs) != 0) {
293 dev_err(dwmac->dev, "Unable to initialize TSE PCS");
301 static int socfpga_dwmac_probe(struct platform_device *pdev)
303 struct plat_stmmacenet_data *plat_dat;
304 struct stmmac_resources stmmac_res;
305 struct device *dev = &pdev->dev;
307 struct socfpga_dwmac *dwmac;
308 struct net_device *ndev;
309 struct stmmac_priv *stpriv;
311 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
315 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
316 if (IS_ERR(plat_dat))
317 return PTR_ERR(plat_dat);
319 dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL);
322 goto err_remove_config_dt;
325 dwmac->stmmac_ocp_rst = devm_reset_control_get_optional(dev, "stmmaceth-ocp");
326 if (IS_ERR(dwmac->stmmac_ocp_rst)) {
327 ret = PTR_ERR(dwmac->stmmac_ocp_rst);
328 dev_err(dev, "error getting reset control of ocp %d\n", ret);
329 goto err_remove_config_dt;
332 reset_control_deassert(dwmac->stmmac_ocp_rst);
334 ret = socfpga_dwmac_parse_data(dwmac, dev);
336 dev_err(dev, "Unable to parse OF data\n");
337 goto err_remove_config_dt;
340 plat_dat->bsp_priv = dwmac;
341 plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
343 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
345 goto err_remove_config_dt;
347 ndev = platform_get_drvdata(pdev);
348 stpriv = netdev_priv(ndev);
350 /* The socfpga driver needs to control the stmmac reset to set the phy
351 * mode. Create a copy of the core reset handle so it can be used by
354 dwmac->stmmac_rst = stpriv->stmmac_rst;
356 ret = socfpga_dwmac_set_phy_mode(dwmac);
363 stmmac_dvr_remove(&pdev->dev);
364 err_remove_config_dt:
365 stmmac_remove_config_dt(pdev, plat_dat);
370 #ifdef CONFIG_PM_SLEEP
371 static int socfpga_dwmac_resume(struct device *dev)
373 struct net_device *ndev = dev_get_drvdata(dev);
374 struct stmmac_priv *priv = netdev_priv(ndev);
376 socfpga_dwmac_set_phy_mode(priv->plat->bsp_priv);
378 /* Before the enet controller is suspended, the phy is suspended.
379 * This causes the phy clock to be gated. The enet controller is
380 * resumed before the phy, so the clock is still gated "off" when
381 * the enet controller is resumed. This code makes sure the phy
382 * is "resumed" before reinitializing the enet controller since
383 * the enet controller depends on an active phy clock to complete
384 * a DMA reset. A DMA reset will "time out" if executed
385 * with no phy clock input on the Synopsys enet controller.
386 * Verified through Synopsys Case #8000711656.
388 * Note that the phy clock is also gated when the phy is isolated.
389 * Phy "suspend" and "isolate" controls are located in phy basic
390 * control register 0, and can be modified by the phy driver
394 phy_resume(priv->phydev);
396 return stmmac_resume(dev);
398 #endif /* CONFIG_PM_SLEEP */
400 static SIMPLE_DEV_PM_OPS(socfpga_dwmac_pm_ops, stmmac_suspend,
401 socfpga_dwmac_resume);
403 static const struct of_device_id socfpga_dwmac_match[] = {
404 { .compatible = "altr,socfpga-stmmac" },
407 MODULE_DEVICE_TABLE(of, socfpga_dwmac_match);
409 static struct platform_driver socfpga_dwmac_driver = {
410 .probe = socfpga_dwmac_probe,
411 .remove = stmmac_pltfr_remove,
413 .name = "socfpga-dwmac",
414 .pm = &socfpga_dwmac_pm_ops,
415 .of_match_table = socfpga_dwmac_match,
418 module_platform_driver(socfpga_dwmac_driver);
420 MODULE_LICENSE("GPL v2");