1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*******************************************************************************
3 STMMAC Common Header File
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9 *******************************************************************************/
14 #include <linux/etherdevice.h>
15 #include <linux/netdevice.h>
16 #include <linux/stmmac.h>
17 #include <linux/phy.h>
18 #include <linux/pcs/pcs-xpcs.h>
19 #include <linux/module.h>
20 #if IS_ENABLED(CONFIG_VLAN_8021Q)
21 #define STMMAC_VLAN_TAG_USED
22 #include <linux/if_vlan.h>
29 /* Synopsys Core versions */
30 #define DWMAC_CORE_3_40 0x34
31 #define DWMAC_CORE_3_50 0x35
32 #define DWMAC_CORE_4_00 0x40
33 #define DWMAC_CORE_4_10 0x41
34 #define DWMAC_CORE_5_00 0x50
35 #define DWMAC_CORE_5_10 0x51
36 #define DWXGMAC_CORE_2_10 0x21
37 #define DWXLGMAC_CORE_2_00 0x20
40 #define DWXGMAC_ID 0x76
41 #define DWXLGMAC_ID 0x27
43 #define STMMAC_CHAN0 0 /* Always supported and default for all chips */
45 /* TX and RX Descriptor Length, these need to be power of two.
46 * TX descriptor length less than 64 may cause transmit queue timed out error.
47 * RX descriptor length less than 64 may cause inconsistent Rx chain error.
49 #define DMA_MIN_TX_SIZE 64
50 #define DMA_MAX_TX_SIZE 1024
51 #define DMA_DEFAULT_TX_SIZE 512
52 #define DMA_MIN_RX_SIZE 64
53 #define DMA_MAX_RX_SIZE 1024
54 #define DMA_DEFAULT_RX_SIZE 512
55 #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
57 #undef FRAME_FILTER_DEBUG
58 /* #define FRAME_FILTER_DEBUG */
60 /* Extra statistic and debug information exposed by ethtool */
61 struct stmmac_extra_stats {
63 unsigned long tx_underflow ____cacheline_aligned;
64 unsigned long tx_carrier;
65 unsigned long tx_losscarrier;
66 unsigned long vlan_tag;
67 unsigned long tx_deferred;
68 unsigned long tx_vlan;
69 unsigned long tx_jabber;
70 unsigned long tx_frame_flushed;
71 unsigned long tx_payload_error;
72 unsigned long tx_ip_header_error;
74 unsigned long rx_desc;
75 unsigned long sa_filter_fail;
76 unsigned long overflow_error;
77 unsigned long ipc_csum_error;
78 unsigned long rx_collision;
79 unsigned long rx_crc_errors;
80 unsigned long dribbling_bit;
81 unsigned long rx_length;
83 unsigned long rx_multicast;
84 unsigned long rx_gmac_overflow;
85 unsigned long rx_watchdog;
86 unsigned long da_rx_filter_fail;
87 unsigned long sa_rx_filter_fail;
88 unsigned long rx_missed_cntr;
89 unsigned long rx_overflow_cntr;
90 unsigned long rx_vlan;
91 unsigned long rx_split_hdr_pkt_n;
92 /* Tx/Rx IRQ error info */
93 unsigned long tx_undeflow_irq;
94 unsigned long tx_process_stopped_irq;
95 unsigned long tx_jabber_irq;
96 unsigned long rx_overflow_irq;
97 unsigned long rx_buf_unav_irq;
98 unsigned long rx_process_stopped_irq;
99 unsigned long rx_watchdog_irq;
100 unsigned long tx_early_irq;
101 unsigned long fatal_bus_error_irq;
102 /* Tx/Rx IRQ Events */
103 unsigned long rx_early_irq;
104 unsigned long threshold;
105 unsigned long tx_pkt_n;
106 unsigned long rx_pkt_n;
107 unsigned long normal_irq_n;
108 unsigned long rx_normal_irq_n;
109 unsigned long napi_poll;
110 unsigned long tx_normal_irq_n;
111 unsigned long tx_clean;
112 unsigned long tx_set_ic_bit;
113 unsigned long irq_receive_pmt_irq_n;
115 unsigned long mmc_tx_irq_n;
116 unsigned long mmc_rx_irq_n;
117 unsigned long mmc_rx_csum_offload_irq_n;
119 unsigned long irq_tx_path_in_lpi_mode_n;
120 unsigned long irq_tx_path_exit_lpi_mode_n;
121 unsigned long irq_rx_path_in_lpi_mode_n;
122 unsigned long irq_rx_path_exit_lpi_mode_n;
123 unsigned long phy_eee_wakeup_error_n;
124 /* Extended RDES status */
125 unsigned long ip_hdr_err;
126 unsigned long ip_payload_err;
127 unsigned long ip_csum_bypassed;
128 unsigned long ipv4_pkt_rcvd;
129 unsigned long ipv6_pkt_rcvd;
130 unsigned long no_ptp_rx_msg_type_ext;
131 unsigned long ptp_rx_msg_type_sync;
132 unsigned long ptp_rx_msg_type_follow_up;
133 unsigned long ptp_rx_msg_type_delay_req;
134 unsigned long ptp_rx_msg_type_delay_resp;
135 unsigned long ptp_rx_msg_type_pdelay_req;
136 unsigned long ptp_rx_msg_type_pdelay_resp;
137 unsigned long ptp_rx_msg_type_pdelay_follow_up;
138 unsigned long ptp_rx_msg_type_announce;
139 unsigned long ptp_rx_msg_type_management;
140 unsigned long ptp_rx_msg_pkt_reserved_type;
141 unsigned long ptp_frame_type;
142 unsigned long ptp_ver;
143 unsigned long timestamp_dropped;
144 unsigned long av_pkt_rcvd;
145 unsigned long av_tagged_pkt_rcvd;
146 unsigned long vlan_tag_priority_val;
147 unsigned long l3_filter_match;
148 unsigned long l4_filter_match;
149 unsigned long l3_l4_filter_no_match;
151 unsigned long irq_pcs_ane_n;
152 unsigned long irq_pcs_link_n;
153 unsigned long irq_rgmii_n;
154 unsigned long pcs_link;
155 unsigned long pcs_duplex;
156 unsigned long pcs_speed;
158 unsigned long mtl_tx_status_fifo_full;
159 unsigned long mtl_tx_fifo_not_empty;
160 unsigned long mmtl_fifo_ctrl;
161 unsigned long mtl_tx_fifo_read_ctrl_write;
162 unsigned long mtl_tx_fifo_read_ctrl_wait;
163 unsigned long mtl_tx_fifo_read_ctrl_read;
164 unsigned long mtl_tx_fifo_read_ctrl_idle;
165 unsigned long mac_tx_in_pause;
166 unsigned long mac_tx_frame_ctrl_xfer;
167 unsigned long mac_tx_frame_ctrl_idle;
168 unsigned long mac_tx_frame_ctrl_wait;
169 unsigned long mac_tx_frame_ctrl_pause;
170 unsigned long mac_gmii_tx_proto_engine;
171 unsigned long mtl_rx_fifo_fill_level_full;
172 unsigned long mtl_rx_fifo_fill_above_thresh;
173 unsigned long mtl_rx_fifo_fill_below_thresh;
174 unsigned long mtl_rx_fifo_fill_level_empty;
175 unsigned long mtl_rx_fifo_read_ctrl_flush;
176 unsigned long mtl_rx_fifo_read_ctrl_read_data;
177 unsigned long mtl_rx_fifo_read_ctrl_status;
178 unsigned long mtl_rx_fifo_read_ctrl_idle;
179 unsigned long mtl_rx_fifo_ctrl_active;
180 unsigned long mac_rx_frame_ctrl_fifo;
181 unsigned long mac_gmii_rx_proto_engine;
183 unsigned long tx_tso_frames;
184 unsigned long tx_tso_nfrags;
187 /* Safety Feature statistics exposed by ethtool */
188 struct stmmac_safety_stats {
189 unsigned long mac_errors[32];
190 unsigned long mtl_errors[32];
191 unsigned long dma_errors[32];
192 unsigned long dma_dpp_errors[32];
195 /* Number of fields in Safety Stats */
196 #define STMMAC_SAFETY_FEAT_SIZE \
197 (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))
199 /* CSR Frequency Access Defines*/
200 #define CSR_F_35M 35000000
201 #define CSR_F_60M 60000000
202 #define CSR_F_100M 100000000
203 #define CSR_F_150M 150000000
204 #define CSR_F_250M 250000000
205 #define CSR_F_300M 300000000
207 #define MAC_CSR_H_FRQ_MASK 0x20
209 #define HASH_TABLE_SIZE 64
210 #define PAUSE_TIME 0xffff
212 /* Flow Control defines */
216 #define FLOW_AUTO (FLOW_TX | FLOW_RX)
219 #define STMMAC_PCS_RGMII (1 << 0)
220 #define STMMAC_PCS_SGMII (1 << 1)
221 #define STMMAC_PCS_TBI (1 << 2)
222 #define STMMAC_PCS_RTBI (1 << 3)
224 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
226 /* DAM HW feature register fields */
227 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
228 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
229 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
230 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
231 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
232 #define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
233 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
234 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
235 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
236 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
237 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
238 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
239 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
240 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
241 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
242 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
243 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
244 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
245 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
246 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
247 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
248 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
249 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
250 /* Timestamping with Internal System Time */
251 #define DMA_HW_FEAT_INTTSEN 0x02000000
252 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
253 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
254 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
255 #define DEFAULT_DMA_PBL 8
257 /* PCS status and mask defines */
258 #define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */
259 #define PCS_LINK_IRQ BIT(1) /* PCS Link */
260 #define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */
262 /* Max/Min RI Watchdog Timer count value */
263 #define MAX_DMA_RIWT 0xff
264 #define MIN_DMA_RIWT 0x10
265 #define DEF_DMA_RIWT 0xa0
266 /* Tx coalesce parameters */
267 #define STMMAC_COAL_TX_TIMER 1000
268 #define STMMAC_MAX_COAL_TX_TICK 100000
269 #define STMMAC_TX_MAX_FRAMES 256
270 #define STMMAC_TX_FRAMES 25
271 #define STMMAC_RX_FRAMES 0
275 PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */
276 PACKET_PTPQ = 0x2, /* PTP Packets */
277 PACKET_DCBCPQ = 0x3, /* DCB Control Packets */
278 PACKET_UPQ = 0x4, /* Untagged Packets */
279 PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */
283 enum rx_frame_status {
293 enum tx_frame_status {
300 enum dma_irq_status {
302 tx_hard_error_bump_tc = 0x2,
307 /* EEE and LPI defines */
308 #define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
309 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
310 #define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
311 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
313 #define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
315 /* Physical Coding Sublayer */
319 unsigned int lp_pause;
320 unsigned int lp_duplex;
323 #define STMMAC_PCS_PAUSE 1
324 #define STMMAC_PCS_ASYM_PAUSE 2
326 /* DMA HW capabilities */
327 struct dma_features {
328 unsigned int mbps_10_100;
329 unsigned int mbps_1000;
330 unsigned int half_duplex;
331 unsigned int hash_filter;
332 unsigned int multi_addr;
334 unsigned int sma_mdio;
335 unsigned int pmt_remote_wake_up;
336 unsigned int pmt_magic_frame;
339 unsigned int time_stamp;
341 unsigned int atime_stamp;
342 /* 802.3az - Energy-Efficient Ethernet (EEE) */
345 unsigned int hash_tb_sz;
350 unsigned int rx_coe_type1;
351 unsigned int rx_coe_type2;
352 unsigned int rxfifo_over_2048;
353 /* TX and RX number of channels */
354 unsigned int number_rx_channel;
355 unsigned int number_tx_channel;
356 /* TX and RX number of queues */
357 unsigned int number_rx_queues;
358 unsigned int number_tx_queues;
360 unsigned int pps_out_num;
361 /* Alternate (enhanced) DESC mode */
362 unsigned int enh_desc;
363 /* TX and RX FIFO sizes */
364 unsigned int tx_fifo_size;
365 unsigned int rx_fifo_size;
366 /* Automotive Safety Package */
378 unsigned int l3l4fnum;
379 unsigned int arpoffsel;
388 /* RX Buffer size must be multiple of 4/8/16 bytes */
389 #define BUF_SIZE_16KiB 16368
390 #define BUF_SIZE_8KiB 8188
391 #define BUF_SIZE_4KiB 4096
392 #define BUF_SIZE_2KiB 2048
394 /* Power Down and WOL */
395 #define PMT_NOT_SUPPORTED 0
396 #define PMT_SUPPORTED 1
398 /* Common MAC defines */
399 #define MAC_CTRL_REG 0x00000000 /* MAC Control */
400 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
401 #define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
403 /* Default LPI timers */
404 #define STMMAC_DEFAULT_LIT_LS 0x3E8
405 #define STMMAC_DEFAULT_TWT_LS 0x1E
407 #define STMMAC_CHAIN_MODE 0x1
408 #define STMMAC_RING_MODE 0x2
410 #define JUMBO_LEN 9000
412 /* Receive Side Scaling */
413 #define STMMAC_RSS_HASH_KEY_SIZE 40
414 #define STMMAC_RSS_MAX_TABLE_SIZE 256
417 #define STMMAC_VLAN_NONE 0x0
418 #define STMMAC_VLAN_REMOVE 0x1
419 #define STMMAC_VLAN_INSERT 0x2
420 #define STMMAC_VLAN_REPLACE 0x3
422 extern const struct stmmac_desc_ops enh_desc_ops;
423 extern const struct stmmac_desc_ops ndesc_ops;
425 struct mac_device_info;
427 extern const struct stmmac_hwtimestamp stmmac_ptp;
428 extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
451 unsigned int addr; /* MII Address */
452 unsigned int data; /* MII Data */
453 unsigned int addr_shift; /* MII address shift */
454 unsigned int reg_shift; /* MII reg shift */
455 unsigned int addr_mask; /* MII address mask */
456 unsigned int reg_mask; /* MII reg mask */
457 unsigned int clk_csr_shift;
458 unsigned int clk_csr_mask;
461 struct mac_device_info {
462 const struct stmmac_ops *mac;
463 const struct stmmac_desc_ops *desc;
464 const struct stmmac_dma_ops *dma;
465 const struct stmmac_mode_ops *mode;
466 const struct stmmac_hwtimestamp *ptp;
467 const struct stmmac_tc_ops *tc;
468 const struct stmmac_mmc_ops *mmc;
469 const struct mdio_xpcs_ops *xpcs;
470 struct mdio_xpcs_args xpcs_args;
471 struct mii_regs mii; /* MII register Addresses */
472 struct mac_link link;
473 void __iomem *pcsr; /* vpointer to device CSRs */
474 unsigned int multicast_filter_bins;
475 unsigned int unicast_filter_entries;
476 unsigned int mcast_bits_log2;
477 unsigned int rx_csum;
482 unsigned int num_vlan;
488 struct stmmac_rx_routing {
493 int dwmac100_setup(struct stmmac_priv *priv);
494 int dwmac1000_setup(struct stmmac_priv *priv);
495 int dwmac4_setup(struct stmmac_priv *priv);
496 int dwxgmac2_setup(struct stmmac_priv *priv);
497 int dwxlgmac2_setup(struct stmmac_priv *priv);
499 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
500 unsigned int high, unsigned int low);
501 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
502 unsigned int high, unsigned int low);
503 void stmmac_set_mac(void __iomem *ioaddr, bool enable);
505 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
506 unsigned int high, unsigned int low);
507 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
508 unsigned int high, unsigned int low);
509 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
511 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
513 extern const struct stmmac_mode_ops ring_mode_ops;
514 extern const struct stmmac_mode_ops chain_mode_ops;
515 extern const struct stmmac_desc_ops dwmac4_desc_ops;
517 #endif /* __COMMON_H__ */