drivers/net/ethernet/socionext/netsec.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 #include <linux/types.h>
   4 #include <linux/clk.h>
   5 #include <linux/platform_device.h>
   6 #include <linux/pm_runtime.h>
   7 #include <linux/acpi.h>
   8 #include <linux/of_mdio.h>
   9 #include <linux/etherdevice.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/io.h>
  12
  13 #include <net/tcp.h>
  14 #include <net/ip6_checksum.h>
  15
  16 #define NETSEC_REG_SOFT_RST                     0x104
  17 #define NETSEC_REG_COM_INIT                     0x120
  18
  19 #define NETSEC_REG_TOP_STATUS                   0x200
  20 #define NETSEC_IRQ_RX                           BIT(1)
  21 #define NETSEC_IRQ_TX                           BIT(0)
  22
  23 #define NETSEC_REG_TOP_INTEN                    0x204
  24 #define NETSEC_REG_INTEN_SET                    0x234
  25 #define NETSEC_REG_INTEN_CLR                    0x238
  26
  27 #define NETSEC_REG_NRM_TX_STATUS                0x400
  28 #define NETSEC_REG_NRM_TX_INTEN                 0x404
  29 #define NETSEC_REG_NRM_TX_INTEN_SET             0x428
  30 #define NETSEC_REG_NRM_TX_INTEN_CLR             0x42c
  31 #define NRM_TX_ST_NTOWNR        BIT(17)
  32 #define NRM_TX_ST_TR_ERR        BIT(16)
  33 #define NRM_TX_ST_TXDONE        BIT(15)
  34 #define NRM_TX_ST_TMREXP        BIT(14)
  35
  36 #define NETSEC_REG_NRM_RX_STATUS                0x440
  37 #define NETSEC_REG_NRM_RX_INTEN                 0x444
  38 #define NETSEC_REG_NRM_RX_INTEN_SET             0x468
  39 #define NETSEC_REG_NRM_RX_INTEN_CLR             0x46c
  40 #define NRM_RX_ST_RC_ERR        BIT(16)
  41 #define NRM_RX_ST_PKTCNT        BIT(15)
  42 #define NRM_RX_ST_TMREXP        BIT(14)
  43
  44 #define NETSEC_REG_PKT_CMD_BUF                  0xd0
  45
  46 #define NETSEC_REG_CLK_EN                       0x100
  47
  48 #define NETSEC_REG_PKT_CTRL                     0x140
  49
  50 #define NETSEC_REG_DMA_TMR_CTRL                 0x20c
  51 #define NETSEC_REG_F_TAIKI_MC_VER               0x22c
  52 #define NETSEC_REG_F_TAIKI_VER                  0x230
  53 #define NETSEC_REG_DMA_HM_CTRL                  0x214
  54 #define NETSEC_REG_DMA_MH_CTRL                  0x220
  55 #define NETSEC_REG_ADDR_DIS_CORE                0x218
  56 #define NETSEC_REG_DMAC_HM_CMD_BUF              0x210
  57 #define NETSEC_REG_DMAC_MH_CMD_BUF              0x21c
  58
  59 #define NETSEC_REG_NRM_TX_PKTCNT                0x410
  60
  61 #define NETSEC_REG_NRM_TX_DONE_PKTCNT           0x414
  62 #define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT     0x418
  63
  64 #define NETSEC_REG_NRM_TX_TMR                   0x41c
  65
  66 #define NETSEC_REG_NRM_RX_PKTCNT                0x454
  67 #define NETSEC_REG_NRM_RX_RXINT_PKTCNT          0x458
  68 #define NETSEC_REG_NRM_TX_TXINT_TMR             0x420
  69 #define NETSEC_REG_NRM_RX_RXINT_TMR             0x460
  70
  71 #define NETSEC_REG_NRM_RX_TMR                   0x45c
  72
  73 #define NETSEC_REG_NRM_TX_DESC_START_UP         0x434
  74 #define NETSEC_REG_NRM_TX_DESC_START_LW         0x408
  75 #define NETSEC_REG_NRM_RX_DESC_START_UP         0x474
  76 #define NETSEC_REG_NRM_RX_DESC_START_LW         0x448
  77
  78 #define NETSEC_REG_NRM_TX_CONFIG                0x430
  79 #define NETSEC_REG_NRM_RX_CONFIG                0x470
  80
  81 #define MAC_REG_STATUS                          0x1024
  82 #define MAC_REG_DATA                            0x11c0
  83 #define MAC_REG_CMD                             0x11c4
  84 #define MAC_REG_FLOW_TH                         0x11cc
  85 #define MAC_REG_INTF_SEL                        0x11d4
  86 #define MAC_REG_DESC_INIT                       0x11fc
  87 #define MAC_REG_DESC_SOFT_RST                   0x1204
  88 #define NETSEC_REG_MODE_TRANS_COMP_STATUS       0x500
  89
  90 #define GMAC_REG_MCR                            0x0000
  91 #define GMAC_REG_MFFR                           0x0004
  92 #define GMAC_REG_GAR                            0x0010
  93 #define GMAC_REG_GDR                            0x0014
  94 #define GMAC_REG_FCR                            0x0018
  95 #define GMAC_REG_BMR                            0x1000
  96 #define GMAC_REG_RDLAR                          0x100c
  97 #define GMAC_REG_TDLAR                          0x1010
  98 #define GMAC_REG_OMR                            0x1018
  99
 100 #define MHZ(n)          ((n) * 1000 * 1000)
 101
 102 #define NETSEC_TX_SHIFT_OWN_FIELD               31
 103 #define NETSEC_TX_SHIFT_LD_FIELD                30
 104 #define NETSEC_TX_SHIFT_DRID_FIELD              24
 105 #define NETSEC_TX_SHIFT_PT_FIELD                21
 106 #define NETSEC_TX_SHIFT_TDRID_FIELD             16
 107 #define NETSEC_TX_SHIFT_CC_FIELD                15
 108 #define NETSEC_TX_SHIFT_FS_FIELD                9
 109 #define NETSEC_TX_LAST                          8
 110 #define NETSEC_TX_SHIFT_CO                      7
 111 #define NETSEC_TX_SHIFT_SO                      6
 112 #define NETSEC_TX_SHIFT_TRS_FIELD               4
 113
 114 #define NETSEC_RX_PKT_OWN_FIELD                 31
 115 #define NETSEC_RX_PKT_LD_FIELD                  30
 116 #define NETSEC_RX_PKT_SDRID_FIELD               24
 117 #define NETSEC_RX_PKT_FR_FIELD                  23
 118 #define NETSEC_RX_PKT_ER_FIELD                  21
 119 #define NETSEC_RX_PKT_ERR_FIELD                 16
 120 #define NETSEC_RX_PKT_TDRID_FIELD               12
 121 #define NETSEC_RX_PKT_FS_FIELD                  9
 122 #define NETSEC_RX_PKT_LS_FIELD                  8
 123 #define NETSEC_RX_PKT_CO_FIELD                  6
 124
 125 #define NETSEC_RX_PKT_ERR_MASK                  3
 126
 127 #define NETSEC_MAX_TX_PKT_LEN                   1518
 128 #define NETSEC_MAX_TX_JUMBO_PKT_LEN             9018
 129
 130 #define NETSEC_RING_GMAC                        15
 131 #define NETSEC_RING_MAX                         2
 132
 133 #define NETSEC_TCP_SEG_LEN_MAX                  1460
 134 #define NETSEC_TCP_JUMBO_SEG_LEN_MAX            8960
 135
 136 #define NETSEC_RX_CKSUM_NOTAVAIL                0
 137 #define NETSEC_RX_CKSUM_OK                      1
 138 #define NETSEC_RX_CKSUM_NG                      2
 139
 140 #define NETSEC_TOP_IRQ_REG_CODE_LOAD_END        BIT(20)
 141 #define NETSEC_IRQ_TRANSITION_COMPLETE          BIT(4)
 142
 143 #define NETSEC_MODE_TRANS_COMP_IRQ_N2T          BIT(20)
 144 #define NETSEC_MODE_TRANS_COMP_IRQ_T2N          BIT(19)
 145
 146 #define NETSEC_INT_PKTCNT_MAX                   2047
 147
 148 #define NETSEC_FLOW_START_TH_MAX                95
 149 #define NETSEC_FLOW_STOP_TH_MAX                 95
 150 #define NETSEC_FLOW_PAUSE_TIME_MIN              5
 151
 152 #define NETSEC_CLK_EN_REG_DOM_ALL               0x3f
 153
 154 #define NETSEC_PKT_CTRL_REG_MODE_NRM            BIT(28)
 155 #define NETSEC_PKT_CTRL_REG_EN_JUMBO            BIT(27)
 156 #define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER       BIT(3)
 157 #define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE   BIT(2)
 158 #define NETSEC_PKT_CTRL_REG_LOG_HD_ER           BIT(1)
 159 #define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH        BIT(0)
 160
 161 #define NETSEC_CLK_EN_REG_DOM_G                 BIT(5)
 162 #define NETSEC_CLK_EN_REG_DOM_C                 BIT(1)
 163 #define NETSEC_CLK_EN_REG_DOM_D                 BIT(0)
 164
 165 #define NETSEC_COM_INIT_REG_DB                  BIT(2)
 166 #define NETSEC_COM_INIT_REG_CLS                 BIT(1)
 167 #define NETSEC_COM_INIT_REG_ALL                 (NETSEC_COM_INIT_REG_CLS | \
 168                                                  NETSEC_COM_INIT_REG_DB)
 169
 170 #define NETSEC_SOFT_RST_REG_RESET               0
 171 #define NETSEC_SOFT_RST_REG_RUN                 BIT(31)
 172
 173 #define NETSEC_DMA_CTRL_REG_STOP                1
 174 #define MH_CTRL__MODE_TRANS                     BIT(20)
 175
 176 #define NETSEC_GMAC_CMD_ST_READ                 0
 177 #define NETSEC_GMAC_CMD_ST_WRITE                BIT(28)
 178 #define NETSEC_GMAC_CMD_ST_BUSY                 BIT(31)
 179
 180 #define NETSEC_GMAC_BMR_REG_COMMON              0x00412080
 181 #define NETSEC_GMAC_BMR_REG_RESET               0x00020181
 182 #define NETSEC_GMAC_BMR_REG_SWR                 0x00000001
 183
 184 #define NETSEC_GMAC_OMR_REG_ST                  BIT(13)
 185 #define NETSEC_GMAC_OMR_REG_SR                  BIT(1)
 186
 187 #define NETSEC_GMAC_MCR_REG_IBN                 BIT(30)
 188 #define NETSEC_GMAC_MCR_REG_CST                 BIT(25)
 189 #define NETSEC_GMAC_MCR_REG_JE                  BIT(20)
 190 #define NETSEC_MCR_PS                           BIT(15)
 191 #define NETSEC_GMAC_MCR_REG_FES                 BIT(14)
 192 #define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON  0x0000280c
 193 #define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON  0x0001a00c
 194
 195 #define NETSEC_FCR_RFE                          BIT(2)
 196 #define NETSEC_FCR_TFE                          BIT(1)
 197
 198 #define NETSEC_GMAC_GAR_REG_GW                  BIT(1)
 199 #define NETSEC_GMAC_GAR_REG_GB                  BIT(0)
 200
 201 #define NETSEC_GMAC_GAR_REG_SHIFT_PA            11
 202 #define NETSEC_GMAC_GAR_REG_SHIFT_GR            6
 203 #define GMAC_REG_SHIFT_CR_GAR                   2
 204
 205 #define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ        2
 206 #define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ        3
 207 #define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ       0
 208 #define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ      1
 209 #define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ      4
 210 #define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ      5
 211
 212 #define NETSEC_GMAC_RDLAR_REG_COMMON            0x18000
 213 #define NETSEC_GMAC_TDLAR_REG_COMMON            0x1c000
 214
 215 #define NETSEC_REG_NETSEC_VER_F_TAIKI           0x50000
 216
 217 #define NETSEC_REG_DESC_RING_CONFIG_CFG_UP      BIT(31)
 218 #define NETSEC_REG_DESC_RING_CONFIG_CH_RST      BIT(30)
 219 #define NETSEC_REG_DESC_TMR_MODE                4
 220 #define NETSEC_REG_DESC_ENDIAN                  0
 221
 222 #define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST       1
 223 #define NETSEC_MAC_DESC_INIT_REG_INIT           1
 224
 225 #define NETSEC_EEPROM_MAC_ADDRESS               0x00
 226 #define NETSEC_EEPROM_HM_ME_ADDRESS_H           0x08
 227 #define NETSEC_EEPROM_HM_ME_ADDRESS_L           0x0C
 228 #define NETSEC_EEPROM_HM_ME_SIZE                0x10
 229 #define NETSEC_EEPROM_MH_ME_ADDRESS_H           0x14
 230 #define NETSEC_EEPROM_MH_ME_ADDRESS_L           0x18
 231 #define NETSEC_EEPROM_MH_ME_SIZE                0x1C
 232 #define NETSEC_EEPROM_PKT_ME_ADDRESS            0x20
 233 #define NETSEC_EEPROM_PKT_ME_SIZE               0x24
 234
 235 #define DESC_NUM        256
 236
 237 #define DESC_SZ sizeof(struct netsec_de)
 238
 239 #define NETSEC_F_NETSEC_VER_MAJOR_NUM(x)        ((x) & 0xffff0000)
 240
 241 enum ring_id {
 242         NETSEC_RING_TX = 0,
 243         NETSEC_RING_RX
 244 };
 245
 246 struct netsec_desc {
 247         struct sk_buff *skb;
 248         dma_addr_t dma_addr;
 249         void *addr;
 250         u16 len;
 251 };
 252
 253 struct netsec_desc_ring {
 254         dma_addr_t desc_dma;
 255         struct netsec_desc *desc;
 256         void *vaddr;
 257         u16 pkt_cnt;
 258         u16 head, tail;
 259 };
 260
 261 struct netsec_priv {
 262         struct netsec_desc_ring desc_ring[NETSEC_RING_MAX];
 263         struct ethtool_coalesce et_coalesce;
 264         spinlock_t reglock; /* protect reg access */
 265         struct napi_struct napi;
 266         phy_interface_t phy_interface;
 267         struct net_device *ndev;
 268         struct device_node *phy_np;
 269         struct phy_device *phydev;
 270         struct mii_bus *mii_bus;
 271         void __iomem *ioaddr;
 272         void __iomem *eeprom_base;
 273         struct device *dev;
 274         struct clk *clk;
 275         u32 msg_enable;
 276         u32 freq;
 277         u32 phy_addr;
 278         bool rx_cksum_offload_flag;
 279 };
 280
 281 struct netsec_de { /* Netsec Descriptor layout */
 282         u32 attr;
 283         u32 data_buf_addr_up;
 284         u32 data_buf_addr_lw;
 285         u32 buf_len_info;
 286 };
 287
 288 struct netsec_tx_pkt_ctrl {
 289         u16 tcp_seg_len;
 290         bool tcp_seg_offload_flag;
 291         bool cksum_offload_flag;
 292 };
 293
 294 struct netsec_rx_pkt_info {
 295         int rx_cksum_result;
 296         int err_code;
 297         bool err_flag;
 298 };
 299
 300 static void netsec_write(struct netsec_priv *priv, u32 reg_addr, u32 val)
 301 {
 302         writel(val, priv->ioaddr + reg_addr);
 303 }
 304
 305 static u32 netsec_read(struct netsec_priv *priv, u32 reg_addr)
 306 {
 307         return readl(priv->ioaddr + reg_addr);
 308 }
 309
 310 /************* MDIO BUS OPS FOLLOW *************/
 311
 312 #define TIMEOUT_SPINS_MAC               1000
 313 #define TIMEOUT_SECONDARY_MS_MAC        100
 314
 315 static u32 netsec_clk_type(u32 freq)
 316 {
 317         if (freq < MHZ(35))
 318                 return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ;
 319         if (freq < MHZ(60))
 320                 return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ;
 321         if (freq < MHZ(100))
 322                 return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ;
 323         if (freq < MHZ(150))
 324                 return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ;
 325         if (freq < MHZ(250))
 326                 return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ;
 327
 328         return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ;
 329 }
 330
 331 static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask)
 332 {
 333         u32 timeout = TIMEOUT_SPINS_MAC;
 334
 335         while (--timeout && netsec_read(priv, addr) & mask)
 336                 cpu_relax();
 337         if (timeout)
 338                 return 0;
 339
 340         timeout = TIMEOUT_SECONDARY_MS_MAC;
 341         while (--timeout && netsec_read(priv, addr) & mask)
 342                 usleep_range(1000, 2000);
 343
 344         if (timeout)
 345                 return 0;
 346
 347         netdev_WARN(priv->ndev, "%s: timeout\n", __func__);
 348
 349         return -ETIMEDOUT;
 350 }
 351
 352 static int netsec_mac_write(struct netsec_priv *priv, u32 addr, u32 value)
 353 {
 354         netsec_write(priv, MAC_REG_DATA, value);
 355         netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE);
 356         return netsec_wait_while_busy(priv,
 357                                       MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
 358 }
 359
 360 static int netsec_mac_read(struct netsec_priv *priv, u32 addr, u32 *read)
 361 {
 362         int ret;
 363
 364         netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ);
 365         ret = netsec_wait_while_busy(priv,
 366                                      MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
 367         if (ret)
 368                 return ret;
 369
 370         *read = netsec_read(priv, MAC_REG_DATA);
 371
 372         return 0;
 373 }
 374
 375 static int netsec_mac_wait_while_busy(struct netsec_priv *priv,
 376                                       u32 addr, u32 mask)
 377 {
 378         u32 timeout = TIMEOUT_SPINS_MAC;
 379         int ret, data;
 380
 381         do {
 382                 ret = netsec_mac_read(priv, addr, &data);
 383                 if (ret)
 384                         break;
 385                 cpu_relax();
 386         } while (--timeout && (data & mask));
 387
 388         if (timeout)
 389                 return 0;
 390
 391         timeout = TIMEOUT_SECONDARY_MS_MAC;
 392         do {
 393                 usleep_range(1000, 2000);
 394
 395                 ret = netsec_mac_read(priv, addr, &data);
 396                 if (ret)
 397                         break;
 398                 cpu_relax();
 399         } while (--timeout && (data & mask));
 400
 401         if (timeout && !ret)
 402                 return 0;
 403
 404         netdev_WARN(priv->ndev, "%s: timeout\n", __func__);
 405
 406         return -ETIMEDOUT;
 407 }
 408
 409 static int netsec_mac_update_to_phy_state(struct netsec_priv *priv)
 410 {
 411         struct phy_device *phydev = priv->ndev->phydev;
 412         u32 value = 0;
 413
 414         value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON :
 415                                  NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON;
 416
 417         if (phydev->speed != SPEED_1000)
 418                 value |= NETSEC_MCR_PS;
 419
 420         if (priv->phy_interface != PHY_INTERFACE_MODE_GMII &&
 421             phydev->speed == SPEED_100)
 422                 value |= NETSEC_GMAC_MCR_REG_FES;
 423
 424         value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE;
 425
 426         if (phy_interface_mode_is_rgmii(priv->phy_interface))
 427                 value |= NETSEC_GMAC_MCR_REG_IBN;
 428
 429         if (netsec_mac_write(priv, GMAC_REG_MCR, value))
 430                 return -ETIMEDOUT;
 431
 432         return 0;
 433 }
 434
 435 static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr);
 436
 437 static int netsec_phy_write(struct mii_bus *bus,
 438                             int phy_addr, int reg, u16 val)
 439 {
 440         int status;
 441         struct netsec_priv *priv = bus->priv;
 442
 443         if (netsec_mac_write(priv, GMAC_REG_GDR, val))
 444                 return -ETIMEDOUT;
 445         if (netsec_mac_write(priv, GMAC_REG_GAR,
 446                              phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
 447                              reg << NETSEC_GMAC_GAR_REG_SHIFT_GR |
 448                              NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB |
 449                              (netsec_clk_type(priv->freq) <<
 450                               GMAC_REG_SHIFT_CR_GAR)))
 451                 return -ETIMEDOUT;
 452
 453         status = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
 454                                             NETSEC_GMAC_GAR_REG_GB);
 455
 456         /* Developerbox implements RTL8211E PHY and there is
 457          * a compatibility problem with F_GMAC4.
 458          * RTL8211E expects MDC clock must be kept toggling for several
 459          * clock cycle with MDIO high before entering the IDLE state.
 460          * To meet this requirement, netsec driver needs to issue dummy
 461          * read(e.g. read PHYID1(offset 0x2) register) right after write.
 462          */
 463         netsec_phy_read(bus, phy_addr, MII_PHYSID1);
 464
 465         return status;
 466 }
 467
 468 static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)
 469 {
 470         struct netsec_priv *priv = bus->priv;
 471         u32 data;
 472         int ret;
 473
 474         if (netsec_mac_write(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB |
 475                              phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
 476                              reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
 477                              (netsec_clk_type(priv->freq) <<
 478                               GMAC_REG_SHIFT_CR_GAR)))
 479                 return -ETIMEDOUT;
 480
 481         ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
 482                                          NETSEC_GMAC_GAR_REG_GB);
 483         if (ret)
 484                 return ret;
 485
 486         ret = netsec_mac_read(priv, GMAC_REG_GDR, &data);
 487         if (ret)
 488                 return ret;
 489
 490         return data;
 491 }
 492
 493 /************* ETHTOOL_OPS FOLLOW *************/
 494
 495 static void netsec_et_get_drvinfo(struct net_device *net_device,
 496                                   struct ethtool_drvinfo *info)
 497 {
 498         strlcpy(info->driver, "netsec", sizeof(info->driver));
 499         strlcpy(info->bus_info, dev_name(net_device->dev.parent),
 500                 sizeof(info->bus_info));
 501 }
 502
 503 static int netsec_et_get_coalesce(struct net_device *net_device,
 504                                   struct ethtool_coalesce *et_coalesce)
 505 {
 506         struct netsec_priv *priv = netdev_priv(net_device);
 507
 508         *et_coalesce = priv->et_coalesce;
 509
 510         return 0;
 511 }
 512
 513 static int netsec_et_set_coalesce(struct net_device *net_device,
 514                                   struct ethtool_coalesce *et_coalesce)
 515 {
 516         struct netsec_priv *priv = netdev_priv(net_device);
 517
 518         priv->et_coalesce = *et_coalesce;
 519
 520         if (priv->et_coalesce.tx_coalesce_usecs < 50)
 521                 priv->et_coalesce.tx_coalesce_usecs = 50;
 522         if (priv->et_coalesce.tx_max_coalesced_frames < 1)
 523                 priv->et_coalesce.tx_max_coalesced_frames = 1;
 524
 525         netsec_write(priv, NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT,
 526                      priv->et_coalesce.tx_max_coalesced_frames);
 527         netsec_write(priv, NETSEC_REG_NRM_TX_TXINT_TMR,
 528                      priv->et_coalesce.tx_coalesce_usecs);
 529         netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TXDONE);
 530         netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TMREXP);
 531
 532         if (priv->et_coalesce.rx_coalesce_usecs < 50)
 533                 priv->et_coalesce.rx_coalesce_usecs = 50;
 534         if (priv->et_coalesce.rx_max_coalesced_frames < 1)
 535                 priv->et_coalesce.rx_max_coalesced_frames = 1;
 536
 537         netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_PKTCNT,
 538                      priv->et_coalesce.rx_max_coalesced_frames);
 539         netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_TMR,
 540                      priv->et_coalesce.rx_coalesce_usecs);
 541         netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_PKTCNT);
 542         netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_TMREXP);
 543
 544         return 0;
 545 }
 546
 547 static u32 netsec_et_get_msglevel(struct net_device *dev)
 548 {
 549         struct netsec_priv *priv = netdev_priv(dev);
 550
 551         return priv->msg_enable;
 552 }
 553
 554 static void netsec_et_set_msglevel(struct net_device *dev, u32 datum)
 555 {
 556         struct netsec_priv *priv = netdev_priv(dev);
 557
 558         priv->msg_enable = datum;
 559 }
 560
 561 static const struct ethtool_ops netsec_ethtool_ops = {
 562         .get_drvinfo            = netsec_et_get_drvinfo,
 563         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
 564         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
 565         .get_link               = ethtool_op_get_link,
 566         .get_coalesce           = netsec_et_get_coalesce,
 567         .set_coalesce           = netsec_et_set_coalesce,
 568         .get_msglevel           = netsec_et_get_msglevel,
 569         .set_msglevel           = netsec_et_set_msglevel,
 570 };
 571
 572 /************* NETDEV_OPS FOLLOW *************/
 573
 574 static struct sk_buff *netsec_alloc_skb(struct netsec_priv *priv,
 575                                         struct netsec_desc *desc)
 576 {
 577         struct sk_buff *skb;
 578
 579         if (device_get_dma_attr(priv->dev) == DEV_DMA_COHERENT) {
 580                 skb = netdev_alloc_skb_ip_align(priv->ndev, desc->len);
 581         } else {
 582                 desc->len = L1_CACHE_ALIGN(desc->len);
 583                 skb = netdev_alloc_skb(priv->ndev, desc->len);
 584         }
 585         if (!skb)
 586                 return NULL;
 587
 588         desc->addr = skb->data;
 589         desc->dma_addr = dma_map_single(priv->dev, desc->addr, desc->len,
 590                                         DMA_FROM_DEVICE);
 591         if (dma_mapping_error(priv->dev, desc->dma_addr)) {
 592                 dev_kfree_skb_any(skb);
 593                 return NULL;
 594         }
 595         return skb;
 596 }
 597
 598 static void netsec_set_rx_de(struct netsec_priv *priv,
 599                              struct netsec_desc_ring *dring, u16 idx,
 600                              const struct netsec_desc *desc,
 601                              struct sk_buff *skb)
 602 {
 603         struct netsec_de *de = dring->vaddr + DESC_SZ * idx;
 604         u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) |
 605                    (1 << NETSEC_RX_PKT_FS_FIELD) |
 606                    (1 << NETSEC_RX_PKT_LS_FIELD);
 607
 608         if (idx == DESC_NUM - 1)
 609                 attr |= (1 << NETSEC_RX_PKT_LD_FIELD);
 610
 611         de->data_buf_addr_up = upper_32_bits(desc->dma_addr);
 612         de->data_buf_addr_lw = lower_32_bits(desc->dma_addr);
 613         de->buf_len_info = desc->len;
 614         de->attr = attr;
 615         dma_wmb();
 616
 617         dring->desc[idx].dma_addr = desc->dma_addr;
 618         dring->desc[idx].addr = desc->addr;
 619         dring->desc[idx].len = desc->len;
 620         dring->desc[idx].skb = skb;
 621 }
 622
 623 static struct sk_buff *netsec_get_rx_de(struct netsec_priv *priv,
 624                                         struct netsec_desc_ring *dring,
 625                                         u16 idx,
 626                                         struct netsec_rx_pkt_info *rxpi,
 627                                         struct netsec_desc *desc, u16 *len)
 628 {
 629         struct netsec_de de = {};
 630
 631         memcpy(&de, dring->vaddr + DESC_SZ * idx, DESC_SZ);
 632
 633         *len = de.buf_len_info >> 16;
 634
 635         rxpi->err_flag = (de.attr >> NETSEC_RX_PKT_ER_FIELD) & 1;
 636         rxpi->rx_cksum_result = (de.attr >> NETSEC_RX_PKT_CO_FIELD) & 3;
 637         rxpi->err_code = (de.attr >> NETSEC_RX_PKT_ERR_FIELD) &
 638                                                         NETSEC_RX_PKT_ERR_MASK;
 639         *desc = dring->desc[idx];
 640         return desc->skb;
 641 }
 642
 643 static struct sk_buff *netsec_get_rx_pkt_data(struct netsec_priv *priv,
 644                                               struct netsec_rx_pkt_info *rxpi,
 645                                               struct netsec_desc *desc,
 646                                               u16 *len)
 647 {
 648         struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
 649         struct sk_buff *tmp_skb, *skb = NULL;
 650         struct netsec_desc td;
 651         int tail;
 652
 653         *rxpi = (struct netsec_rx_pkt_info){};
 654
 655         td.len = priv->ndev->mtu + 22;
 656
 657         tmp_skb = netsec_alloc_skb(priv, &td);
 658
 659         tail = dring->tail;
 660
 661         if (!tmp_skb) {
 662                 netsec_set_rx_de(priv, dring, tail, &dring->desc[tail],
 663                                  dring->desc[tail].skb);
 664         } else {
 665                 skb = netsec_get_rx_de(priv, dring, tail, rxpi, desc, len);
 666                 netsec_set_rx_de(priv, dring, tail, &td, tmp_skb);
 667         }
 668
 669         /* move tail ahead */
 670         dring->tail = (dring->tail + 1) % DESC_NUM;
 671
 672         return skb;
 673 }
 674
 675 static int netsec_clean_tx_dring(struct netsec_priv *priv, int budget)
 676 {
 677         struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX];
 678         unsigned int pkts, bytes;
 679
 680         dring->pkt_cnt += netsec_read(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT);
 681
 682         if (dring->pkt_cnt < budget)
 683                 budget = dring->pkt_cnt;
 684
 685         pkts = 0;
 686         bytes = 0;
 687
 688         while (pkts < budget) {
 689                 struct netsec_desc *desc;
 690                 struct netsec_de *entry;
 691                 int tail, eop;
 692
 693                 tail = dring->tail;
 694
 695                 /* move tail ahead */
 696                 dring->tail = (tail + 1) % DESC_NUM;
 697
 698                 desc = &dring->desc[tail];
 699                 entry = dring->vaddr + DESC_SZ * tail;
 700
 701                 eop = (entry->attr >> NETSEC_TX_LAST) & 1;
 702
 703                 dma_unmap_single(priv->dev, desc->dma_addr, desc->len,
 704                                  DMA_TO_DEVICE);
 705                 if (eop) {
 706                         pkts++;
 707                         bytes += desc->skb->len;
 708                         dev_kfree_skb(desc->skb);
 709                 }
 710                 *desc = (struct netsec_desc){};
 711         }
 712         dring->pkt_cnt -= budget;
 713
 714         priv->ndev->stats.tx_packets += budget;
 715         priv->ndev->stats.tx_bytes += bytes;
 716
 717         netdev_completed_queue(priv->ndev, budget, bytes);
 718
 719         return budget;
 720 }
 721
 722 static int netsec_process_tx(struct netsec_priv *priv, int budget)
 723 {
 724         struct net_device *ndev = priv->ndev;
 725         int new, done = 0;
 726
 727         do {
 728                 new = netsec_clean_tx_dring(priv, budget);
 729                 done += new;
 730                 budget -= new;
 731         } while (new);
 732
 733         if (done && netif_queue_stopped(ndev))
 734                 netif_wake_queue(ndev);
 735
 736         return done;
 737 }
 738
 739 static int netsec_process_rx(struct netsec_priv *priv, int budget)
 740 {
 741         struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
 742         struct net_device *ndev = priv->ndev;
 743         struct netsec_rx_pkt_info rx_info;
 744         int done = 0;
 745         struct netsec_desc desc;
 746         struct sk_buff *skb;
 747         u16 len;
 748
 749         while (done < budget) {
 750                 u16 idx = dring->tail;
 751                 struct netsec_de *de = dring->vaddr + (DESC_SZ * idx);
 752
 753                 if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD)) {
 754                         /* reading the register clears the irq */
 755                         netsec_read(priv, NETSEC_REG_NRM_RX_PKTCNT);
 756                         break;
 757                 }
 758
 759                 /* This  barrier is needed to keep us from reading
 760                  * any other fields out of the netsec_de until we have
 761                  * verified the descriptor has been written back
 762                  */
 763                 dma_rmb();
 764                 done++;
 765                 skb = netsec_get_rx_pkt_data(priv, &rx_info, &desc, &len);
 766                 if (unlikely(!skb) || rx_info.err_flag) {
 767                         netif_err(priv, drv, priv->ndev,
 768                                   "%s: rx fail err(%d)\n",
 769                                   __func__, rx_info.err_code);
 770                         ndev->stats.rx_dropped++;
 771                         continue;
 772                 }
 773
 774                 dma_unmap_single(priv->dev, desc.dma_addr, desc.len,
 775                                  DMA_FROM_DEVICE);
 776                 skb_put(skb, len);
 777                 skb->protocol = eth_type_trans(skb, priv->ndev);
 778
 779                 if (priv->rx_cksum_offload_flag &&
 780                     rx_info.rx_cksum_result == NETSEC_RX_CKSUM_OK)
 781                         skb->ip_summed = CHECKSUM_UNNECESSARY;
 782
 783                 if (napi_gro_receive(&priv->napi, skb) != GRO_DROP) {
 784                         ndev->stats.rx_packets++;
 785                         ndev->stats.rx_bytes += len;
 786                 }
 787         }
 788
 789         return done;
 790 }
 791
 792 static int netsec_napi_poll(struct napi_struct *napi, int budget)
 793 {
 794         struct netsec_priv *priv;
 795         int tx, rx, done, todo;
 796
 797         priv = container_of(napi, struct netsec_priv, napi);
 798
 799         todo = budget;
 800         do {
 801                 if (!todo)
 802                         break;
 803
 804                 tx = netsec_process_tx(priv, todo);
 805                 todo -= tx;
 806
 807                 if (!todo)
 808                         break;
 809
 810                 rx = netsec_process_rx(priv, todo);
 811                 todo -= rx;
 812         } while (rx || tx);
 813
 814         done = budget - todo;
 815
 816         if (done < budget && napi_complete_done(napi, done)) {
 817                 unsigned long flags;
 818
 819                 spin_lock_irqsave(&priv->reglock, flags);
 820                 netsec_write(priv, NETSEC_REG_INTEN_SET,
 821                              NETSEC_IRQ_RX | NETSEC_IRQ_TX);
 822                 spin_unlock_irqrestore(&priv->reglock, flags);
 823         }
 824
 825         return done;
 826 }
 827
 828 static void netsec_set_tx_de(struct netsec_priv *priv,
 829                              struct netsec_desc_ring *dring,
 830                              const struct netsec_tx_pkt_ctrl *tx_ctrl,
 831                              const struct netsec_desc *desc,
 832                              struct sk_buff *skb)
 833 {
 834         int idx = dring->head;
 835         struct netsec_de *de;
 836         u32 attr;
 837
 838         de = dring->vaddr + (DESC_SZ * idx);
 839
 840         attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) |
 841                (1 << NETSEC_TX_SHIFT_PT_FIELD) |
 842                (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) |
 843                (1 << NETSEC_TX_SHIFT_FS_FIELD) |
 844                (1 << NETSEC_TX_LAST) |
 845                (tx_ctrl->cksum_offload_flag << NETSEC_TX_SHIFT_CO) |
 846                (tx_ctrl->tcp_seg_offload_flag << NETSEC_TX_SHIFT_SO) |
 847                (1 << NETSEC_TX_SHIFT_TRS_FIELD);
 848         if (idx == DESC_NUM - 1)
 849                 attr |= (1 << NETSEC_TX_SHIFT_LD_FIELD);
 850
 851         de->data_buf_addr_up = upper_32_bits(desc->dma_addr);
 852         de->data_buf_addr_lw = lower_32_bits(desc->dma_addr);
 853         de->buf_len_info = (tx_ctrl->tcp_seg_len << 16) | desc->len;
 854         de->attr = attr;
 855         dma_wmb();
 856
 857         dring->desc[idx] = *desc;
 858         dring->desc[idx].skb = skb;
 859
 860         /* move head ahead */
 861         dring->head = (dring->head + 1) % DESC_NUM;
 862 }
 863
 864 static netdev_tx_t netsec_netdev_start_xmit(struct sk_buff *skb,
 865                                             struct net_device *ndev)
 866 {
 867         struct netsec_priv *priv = netdev_priv(ndev);
 868         struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX];
 869         struct netsec_tx_pkt_ctrl tx_ctrl = {};
 870         struct netsec_desc tx_desc;
 871         u16 tso_seg_len = 0;
 872         int filled;
 873
 874         /* differentiate between full/emtpy ring */
 875         if (dring->head >= dring->tail)
 876                 filled = dring->head - dring->tail;
 877         else
 878                 filled = dring->head + DESC_NUM - dring->tail;
 879
 880         if (DESC_NUM - filled < 2) { /* if less than 2 available */
 881                 netif_err(priv, drv, priv->ndev, "%s: TxQFull!\n", __func__);
 882                 netif_stop_queue(priv->ndev);
 883                 dma_wmb();
 884                 return NETDEV_TX_BUSY;
 885         }
 886
 887         if (skb->ip_summed == CHECKSUM_PARTIAL)
 888                 tx_ctrl.cksum_offload_flag = true;
 889
 890         if (skb_is_gso(skb))
 891                 tso_seg_len = skb_shinfo(skb)->gso_size;
 892
 893         if (tso_seg_len > 0) {
 894                 if (skb->protocol == htons(ETH_P_IP)) {
 895                         ip_hdr(skb)->tot_len = 0;
 896                         tcp_hdr(skb)->check =
 897                                 ~tcp_v4_check(0, ip_hdr(skb)->saddr,
 898                                               ip_hdr(skb)->daddr, 0);
 899                 } else {
 900                         ipv6_hdr(skb)->payload_len = 0;
 901                         tcp_hdr(skb)->check =
 902                                 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
 903                                                  &ipv6_hdr(skb)->daddr,
 904                                                  0, IPPROTO_TCP, 0);
 905                 }
 906
 907                 tx_ctrl.tcp_seg_offload_flag = true;
 908                 tx_ctrl.tcp_seg_len = tso_seg_len;
 909         }
 910
 911         tx_desc.dma_addr = dma_map_single(priv->dev, skb->data,
 912                                           skb_headlen(skb), DMA_TO_DEVICE);
 913         if (dma_mapping_error(priv->dev, tx_desc.dma_addr)) {
 914                 netif_err(priv, drv, priv->ndev,
 915                           "%s: DMA mapping failed\n", __func__);
 916                 ndev->stats.tx_dropped++;
 917                 dev_kfree_skb_any(skb);
 918                 return NETDEV_TX_OK;
 919         }
 920         tx_desc.addr = skb->data;
 921         tx_desc.len = skb_headlen(skb);
 922
 923         skb_tx_timestamp(skb);
 924         netdev_sent_queue(priv->ndev, skb->len);
 925
 926         netsec_set_tx_de(priv, dring, &tx_ctrl, &tx_desc, skb);
 927         netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */
 928
 929         return NETDEV_TX_OK;
 930 }
 931
 932 static void netsec_uninit_pkt_dring(struct netsec_priv *priv, int id)
 933 {
 934         struct netsec_desc_ring *dring = &priv->desc_ring[id];
 935         struct netsec_desc *desc;
 936         u16 idx;
 937
 938         if (!dring->vaddr || !dring->desc)
 939                 return;
 940
 941         for (idx = 0; idx < DESC_NUM; idx++) {
 942                 desc = &dring->desc[idx];
 943                 if (!desc->addr)
 944                         continue;
 945
 946                 dma_unmap_single(priv->dev, desc->dma_addr, desc->len,
 947                                  id == NETSEC_RING_RX ? DMA_FROM_DEVICE :
 948                                                               DMA_TO_DEVICE);
 949                 dev_kfree_skb(desc->skb);
 950         }
 951
 952         memset(dring->desc, 0, sizeof(struct netsec_desc) * DESC_NUM);
 953         memset(dring->vaddr, 0, DESC_SZ * DESC_NUM);
 954
 955         dring->head = 0;
 956         dring->tail = 0;
 957         dring->pkt_cnt = 0;
 958
 959         if (id == NETSEC_RING_TX)
 960                 netdev_reset_queue(priv->ndev);
 961 }
 962
 963 static void netsec_free_dring(struct netsec_priv *priv, int id)
 964 {
 965         struct netsec_desc_ring *dring = &priv->desc_ring[id];
 966
 967         if (dring->vaddr) {
 968                 dma_free_coherent(priv->dev, DESC_SZ * DESC_NUM,
 969                                   dring->vaddr, dring->desc_dma);
 970                 dring->vaddr = NULL;
 971         }
 972
 973         kfree(dring->desc);
 974         dring->desc = NULL;
 975 }
 976
 977 static int netsec_alloc_dring(struct netsec_priv *priv, enum ring_id id)
 978 {
 979         struct netsec_desc_ring *dring = &priv->desc_ring[id];
 980         int ret = 0;
 981
 982         dring->vaddr = dma_zalloc_coherent(priv->dev, DESC_SZ * DESC_NUM,
 983                                            &dring->desc_dma, GFP_KERNEL);
 984         if (!dring->vaddr) {
 985                 ret = -ENOMEM;
 986                 goto err;
 987         }
 988
 989         dring->desc = kcalloc(DESC_NUM, sizeof(*dring->desc), GFP_KERNEL);
 990         if (!dring->desc) {
 991                 ret = -ENOMEM;
 992                 goto err;
 993         }
 994
 995         return 0;
 996 err:
 997         netsec_free_dring(priv, id);
 998
 999         return ret;
1000 }
1001
1002 static int netsec_setup_rx_dring(struct netsec_priv *priv)
1003 {
1004         struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
1005         struct netsec_desc desc;
1006         struct sk_buff *skb;
1007         int n;
1008
1009         desc.len = priv->ndev->mtu + 22;
1010
1011         for (n = 0; n < DESC_NUM; n++) {
1012                 skb = netsec_alloc_skb(priv, &desc);
1013                 if (!skb) {
1014                         netsec_uninit_pkt_dring(priv, NETSEC_RING_RX);
1015                         return -ENOMEM;
1016                 }
1017                 netsec_set_rx_de(priv, dring, n, &desc, skb);
1018         }
1019
1020         return 0;
1021 }
1022
1023 static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg,
1024                                            u32 addr_h, u32 addr_l, u32 size)
1025 {
1026         u64 base = (u64)addr_h << 32 | addr_l;
1027         void __iomem *ucode;
1028         u32 i;
1029
1030         ucode = ioremap(base, size * sizeof(u32));
1031         if (!ucode)
1032                 return -ENOMEM;
1033
1034         for (i = 0; i < size; i++)
1035                 netsec_write(priv, reg, readl(ucode + i * 4));
1036
1037         iounmap(ucode);
1038         return 0;
1039 }
1040
1041 static int netsec_netdev_load_microcode(struct netsec_priv *priv)
1042 {
1043         u32 addr_h, addr_l, size;
1044         int err;
1045
1046         addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_H);
1047         addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_L);
1048         size = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_SIZE);
1049         err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF,
1050                                               addr_h, addr_l, size);
1051         if (err)
1052                 return err;
1053
1054         addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_H);
1055         addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_L);
1056         size = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_SIZE);
1057         err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF,
1058                                               addr_h, addr_l, size);
1059         if (err)
1060                 return err;
1061
1062         addr_h = 0;
1063         addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_ADDRESS);
1064         size = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_SIZE);
1065         err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF,
1066                                               addr_h, addr_l, size);
1067         if (err)
1068                 return err;
1069
1070         return 0;
1071 }
1072
1073 static int netsec_reset_hardware(struct netsec_priv *priv,
1074                                  bool load_ucode)
1075 {
1076         u32 value;
1077         int err;
1078
1079         /* stop DMA engines */
1080         if (!netsec_read(priv, NETSEC_REG_ADDR_DIS_CORE)) {
1081                 netsec_write(priv, NETSEC_REG_DMA_HM_CTRL,
1082                              NETSEC_DMA_CTRL_REG_STOP);
1083                 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL,
1084                              NETSEC_DMA_CTRL_REG_STOP);
1085
1086                 while (netsec_read(priv, NETSEC_REG_DMA_HM_CTRL) &
1087                        NETSEC_DMA_CTRL_REG_STOP)
1088                         cpu_relax();
1089
1090                 while (netsec_read(priv, NETSEC_REG_DMA_MH_CTRL) &
1091                        NETSEC_DMA_CTRL_REG_STOP)
1092                         cpu_relax();
1093         }
1094
1095         netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET);
1096         netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN);
1097         netsec_write(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL);
1098
1099         while (netsec_read(priv, NETSEC_REG_COM_INIT) != 0)
1100                 cpu_relax();
1101
1102         /* set desc_start addr */
1103         netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
1104                      upper_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma));
1105         netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
1106                      lower_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma));
1107
1108         netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
1109                      upper_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma));
1110         netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
1111                      lower_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma));
1112
1113         /* set normal tx dring ring config */
1114         netsec_write(priv, NETSEC_REG_NRM_TX_CONFIG,
1115                      1 << NETSEC_REG_DESC_ENDIAN);
1116         netsec_write(priv, NETSEC_REG_NRM_RX_CONFIG,
1117                      1 << NETSEC_REG_DESC_ENDIAN);
1118
1119         if (load_ucode) {
1120                 err = netsec_netdev_load_microcode(priv);
1121                 if (err) {
1122                         netif_err(priv, probe, priv->ndev,
1123                                   "%s: failed to load microcode (%d)\n",
1124                                   __func__, err);
1125                         return err;
1126                 }
1127         }
1128
1129         /* start DMA engines */
1130         netsec_write(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1);
1131         netsec_write(priv, NETSEC_REG_ADDR_DIS_CORE, 0);
1132
1133         usleep_range(1000, 2000);
1134
1135         if (!(netsec_read(priv, NETSEC_REG_TOP_STATUS) &
1136               NETSEC_TOP_IRQ_REG_CODE_LOAD_END)) {
1137                 netif_err(priv, probe, priv->ndev,
1138                           "microengine start failed\n");
1139                 return -ENXIO;
1140         }
1141         netsec_write(priv, NETSEC_REG_TOP_STATUS,
1142                      NETSEC_TOP_IRQ_REG_CODE_LOAD_END);
1143
1144         value = NETSEC_PKT_CTRL_REG_MODE_NRM;
1145         if (priv->ndev->mtu > ETH_DATA_LEN)
1146                 value |= NETSEC_PKT_CTRL_REG_EN_JUMBO;
1147
1148         /* change to normal mode */
1149         netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS);
1150         netsec_write(priv, NETSEC_REG_PKT_CTRL, value);
1151
1152         while ((netsec_read(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) &
1153                 NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0)
1154                 cpu_relax();
1155
1156         /* clear any pending EMPTY/ERR irq status */
1157         netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, ~0);
1158
1159         /* Disable TX & RX intr */
1160         netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0);
1161
1162         return 0;
1163 }
1164
1165 static int netsec_start_gmac(struct netsec_priv *priv)
1166 {
1167         struct phy_device *phydev = priv->ndev->phydev;
1168         u32 value = 0;
1169         int ret;
1170
1171         if (phydev->speed != SPEED_1000)
1172                 value = (NETSEC_GMAC_MCR_REG_CST |
1173                          NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON);
1174
1175         if (netsec_mac_write(priv, GMAC_REG_MCR, value))
1176                 return -ETIMEDOUT;
1177         if (netsec_mac_write(priv, GMAC_REG_BMR,
1178                              NETSEC_GMAC_BMR_REG_RESET))
1179                 return -ETIMEDOUT;
1180
1181         /* Wait soft reset */
1182         usleep_range(1000, 5000);
1183
1184         ret = netsec_mac_read(priv, GMAC_REG_BMR, &value);
1185         if (ret)
1186                 return ret;
1187         if (value & NETSEC_GMAC_BMR_REG_SWR)
1188                 return -EAGAIN;
1189
1190         netsec_write(priv, MAC_REG_DESC_SOFT_RST, 1);
1191         if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1))
1192                 return -ETIMEDOUT;
1193
1194         netsec_write(priv, MAC_REG_DESC_INIT, 1);
1195         if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1))
1196                 return -ETIMEDOUT;
1197
1198         if (netsec_mac_write(priv, GMAC_REG_BMR,
1199                              NETSEC_GMAC_BMR_REG_COMMON))
1200                 return -ETIMEDOUT;
1201         if (netsec_mac_write(priv, GMAC_REG_RDLAR,
1202                              NETSEC_GMAC_RDLAR_REG_COMMON))
1203                 return -ETIMEDOUT;
1204         if (netsec_mac_write(priv, GMAC_REG_TDLAR,
1205                              NETSEC_GMAC_TDLAR_REG_COMMON))
1206                 return -ETIMEDOUT;
1207         if (netsec_mac_write(priv, GMAC_REG_MFFR, 0x80000001))
1208                 return -ETIMEDOUT;
1209
1210         ret = netsec_mac_update_to_phy_state(priv);
1211         if (ret)
1212                 return ret;
1213
1214         ret = netsec_mac_read(priv, GMAC_REG_OMR, &value);
1215         if (ret)
1216                 return ret;
1217
1218         value |= NETSEC_GMAC_OMR_REG_SR;
1219         value |= NETSEC_GMAC_OMR_REG_ST;
1220
1221         netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
1222         netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
1223
1224         netsec_et_set_coalesce(priv->ndev, &priv->et_coalesce);
1225
1226         if (netsec_mac_write(priv, GMAC_REG_OMR, value))
1227                 return -ETIMEDOUT;
1228
1229         return 0;
1230 }
1231
1232 static int netsec_stop_gmac(struct netsec_priv *priv)
1233 {
1234         u32 value;
1235         int ret;
1236
1237         ret = netsec_mac_read(priv, GMAC_REG_OMR, &value);
1238         if (ret)
1239                 return ret;
1240         value &= ~NETSEC_GMAC_OMR_REG_SR;
1241         value &= ~NETSEC_GMAC_OMR_REG_ST;
1242
1243         /* disable all interrupts */
1244         netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
1245         netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
1246
1247         return netsec_mac_write(priv, GMAC_REG_OMR, value);
1248 }
1249
1250 static void netsec_phy_adjust_link(struct net_device *ndev)
1251 {
1252         struct netsec_priv *priv = netdev_priv(ndev);
1253
1254         if (ndev->phydev->link)
1255                 netsec_start_gmac(priv);
1256         else
1257                 netsec_stop_gmac(priv);
1258
1259         phy_print_status(ndev->phydev);
1260 }
1261
1262 static irqreturn_t netsec_irq_handler(int irq, void *dev_id)
1263 {
1264         struct netsec_priv *priv = dev_id;
1265         u32 val, status = netsec_read(priv, NETSEC_REG_TOP_STATUS);
1266         unsigned long flags;
1267
1268         /* Disable interrupts */
1269         if (status & NETSEC_IRQ_TX) {
1270                 val = netsec_read(priv, NETSEC_REG_NRM_TX_STATUS);
1271                 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, val);
1272         }
1273         if (status & NETSEC_IRQ_RX) {
1274                 val = netsec_read(priv, NETSEC_REG_NRM_RX_STATUS);
1275                 netsec_write(priv, NETSEC_REG_NRM_RX_STATUS, val);
1276         }
1277
1278         spin_lock_irqsave(&priv->reglock, flags);
1279         netsec_write(priv, NETSEC_REG_INTEN_CLR, NETSEC_IRQ_RX | NETSEC_IRQ_TX);
1280         spin_unlock_irqrestore(&priv->reglock, flags);
1281
1282         napi_schedule(&priv->napi);
1283
1284         return IRQ_HANDLED;
1285 }
1286
1287 static int netsec_netdev_open(struct net_device *ndev)
1288 {
1289         struct netsec_priv *priv = netdev_priv(ndev);
1290         int ret;
1291
1292         pm_runtime_get_sync(priv->dev);
1293
1294         ret = netsec_setup_rx_dring(priv);
1295         if (ret) {
1296                 netif_err(priv, probe, priv->ndev,
1297                           "%s: fail setup ring\n", __func__);
1298                 goto err1;
1299         }
1300
1301         ret = request_irq(priv->ndev->irq, netsec_irq_handler,
1302                           IRQF_SHARED, "netsec", priv);
1303         if (ret) {
1304                 netif_err(priv, drv, priv->ndev, "request_irq failed\n");
1305                 goto err2;
1306         }
1307
1308         if (dev_of_node(priv->dev)) {
1309                 if (!of_phy_connect(priv->ndev, priv->phy_np,
1310                                     netsec_phy_adjust_link, 0,
1311                                     priv->phy_interface)) {
1312                         netif_err(priv, link, priv->ndev, "missing PHY\n");
1313                         ret = -ENODEV;
1314                         goto err3;
1315                 }
1316         } else {
1317                 ret = phy_connect_direct(priv->ndev, priv->phydev,
1318                                          netsec_phy_adjust_link,
1319                                          priv->phy_interface);
1320                 if (ret) {
1321                         netif_err(priv, link, priv->ndev,
1322                                   "phy_connect_direct() failed (%d)\n", ret);
1323                         goto err3;
1324                 }
1325         }
1326
1327         phy_start(ndev->phydev);
1328
1329         netsec_start_gmac(priv);
1330         napi_enable(&priv->napi);
1331         netif_start_queue(ndev);
1332
1333         /* Enable TX+RX intr. */
1334         netsec_write(priv, NETSEC_REG_INTEN_SET, NETSEC_IRQ_RX | NETSEC_IRQ_TX);
1335
1336         return 0;
1337 err3:
1338         free_irq(priv->ndev->irq, priv);
1339 err2:
1340         netsec_uninit_pkt_dring(priv, NETSEC_RING_RX);
1341 err1:
1342         pm_runtime_put_sync(priv->dev);
1343         return ret;
1344 }
1345
1346 static int netsec_netdev_stop(struct net_device *ndev)
1347 {
1348         int ret;
1349         struct netsec_priv *priv = netdev_priv(ndev);
1350
1351         netif_stop_queue(priv->ndev);
1352         dma_wmb();
1353
1354         napi_disable(&priv->napi);
1355
1356         netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0);
1357         netsec_stop_gmac(priv);
1358
1359         free_irq(priv->ndev->irq, priv);
1360
1361         netsec_uninit_pkt_dring(priv, NETSEC_RING_TX);
1362         netsec_uninit_pkt_dring(priv, NETSEC_RING_RX);
1363
1364         phy_stop(ndev->phydev);
1365         phy_disconnect(ndev->phydev);
1366
1367         ret = netsec_reset_hardware(priv, false);
1368
1369         pm_runtime_put_sync(priv->dev);
1370
1371         return ret;
1372 }
1373
1374 static int netsec_netdev_init(struct net_device *ndev)
1375 {
1376         struct netsec_priv *priv = netdev_priv(ndev);
1377         int ret;
1378         u16 data;
1379
1380         ret = netsec_alloc_dring(priv, NETSEC_RING_TX);
1381         if (ret)
1382                 return ret;
1383
1384         ret = netsec_alloc_dring(priv, NETSEC_RING_RX);
1385         if (ret)
1386                 goto err1;
1387
1388         /* set phy power down */
1389         data = netsec_phy_read(priv->mii_bus, priv->phy_addr, MII_BMCR);
1390         netsec_phy_write(priv->mii_bus, priv->phy_addr, MII_BMCR,
1391                          data | BMCR_PDOWN);
1392
1393         ret = netsec_reset_hardware(priv, true);
1394         if (ret)
1395                 goto err2;
1396
1397         /* Restore phy power state */
1398         netsec_phy_write(priv->mii_bus, priv->phy_addr, MII_BMCR, data);
1399
1400         return 0;
1401 err2:
1402         netsec_free_dring(priv, NETSEC_RING_RX);
1403 err1:
1404         netsec_free_dring(priv, NETSEC_RING_TX);
1405         return ret;
1406 }
1407
1408 static void netsec_netdev_uninit(struct net_device *ndev)
1409 {
1410         struct netsec_priv *priv = netdev_priv(ndev);
1411
1412         netsec_free_dring(priv, NETSEC_RING_RX);
1413         netsec_free_dring(priv, NETSEC_RING_TX);
1414 }
1415
1416 static int netsec_netdev_set_features(struct net_device *ndev,
1417                                       netdev_features_t features)
1418 {
1419         struct netsec_priv *priv = netdev_priv(ndev);
1420
1421         priv->rx_cksum_offload_flag = !!(features & NETIF_F_RXCSUM);
1422
1423         return 0;
1424 }
1425
1426 static int netsec_netdev_ioctl(struct net_device *ndev, struct ifreq *ifr,
1427                                int cmd)
1428 {
1429         return phy_mii_ioctl(ndev->phydev, ifr, cmd);
1430 }
1431
1432 static const struct net_device_ops netsec_netdev_ops = {
1433         .ndo_init               = netsec_netdev_init,
1434         .ndo_uninit             = netsec_netdev_uninit,
1435         .ndo_open               = netsec_netdev_open,
1436         .ndo_stop               = netsec_netdev_stop,
1437         .ndo_start_xmit         = netsec_netdev_start_xmit,
1438         .ndo_set_features       = netsec_netdev_set_features,
1439         .ndo_set_mac_address    = eth_mac_addr,
1440         .ndo_validate_addr      = eth_validate_addr,
1441         .ndo_do_ioctl           = netsec_netdev_ioctl,
1442 };
1443
1444 static int netsec_of_probe(struct platform_device *pdev,
1445                            struct netsec_priv *priv, u32 *phy_addr)
1446 {
1447         priv->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1448         if (!priv->phy_np) {
1449                 dev_err(&pdev->dev, "missing required property 'phy-handle'\n");
1450                 return -EINVAL;
1451         }
1452
1453         *phy_addr = of_mdio_parse_addr(&pdev->dev, priv->phy_np);
1454
1455         priv->clk = devm_clk_get(&pdev->dev, NULL); /* get by 'phy_ref_clk' */
1456         if (IS_ERR(priv->clk)) {
1457                 dev_err(&pdev->dev, "phy_ref_clk not found\n");
1458                 return PTR_ERR(priv->clk);
1459         }
1460         priv->freq = clk_get_rate(priv->clk);
1461
1462         return 0;
1463 }
1464
1465 static int netsec_acpi_probe(struct platform_device *pdev,
1466                              struct netsec_priv *priv, u32 *phy_addr)
1467 {
1468         int ret;
1469
1470         if (!IS_ENABLED(CONFIG_ACPI))
1471                 return -ENODEV;
1472
1473         ret = device_property_read_u32(&pdev->dev, "phy-channel", phy_addr);
1474         if (ret) {
1475                 dev_err(&pdev->dev,
1476                         "missing required property 'phy-channel'\n");
1477                 return ret;
1478         }
1479
1480         ret = device_property_read_u32(&pdev->dev,
1481                                        "socionext,phy-clock-frequency",
1482                                        &priv->freq);
1483         if (ret)
1484                 dev_err(&pdev->dev,
1485                         "missing required property 'socionext,phy-clock-frequency'\n");
1486         return ret;
1487 }
1488
1489 static void netsec_unregister_mdio(struct netsec_priv *priv)
1490 {
1491         struct phy_device *phydev = priv->phydev;
1492
1493         if (!dev_of_node(priv->dev) && phydev) {
1494                 phy_device_remove(phydev);
1495                 phy_device_free(phydev);
1496         }
1497
1498         mdiobus_unregister(priv->mii_bus);
1499 }
1500
1501 static int netsec_register_mdio(struct netsec_priv *priv, u32 phy_addr)
1502 {
1503         struct mii_bus *bus;
1504         int ret;
1505
1506         bus = devm_mdiobus_alloc(priv->dev);
1507         if (!bus)
1508                 return -ENOMEM;
1509
1510         snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(priv->dev));
1511         bus->priv = priv;
1512         bus->name = "SNI NETSEC MDIO";
1513         bus->read = netsec_phy_read;
1514         bus->write = netsec_phy_write;
1515         bus->parent = priv->dev;
1516         priv->mii_bus = bus;
1517
1518         if (dev_of_node(priv->dev)) {
1519                 struct device_node *mdio_node, *parent = dev_of_node(priv->dev);
1520
1521                 mdio_node = of_get_child_by_name(parent, "mdio");
1522                 if (mdio_node) {
1523                         parent = mdio_node;
1524                 } else {
1525                         /* older f/w doesn't populate the mdio subnode,
1526                          * allow relaxed upgrade of f/w in due time.
1527                          */
1528                         dev_info(priv->dev, "Upgrade f/w for mdio subnode!\n");
1529                 }
1530
1531                 ret = of_mdiobus_register(bus, parent);
1532                 of_node_put(mdio_node);
1533
1534                 if (ret) {
1535                         dev_err(priv->dev, "mdiobus register err(%d)\n", ret);
1536                         return ret;
1537                 }
1538         } else {
1539                 /* Mask out all PHYs from auto probing. */
1540                 bus->phy_mask = ~0;
1541                 ret = mdiobus_register(bus);
1542                 if (ret) {
1543                         dev_err(priv->dev, "mdiobus register err(%d)\n", ret);
1544                         return ret;
1545                 }
1546
1547                 priv->phydev = get_phy_device(bus, phy_addr, false);
1548                 if (IS_ERR(priv->phydev)) {
1549                         ret = PTR_ERR(priv->phydev);
1550                         dev_err(priv->dev, "get_phy_device err(%d)\n", ret);
1551                         priv->phydev = NULL;
1552                         mdiobus_unregister(bus);
1553                         return -ENODEV;
1554                 }
1555
1556                 ret = phy_device_register(priv->phydev);
1557                 if (ret) {
1558                         phy_device_free(priv->phydev);
1559                         mdiobus_unregister(bus);
1560                         dev_err(priv->dev,
1561                                 "phy_device_register err(%d)\n", ret);
1562                 }
1563         }
1564
1565         return ret;
1566 }
1567
1568 static int netsec_probe(struct platform_device *pdev)
1569 {
1570         struct resource *mmio_res, *eeprom_res, *irq_res;
1571         u8 *mac, macbuf[ETH_ALEN];
1572         struct netsec_priv *priv;
1573         u32 hw_ver, phy_addr = 0;
1574         struct net_device *ndev;
1575         int ret;
1576
1577         mmio_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1578         if (!mmio_res) {
1579                 dev_err(&pdev->dev, "No MMIO resource found.\n");
1580                 return -ENODEV;
1581         }
1582
1583         eeprom_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1584         if (!eeprom_res) {
1585                 dev_info(&pdev->dev, "No EEPROM resource found.\n");
1586                 return -ENODEV;
1587         }
1588
1589         irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1590         if (!irq_res) {
1591                 dev_err(&pdev->dev, "No IRQ resource found.\n");
1592                 return -ENODEV;
1593         }
1594
1595         ndev = alloc_etherdev(sizeof(*priv));
1596         if (!ndev)
1597                 return -ENOMEM;
1598
1599         priv = netdev_priv(ndev);
1600
1601         spin_lock_init(&priv->reglock);
1602         SET_NETDEV_DEV(ndev, &pdev->dev);
1603         platform_set_drvdata(pdev, priv);
1604         ndev->irq = irq_res->start;
1605         priv->dev = &pdev->dev;
1606         priv->ndev = ndev;
1607
1608         priv->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV |
1609                            NETIF_MSG_LINK | NETIF_MSG_PROBE;
1610
1611         priv->phy_interface = device_get_phy_mode(&pdev->dev);
1612         if ((int)priv->phy_interface < 0) {
1613                 dev_err(&pdev->dev, "missing required property 'phy-mode'\n");
1614                 ret = -ENODEV;
1615                 goto free_ndev;
1616         }
1617
1618         priv->ioaddr = devm_ioremap(&pdev->dev, mmio_res->start,
1619                                     resource_size(mmio_res));
1620         if (!priv->ioaddr) {
1621                 dev_err(&pdev->dev, "devm_ioremap() failed\n");
1622                 ret = -ENXIO;
1623                 goto free_ndev;
1624         }
1625
1626         priv->eeprom_base = devm_ioremap(&pdev->dev, eeprom_res->start,
1627                                          resource_size(eeprom_res));
1628         if (!priv->eeprom_base) {
1629                 dev_err(&pdev->dev, "devm_ioremap() failed for EEPROM\n");
1630                 ret = -ENXIO;
1631                 goto free_ndev;
1632         }
1633
1634         mac = device_get_mac_address(&pdev->dev, macbuf, sizeof(macbuf));
1635         if (mac)
1636                 ether_addr_copy(ndev->dev_addr, mac);
1637
1638         if (priv->eeprom_base &&
1639             (!mac || !is_valid_ether_addr(ndev->dev_addr))) {
1640                 void __iomem *macp = priv->eeprom_base +
1641                                         NETSEC_EEPROM_MAC_ADDRESS;
1642
1643                 ndev->dev_addr[0] = readb(macp + 3);
1644                 ndev->dev_addr[1] = readb(macp + 2);
1645                 ndev->dev_addr[2] = readb(macp + 1);
1646                 ndev->dev_addr[3] = readb(macp + 0);
1647                 ndev->dev_addr[4] = readb(macp + 7);
1648                 ndev->dev_addr[5] = readb(macp + 6);
1649         }
1650
1651         if (!is_valid_ether_addr(ndev->dev_addr)) {
1652                 dev_warn(&pdev->dev, "No MAC address found, using random\n");
1653                 eth_hw_addr_random(ndev);
1654         }
1655
1656         if (dev_of_node(&pdev->dev))
1657                 ret = netsec_of_probe(pdev, priv, &phy_addr);
1658         else
1659                 ret = netsec_acpi_probe(pdev, priv, &phy_addr);
1660         if (ret)
1661                 goto free_ndev;
1662
1663         priv->phy_addr = phy_addr;
1664
1665         if (!priv->freq) {
1666                 dev_err(&pdev->dev, "missing PHY reference clock frequency\n");
1667                 ret = -ENODEV;
1668                 goto free_ndev;
1669         }
1670
1671         /* default for throughput */
1672         priv->et_coalesce.rx_coalesce_usecs = 500;
1673         priv->et_coalesce.rx_max_coalesced_frames = 8;
1674         priv->et_coalesce.tx_coalesce_usecs = 500;
1675         priv->et_coalesce.tx_max_coalesced_frames = 8;
1676
1677         ret = device_property_read_u32(&pdev->dev, "max-frame-size",
1678                                        &ndev->max_mtu);
1679         if (ret < 0)
1680                 ndev->max_mtu = ETH_DATA_LEN;
1681
1682         /* runtime_pm coverage just for probe, open/close also cover it */
1683         pm_runtime_enable(&pdev->dev);
1684         pm_runtime_get_sync(&pdev->dev);
1685
1686         hw_ver = netsec_read(priv, NETSEC_REG_F_TAIKI_VER);
1687         /* this driver only supports F_TAIKI style NETSEC */
1688         if (NETSEC_F_NETSEC_VER_MAJOR_NUM(hw_ver) !=
1689             NETSEC_F_NETSEC_VER_MAJOR_NUM(NETSEC_REG_NETSEC_VER_F_TAIKI)) {
1690                 ret = -ENODEV;
1691                 goto pm_disable;
1692         }
1693
1694         dev_info(&pdev->dev, "hardware revision %d.%d\n",
1695                  hw_ver >> 16, hw_ver & 0xffff);
1696
1697         netif_napi_add(ndev, &priv->napi, netsec_napi_poll, NAPI_POLL_WEIGHT);
1698
1699         ndev->netdev_ops = &netsec_netdev_ops;
1700         ndev->ethtool_ops = &netsec_ethtool_ops;
1701
1702         ndev->features |= NETIF_F_HIGHDMA | NETIF_F_RXCSUM | NETIF_F_GSO |
1703                                 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1704         ndev->hw_features = ndev->features;
1705
1706         priv->rx_cksum_offload_flag = true;
1707
1708         ret = netsec_register_mdio(priv, phy_addr);
1709         if (ret)
1710                 goto unreg_napi;
1711
1712         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)))
1713                 dev_warn(&pdev->dev, "Failed to set DMA mask\n");
1714
1715         ret = register_netdev(ndev);
1716         if (ret) {
1717                 netif_err(priv, probe, ndev, "register_netdev() failed\n");
1718                 goto unreg_mii;
1719         }
1720
1721         pm_runtime_put_sync(&pdev->dev);
1722         return 0;
1723
1724 unreg_mii:
1725         netsec_unregister_mdio(priv);
1726 unreg_napi:
1727         netif_napi_del(&priv->napi);
1728 pm_disable:
1729         pm_runtime_put_sync(&pdev->dev);
1730         pm_runtime_disable(&pdev->dev);
1731 free_ndev:
1732         free_netdev(ndev);
1733         dev_err(&pdev->dev, "init failed\n");
1734
1735         return ret;
1736 }
1737
1738 static int netsec_remove(struct platform_device *pdev)
1739 {
1740         struct netsec_priv *priv = platform_get_drvdata(pdev);
1741
1742         unregister_netdev(priv->ndev);
1743
1744         netsec_unregister_mdio(priv);
1745
1746         netif_napi_del(&priv->napi);
1747
1748         pm_runtime_disable(&pdev->dev);
1749         free_netdev(priv->ndev);
1750
1751         return 0;
1752 }
1753
1754 #ifdef CONFIG_PM
1755 static int netsec_runtime_suspend(struct device *dev)
1756 {
1757         struct netsec_priv *priv = dev_get_drvdata(dev);
1758
1759         netsec_write(priv, NETSEC_REG_CLK_EN, 0);
1760
1761         clk_disable_unprepare(priv->clk);
1762
1763         return 0;
1764 }
1765
1766 static int netsec_runtime_resume(struct device *dev)
1767 {
1768         struct netsec_priv *priv = dev_get_drvdata(dev);
1769
1770         clk_prepare_enable(priv->clk);
1771
1772         netsec_write(priv, NETSEC_REG_CLK_EN, NETSEC_CLK_EN_REG_DOM_D |
1773                                                NETSEC_CLK_EN_REG_DOM_C |
1774                                                NETSEC_CLK_EN_REG_DOM_G);
1775         return 0;
1776 }
1777 #endif
1778
1779 static const struct dev_pm_ops netsec_pm_ops = {
1780         SET_RUNTIME_PM_OPS(netsec_runtime_suspend, netsec_runtime_resume, NULL)
1781 };
1782
1783 static const struct of_device_id netsec_dt_ids[] = {
1784         { .compatible = "socionext,synquacer-netsec" },
1785         { }
1786 };
1787 MODULE_DEVICE_TABLE(of, netsec_dt_ids);
1788
1789 #ifdef CONFIG_ACPI
1790 static const struct acpi_device_id netsec_acpi_ids[] = {
1791         { "SCX0001" },
1792         { }
1793 };
1794 MODULE_DEVICE_TABLE(acpi, netsec_acpi_ids);
1795 #endif
1796
1797 static struct platform_driver netsec_driver = {
1798         .probe  = netsec_probe,
1799         .remove = netsec_remove,
1800         .driver = {
1801                 .name = "netsec",
1802                 .pm = &netsec_pm_ops,
1803                 .of_match_table = netsec_dt_ids,
1804                 .acpi_match_table = ACPI_PTR(netsec_acpi_ids),
1805         },
1806 };
1807 module_platform_driver(netsec_driver);
1808
1809 MODULE_AUTHOR("Jassi Brar <jaswinder.singh@linaro.org>");
1810 MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
1811 MODULE_DESCRIPTION("NETSEC Ethernet driver");
1812 MODULE_LICENSE("GPL");