2 sis190.c: Silicon Integrated Systems SiS190 ethernet driver
4 Copyright (c) 2003 K.M. Liu <kmliu@sis.com>
5 Copyright (c) 2003, 2004 Jeff Garzik <jgarzik@pobox.com>
6 Copyright (c) 2003, 2004, 2005 Francois Romieu <romieu@fr.zoreil.com>
8 Based on r8169.c, tg3.c, 8139cp.c, skge.c, epic100.c and SiS 190/191
11 This software may be used and distributed according to the terms of
12 the GNU General Public License (GPL), incorporated herein by reference.
13 Drivers based on or derived from this code fall under the GPL and must
14 retain the authorship, copyright and license notice. This file is not
15 a complete program and may only be used when the entire operating
16 system is licensed under the GPL.
18 See the file COPYING in this distribution for more information.
22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/netdevice.h>
28 #include <linux/rtnetlink.h>
29 #include <linux/etherdevice.h>
30 #include <linux/ethtool.h>
31 #include <linux/pci.h>
32 #include <linux/mii.h>
33 #include <linux/delay.h>
34 #include <linux/crc32.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/slab.h>
39 #define PHY_MAX_ADDR 32
40 #define PHY_ID_ANY 0x1f
41 #define MII_REG_ANY 0x1f
43 #define DRV_VERSION "1.4"
44 #define DRV_NAME "sis190"
45 #define SIS190_DRIVER_NAME DRV_NAME " Gigabit Ethernet driver " DRV_VERSION
47 #define sis190_rx_skb netif_rx
48 #define sis190_rx_quota(count, quota) count
50 #define NUM_TX_DESC 64 /* [8..1024] */
51 #define NUM_RX_DESC 64 /* [8..8192] */
52 #define TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
53 #define RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
54 #define RX_BUF_SIZE 1536
55 #define RX_BUF_MASK 0xfff8
57 #define SIS190_REGS_SIZE 0x80
58 #define SIS190_TX_TIMEOUT (6*HZ)
59 #define SIS190_PHY_TIMEOUT (10*HZ)
60 #define SIS190_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
61 NETIF_MSG_LINK | NETIF_MSG_IFUP | \
64 /* Enhanced PHY access register bit definitions */
65 #define EhnMIIread 0x0000
66 #define EhnMIIwrite 0x0020
67 #define EhnMIIdataShift 16
68 #define EhnMIIpmdShift 6 /* 7016 only */
69 #define EhnMIIregShift 11
70 #define EhnMIIreq 0x0010
71 #define EhnMIInotDone 0x0010
73 /* Write/read MMIO register */
74 #define SIS_W8(reg, val) writeb ((val), ioaddr + (reg))
75 #define SIS_W16(reg, val) writew ((val), ioaddr + (reg))
76 #define SIS_W32(reg, val) writel ((val), ioaddr + (reg))
77 #define SIS_R8(reg) readb (ioaddr + (reg))
78 #define SIS_R16(reg) readw (ioaddr + (reg))
79 #define SIS_R32(reg) readl (ioaddr + (reg))
81 #define SIS_PCI_COMMIT() SIS_R32(IntrControl)
83 enum sis190_registers {
85 TxDescStartAddr = 0x04,
86 rsv0 = 0x08, // reserved
87 TxSts = 0x0c, // unused (Control/Status)
89 RxDescStartAddr = 0x14,
90 rsv1 = 0x18, // reserved
91 RxSts = 0x1c, // unused
95 IntrTimer = 0x2c, // unused (Interrupt Timer)
96 PMControl = 0x30, // unused (Power Mgmt Control/Status)
97 rsv2 = 0x34, // reserved
100 StationControl = 0x40,
102 GIoCR = 0x48, // unused (GMAC IO Compensation)
103 GIoCtrl = 0x4c, // unused (GMAC IO Control)
105 TxLimit = 0x54, // unused (Tx MAC Timer/TryLimit)
106 RGDelay = 0x58, // unused (RGMII Tx Internal Delay)
107 rsv3 = 0x5c, // reserved
111 // Undocumented = 0x6c,
113 RxWolData = 0x74, // unused (Rx WOL Data Access)
114 RxMPSControl = 0x78, // unused (Rx MPS Control)
115 rsv4 = 0x7c, // reserved
118 enum sis190_register_content {
120 SoftInt = 0x40000000, // unused
121 Timeup = 0x20000000, // unused
122 PauseFrame = 0x00080000, // unused
123 MagicPacket = 0x00040000, // unused
124 WakeupFrame = 0x00020000, // unused
125 LinkChange = 0x00010000,
126 RxQEmpty = 0x00000080,
128 TxQ1Empty = 0x00000020, // unused
129 TxQ1Int = 0x00000010,
130 TxQ0Empty = 0x00000008, // unused
131 TxQ0Int = 0x00000004,
137 CmdRxEnb = 0x08, // unused
139 RxBufEmpty = 0x01, // unused
142 Cfg9346_Lock = 0x00, // unused
143 Cfg9346_Unlock = 0xc0, // unused
146 AcceptErr = 0x20, // unused
147 AcceptRunt = 0x10, // unused
148 AcceptBroadcast = 0x0800,
149 AcceptMulticast = 0x0400,
150 AcceptMyPhys = 0x0200,
151 AcceptAllPhys = 0x0100,
155 RxCfgDMAShift = 8, // 0x1a in RxControl ?
158 TxInterFrameGapShift = 24,
159 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
161 LinkStatus = 0x02, // unused
162 FullDup = 0x01, // unused
165 TBILinkOK = 0x02000000, // unused
182 enum _DescStatusBit {
184 OWNbit = 0x80000000, // RXOWN/TXOWN
185 INTbit = 0x40000000, // RXINT/TXINT
186 CRCbit = 0x00020000, // CRCOFF/CRCEN
187 PADbit = 0x00010000, // PREADD/PADEN
189 RingEnd = 0x80000000,
191 LSEN = 0x08000000, // TSO ? -- FR
210 ColCountMask = 0x0000ffff,
224 RxDescCountMask = 0x7f000000, // multi-desc pkt when > 1 ? -- FR
233 RxSizeMask = 0x0000ffff
235 * The asic could apparently do vlan, TSO, jumbo (sis191 only) and
236 * provide two (unused with Linux) Tx queues. No publicly
237 * available documentation alas.
241 enum sis190_eeprom_access_register_bits {
242 EECS = 0x00000001, // unused
243 EECLK = 0x00000002, // unused
244 EEDO = 0x00000008, // unused
245 EEDI = 0x00000004, // unused
248 EEWOP = 0x00000100 // unused
251 /* EEPROM Addresses */
252 enum sis190_eeprom_address {
253 EEPROMSignature = 0x00,
254 EEPROMCLK = 0x01, // unused
259 enum sis190_feature {
265 struct sis190_private {
266 void __iomem *mmio_addr;
267 struct pci_dev *pci_dev;
268 struct net_device *dev;
277 struct RxDesc *RxDescRing;
278 struct TxDesc *TxDescRing;
279 struct sk_buff *Rx_skbuff[NUM_RX_DESC];
280 struct sk_buff *Tx_skbuff[NUM_TX_DESC];
281 struct work_struct phy_task;
282 struct timer_list timer;
284 struct mii_if_info mii_if;
285 struct list_head first_phy;
296 struct list_head list;
303 enum sis190_phy_type {
310 static struct mii_chip_info {
315 } mii_chip_table[] = {
316 { "Atheros PHY", { 0x004d, 0xd010 }, LAN, 0 },
317 { "Atheros PHY AR8012", { 0x004d, 0xd020 }, LAN, 0 },
318 { "Broadcom PHY BCM5461", { 0x0020, 0x60c0 }, LAN, F_PHY_BCM5461 },
319 { "Broadcom PHY AC131", { 0x0143, 0xbc70 }, LAN, 0 },
320 { "Agere PHY ET1101B", { 0x0282, 0xf010 }, LAN, 0 },
321 { "Marvell PHY 88E1111", { 0x0141, 0x0cc0 }, LAN, F_PHY_88E1111 },
322 { "Realtek PHY RTL8201", { 0x0000, 0x8200 }, LAN, 0 },
326 static const struct {
328 } sis_chip_info[] = {
329 { "SiS 190 PCI Fast Ethernet adapter" },
330 { "SiS 191 PCI Gigabit Ethernet adapter" },
333 static const struct pci_device_id sis190_pci_tbl[] = {
334 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0190), 0, 0, 0 },
335 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0191), 0, 0, 1 },
339 MODULE_DEVICE_TABLE(pci, sis190_pci_tbl);
341 static int rx_copybreak = 200;
347 MODULE_DESCRIPTION("SiS sis190/191 Gigabit Ethernet driver");
348 module_param(rx_copybreak, int, 0);
349 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
350 module_param_named(debug, debug.msg_enable, int, 0);
351 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
352 MODULE_AUTHOR("K.M. Liu <kmliu@sis.com>, Ueimor <romieu@fr.zoreil.com>");
353 MODULE_VERSION(DRV_VERSION);
354 MODULE_LICENSE("GPL");
356 static const u32 sis190_intr_mask =
357 RxQEmpty | RxQInt | TxQ1Int | TxQ0Int | RxHalt | TxHalt | LinkChange;
360 * Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
361 * The chips use a 64 element hash table based on the Ethernet CRC.
363 static const int multicast_filter_limit = 32;
365 static void __mdio_cmd(void __iomem *ioaddr, u32 ctl)
369 SIS_W32(GMIIControl, ctl);
373 for (i = 0; i < 100; i++) {
374 if (!(SIS_R32(GMIIControl) & EhnMIInotDone))
380 pr_err("PHY command failed !\n");
383 static void mdio_write(void __iomem *ioaddr, int phy_id, int reg, int val)
385 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIwrite |
386 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift) |
387 (((u32) val) << EhnMIIdataShift));
390 static int mdio_read(void __iomem *ioaddr, int phy_id, int reg)
392 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIread |
393 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift));
395 return (u16) (SIS_R32(GMIIControl) >> EhnMIIdataShift);
398 static void __mdio_write(struct net_device *dev, int phy_id, int reg, int val)
400 struct sis190_private *tp = netdev_priv(dev);
402 mdio_write(tp->mmio_addr, phy_id, reg, val);
405 static int __mdio_read(struct net_device *dev, int phy_id, int reg)
407 struct sis190_private *tp = netdev_priv(dev);
409 return mdio_read(tp->mmio_addr, phy_id, reg);
412 static u16 mdio_read_latched(void __iomem *ioaddr, int phy_id, int reg)
414 mdio_read(ioaddr, phy_id, reg);
415 return mdio_read(ioaddr, phy_id, reg);
418 static u16 sis190_read_eeprom(void __iomem *ioaddr, u32 reg)
423 if (!(SIS_R32(ROMControl) & 0x0002))
426 SIS_W32(ROMInterface, EEREQ | EEROP | (reg << 10));
428 for (i = 0; i < 200; i++) {
429 if (!(SIS_R32(ROMInterface) & EEREQ)) {
430 data = (SIS_R32(ROMInterface) & 0xffff0000) >> 16;
439 static void sis190_irq_mask_and_ack(void __iomem *ioaddr)
441 SIS_W32(IntrMask, 0x00);
442 SIS_W32(IntrStatus, 0xffffffff);
446 static void sis190_asic_down(void __iomem *ioaddr)
448 /* Stop the chip's Tx and Rx DMA processes. */
450 SIS_W32(TxControl, 0x1a00);
451 SIS_W32(RxControl, 0x1a00);
453 sis190_irq_mask_and_ack(ioaddr);
456 static void sis190_mark_as_last_descriptor(struct RxDesc *desc)
458 desc->size |= cpu_to_le32(RingEnd);
461 static inline void sis190_give_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
463 u32 eor = le32_to_cpu(desc->size) & RingEnd;
466 desc->size = cpu_to_le32((rx_buf_sz & RX_BUF_MASK) | eor);
468 desc->status = cpu_to_le32(OWNbit | INTbit);
471 static inline void sis190_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
474 desc->addr = cpu_to_le32(mapping);
475 sis190_give_to_asic(desc, rx_buf_sz);
478 static inline void sis190_make_unusable_by_asic(struct RxDesc *desc)
481 desc->addr = cpu_to_le32(0xdeadbeef);
482 desc->size &= cpu_to_le32(RingEnd);
487 static struct sk_buff *sis190_alloc_rx_skb(struct sis190_private *tp,
490 u32 rx_buf_sz = tp->rx_buf_sz;
494 skb = netdev_alloc_skb(tp->dev, rx_buf_sz);
496 goto skb_alloc_failed;
497 mapping = dma_map_single(&tp->pci_dev->dev, skb->data, tp->rx_buf_sz,
499 if (dma_mapping_error(&tp->pci_dev->dev, mapping))
501 sis190_map_to_asic(desc, mapping, rx_buf_sz);
506 dev_kfree_skb_any(skb);
508 sis190_make_unusable_by_asic(desc);
512 static u32 sis190_rx_fill(struct sis190_private *tp, struct net_device *dev,
517 for (cur = start; cur < end; cur++) {
518 unsigned int i = cur % NUM_RX_DESC;
520 if (tp->Rx_skbuff[i])
523 tp->Rx_skbuff[i] = sis190_alloc_rx_skb(tp, tp->RxDescRing + i);
525 if (!tp->Rx_skbuff[i])
531 static bool sis190_try_rx_copy(struct sis190_private *tp,
532 struct sk_buff **sk_buff, int pkt_size,
538 if (pkt_size >= rx_copybreak)
541 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
545 dma_sync_single_for_cpu(&tp->pci_dev->dev, addr, tp->rx_buf_sz,
547 skb_copy_to_linear_data(skb, sk_buff[0]->data, pkt_size);
554 static inline int sis190_rx_pkt_err(u32 status, struct net_device_stats *stats)
556 #define ErrMask (OVRUN | SHORT | LIMIT | MIIER | NIBON | COLON | ABORT)
558 if ((status & CRCOK) && !(status & ErrMask))
561 if (!(status & CRCOK))
562 stats->rx_crc_errors++;
563 else if (status & OVRUN)
564 stats->rx_over_errors++;
565 else if (status & (SHORT | LIMIT))
566 stats->rx_length_errors++;
567 else if (status & (MIIER | NIBON | COLON))
568 stats->rx_frame_errors++;
574 static int sis190_rx_interrupt(struct net_device *dev,
575 struct sis190_private *tp, void __iomem *ioaddr)
577 struct net_device_stats *stats = &dev->stats;
578 u32 rx_left, cur_rx = tp->cur_rx;
581 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
582 rx_left = sis190_rx_quota(rx_left, (u32) dev->quota);
584 for (; rx_left > 0; rx_left--, cur_rx++) {
585 unsigned int entry = cur_rx % NUM_RX_DESC;
586 struct RxDesc *desc = tp->RxDescRing + entry;
589 if (le32_to_cpu(desc->status) & OWNbit)
592 status = le32_to_cpu(desc->PSize);
594 //netif_info(tp, intr, dev, "Rx PSize = %08x\n", status);
596 if (sis190_rx_pkt_err(status, stats) < 0)
597 sis190_give_to_asic(desc, tp->rx_buf_sz);
599 struct sk_buff *skb = tp->Rx_skbuff[entry];
600 dma_addr_t addr = le32_to_cpu(desc->addr);
601 int pkt_size = (status & RxSizeMask) - 4;
602 struct pci_dev *pdev = tp->pci_dev;
604 if (unlikely(pkt_size > tp->rx_buf_sz)) {
605 netif_info(tp, intr, dev,
606 "(frag) status = %08x\n", status);
608 stats->rx_length_errors++;
609 sis190_give_to_asic(desc, tp->rx_buf_sz);
614 if (sis190_try_rx_copy(tp, &skb, pkt_size, addr)) {
615 dma_sync_single_for_device(&pdev->dev, addr,
618 sis190_give_to_asic(desc, tp->rx_buf_sz);
620 dma_unmap_single(&pdev->dev, addr,
623 tp->Rx_skbuff[entry] = NULL;
624 sis190_make_unusable_by_asic(desc);
627 skb_put(skb, pkt_size);
628 skb->protocol = eth_type_trans(skb, dev);
633 stats->rx_bytes += pkt_size;
634 if ((status & BCAST) == MCAST)
638 count = cur_rx - tp->cur_rx;
641 delta = sis190_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
643 netif_info(tp, intr, dev, "no Rx buffer allocated\n");
644 tp->dirty_rx += delta;
646 if ((tp->dirty_rx + NUM_RX_DESC) == tp->cur_rx)
647 netif_emerg(tp, intr, dev, "Rx buffers exhausted\n");
652 static void sis190_unmap_tx_skb(struct pci_dev *pdev, struct sk_buff *skb,
657 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
659 dma_unmap_single(&pdev->dev, le32_to_cpu(desc->addr), len,
662 memset(desc, 0x00, sizeof(*desc));
665 static inline int sis190_tx_pkt_err(u32 status, struct net_device_stats *stats)
667 #define TxErrMask (WND | TABRT | FIFO | LINK)
669 if (!unlikely(status & TxErrMask))
673 stats->tx_window_errors++;
675 stats->tx_aborted_errors++;
677 stats->tx_fifo_errors++;
679 stats->tx_carrier_errors++;
686 static void sis190_tx_interrupt(struct net_device *dev,
687 struct sis190_private *tp, void __iomem *ioaddr)
689 struct net_device_stats *stats = &dev->stats;
690 u32 pending, dirty_tx = tp->dirty_tx;
692 * It would not be needed if queueing was allowed to be enabled
693 * again too early (hint: think preempt and unclocked smp systems).
695 unsigned int queue_stopped;
698 pending = tp->cur_tx - dirty_tx;
699 queue_stopped = (pending == NUM_TX_DESC);
701 for (; pending; pending--, dirty_tx++) {
702 unsigned int entry = dirty_tx % NUM_TX_DESC;
703 struct TxDesc *txd = tp->TxDescRing + entry;
704 u32 status = le32_to_cpu(txd->status);
710 skb = tp->Tx_skbuff[entry];
712 if (likely(sis190_tx_pkt_err(status, stats) == 0)) {
714 stats->tx_bytes += skb->len;
715 stats->collisions += ((status & ColCountMask) - 1);
718 sis190_unmap_tx_skb(tp->pci_dev, skb, txd);
719 tp->Tx_skbuff[entry] = NULL;
720 dev_consume_skb_irq(skb);
723 if (tp->dirty_tx != dirty_tx) {
724 tp->dirty_tx = dirty_tx;
727 netif_wake_queue(dev);
732 * The interrupt handler does all of the Rx thread work and cleans up after
735 static irqreturn_t sis190_irq(int irq, void *__dev)
737 struct net_device *dev = __dev;
738 struct sis190_private *tp = netdev_priv(dev);
739 void __iomem *ioaddr = tp->mmio_addr;
740 unsigned int handled = 0;
743 status = SIS_R32(IntrStatus);
745 if ((status == 0xffffffff) || !status)
750 if (unlikely(!netif_running(dev))) {
751 sis190_asic_down(ioaddr);
755 SIS_W32(IntrStatus, status);
757 // netif_info(tp, intr, dev, "status = %08x\n", status);
759 if (status & LinkChange) {
760 netif_info(tp, intr, dev, "link change\n");
761 del_timer(&tp->timer);
762 schedule_work(&tp->phy_task);
766 sis190_rx_interrupt(dev, tp, ioaddr);
768 if (status & TxQ0Int)
769 sis190_tx_interrupt(dev, tp, ioaddr);
771 return IRQ_RETVAL(handled);
774 #ifdef CONFIG_NET_POLL_CONTROLLER
775 static void sis190_netpoll(struct net_device *dev)
777 struct sis190_private *tp = netdev_priv(dev);
778 const int irq = tp->pci_dev->irq;
781 sis190_irq(irq, dev);
786 static void sis190_free_rx_skb(struct sis190_private *tp,
787 struct sk_buff **sk_buff, struct RxDesc *desc)
789 struct pci_dev *pdev = tp->pci_dev;
791 dma_unmap_single(&pdev->dev, le32_to_cpu(desc->addr), tp->rx_buf_sz,
793 dev_kfree_skb(*sk_buff);
795 sis190_make_unusable_by_asic(desc);
798 static void sis190_rx_clear(struct sis190_private *tp)
802 for (i = 0; i < NUM_RX_DESC; i++) {
803 if (!tp->Rx_skbuff[i])
805 sis190_free_rx_skb(tp, tp->Rx_skbuff + i, tp->RxDescRing + i);
809 static void sis190_init_ring_indexes(struct sis190_private *tp)
811 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
814 static int sis190_init_ring(struct net_device *dev)
816 struct sis190_private *tp = netdev_priv(dev);
818 sis190_init_ring_indexes(tp);
820 memset(tp->Tx_skbuff, 0x0, NUM_TX_DESC * sizeof(struct sk_buff *));
821 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
823 if (sis190_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
826 sis190_mark_as_last_descriptor(tp->RxDescRing + NUM_RX_DESC - 1);
835 static void sis190_set_rx_mode(struct net_device *dev)
837 struct sis190_private *tp = netdev_priv(dev);
838 void __iomem *ioaddr = tp->mmio_addr;
840 u32 mc_filter[2]; /* Multicast hash filter */
843 if (dev->flags & IFF_PROMISC) {
845 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
847 mc_filter[1] = mc_filter[0] = 0xffffffff;
848 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
849 (dev->flags & IFF_ALLMULTI)) {
850 /* Too many to filter perfectly -- accept all multicasts. */
851 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
852 mc_filter[1] = mc_filter[0] = 0xffffffff;
854 struct netdev_hw_addr *ha;
856 rx_mode = AcceptBroadcast | AcceptMyPhys;
857 mc_filter[1] = mc_filter[0] = 0;
858 netdev_for_each_mc_addr(ha, dev) {
860 ether_crc(ETH_ALEN, ha->addr) & 0x3f;
861 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
862 rx_mode |= AcceptMulticast;
866 spin_lock_irqsave(&tp->lock, flags);
868 SIS_W16(RxMacControl, rx_mode | 0x2);
869 SIS_W32(RxHashTable, mc_filter[0]);
870 SIS_W32(RxHashTable + 4, mc_filter[1]);
872 spin_unlock_irqrestore(&tp->lock, flags);
875 static void sis190_soft_reset(void __iomem *ioaddr)
877 SIS_W32(IntrControl, 0x8000);
879 SIS_W32(IntrControl, 0x0);
880 sis190_asic_down(ioaddr);
883 static void sis190_hw_start(struct net_device *dev)
885 struct sis190_private *tp = netdev_priv(dev);
886 void __iomem *ioaddr = tp->mmio_addr;
888 sis190_soft_reset(ioaddr);
890 SIS_W32(TxDescStartAddr, tp->tx_dma);
891 SIS_W32(RxDescStartAddr, tp->rx_dma);
893 SIS_W32(IntrStatus, 0xffffffff);
894 SIS_W32(IntrMask, 0x0);
895 SIS_W32(GMIIControl, 0x0);
896 SIS_W32(TxMacControl, 0x60);
897 SIS_W16(RxMacControl, 0x02);
898 SIS_W32(RxHashTable, 0x0);
900 SIS_W32(RxWolCtrl, 0x0);
901 SIS_W32(RxWolData, 0x0);
905 sis190_set_rx_mode(dev);
907 /* Enable all known interrupts by setting the interrupt mask. */
908 SIS_W32(IntrMask, sis190_intr_mask);
910 SIS_W32(TxControl, 0x1a00 | CmdTxEnb);
911 SIS_W32(RxControl, 0x1a1d);
913 netif_start_queue(dev);
916 static void sis190_phy_task(struct work_struct *work)
918 struct sis190_private *tp =
919 container_of(work, struct sis190_private, phy_task);
920 struct net_device *dev = tp->dev;
921 void __iomem *ioaddr = tp->mmio_addr;
922 int phy_id = tp->mii_if.phy_id;
927 if (!netif_running(dev))
930 val = mdio_read(ioaddr, phy_id, MII_BMCR);
931 if (val & BMCR_RESET) {
932 // FIXME: needlessly high ? -- FR 02/07/2005
933 mod_timer(&tp->timer, jiffies + HZ/10);
937 val = mdio_read_latched(ioaddr, phy_id, MII_BMSR);
938 if (!(val & BMSR_ANEGCOMPLETE) && tp->link_status != LNK_AUTONEG) {
939 netif_carrier_off(dev);
940 netif_warn(tp, link, dev, "auto-negotiating...\n");
941 tp->link_status = LNK_AUTONEG;
942 } else if ((val & BMSR_LSTATUS) && tp->link_status != LNK_ON) {
949 { LPA_1000FULL, 0x07000c00 | 0x00001000,
950 "1000 Mbps Full Duplex" },
951 { LPA_1000HALF, 0x07000c00,
952 "1000 Mbps Half Duplex" },
953 { LPA_100FULL, 0x04000800 | 0x00001000,
954 "100 Mbps Full Duplex" },
955 { LPA_100HALF, 0x04000800,
956 "100 Mbps Half Duplex" },
957 { LPA_10FULL, 0x04000400 | 0x00001000,
958 "10 Mbps Full Duplex" },
959 { LPA_10HALF, 0x04000400,
960 "10 Mbps Half Duplex" },
961 { 0, 0x04000400, "unknown" }
963 u16 adv, autoexp, gigadv, gigrec;
965 val = mdio_read(ioaddr, phy_id, 0x1f);
966 netif_info(tp, link, dev, "mii ext = %04x\n", val);
968 val = mdio_read(ioaddr, phy_id, MII_LPA);
969 adv = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
970 autoexp = mdio_read(ioaddr, phy_id, MII_EXPANSION);
971 netif_info(tp, link, dev, "mii lpa=%04x adv=%04x exp=%04x\n",
974 if (val & LPA_NPAGE && autoexp & EXPANSION_NWAY) {
975 /* check for gigabit speed */
976 gigadv = mdio_read(ioaddr, phy_id, MII_CTRL1000);
977 gigrec = mdio_read(ioaddr, phy_id, MII_STAT1000);
978 val = (gigadv & (gigrec >> 2));
979 if (val & ADVERTISE_1000FULL)
981 else if (val & ADVERTISE_1000HALF)
987 for (p = reg31; p->val; p++) {
988 if ((val & p->val) == p->val)
993 p->ctl |= SIS_R32(StationControl) & ~0x0f001c00;
995 if ((tp->features & F_HAS_RGMII) &&
996 (tp->features & F_PHY_BCM5461)) {
997 // Set Tx Delay in RGMII mode.
998 mdio_write(ioaddr, phy_id, 0x18, 0xf1c7);
1000 mdio_write(ioaddr, phy_id, 0x1c, 0x8c00);
1001 p->ctl |= 0x03000000;
1004 SIS_W32(StationControl, p->ctl);
1006 if (tp->features & F_HAS_RGMII) {
1007 SIS_W32(RGDelay, 0x0441);
1008 SIS_W32(RGDelay, 0x0440);
1011 tp->negotiated_lpa = p->val;
1013 netif_info(tp, link, dev, "link on %s mode\n", p->msg);
1014 netif_carrier_on(dev);
1015 tp->link_status = LNK_ON;
1016 } else if (!(val & BMSR_LSTATUS) && tp->link_status != LNK_AUTONEG)
1017 tp->link_status = LNK_OFF;
1018 mod_timer(&tp->timer, jiffies + SIS190_PHY_TIMEOUT);
1024 static void sis190_phy_timer(struct timer_list *t)
1026 struct sis190_private *tp = from_timer(tp, t, timer);
1027 struct net_device *dev = tp->dev;
1029 if (likely(netif_running(dev)))
1030 schedule_work(&tp->phy_task);
1033 static inline void sis190_delete_timer(struct net_device *dev)
1035 struct sis190_private *tp = netdev_priv(dev);
1037 del_timer_sync(&tp->timer);
1040 static inline void sis190_request_timer(struct net_device *dev)
1042 struct sis190_private *tp = netdev_priv(dev);
1043 struct timer_list *timer = &tp->timer;
1045 timer_setup(timer, sis190_phy_timer, 0);
1046 timer->expires = jiffies + SIS190_PHY_TIMEOUT;
1050 static void sis190_set_rxbufsize(struct sis190_private *tp,
1051 struct net_device *dev)
1053 unsigned int mtu = dev->mtu;
1055 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1056 /* RxDesc->size has a licence to kill the lower bits */
1057 if (tp->rx_buf_sz & 0x07) {
1059 tp->rx_buf_sz &= RX_BUF_MASK;
1063 static int sis190_open(struct net_device *dev)
1065 struct sis190_private *tp = netdev_priv(dev);
1066 struct pci_dev *pdev = tp->pci_dev;
1069 sis190_set_rxbufsize(tp, dev);
1072 * Rx and Tx descriptors need 256 bytes alignment.
1073 * dma_alloc_coherent() guarantees a stronger alignment.
1075 tp->TxDescRing = dma_alloc_coherent(&pdev->dev, TX_RING_BYTES,
1076 &tp->tx_dma, GFP_KERNEL);
1077 if (!tp->TxDescRing)
1080 tp->RxDescRing = dma_alloc_coherent(&pdev->dev, RX_RING_BYTES,
1081 &tp->rx_dma, GFP_KERNEL);
1082 if (!tp->RxDescRing)
1085 rc = sis190_init_ring(dev);
1089 sis190_request_timer(dev);
1091 rc = request_irq(pdev->irq, sis190_irq, IRQF_SHARED, dev->name, dev);
1093 goto err_release_timer_2;
1095 sis190_hw_start(dev);
1099 err_release_timer_2:
1100 sis190_delete_timer(dev);
1101 sis190_rx_clear(tp);
1103 dma_free_coherent(&pdev->dev, RX_RING_BYTES, tp->RxDescRing,
1106 dma_free_coherent(&pdev->dev, TX_RING_BYTES, tp->TxDescRing,
1111 static void sis190_tx_clear(struct sis190_private *tp)
1115 for (i = 0; i < NUM_TX_DESC; i++) {
1116 struct sk_buff *skb = tp->Tx_skbuff[i];
1121 sis190_unmap_tx_skb(tp->pci_dev, skb, tp->TxDescRing + i);
1122 tp->Tx_skbuff[i] = NULL;
1125 tp->dev->stats.tx_dropped++;
1127 tp->cur_tx = tp->dirty_tx = 0;
1130 static void sis190_down(struct net_device *dev)
1132 struct sis190_private *tp = netdev_priv(dev);
1133 void __iomem *ioaddr = tp->mmio_addr;
1134 unsigned int poll_locked = 0;
1136 sis190_delete_timer(dev);
1138 netif_stop_queue(dev);
1141 spin_lock_irq(&tp->lock);
1143 sis190_asic_down(ioaddr);
1145 spin_unlock_irq(&tp->lock);
1147 synchronize_irq(tp->pci_dev->irq);
1154 } while (SIS_R32(IntrMask));
1156 sis190_tx_clear(tp);
1157 sis190_rx_clear(tp);
1160 static int sis190_close(struct net_device *dev)
1162 struct sis190_private *tp = netdev_priv(dev);
1163 struct pci_dev *pdev = tp->pci_dev;
1167 free_irq(pdev->irq, dev);
1169 dma_free_coherent(&pdev->dev, TX_RING_BYTES, tp->TxDescRing,
1171 dma_free_coherent(&pdev->dev, RX_RING_BYTES, tp->RxDescRing,
1174 tp->TxDescRing = NULL;
1175 tp->RxDescRing = NULL;
1180 static netdev_tx_t sis190_start_xmit(struct sk_buff *skb,
1181 struct net_device *dev)
1183 struct sis190_private *tp = netdev_priv(dev);
1184 void __iomem *ioaddr = tp->mmio_addr;
1185 u32 len, entry, dirty_tx;
1186 struct TxDesc *desc;
1189 if (unlikely(skb->len < ETH_ZLEN)) {
1190 if (skb_padto(skb, ETH_ZLEN)) {
1191 dev->stats.tx_dropped++;
1199 entry = tp->cur_tx % NUM_TX_DESC;
1200 desc = tp->TxDescRing + entry;
1202 if (unlikely(le32_to_cpu(desc->status) & OWNbit)) {
1203 netif_stop_queue(dev);
1204 netif_err(tp, tx_err, dev,
1205 "BUG! Tx Ring full when queue awake!\n");
1206 return NETDEV_TX_BUSY;
1209 mapping = dma_map_single(&tp->pci_dev->dev, skb->data, len,
1211 if (dma_mapping_error(&tp->pci_dev->dev, mapping)) {
1212 netif_err(tp, tx_err, dev,
1213 "PCI mapping failed, dropping packet");
1214 return NETDEV_TX_BUSY;
1217 tp->Tx_skbuff[entry] = skb;
1219 desc->PSize = cpu_to_le32(len);
1220 desc->addr = cpu_to_le32(mapping);
1222 desc->size = cpu_to_le32(len);
1223 if (entry == (NUM_TX_DESC - 1))
1224 desc->size |= cpu_to_le32(RingEnd);
1228 desc->status = cpu_to_le32(OWNbit | INTbit | DEFbit | CRCbit | PADbit);
1229 if (tp->negotiated_lpa & (LPA_1000HALF | LPA_100HALF | LPA_10HALF)) {
1231 desc->status |= cpu_to_le32(COLEN | CRSEN | BKFEN);
1232 if (tp->negotiated_lpa & (LPA_1000HALF | LPA_1000FULL))
1233 desc->status |= cpu_to_le32(EXTEN | BSTEN); /* gigabit HD */
1240 SIS_W32(TxControl, 0x1a00 | CmdReset | CmdTxEnb);
1242 dirty_tx = tp->dirty_tx;
1243 if ((tp->cur_tx - NUM_TX_DESC) == dirty_tx) {
1244 netif_stop_queue(dev);
1246 if (dirty_tx != tp->dirty_tx)
1247 netif_wake_queue(dev);
1250 return NETDEV_TX_OK;
1253 static void sis190_free_phy(struct list_head *first_phy)
1255 struct sis190_phy *cur, *next;
1257 list_for_each_entry_safe(cur, next, first_phy, list) {
1263 * sis190_default_phy - Select default PHY for sis190 mac.
1264 * @dev: the net device to probe for
1266 * Select first detected PHY with link as default.
1267 * If no one is link on, select PHY whose types is HOME as default.
1268 * If HOME doesn't exist, select LAN.
1270 static u16 sis190_default_phy(struct net_device *dev)
1272 struct sis190_phy *phy, *phy_home, *phy_default, *phy_lan;
1273 struct sis190_private *tp = netdev_priv(dev);
1274 struct mii_if_info *mii_if = &tp->mii_if;
1275 void __iomem *ioaddr = tp->mmio_addr;
1278 phy_home = phy_default = phy_lan = NULL;
1280 list_for_each_entry(phy, &tp->first_phy, list) {
1281 status = mdio_read_latched(ioaddr, phy->phy_id, MII_BMSR);
1283 // Link ON & Not select default PHY & not ghost PHY.
1284 if ((status & BMSR_LSTATUS) &&
1286 (phy->type != UNKNOWN)) {
1289 status = mdio_read(ioaddr, phy->phy_id, MII_BMCR);
1290 mdio_write(ioaddr, phy->phy_id, MII_BMCR,
1291 status | BMCR_ANENABLE | BMCR_ISOLATE);
1292 if (phy->type == HOME)
1294 else if (phy->type == LAN)
1301 phy_default = phy_home;
1303 phy_default = phy_lan;
1305 phy_default = list_first_entry(&tp->first_phy,
1306 struct sis190_phy, list);
1309 if (mii_if->phy_id != phy_default->phy_id) {
1310 mii_if->phy_id = phy_default->phy_id;
1311 if (netif_msg_probe(tp))
1312 pr_info("%s: Using transceiver at address %d as default\n",
1313 pci_name(tp->pci_dev), mii_if->phy_id);
1316 status = mdio_read(ioaddr, mii_if->phy_id, MII_BMCR);
1317 status &= (~BMCR_ISOLATE);
1319 mdio_write(ioaddr, mii_if->phy_id, MII_BMCR, status);
1320 status = mdio_read_latched(ioaddr, mii_if->phy_id, MII_BMSR);
1325 static void sis190_init_phy(struct net_device *dev, struct sis190_private *tp,
1326 struct sis190_phy *phy, unsigned int phy_id,
1329 void __iomem *ioaddr = tp->mmio_addr;
1330 struct mii_chip_info *p;
1332 INIT_LIST_HEAD(&phy->list);
1333 phy->status = mii_status;
1334 phy->phy_id = phy_id;
1336 phy->id[0] = mdio_read(ioaddr, phy_id, MII_PHYSID1);
1337 phy->id[1] = mdio_read(ioaddr, phy_id, MII_PHYSID2);
1339 for (p = mii_chip_table; p->type; p++) {
1340 if ((p->id[0] == phy->id[0]) &&
1341 (p->id[1] == (phy->id[1] & 0xfff0))) {
1347 phy->type = (p->type == MIX) ?
1348 ((mii_status & (BMSR_100FULL | BMSR_100HALF)) ?
1349 LAN : HOME) : p->type;
1350 tp->features |= p->feature;
1351 if (netif_msg_probe(tp))
1352 pr_info("%s: %s transceiver at address %d\n",
1353 pci_name(tp->pci_dev), p->name, phy_id);
1355 phy->type = UNKNOWN;
1356 if (netif_msg_probe(tp))
1357 pr_info("%s: unknown PHY 0x%x:0x%x transceiver at address %d\n",
1358 pci_name(tp->pci_dev),
1359 phy->id[0], (phy->id[1] & 0xfff0), phy_id);
1363 static void sis190_mii_probe_88e1111_fixup(struct sis190_private *tp)
1365 if (tp->features & F_PHY_88E1111) {
1366 void __iomem *ioaddr = tp->mmio_addr;
1367 int phy_id = tp->mii_if.phy_id;
1373 p = (tp->features & F_HAS_RGMII) ? reg[0] : reg[1];
1375 mdio_write(ioaddr, phy_id, 0x1b, p[0]);
1377 mdio_write(ioaddr, phy_id, 0x14, p[1]);
1383 * sis190_mii_probe - Probe MII PHY for sis190
1384 * @dev: the net device to probe for
1386 * Search for total of 32 possible mii phy addresses.
1387 * Identify and set current phy if found one,
1388 * return error if it failed to found.
1390 static int sis190_mii_probe(struct net_device *dev)
1392 struct sis190_private *tp = netdev_priv(dev);
1393 struct mii_if_info *mii_if = &tp->mii_if;
1394 void __iomem *ioaddr = tp->mmio_addr;
1398 INIT_LIST_HEAD(&tp->first_phy);
1400 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1401 struct sis190_phy *phy;
1404 status = mdio_read_latched(ioaddr, phy_id, MII_BMSR);
1406 // Try next mii if the current one is not accessible.
1407 if (status == 0xffff || status == 0x0000)
1410 phy = kmalloc(sizeof(*phy), GFP_KERNEL);
1412 sis190_free_phy(&tp->first_phy);
1417 sis190_init_phy(dev, tp, phy, phy_id, status);
1419 list_add(&tp->first_phy, &phy->list);
1422 if (list_empty(&tp->first_phy)) {
1423 if (netif_msg_probe(tp))
1424 pr_info("%s: No MII transceivers found!\n",
1425 pci_name(tp->pci_dev));
1430 /* Select default PHY for mac */
1431 sis190_default_phy(dev);
1433 sis190_mii_probe_88e1111_fixup(tp);
1436 mii_if->mdio_read = __mdio_read;
1437 mii_if->mdio_write = __mdio_write;
1438 mii_if->phy_id_mask = PHY_ID_ANY;
1439 mii_if->reg_num_mask = MII_REG_ANY;
1444 static void sis190_mii_remove(struct net_device *dev)
1446 struct sis190_private *tp = netdev_priv(dev);
1448 sis190_free_phy(&tp->first_phy);
1451 static void sis190_release_board(struct pci_dev *pdev)
1453 struct net_device *dev = pci_get_drvdata(pdev);
1454 struct sis190_private *tp = netdev_priv(dev);
1456 iounmap(tp->mmio_addr);
1457 pci_release_regions(pdev);
1458 pci_disable_device(pdev);
1462 static struct net_device *sis190_init_board(struct pci_dev *pdev)
1464 struct sis190_private *tp;
1465 struct net_device *dev;
1466 void __iomem *ioaddr;
1469 dev = alloc_etherdev(sizeof(*tp));
1475 SET_NETDEV_DEV(dev, &pdev->dev);
1477 tp = netdev_priv(dev);
1479 tp->msg_enable = netif_msg_init(debug.msg_enable, SIS190_MSG_DEFAULT);
1481 rc = pci_enable_device(pdev);
1483 if (netif_msg_probe(tp))
1484 pr_err("%s: enable failure\n", pci_name(pdev));
1485 goto err_free_dev_1;
1490 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1491 if (netif_msg_probe(tp))
1492 pr_err("%s: region #0 is no MMIO resource\n",
1494 goto err_pci_disable_2;
1496 if (pci_resource_len(pdev, 0) < SIS190_REGS_SIZE) {
1497 if (netif_msg_probe(tp))
1498 pr_err("%s: invalid PCI region size(s)\n",
1500 goto err_pci_disable_2;
1503 rc = pci_request_regions(pdev, DRV_NAME);
1505 if (netif_msg_probe(tp))
1506 pr_err("%s: could not request regions\n",
1508 goto err_pci_disable_2;
1511 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1513 if (netif_msg_probe(tp))
1514 pr_err("%s: DMA configuration failed\n",
1516 goto err_free_res_3;
1519 pci_set_master(pdev);
1521 ioaddr = ioremap(pci_resource_start(pdev, 0), SIS190_REGS_SIZE);
1523 if (netif_msg_probe(tp))
1524 pr_err("%s: cannot remap MMIO, aborting\n",
1527 goto err_free_res_3;
1531 tp->mmio_addr = ioaddr;
1532 tp->link_status = LNK_OFF;
1534 sis190_irq_mask_and_ack(ioaddr);
1536 sis190_soft_reset(ioaddr);
1541 pci_release_regions(pdev);
1543 pci_disable_device(pdev);
1551 static void sis190_tx_timeout(struct net_device *dev, unsigned int txqueue)
1553 struct sis190_private *tp = netdev_priv(dev);
1554 void __iomem *ioaddr = tp->mmio_addr;
1557 /* Disable Tx, if not already */
1558 tmp8 = SIS_R8(TxControl);
1559 if (tmp8 & CmdTxEnb)
1560 SIS_W8(TxControl, tmp8 & ~CmdTxEnb);
1562 netif_info(tp, tx_err, dev, "Transmit timeout, status %08x %08x\n",
1563 SIS_R32(TxControl), SIS_R32(TxSts));
1565 /* Disable interrupts by clearing the interrupt mask. */
1566 SIS_W32(IntrMask, 0x0000);
1568 /* Stop a shared interrupt from scavenging while we are. */
1569 spin_lock_irq(&tp->lock);
1570 sis190_tx_clear(tp);
1571 spin_unlock_irq(&tp->lock);
1573 /* ...and finally, reset everything. */
1574 sis190_hw_start(dev);
1576 netif_wake_queue(dev);
1579 static void sis190_set_rgmii(struct sis190_private *tp, u8 reg)
1581 tp->features |= (reg & 0x80) ? F_HAS_RGMII : 0;
1584 static int sis190_get_mac_addr_from_eeprom(struct pci_dev *pdev,
1585 struct net_device *dev)
1587 struct sis190_private *tp = netdev_priv(dev);
1588 void __iomem *ioaddr = tp->mmio_addr;
1589 __le16 addr[ETH_ALEN / 2];
1593 if (netif_msg_probe(tp))
1594 pr_info("%s: Read MAC address from EEPROM\n", pci_name(pdev));
1596 /* Check to see if there is a sane EEPROM */
1597 sig = (u16) sis190_read_eeprom(ioaddr, EEPROMSignature);
1599 if ((sig == 0xffff) || (sig == 0x0000)) {
1600 if (netif_msg_probe(tp))
1601 pr_info("%s: Error EEPROM read %x\n",
1602 pci_name(pdev), sig);
1606 /* Get MAC address from EEPROM */
1607 for (i = 0; i < ETH_ALEN / 2; i++) {
1608 u16 w = sis190_read_eeprom(ioaddr, EEPROMMACAddr + i);
1610 addr[i] = cpu_to_le16(w);
1612 eth_hw_addr_set(dev, (u8 *)addr);
1614 sis190_set_rgmii(tp, sis190_read_eeprom(ioaddr, EEPROMInfo));
1620 * sis190_get_mac_addr_from_apc - Get MAC address for SiS96x model
1622 * @dev: network device to get address for
1624 * SiS96x model, use APC CMOS RAM to store MAC address.
1625 * APC CMOS RAM is accessed through ISA bridge.
1626 * MAC address is read into @net_dev->dev_addr.
1628 static int sis190_get_mac_addr_from_apc(struct pci_dev *pdev,
1629 struct net_device *dev)
1631 static const u16 ids[] = { 0x0965, 0x0966, 0x0968 };
1632 struct sis190_private *tp = netdev_priv(dev);
1633 struct pci_dev *isa_bridge;
1638 if (netif_msg_probe(tp))
1639 pr_info("%s: Read MAC address from APC\n", pci_name(pdev));
1641 for (i = 0; i < ARRAY_SIZE(ids); i++) {
1642 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, ids[i], NULL);
1648 if (netif_msg_probe(tp))
1649 pr_info("%s: Can not find ISA bridge\n",
1654 /* Enable port 78h & 79h to access APC Registers. */
1655 pci_read_config_byte(isa_bridge, 0x48, &tmp8);
1656 reg = (tmp8 & ~0x02);
1657 pci_write_config_byte(isa_bridge, 0x48, reg);
1659 pci_read_config_byte(isa_bridge, 0x48, ®);
1661 for (i = 0; i < ETH_ALEN; i++) {
1662 outb(0x9 + i, 0x78);
1663 addr[i] = inb(0x79);
1665 eth_hw_addr_set(dev, addr);
1670 sis190_set_rgmii(tp, reg);
1672 /* Restore the value to ISA Bridge */
1673 pci_write_config_byte(isa_bridge, 0x48, tmp8);
1674 pci_dev_put(isa_bridge);
1680 * sis190_init_rxfilter - Initialize the Rx filter
1681 * @dev: network device to initialize
1683 * Set receive filter address to our MAC address
1684 * and enable packet filtering.
1686 static inline void sis190_init_rxfilter(struct net_device *dev)
1688 struct sis190_private *tp = netdev_priv(dev);
1689 void __iomem *ioaddr = tp->mmio_addr;
1693 ctl = SIS_R16(RxMacControl);
1695 * Disable packet filtering before setting filter.
1696 * Note: SiS's driver writes 32 bits but RxMacControl is 16 bits
1697 * only and followed by RxMacAddr (6 bytes). Strange. -- FR
1699 SIS_W16(RxMacControl, ctl & ~0x0f00);
1701 for (i = 0; i < ETH_ALEN; i++)
1702 SIS_W8(RxMacAddr + i, dev->dev_addr[i]);
1704 SIS_W16(RxMacControl, ctl);
1708 static int sis190_get_mac_addr(struct pci_dev *pdev, struct net_device *dev)
1712 rc = sis190_get_mac_addr_from_eeprom(pdev, dev);
1716 pci_read_config_byte(pdev, 0x73, ®);
1718 if (reg & 0x00000001)
1719 rc = sis190_get_mac_addr_from_apc(pdev, dev);
1724 static void sis190_set_speed_auto(struct net_device *dev)
1726 struct sis190_private *tp = netdev_priv(dev);
1727 void __iomem *ioaddr = tp->mmio_addr;
1728 int phy_id = tp->mii_if.phy_id;
1731 netif_info(tp, link, dev, "Enabling Auto-negotiation\n");
1733 val = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
1735 // Enable 10/100 Full/Half Mode, leave MII_ADVERTISE bit4:0
1737 mdio_write(ioaddr, phy_id, MII_ADVERTISE, (val & ADVERTISE_SLCT) |
1738 ADVERTISE_100FULL | ADVERTISE_10FULL |
1739 ADVERTISE_100HALF | ADVERTISE_10HALF);
1741 // Enable 1000 Full Mode.
1742 mdio_write(ioaddr, phy_id, MII_CTRL1000, ADVERTISE_1000FULL);
1744 // Enable auto-negotiation and restart auto-negotiation.
1745 mdio_write(ioaddr, phy_id, MII_BMCR,
1746 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET);
1749 static int sis190_get_link_ksettings(struct net_device *dev,
1750 struct ethtool_link_ksettings *cmd)
1752 struct sis190_private *tp = netdev_priv(dev);
1754 mii_ethtool_get_link_ksettings(&tp->mii_if, cmd);
1759 static int sis190_set_link_ksettings(struct net_device *dev,
1760 const struct ethtool_link_ksettings *cmd)
1762 struct sis190_private *tp = netdev_priv(dev);
1764 return mii_ethtool_set_link_ksettings(&tp->mii_if, cmd);
1767 static void sis190_get_drvinfo(struct net_device *dev,
1768 struct ethtool_drvinfo *info)
1770 struct sis190_private *tp = netdev_priv(dev);
1772 strscpy(info->driver, DRV_NAME, sizeof(info->driver));
1773 strscpy(info->version, DRV_VERSION, sizeof(info->version));
1774 strscpy(info->bus_info, pci_name(tp->pci_dev),
1775 sizeof(info->bus_info));
1778 static int sis190_get_regs_len(struct net_device *dev)
1780 return SIS190_REGS_SIZE;
1783 static void sis190_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1786 struct sis190_private *tp = netdev_priv(dev);
1787 unsigned long flags;
1789 spin_lock_irqsave(&tp->lock, flags);
1790 memcpy_fromio(p, tp->mmio_addr, regs->len);
1791 spin_unlock_irqrestore(&tp->lock, flags);
1794 static int sis190_nway_reset(struct net_device *dev)
1796 struct sis190_private *tp = netdev_priv(dev);
1798 return mii_nway_restart(&tp->mii_if);
1801 static u32 sis190_get_msglevel(struct net_device *dev)
1803 struct sis190_private *tp = netdev_priv(dev);
1805 return tp->msg_enable;
1808 static void sis190_set_msglevel(struct net_device *dev, u32 value)
1810 struct sis190_private *tp = netdev_priv(dev);
1812 tp->msg_enable = value;
1815 static const struct ethtool_ops sis190_ethtool_ops = {
1816 .get_drvinfo = sis190_get_drvinfo,
1817 .get_regs_len = sis190_get_regs_len,
1818 .get_regs = sis190_get_regs,
1819 .get_link = ethtool_op_get_link,
1820 .get_msglevel = sis190_get_msglevel,
1821 .set_msglevel = sis190_set_msglevel,
1822 .nway_reset = sis190_nway_reset,
1823 .get_link_ksettings = sis190_get_link_ksettings,
1824 .set_link_ksettings = sis190_set_link_ksettings,
1827 static int sis190_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1829 struct sis190_private *tp = netdev_priv(dev);
1831 return !netif_running(dev) ? -EINVAL :
1832 generic_mii_ioctl(&tp->mii_if, if_mii(ifr), cmd, NULL);
1835 static int sis190_mac_addr(struct net_device *dev, void *p)
1839 rc = eth_mac_addr(dev, p);
1841 sis190_init_rxfilter(dev);
1845 static const struct net_device_ops sis190_netdev_ops = {
1846 .ndo_open = sis190_open,
1847 .ndo_stop = sis190_close,
1848 .ndo_eth_ioctl = sis190_ioctl,
1849 .ndo_start_xmit = sis190_start_xmit,
1850 .ndo_tx_timeout = sis190_tx_timeout,
1851 .ndo_set_rx_mode = sis190_set_rx_mode,
1852 .ndo_set_mac_address = sis190_mac_addr,
1853 .ndo_validate_addr = eth_validate_addr,
1854 #ifdef CONFIG_NET_POLL_CONTROLLER
1855 .ndo_poll_controller = sis190_netpoll,
1859 static int sis190_init_one(struct pci_dev *pdev,
1860 const struct pci_device_id *ent)
1862 static int printed_version = 0;
1863 struct sis190_private *tp;
1864 struct net_device *dev;
1865 void __iomem *ioaddr;
1868 if (!printed_version) {
1869 if (netif_msg_drv(&debug))
1870 pr_info(SIS190_DRIVER_NAME " loaded\n");
1871 printed_version = 1;
1874 dev = sis190_init_board(pdev);
1880 pci_set_drvdata(pdev, dev);
1882 tp = netdev_priv(dev);
1883 ioaddr = tp->mmio_addr;
1885 rc = sis190_get_mac_addr(pdev, dev);
1887 goto err_release_board;
1889 sis190_init_rxfilter(dev);
1891 INIT_WORK(&tp->phy_task, sis190_phy_task);
1893 dev->netdev_ops = &sis190_netdev_ops;
1895 dev->ethtool_ops = &sis190_ethtool_ops;
1896 dev->watchdog_timeo = SIS190_TX_TIMEOUT;
1898 spin_lock_init(&tp->lock);
1900 rc = sis190_mii_probe(dev);
1902 goto err_release_board;
1904 rc = register_netdev(dev);
1906 goto err_remove_mii;
1908 if (netif_msg_probe(tp)) {
1909 netdev_info(dev, "%s: %s at %p (IRQ: %d), %pM\n",
1911 sis_chip_info[ent->driver_data].name,
1912 ioaddr, pdev->irq, dev->dev_addr);
1913 netdev_info(dev, "%s mode.\n",
1914 (tp->features & F_HAS_RGMII) ? "RGMII" : "GMII");
1917 netif_carrier_off(dev);
1919 sis190_set_speed_auto(dev);
1924 sis190_mii_remove(dev);
1926 sis190_release_board(pdev);
1930 static void sis190_remove_one(struct pci_dev *pdev)
1932 struct net_device *dev = pci_get_drvdata(pdev);
1933 struct sis190_private *tp = netdev_priv(dev);
1935 sis190_mii_remove(dev);
1936 cancel_work_sync(&tp->phy_task);
1937 unregister_netdev(dev);
1938 sis190_release_board(pdev);
1941 static struct pci_driver sis190_pci_driver = {
1943 .id_table = sis190_pci_tbl,
1944 .probe = sis190_init_one,
1945 .remove = sis190_remove_one,
1948 module_pci_driver(sis190_pci_driver);