1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2013 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/random.h>
17 #include "net_driver.h"
21 #include "farch_regs.h"
23 #include "workarounds.h"
25 #include "mcdi_pcol.h"
27 #include "siena_sriov.h"
29 /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
31 static void siena_init_wol(struct efx_nic *efx);
34 static void siena_push_irq_moderation(struct efx_channel *channel)
36 struct efx_nic *efx = channel->efx;
37 efx_dword_t timer_cmd;
39 if (channel->irq_moderation_us) {
42 ticks = efx_usecs_to_ticks(efx, channel->irq_moderation_us);
43 EFX_POPULATE_DWORD_2(timer_cmd,
45 FFE_CZ_TIMER_MODE_INT_HLDOFF,
49 EFX_POPULATE_DWORD_2(timer_cmd,
51 FFE_CZ_TIMER_MODE_DIS,
52 FRF_CZ_TC_TIMER_VAL, 0);
54 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
58 void siena_prepare_flush(struct efx_nic *efx)
60 if (efx->fc_disable++ == 0)
61 efx_mcdi_set_mac(efx);
64 void siena_finish_flush(struct efx_nic *efx)
66 if (--efx->fc_disable == 0)
67 efx_mcdi_set_mac(efx);
70 static const struct efx_farch_register_test siena_register_tests[] = {
72 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
74 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
76 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
78 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
80 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
81 { FR_AZ_SRM_TX_DC_CFG,
82 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
84 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
86 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
88 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
90 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
91 { FR_CZ_RX_RSS_IPV6_REG1,
92 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
93 { FR_CZ_RX_RSS_IPV6_REG2,
94 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
95 { FR_CZ_RX_RSS_IPV6_REG3,
96 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
99 static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
101 enum reset_type reset_method = RESET_TYPE_ALL;
104 efx_reset_down(efx, reset_method);
106 /* Reset the chip immediately so that it is completely
107 * quiescent regardless of what any VF driver does.
109 rc = efx_mcdi_reset(efx, reset_method);
114 efx_farch_test_registers(efx, siena_register_tests,
115 ARRAY_SIZE(siena_register_tests))
118 rc = efx_mcdi_reset(efx, reset_method);
120 rc2 = efx_reset_up(efx, reset_method, rc == 0);
121 return rc ? rc : rc2;
124 /**************************************************************************
128 **************************************************************************
131 static void siena_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
133 _efx_writed(efx, cpu_to_le32(host_time),
134 FR_CZ_MC_TREG_SMEM + MC_SMEM_P0_PTP_TIME_OFST);
137 static int siena_ptp_set_ts_config(struct efx_nic *efx,
138 struct hwtstamp_config *init)
142 switch (init->rx_filter) {
143 case HWTSTAMP_FILTER_NONE:
144 /* if TX timestamping is still requested then leave PTP on */
145 return efx_ptp_change_mode(efx,
146 init->tx_type != HWTSTAMP_TX_OFF,
147 efx_ptp_get_mode(efx));
148 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
149 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
150 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
151 init->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
152 return efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V1);
153 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
154 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
155 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
156 init->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
157 rc = efx_ptp_change_mode(efx, true,
158 MC_CMD_PTP_MODE_V2_ENHANCED);
159 /* bug 33070 - old versions of the firmware do not support the
160 * improved UUID filtering option. Similarly old versions of the
161 * application do not expect it to be enabled. If the firmware
162 * does not accept the enhanced mode, fall back to the standard
163 * PTP v2 UUID filtering. */
165 rc = efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V2);
172 /**************************************************************************
176 **************************************************************************
179 static int siena_map_reset_flags(u32 *flags)
182 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
183 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
185 SIENA_RESET_MC = (SIENA_RESET_PORT |
186 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
189 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
190 *flags &= ~SIENA_RESET_MC;
191 return RESET_TYPE_WORLD;
194 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
195 *flags &= ~SIENA_RESET_PORT;
196 return RESET_TYPE_ALL;
199 /* no invisible reset implemented */
205 /* When a PCI device is isolated from the bus, a subsequent MMIO read is
206 * required for the kernel EEH mechanisms to notice. As the Solarflare driver
207 * was written to minimise MMIO read (for latency) then a periodic call to check
208 * the EEH status of the device is required so that device recovery can happen
209 * in a timely fashion.
211 static void siena_monitor(struct efx_nic *efx)
213 struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev);
215 eeh_dev_check_failure(eehdev);
219 static int siena_probe_nvconfig(struct efx_nic *efx)
224 rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps);
226 efx->timer_quantum_ns =
227 (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ?
228 3072 : 6144; /* 768 cycles */
229 efx->timer_max_ns = efx->type->timer_period_max *
230 efx->timer_quantum_ns;
235 static int siena_dimension_resources(struct efx_nic *efx)
237 /* Each port has a small block of internal SRAM dedicated to
238 * the buffer table and descriptor caches. In theory we can
239 * map both blocks to one port, but we don't.
241 efx_farch_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
245 static unsigned int siena_mem_map_size(struct efx_nic *efx)
247 return FR_CZ_MC_TREG_SMEM +
248 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS;
251 static int siena_probe_nic(struct efx_nic *efx)
253 struct siena_nic_data *nic_data;
257 /* Allocate storage for hardware specific data */
258 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
262 efx->nic_data = nic_data;
264 if (efx_farch_fpga_ver(efx) != 0) {
265 netif_err(efx, probe, efx->net_dev,
266 "Siena FPGA not supported\n");
271 efx->max_channels = EFX_MAX_CHANNELS;
272 efx->max_tx_channels = EFX_MAX_CHANNELS;
274 efx_reado(efx, ®, FR_AZ_CS_DEBUG);
275 efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
277 rc = efx_mcdi_init(efx);
281 /* Now we can reset the NIC */
282 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
284 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
290 /* Allocate memory for INT_KER */
291 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
295 BUG_ON(efx->irq_status.dma_addr & 0x0f);
297 netif_dbg(efx, probe, efx->net_dev,
298 "INT_KER at %llx (virt %p phys %llx)\n",
299 (unsigned long long)efx->irq_status.dma_addr,
300 efx->irq_status.addr,
301 (unsigned long long)virt_to_phys(efx->irq_status.addr));
303 /* Read in the non-volatile configuration */
304 rc = siena_probe_nvconfig(efx);
306 netif_err(efx, probe, efx->net_dev,
307 "NVRAM is invalid therefore using defaults\n");
308 efx->phy_type = PHY_TYPE_NONE;
309 efx->mdio.prtad = MDIO_PRTAD_NONE;
314 rc = efx_mcdi_mon_probe(efx);
318 #ifdef CONFIG_SFC_SRIOV
319 efx_siena_sriov_probe(efx);
321 efx_ptp_defer_probe_with_channel(efx);
326 efx_nic_free_buffer(efx, &efx->irq_status);
329 efx_mcdi_detach(efx);
332 kfree(efx->nic_data);
336 static int siena_rx_pull_rss_config(struct efx_nic *efx)
340 /* Read from IPv6 RSS key as that's longer (the IPv4 key is just the
341 * first 128 bits of the same key, assuming it's been set by
342 * siena_rx_push_rss_config, below)
344 efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
345 memcpy(efx->rx_hash_key, &temp, sizeof(temp));
346 efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
347 memcpy(efx->rx_hash_key + sizeof(temp), &temp, sizeof(temp));
348 efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
349 memcpy(efx->rx_hash_key + 2 * sizeof(temp), &temp,
350 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
351 efx_farch_rx_pull_indir_table(efx);
355 static int siena_rx_push_rss_config(struct efx_nic *efx, bool user,
356 const u32 *rx_indir_table, const u8 *key)
360 /* Set hash key for IPv4 */
362 memcpy(efx->rx_hash_key, key, sizeof(temp));
363 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
364 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
366 /* Enable IPv6 RSS */
367 BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
368 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
369 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
370 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
371 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
372 memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
373 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
374 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
375 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
376 memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
377 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
378 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
380 memcpy(efx->rx_indir_table, rx_indir_table,
381 sizeof(efx->rx_indir_table));
382 efx_farch_rx_push_indir_table(efx);
387 /* This call performs hardware-specific global initialisation, such as
388 * defining the descriptor cache sizes and number of RSS channels.
389 * It does not set up any buffers, descriptor rings or event queues.
391 static int siena_init_nic(struct efx_nic *efx)
396 /* Recover from a failed assertion post-reset */
397 rc = efx_mcdi_handle_assertion(efx);
401 /* Squash TX of packets of 16 bytes or less */
402 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
403 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
404 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
406 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
407 * descriptors (which is bad).
409 efx_reado(efx, &temp, FR_AZ_TX_CFG);
410 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
411 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
412 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
414 efx_reado(efx, &temp, FR_AZ_RX_CFG);
415 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
416 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
417 /* Enable hash insertion. This is broken for the 'Falcon' hash
418 * if IPv6 hashing is also enabled, so also select Toeplitz
419 * TCP/IPv4 and IPv4 hashes. */
420 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
421 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
422 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
423 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE,
424 EFX_RX_USR_BUF_SIZE >> 5);
425 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
427 siena_rx_push_rss_config(efx, false, efx->rx_indir_table, NULL);
428 efx->rss_active = true;
430 /* Enable event logging */
431 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
435 /* Set destination of both TX and RX Flush events */
436 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
437 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
439 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
440 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
442 efx_farch_init_common(efx);
446 static void siena_remove_nic(struct efx_nic *efx)
448 efx_mcdi_mon_remove(efx);
450 efx_nic_free_buffer(efx, &efx->irq_status);
452 efx_mcdi_reset(efx, RESET_TYPE_ALL);
454 efx_mcdi_detach(efx);
457 /* Tear down the private nic state */
458 kfree(efx->nic_data);
459 efx->nic_data = NULL;
462 #define SIENA_DMA_STAT(ext_name, mcdi_name) \
463 [SIENA_STAT_ ## ext_name] = \
464 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
465 #define SIENA_OTHER_STAT(ext_name) \
466 [SIENA_STAT_ ## ext_name] = { #ext_name, 0, 0 }
467 #define GENERIC_SW_STAT(ext_name) \
468 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
470 static const struct efx_hw_stat_desc siena_stat_desc[SIENA_STAT_COUNT] = {
471 SIENA_DMA_STAT(tx_bytes, TX_BYTES),
472 SIENA_OTHER_STAT(tx_good_bytes),
473 SIENA_DMA_STAT(tx_bad_bytes, TX_BAD_BYTES),
474 SIENA_DMA_STAT(tx_packets, TX_PKTS),
475 SIENA_DMA_STAT(tx_bad, TX_BAD_FCS_PKTS),
476 SIENA_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
477 SIENA_DMA_STAT(tx_control, TX_CONTROL_PKTS),
478 SIENA_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
479 SIENA_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
480 SIENA_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
481 SIENA_DMA_STAT(tx_lt64, TX_LT64_PKTS),
482 SIENA_DMA_STAT(tx_64, TX_64_PKTS),
483 SIENA_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
484 SIENA_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
485 SIENA_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
486 SIENA_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
487 SIENA_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
488 SIENA_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
489 SIENA_DMA_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS),
490 SIENA_OTHER_STAT(tx_collision),
491 SIENA_DMA_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS),
492 SIENA_DMA_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS),
493 SIENA_DMA_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS),
494 SIENA_DMA_STAT(tx_deferred, TX_DEFERRED_PKTS),
495 SIENA_DMA_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS),
496 SIENA_DMA_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS),
497 SIENA_DMA_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS),
498 SIENA_DMA_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS),
499 SIENA_DMA_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS),
500 SIENA_DMA_STAT(rx_bytes, RX_BYTES),
501 SIENA_OTHER_STAT(rx_good_bytes),
502 SIENA_DMA_STAT(rx_bad_bytes, RX_BAD_BYTES),
503 SIENA_DMA_STAT(rx_packets, RX_PKTS),
504 SIENA_DMA_STAT(rx_good, RX_GOOD_PKTS),
505 SIENA_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
506 SIENA_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
507 SIENA_DMA_STAT(rx_control, RX_CONTROL_PKTS),
508 SIENA_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
509 SIENA_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
510 SIENA_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
511 SIENA_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
512 SIENA_DMA_STAT(rx_64, RX_64_PKTS),
513 SIENA_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
514 SIENA_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
515 SIENA_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
516 SIENA_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
517 SIENA_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
518 SIENA_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
519 SIENA_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
520 SIENA_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
521 SIENA_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
522 SIENA_DMA_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS),
523 SIENA_DMA_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS),
524 SIENA_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
525 SIENA_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
526 SIENA_DMA_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS),
527 SIENA_DMA_STAT(rx_nodesc_drop_cnt, RX_NODESC_DROPS),
528 GENERIC_SW_STAT(rx_nodesc_trunc),
529 GENERIC_SW_STAT(rx_noskb_drops),
531 static const unsigned long siena_stat_mask[] = {
532 [0 ... BITS_TO_LONGS(SIENA_STAT_COUNT) - 1] = ~0UL,
535 static size_t siena_describe_nic_stats(struct efx_nic *efx, u8 *names)
537 return efx_nic_describe_stats(siena_stat_desc, SIENA_STAT_COUNT,
538 siena_stat_mask, names);
541 static int siena_try_update_nic_stats(struct efx_nic *efx)
543 struct siena_nic_data *nic_data = efx->nic_data;
544 u64 *stats = nic_data->stats;
546 __le64 generation_start, generation_end;
548 dma_stats = efx->stats_buffer.addr;
550 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
551 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
554 efx_nic_update_stats(siena_stat_desc, SIENA_STAT_COUNT, siena_stat_mask,
555 stats, efx->stats_buffer.addr, false);
557 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
558 if (generation_end != generation_start)
561 /* Update derived statistics */
562 efx_nic_fix_nodesc_drop_stat(efx,
563 &stats[SIENA_STAT_rx_nodesc_drop_cnt]);
564 efx_update_diff_stat(&stats[SIENA_STAT_tx_good_bytes],
565 stats[SIENA_STAT_tx_bytes] -
566 stats[SIENA_STAT_tx_bad_bytes]);
567 stats[SIENA_STAT_tx_collision] =
568 stats[SIENA_STAT_tx_single_collision] +
569 stats[SIENA_STAT_tx_multiple_collision] +
570 stats[SIENA_STAT_tx_excessive_collision] +
571 stats[SIENA_STAT_tx_late_collision];
572 efx_update_diff_stat(&stats[SIENA_STAT_rx_good_bytes],
573 stats[SIENA_STAT_rx_bytes] -
574 stats[SIENA_STAT_rx_bad_bytes]);
575 efx_update_sw_stats(efx, stats);
579 static size_t siena_update_nic_stats(struct efx_nic *efx, u64 *full_stats,
580 struct rtnl_link_stats64 *core_stats)
582 struct siena_nic_data *nic_data = efx->nic_data;
583 u64 *stats = nic_data->stats;
586 /* If we're unlucky enough to read statistics wduring the DMA, wait
587 * up to 10ms for it to finish (typically takes <500us) */
588 for (retry = 0; retry < 100; ++retry) {
589 if (siena_try_update_nic_stats(efx) == 0)
595 memcpy(full_stats, stats, sizeof(u64) * SIENA_STAT_COUNT);
598 core_stats->rx_packets = stats[SIENA_STAT_rx_packets];
599 core_stats->tx_packets = stats[SIENA_STAT_tx_packets];
600 core_stats->rx_bytes = stats[SIENA_STAT_rx_bytes];
601 core_stats->tx_bytes = stats[SIENA_STAT_tx_bytes];
602 core_stats->rx_dropped = stats[SIENA_STAT_rx_nodesc_drop_cnt] +
603 stats[GENERIC_STAT_rx_nodesc_trunc] +
604 stats[GENERIC_STAT_rx_noskb_drops];
605 core_stats->multicast = stats[SIENA_STAT_rx_multicast];
606 core_stats->collisions = stats[SIENA_STAT_tx_collision];
607 core_stats->rx_length_errors =
608 stats[SIENA_STAT_rx_gtjumbo] +
609 stats[SIENA_STAT_rx_length_error];
610 core_stats->rx_crc_errors = stats[SIENA_STAT_rx_bad];
611 core_stats->rx_frame_errors = stats[SIENA_STAT_rx_align_error];
612 core_stats->rx_fifo_errors = stats[SIENA_STAT_rx_overflow];
613 core_stats->tx_window_errors =
614 stats[SIENA_STAT_tx_late_collision];
616 core_stats->rx_errors = (core_stats->rx_length_errors +
617 core_stats->rx_crc_errors +
618 core_stats->rx_frame_errors +
619 stats[SIENA_STAT_rx_symbol_error]);
620 core_stats->tx_errors = (core_stats->tx_window_errors +
621 stats[SIENA_STAT_tx_bad]);
624 return SIENA_STAT_COUNT;
627 static int siena_mac_reconfigure(struct efx_nic *efx)
629 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MCAST_HASH_IN_LEN);
632 BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN !=
633 MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST +
634 sizeof(efx->multicast_hash));
636 efx_farch_filter_sync_rx_mode(efx);
638 WARN_ON(!mutex_is_locked(&efx->mac_lock));
640 rc = efx_mcdi_set_mac(efx);
644 memcpy(MCDI_PTR(inbuf, SET_MCAST_HASH_IN_HASH0),
645 efx->multicast_hash.byte, sizeof(efx->multicast_hash));
646 return efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
647 inbuf, sizeof(inbuf), NULL, 0, NULL);
650 /**************************************************************************
654 **************************************************************************
657 static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
659 struct siena_nic_data *nic_data = efx->nic_data;
661 wol->supported = WAKE_MAGIC;
662 if (nic_data->wol_filter_id != -1)
663 wol->wolopts = WAKE_MAGIC;
666 memset(&wol->sopass, 0, sizeof(wol->sopass));
670 static int siena_set_wol(struct efx_nic *efx, u32 type)
672 struct siena_nic_data *nic_data = efx->nic_data;
675 if (type & ~WAKE_MAGIC)
678 if (type & WAKE_MAGIC) {
679 if (nic_data->wol_filter_id != -1)
680 efx_mcdi_wol_filter_remove(efx,
681 nic_data->wol_filter_id);
682 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
683 &nic_data->wol_filter_id);
687 pci_wake_from_d3(efx->pci_dev, true);
689 rc = efx_mcdi_wol_filter_reset(efx);
690 nic_data->wol_filter_id = -1;
691 pci_wake_from_d3(efx->pci_dev, false);
698 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
704 static void siena_init_wol(struct efx_nic *efx)
706 struct siena_nic_data *nic_data = efx->nic_data;
709 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
712 /* If it failed, attempt to get into a synchronised
713 * state with MC by resetting any set WoL filters */
714 efx_mcdi_wol_filter_reset(efx);
715 nic_data->wol_filter_id = -1;
716 } else if (nic_data->wol_filter_id != -1) {
717 pci_wake_from_d3(efx->pci_dev, true);
721 /**************************************************************************
725 **************************************************************************
728 #define MCDI_PDU(efx) \
729 (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
730 #define MCDI_DOORBELL(efx) \
731 (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
732 #define MCDI_STATUS(efx) \
733 (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
735 static void siena_mcdi_request(struct efx_nic *efx,
736 const efx_dword_t *hdr, size_t hdr_len,
737 const efx_dword_t *sdu, size_t sdu_len)
739 unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
740 unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
742 unsigned int inlen_dw = DIV_ROUND_UP(sdu_len, 4);
744 EFX_WARN_ON_PARANOID(hdr_len != 4);
746 efx_writed(efx, hdr, pdu);
748 for (i = 0; i < inlen_dw; i++)
749 efx_writed(efx, &sdu[i], pdu + hdr_len + 4 * i);
751 /* Ensure the request is written out before the doorbell */
754 /* ring the doorbell with a distinctive value */
755 _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
758 static bool siena_mcdi_poll_response(struct efx_nic *efx)
760 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
763 efx_readd(efx, &hdr, pdu);
765 /* All 1's indicates that shared memory is in reset (and is
766 * not a valid hdr). Wait for it to come out reset before
767 * completing the command
769 return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff &&
770 EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
773 static void siena_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
774 size_t offset, size_t outlen)
776 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
777 unsigned int outlen_dw = DIV_ROUND_UP(outlen, 4);
780 for (i = 0; i < outlen_dw; i++)
781 efx_readd(efx, &outbuf[i], pdu + offset + 4 * i);
784 static int siena_mcdi_poll_reboot(struct efx_nic *efx)
786 struct siena_nic_data *nic_data = efx->nic_data;
787 unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
791 efx_readd(efx, ®, addr);
792 value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
798 efx_writed(efx, ®, addr);
800 /* MAC statistics have been cleared on the NIC; clear the local
801 * copies that we update with efx_update_diff_stat().
803 nic_data->stats[SIENA_STAT_tx_good_bytes] = 0;
804 nic_data->stats[SIENA_STAT_rx_good_bytes] = 0;
806 if (value == MC_STATUS_DWORD_ASSERT)
812 /**************************************************************************
816 **************************************************************************
819 #ifdef CONFIG_SFC_MTD
821 struct siena_nvram_type_info {
826 static const struct siena_nvram_type_info siena_nvram_types[] = {
827 [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO] = { 0, "sfc_dummy_phy" },
828 [MC_CMD_NVRAM_TYPE_MC_FW] = { 0, "sfc_mcfw" },
829 [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP] = { 0, "sfc_mcfw_backup" },
830 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0] = { 0, "sfc_static_cfg" },
831 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1] = { 1, "sfc_static_cfg" },
832 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0] = { 0, "sfc_dynamic_cfg" },
833 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1] = { 1, "sfc_dynamic_cfg" },
834 [MC_CMD_NVRAM_TYPE_EXP_ROM] = { 0, "sfc_exp_rom" },
835 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0] = { 0, "sfc_exp_rom_cfg" },
836 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1] = { 1, "sfc_exp_rom_cfg" },
837 [MC_CMD_NVRAM_TYPE_PHY_PORT0] = { 0, "sfc_phy_fw" },
838 [MC_CMD_NVRAM_TYPE_PHY_PORT1] = { 1, "sfc_phy_fw" },
839 [MC_CMD_NVRAM_TYPE_FPGA] = { 0, "sfc_fpga" },
842 static int siena_mtd_probe_partition(struct efx_nic *efx,
843 struct efx_mcdi_mtd_partition *part,
846 const struct siena_nvram_type_info *info;
847 size_t size, erase_size;
851 if (type >= ARRAY_SIZE(siena_nvram_types) ||
852 siena_nvram_types[type].name == NULL)
855 info = &siena_nvram_types[type];
857 if (info->port != efx_port_num(efx))
860 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
864 return -ENODEV; /* hide it */
866 part->nvram_type = type;
867 part->common.dev_type_name = "Siena NVRAM manager";
868 part->common.type_name = info->name;
870 part->common.mtd.type = MTD_NORFLASH;
871 part->common.mtd.flags = MTD_CAP_NORFLASH;
872 part->common.mtd.size = size;
873 part->common.mtd.erasesize = erase_size;
878 static int siena_mtd_get_fw_subtypes(struct efx_nic *efx,
879 struct efx_mcdi_mtd_partition *parts,
882 uint16_t fw_subtype_list[
883 MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM];
887 rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list, NULL);
891 for (i = 0; i < n_parts; i++)
892 parts[i].fw_subtype = fw_subtype_list[parts[i].nvram_type];
897 static int siena_mtd_probe(struct efx_nic *efx)
899 struct efx_mcdi_mtd_partition *parts;
907 rc = efx_mcdi_nvram_types(efx, &nvram_types);
911 parts = kcalloc(hweight32(nvram_types), sizeof(*parts), GFP_KERNEL);
918 while (nvram_types != 0) {
919 if (nvram_types & 1) {
920 rc = siena_mtd_probe_partition(efx, &parts[n_parts],
924 else if (rc != -ENODEV)
931 rc = siena_mtd_get_fw_subtypes(efx, parts, n_parts);
935 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
942 #endif /* CONFIG_SFC_MTD */
944 /**************************************************************************
946 * Revision-dependent attributes used by efx.c and nic.c
948 **************************************************************************
951 const struct efx_nic_type siena_a0_nic_type = {
953 .mem_bar = EFX_MEM_BAR,
954 .mem_map_size = siena_mem_map_size,
955 .probe = siena_probe_nic,
956 .remove = siena_remove_nic,
957 .init = siena_init_nic,
958 .dimension_resources = siena_dimension_resources,
959 .fini = efx_port_dummy_op_void,
961 .monitor = siena_monitor,
965 .map_reset_reason = efx_mcdi_map_reset_reason,
966 .map_reset_flags = siena_map_reset_flags,
967 .reset = efx_mcdi_reset,
968 .probe_port = efx_mcdi_port_probe,
969 .remove_port = efx_mcdi_port_remove,
970 .fini_dmaq = efx_farch_fini_dmaq,
971 .prepare_flush = siena_prepare_flush,
972 .finish_flush = siena_finish_flush,
973 .prepare_flr = efx_port_dummy_op_void,
974 .finish_flr = efx_farch_finish_flr,
975 .describe_stats = siena_describe_nic_stats,
976 .update_stats = siena_update_nic_stats,
977 .start_stats = efx_mcdi_mac_start_stats,
978 .pull_stats = efx_mcdi_mac_pull_stats,
979 .stop_stats = efx_mcdi_mac_stop_stats,
980 .set_id_led = efx_mcdi_set_id_led,
981 .push_irq_moderation = siena_push_irq_moderation,
982 .reconfigure_mac = siena_mac_reconfigure,
983 .check_mac_fault = efx_mcdi_mac_check_fault,
984 .reconfigure_port = efx_mcdi_port_reconfigure,
985 .get_wol = siena_get_wol,
986 .set_wol = siena_set_wol,
987 .resume_wol = siena_init_wol,
988 .test_chip = siena_test_chip,
989 .test_nvram = efx_mcdi_nvram_test_all,
990 .mcdi_request = siena_mcdi_request,
991 .mcdi_poll_response = siena_mcdi_poll_response,
992 .mcdi_read_response = siena_mcdi_read_response,
993 .mcdi_poll_reboot = siena_mcdi_poll_reboot,
994 .irq_enable_master = efx_farch_irq_enable_master,
995 .irq_test_generate = efx_farch_irq_test_generate,
996 .irq_disable_non_ev = efx_farch_irq_disable_master,
997 .irq_handle_msi = efx_farch_msi_interrupt,
998 .irq_handle_legacy = efx_farch_legacy_interrupt,
999 .tx_probe = efx_farch_tx_probe,
1000 .tx_init = efx_farch_tx_init,
1001 .tx_remove = efx_farch_tx_remove,
1002 .tx_write = efx_farch_tx_write,
1003 .tx_limit_len = efx_farch_tx_limit_len,
1004 .rx_push_rss_config = siena_rx_push_rss_config,
1005 .rx_pull_rss_config = siena_rx_pull_rss_config,
1006 .rx_probe = efx_farch_rx_probe,
1007 .rx_init = efx_farch_rx_init,
1008 .rx_remove = efx_farch_rx_remove,
1009 .rx_write = efx_farch_rx_write,
1010 .rx_defer_refill = efx_farch_rx_defer_refill,
1011 .ev_probe = efx_farch_ev_probe,
1012 .ev_init = efx_farch_ev_init,
1013 .ev_fini = efx_farch_ev_fini,
1014 .ev_remove = efx_farch_ev_remove,
1015 .ev_process = efx_farch_ev_process,
1016 .ev_read_ack = efx_farch_ev_read_ack,
1017 .ev_test_generate = efx_farch_ev_test_generate,
1018 .filter_table_probe = efx_farch_filter_table_probe,
1019 .filter_table_restore = efx_farch_filter_table_restore,
1020 .filter_table_remove = efx_farch_filter_table_remove,
1021 .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
1022 .filter_insert = efx_farch_filter_insert,
1023 .filter_remove_safe = efx_farch_filter_remove_safe,
1024 .filter_get_safe = efx_farch_filter_get_safe,
1025 .filter_clear_rx = efx_farch_filter_clear_rx,
1026 .filter_count_rx_used = efx_farch_filter_count_rx_used,
1027 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
1028 .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
1029 #ifdef CONFIG_RFS_ACCEL
1030 .filter_rfs_insert = efx_farch_filter_rfs_insert,
1031 .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
1033 #ifdef CONFIG_SFC_MTD
1034 .mtd_probe = siena_mtd_probe,
1035 .mtd_rename = efx_mcdi_mtd_rename,
1036 .mtd_read = efx_mcdi_mtd_read,
1037 .mtd_erase = efx_mcdi_mtd_erase,
1038 .mtd_write = efx_mcdi_mtd_write,
1039 .mtd_sync = efx_mcdi_mtd_sync,
1041 .ptp_write_host_time = siena_ptp_write_host_time,
1042 .ptp_set_ts_config = siena_ptp_set_ts_config,
1043 #ifdef CONFIG_SFC_SRIOV
1044 .sriov_configure = efx_siena_sriov_configure,
1045 .sriov_init = efx_siena_sriov_init,
1046 .sriov_fini = efx_siena_sriov_fini,
1047 .sriov_wanted = efx_siena_sriov_wanted,
1048 .sriov_reset = efx_siena_sriov_reset,
1049 .sriov_flr = efx_siena_sriov_flr,
1050 .sriov_set_vf_mac = efx_siena_sriov_set_vf_mac,
1051 .sriov_set_vf_vlan = efx_siena_sriov_set_vf_vlan,
1052 .sriov_set_vf_spoofchk = efx_siena_sriov_set_vf_spoofchk,
1053 .sriov_get_vf_config = efx_siena_sriov_get_vf_config,
1054 .vswitching_probe = efx_port_dummy_op_int,
1055 .vswitching_restore = efx_port_dummy_op_int,
1056 .vswitching_remove = efx_port_dummy_op_void,
1057 .set_mac_address = efx_siena_sriov_mac_address_changed,
1060 .revision = EFX_REV_SIENA_A0,
1061 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1062 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1063 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1064 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1065 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1066 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1067 .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE,
1068 .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST,
1069 .rx_buffer_padding = 0,
1070 .can_rx_scatter = true,
1071 .option_descriptors = false,
1072 .min_interrupt_mode = EFX_INT_MODE_LEGACY,
1073 .max_interrupt_mode = EFX_INT_MODE_MSIX,
1074 .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
1075 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1076 NETIF_F_RXHASH | NETIF_F_NTUPLE),
1078 .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,
1079 .hwtstamp_filters = (1 << HWTSTAMP_FILTER_NONE |
1080 1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT |
1081 1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT),
1082 .rx_hash_key_size = 16,