drivers/net/ethernet/sfc/ef10.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2012-2013 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9
  10 #include "net_driver.h"
  11 #include "ef10_regs.h"
  12 #include "io.h"
  13 #include "mcdi.h"
  14 #include "mcdi_pcol.h"
  15 #include "nic.h"
  16 #include "workarounds.h"
  17 #include "selftest.h"
  18 #include "ef10_sriov.h"
  19 #include <linux/in.h>
  20 #include <linux/jhash.h>
  21 #include <linux/wait.h>
  22 #include <linux/workqueue.h>
  23
  24 /* Hardware control for EF10 architecture including 'Huntington'. */
  25
  26 #define EFX_EF10_DRVGEN_EV              7
  27 enum {
  28         EFX_EF10_TEST = 1,
  29         EFX_EF10_REFILL,
  30 };
  31
  32 /* The reserved RSS context value */
  33 #define EFX_EF10_RSS_CONTEXT_INVALID    0xffffffff
  34 /* The maximum size of a shared RSS context */
  35 /* TODO: this should really be from the mcdi protocol export */
  36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
  37
  38 /* The filter table(s) are managed by firmware and we have write-only
  39  * access.  When removing filters we must identify them to the
  40  * firmware by a 64-bit handle, but this is too wide for Linux kernel
  41  * interfaces (32-bit for RX NFC, 16-bit for RFS).  Also, we need to
  42  * be able to tell in advance whether a requested insertion will
  43  * replace an existing filter.  Therefore we maintain a software hash
  44  * table, which should be at least as large as the hardware hash
  45  * table.
  46  *
  47  * Huntington has a single 8K filter table shared between all filter
  48  * types and both ports.
  49  */
  50 #define HUNT_FILTER_TBL_ROWS 8192
  51
  52 #define EFX_EF10_FILTER_ID_INVALID 0xffff
  53
  54 #define EFX_EF10_FILTER_DEV_UC_MAX      32
  55 #define EFX_EF10_FILTER_DEV_MC_MAX      256
  56
  57 /* VLAN list entry */
  58 struct efx_ef10_vlan {
  59         struct list_head list;
  60         u16 vid;
  61 };
  62
  63 /* Per-VLAN filters information */
  64 struct efx_ef10_filter_vlan {
  65         struct list_head list;
  66         u16 vid;
  67         u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
  68         u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
  69         u16 ucdef;
  70         u16 bcast;
  71         u16 mcdef;
  72 };
  73
  74 struct efx_ef10_dev_addr {
  75         u8 addr[ETH_ALEN];
  76 };
  77
  78 struct efx_ef10_filter_table {
  79 /* The MCDI match masks supported by this fw & hw, in order of priority */
  80         u32 rx_match_mcdi_flags[
  81                 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
  82         unsigned int rx_match_count;
  83
  84         struct {
  85                 unsigned long spec;     /* pointer to spec plus flag bits */
  86 /* BUSY flag indicates that an update is in progress.  AUTO_OLD is
  87  * used to mark and sweep MAC filters for the device address lists.
  88  */
  89 #define EFX_EF10_FILTER_FLAG_BUSY       1UL
  90 #define EFX_EF10_FILTER_FLAG_AUTO_OLD   2UL
  91 #define EFX_EF10_FILTER_FLAGS           3UL
  92                 u64 handle;             /* firmware handle */
  93         } *entry;
  94         wait_queue_head_t waitq;
  95 /* Shadow of net_device address lists, guarded by mac_lock */
  96         struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
  97         struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
  98         int dev_uc_count;
  99         int dev_mc_count;
 100         bool uc_promisc;
 101         bool mc_promisc;
 102 /* Whether in multicast promiscuous mode when last changed */
 103         bool mc_promisc_last;
 104         bool vlan_filter;
 105         struct list_head vlan_list;
 106 };
 107
 108 /* An arbitrary search limit for the software hash table */
 109 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
 110
 111 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
 112 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
 113 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
 114 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
 115                                               struct efx_ef10_filter_vlan *vlan);
 116 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
 117
 118 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
 119 {
 120         efx_dword_t reg;
 121
 122         efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
 123         return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
 124                 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
 125 }
 126
 127 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
 128 {
 129         int bar;
 130
 131         bar = efx->type->mem_bar;
 132         return resource_size(&efx->pci_dev->resource[bar]);
 133 }
 134
 135 static bool efx_ef10_is_vf(struct efx_nic *efx)
 136 {
 137         return efx->type->is_vf;
 138 }
 139
 140 static int efx_ef10_get_pf_index(struct efx_nic *efx)
 141 {
 142         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 143         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 144         size_t outlen;
 145         int rc;
 146
 147         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 148                           sizeof(outbuf), &outlen);
 149         if (rc)
 150                 return rc;
 151         if (outlen < sizeof(outbuf))
 152                 return -EIO;
 153
 154         nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
 155         return 0;
 156 }
 157
 158 #ifdef CONFIG_SFC_SRIOV
 159 static int efx_ef10_get_vf_index(struct efx_nic *efx)
 160 {
 161         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 162         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 163         size_t outlen;
 164         int rc;
 165
 166         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 167                           sizeof(outbuf), &outlen);
 168         if (rc)
 169                 return rc;
 170         if (outlen < sizeof(outbuf))
 171                 return -EIO;
 172
 173         nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
 174         return 0;
 175 }
 176 #endif
 177
 178 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
 179 {
 180         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V2_OUT_LEN);
 181         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 182         size_t outlen;
 183         int rc;
 184
 185         BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
 186
 187         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
 188                           outbuf, sizeof(outbuf), &outlen);
 189         if (rc)
 190                 return rc;
 191         if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
 192                 netif_err(efx, drv, efx->net_dev,
 193                           "unable to read datapath firmware capabilities\n");
 194                 return -EIO;
 195         }
 196
 197         nic_data->datapath_caps =
 198                 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
 199
 200         if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
 201                 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
 202                                 GET_CAPABILITIES_V2_OUT_FLAGS2);
 203                 nic_data->piobuf_size = MCDI_WORD(outbuf,
 204                                 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF);
 205         } else {
 206                 nic_data->datapath_caps2 = 0;
 207                 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE;
 208         }
 209
 210         /* record the DPCPU firmware IDs to determine VEB vswitching support.
 211          */
 212         nic_data->rx_dpcpu_fw_id =
 213                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
 214         nic_data->tx_dpcpu_fw_id =
 215                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
 216
 217         if (!(nic_data->datapath_caps &
 218               (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
 219                 netif_err(efx, probe, efx->net_dev,
 220                           "current firmware does not support an RX prefix\n");
 221                 return -ENODEV;
 222         }
 223
 224         return 0;
 225 }
 226
 227 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
 228 {
 229         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
 230         int rc;
 231
 232         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
 233                           outbuf, sizeof(outbuf), NULL);
 234         if (rc)
 235                 return rc;
 236         rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
 237         return rc > 0 ? rc : -ERANGE;
 238 }
 239
 240 static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
 241 {
 242         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 243         unsigned int implemented;
 244         unsigned int enabled;
 245         int rc;
 246
 247         nic_data->workaround_35388 = false;
 248         nic_data->workaround_61265 = false;
 249
 250         rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
 251
 252         if (rc == -ENOSYS) {
 253                 /* Firmware without GET_WORKAROUNDS - not a problem. */
 254                 rc = 0;
 255         } else if (rc == 0) {
 256                 /* Bug61265 workaround is always enabled if implemented. */
 257                 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
 258                         nic_data->workaround_61265 = true;
 259
 260                 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
 261                         nic_data->workaround_35388 = true;
 262                 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
 263                         /* Workaround is implemented but not enabled.
 264                          * Try to enable it.
 265                          */
 266                         rc = efx_mcdi_set_workaround(efx,
 267                                                      MC_CMD_WORKAROUND_BUG35388,
 268                                                      true, NULL);
 269                         if (rc == 0)
 270                                 nic_data->workaround_35388 = true;
 271                         /* If we failed to set the workaround just carry on. */
 272                         rc = 0;
 273                 }
 274         }
 275
 276         netif_dbg(efx, probe, efx->net_dev,
 277                   "workaround for bug 35388 is %sabled\n",
 278                   nic_data->workaround_35388 ? "en" : "dis");
 279         netif_dbg(efx, probe, efx->net_dev,
 280                   "workaround for bug 61265 is %sabled\n",
 281                   nic_data->workaround_61265 ? "en" : "dis");
 282
 283         return rc;
 284 }
 285
 286 static void efx_ef10_process_timer_config(struct efx_nic *efx,
 287                                           const efx_dword_t *data)
 288 {
 289         unsigned int max_count;
 290
 291         if (EFX_EF10_WORKAROUND_61265(efx)) {
 292                 efx->timer_quantum_ns = MCDI_DWORD(data,
 293                         GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
 294                 efx->timer_max_ns = MCDI_DWORD(data,
 295                         GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
 296         } else if (EFX_EF10_WORKAROUND_35388(efx)) {
 297                 efx->timer_quantum_ns = MCDI_DWORD(data,
 298                         GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
 299                 max_count = MCDI_DWORD(data,
 300                         GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
 301                 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
 302         } else {
 303                 efx->timer_quantum_ns = MCDI_DWORD(data,
 304                         GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
 305                 max_count = MCDI_DWORD(data,
 306                         GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
 307                 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
 308         }
 309
 310         netif_dbg(efx, probe, efx->net_dev,
 311                   "got timer properties from MC: quantum %u ns; max %u ns\n",
 312                   efx->timer_quantum_ns, efx->timer_max_ns);
 313 }
 314
 315 static int efx_ef10_get_timer_config(struct efx_nic *efx)
 316 {
 317         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
 318         int rc;
 319
 320         rc = efx_ef10_get_timer_workarounds(efx);
 321         if (rc)
 322                 return rc;
 323
 324         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
 325                                 outbuf, sizeof(outbuf), NULL);
 326
 327         if (rc == 0) {
 328                 efx_ef10_process_timer_config(efx, outbuf);
 329         } else if (rc == -ENOSYS || rc == -EPERM) {
 330                 /* Not available - fall back to Huntington defaults. */
 331                 unsigned int quantum;
 332
 333                 rc = efx_ef10_get_sysclk_freq(efx);
 334                 if (rc < 0)
 335                         return rc;
 336
 337                 quantum = 1536000 / rc; /* 1536 cycles */
 338                 efx->timer_quantum_ns = quantum;
 339                 efx->timer_max_ns = efx->type->timer_period_max * quantum;
 340                 rc = 0;
 341         } else {
 342                 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
 343                                        MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
 344                                        NULL, 0, rc);
 345         }
 346
 347         return rc;
 348 }
 349
 350 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
 351 {
 352         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
 353         size_t outlen;
 354         int rc;
 355
 356         BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
 357
 358         rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
 359                           outbuf, sizeof(outbuf), &outlen);
 360         if (rc)
 361                 return rc;
 362         if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
 363                 return -EIO;
 364
 365         ether_addr_copy(mac_address,
 366                         MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
 367         return 0;
 368 }
 369
 370 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
 371 {
 372         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
 373         MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
 374         size_t outlen;
 375         int num_addrs, rc;
 376
 377         MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
 378                        EVB_PORT_ID_ASSIGNED);
 379         rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
 380                           sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
 381
 382         if (rc)
 383                 return rc;
 384         if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
 385                 return -EIO;
 386
 387         num_addrs = MCDI_DWORD(outbuf,
 388                                VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
 389
 390         WARN_ON(num_addrs != 1);
 391
 392         ether_addr_copy(mac_address,
 393                         MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
 394
 395         return 0;
 396 }
 397
 398 static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
 399                                                struct device_attribute *attr,
 400                                                char *buf)
 401 {
 402         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 403
 404         return sprintf(buf, "%d\n",
 405                        ((efx->mcdi->fn_flags) &
 406                         (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
 407                        ? 1 : 0);
 408 }
 409
 410 static ssize_t efx_ef10_show_primary_flag(struct device *dev,
 411                                           struct device_attribute *attr,
 412                                           char *buf)
 413 {
 414         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 415
 416         return sprintf(buf, "%d\n",
 417                        ((efx->mcdi->fn_flags) &
 418                         (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
 419                        ? 1 : 0);
 420 }
 421
 422 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
 423 {
 424         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 425         struct efx_ef10_vlan *vlan;
 426
 427         WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
 428
 429         list_for_each_entry(vlan, &nic_data->vlan_list, list) {
 430                 if (vlan->vid == vid)
 431                         return vlan;
 432         }
 433
 434         return NULL;
 435 }
 436
 437 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
 438 {
 439         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 440         struct efx_ef10_vlan *vlan;
 441         int rc;
 442
 443         mutex_lock(&nic_data->vlan_lock);
 444
 445         vlan = efx_ef10_find_vlan(efx, vid);
 446         if (vlan) {
 447                 /* We add VID 0 on init. 8021q adds it on module init
 448                  * for all interfaces with VLAN filtring feature.
 449                  */
 450                 if (vid == 0)
 451                         goto done_unlock;
 452                 netif_warn(efx, drv, efx->net_dev,
 453                            "VLAN %u already added\n", vid);
 454                 rc = -EALREADY;
 455                 goto fail_exist;
 456         }
 457
 458         rc = -ENOMEM;
 459         vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
 460         if (!vlan)
 461                 goto fail_alloc;
 462
 463         vlan->vid = vid;
 464
 465         list_add_tail(&vlan->list, &nic_data->vlan_list);
 466
 467         if (efx->filter_state) {
 468                 mutex_lock(&efx->mac_lock);
 469                 down_write(&efx->filter_sem);
 470                 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
 471                 up_write(&efx->filter_sem);
 472                 mutex_unlock(&efx->mac_lock);
 473                 if (rc)
 474                         goto fail_filter_add_vlan;
 475         }
 476
 477 done_unlock:
 478         mutex_unlock(&nic_data->vlan_lock);
 479         return 0;
 480
 481 fail_filter_add_vlan:
 482         list_del(&vlan->list);
 483         kfree(vlan);
 484 fail_alloc:
 485 fail_exist:
 486         mutex_unlock(&nic_data->vlan_lock);
 487         return rc;
 488 }
 489
 490 static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
 491                                        struct efx_ef10_vlan *vlan)
 492 {
 493         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 494
 495         WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
 496
 497         if (efx->filter_state) {
 498                 down_write(&efx->filter_sem);
 499                 efx_ef10_filter_del_vlan(efx, vlan->vid);
 500                 up_write(&efx->filter_sem);
 501         }
 502
 503         list_del(&vlan->list);
 504         kfree(vlan);
 505 }
 506
 507 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
 508 {
 509         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 510         struct efx_ef10_vlan *vlan;
 511         int rc = 0;
 512
 513         /* 8021q removes VID 0 on module unload for all interfaces
 514          * with VLAN filtering feature. We need to keep it to receive
 515          * untagged traffic.
 516          */
 517         if (vid == 0)
 518                 return 0;
 519
 520         mutex_lock(&nic_data->vlan_lock);
 521
 522         vlan = efx_ef10_find_vlan(efx, vid);
 523         if (!vlan) {
 524                 netif_err(efx, drv, efx->net_dev,
 525                           "VLAN %u to be deleted not found\n", vid);
 526                 rc = -ENOENT;
 527         } else {
 528                 efx_ef10_del_vlan_internal(efx, vlan);
 529         }
 530
 531         mutex_unlock(&nic_data->vlan_lock);
 532
 533         return rc;
 534 }
 535
 536 static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
 537 {
 538         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 539         struct efx_ef10_vlan *vlan, *next_vlan;
 540
 541         mutex_lock(&nic_data->vlan_lock);
 542         list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
 543                 efx_ef10_del_vlan_internal(efx, vlan);
 544         mutex_unlock(&nic_data->vlan_lock);
 545 }
 546
 547 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
 548                    NULL);
 549 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
 550
 551 static int efx_ef10_probe(struct efx_nic *efx)
 552 {
 553         struct efx_ef10_nic_data *nic_data;
 554         struct net_device *net_dev = efx->net_dev;
 555         int i, rc;
 556
 557         /* We can have one VI for each 8K region.  However, until we
 558          * use TX option descriptors we need two TX queues per channel.
 559          */
 560         efx->max_channels = min_t(unsigned int,
 561                                   EFX_MAX_CHANNELS,
 562                                   efx_ef10_mem_map_size(efx) /
 563                                   (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
 564         efx->max_tx_channels = efx->max_channels;
 565         if (WARN_ON(efx->max_channels == 0))
 566                 return -EIO;
 567
 568         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
 569         if (!nic_data)
 570                 return -ENOMEM;
 571         efx->nic_data = nic_data;
 572
 573         /* we assume later that we can copy from this buffer in dwords */
 574         BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
 575
 576         rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
 577                                   8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
 578         if (rc)
 579                 goto fail1;
 580
 581         /* Get the MC's warm boot count.  In case it's rebooting right
 582          * now, be prepared to retry.
 583          */
 584         i = 0;
 585         for (;;) {
 586                 rc = efx_ef10_get_warm_boot_count(efx);
 587                 if (rc >= 0)
 588                         break;
 589                 if (++i == 5)
 590                         goto fail2;
 591                 ssleep(1);
 592         }
 593         nic_data->warm_boot_count = rc;
 594
 595         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
 596
 597         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
 598
 599         /* In case we're recovering from a crash (kexec), we want to
 600          * cancel any outstanding request by the previous user of this
 601          * function.  We send a special message using the least
 602          * significant bits of the 'high' (doorbell) register.
 603          */
 604         _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
 605
 606         rc = efx_mcdi_init(efx);
 607         if (rc)
 608                 goto fail2;
 609
 610         /* Reset (most) configuration for this function */
 611         rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
 612         if (rc)
 613                 goto fail3;
 614
 615         /* Enable event logging */
 616         rc = efx_mcdi_log_ctrl(efx, true, false, 0);
 617         if (rc)
 618                 goto fail3;
 619
 620         rc = device_create_file(&efx->pci_dev->dev,
 621                                 &dev_attr_link_control_flag);
 622         if (rc)
 623                 goto fail3;
 624
 625         rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 626         if (rc)
 627                 goto fail4;
 628
 629         rc = efx_ef10_get_pf_index(efx);
 630         if (rc)
 631                 goto fail5;
 632
 633         rc = efx_ef10_init_datapath_caps(efx);
 634         if (rc < 0)
 635                 goto fail5;
 636
 637         efx->rx_packet_len_offset =
 638                 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
 639
 640         rc = efx_mcdi_port_get_number(efx);
 641         if (rc < 0)
 642                 goto fail5;
 643         efx->port_num = rc;
 644         net_dev->dev_port = rc;
 645
 646         rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
 647         if (rc)
 648                 goto fail5;
 649
 650         rc = efx_ef10_get_timer_config(efx);
 651         if (rc < 0)
 652                 goto fail5;
 653
 654         rc = efx_mcdi_mon_probe(efx);
 655         if (rc && rc != -EPERM)
 656                 goto fail5;
 657
 658         efx_ptp_probe(efx, NULL);
 659
 660 #ifdef CONFIG_SFC_SRIOV
 661         if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
 662                 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
 663                 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
 664
 665                 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
 666         } else
 667 #endif
 668                 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
 669
 670         INIT_LIST_HEAD(&nic_data->vlan_list);
 671         mutex_init(&nic_data->vlan_lock);
 672
 673         /* Add unspecified VID to support VLAN filtering being disabled */
 674         rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
 675         if (rc)
 676                 goto fail_add_vid_unspec;
 677
 678         /* If VLAN filtering is enabled, we need VID 0 to get untagged
 679          * traffic.  It is added automatically if 8021q module is loaded,
 680          * but we can't rely on it since module may be not loaded.
 681          */
 682         rc = efx_ef10_add_vlan(efx, 0);
 683         if (rc)
 684                 goto fail_add_vid_0;
 685
 686         return 0;
 687
 688 fail_add_vid_0:
 689         efx_ef10_cleanup_vlans(efx);
 690 fail_add_vid_unspec:
 691         mutex_destroy(&nic_data->vlan_lock);
 692         efx_ptp_remove(efx);
 693         efx_mcdi_mon_remove(efx);
 694 fail5:
 695         device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 696 fail4:
 697         device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
 698 fail3:
 699         efx_mcdi_fini(efx);
 700 fail2:
 701         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 702 fail1:
 703         kfree(nic_data);
 704         efx->nic_data = NULL;
 705         return rc;
 706 }
 707
 708 static int efx_ef10_free_vis(struct efx_nic *efx)
 709 {
 710         MCDI_DECLARE_BUF_ERR(outbuf);
 711         size_t outlen;
 712         int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
 713                                     outbuf, sizeof(outbuf), &outlen);
 714
 715         /* -EALREADY means nothing to free, so ignore */
 716         if (rc == -EALREADY)
 717                 rc = 0;
 718         if (rc)
 719                 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
 720                                        rc);
 721         return rc;
 722 }
 723
 724 #ifdef EFX_USE_PIO
 725
 726 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 727 {
 728         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 729         MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
 730         unsigned int i;
 731         int rc;
 732
 733         BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
 734
 735         for (i = 0; i < nic_data->n_piobufs; i++) {
 736                 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
 737                                nic_data->piobuf_handle[i]);
 738                 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
 739                                   NULL, 0, NULL);
 740                 WARN_ON(rc);
 741         }
 742
 743         nic_data->n_piobufs = 0;
 744 }
 745
 746 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 747 {
 748         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 749         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
 750         unsigned int i;
 751         size_t outlen;
 752         int rc = 0;
 753
 754         BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
 755
 756         for (i = 0; i < n; i++) {
 757                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
 758                                         outbuf, sizeof(outbuf), &outlen);
 759                 if (rc) {
 760                         /* Don't display the MC error if we didn't have space
 761                          * for a VF.
 762                          */
 763                         if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
 764                                 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
 765                                                        0, outbuf, outlen, rc);
 766                         break;
 767                 }
 768                 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
 769                         rc = -EIO;
 770                         break;
 771                 }
 772                 nic_data->piobuf_handle[i] =
 773                         MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
 774                 netif_dbg(efx, probe, efx->net_dev,
 775                           "allocated PIO buffer %u handle %x\n", i,
 776                           nic_data->piobuf_handle[i]);
 777         }
 778
 779         nic_data->n_piobufs = i;
 780         if (rc)
 781                 efx_ef10_free_piobufs(efx);
 782         return rc;
 783 }
 784
 785 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 786 {
 787         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 788         _MCDI_DECLARE_BUF(inbuf,
 789                           max(MC_CMD_LINK_PIOBUF_IN_LEN,
 790                               MC_CMD_UNLINK_PIOBUF_IN_LEN));
 791         struct efx_channel *channel;
 792         struct efx_tx_queue *tx_queue;
 793         unsigned int offset, index;
 794         int rc;
 795
 796         BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
 797         BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
 798
 799         memset(inbuf, 0, sizeof(inbuf));
 800
 801         /* Link a buffer to each VI in the write-combining mapping */
 802         for (index = 0; index < nic_data->n_piobufs; ++index) {
 803                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
 804                                nic_data->piobuf_handle[index]);
 805                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
 806                                nic_data->pio_write_vi_base + index);
 807                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 808                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 809                                   NULL, 0, NULL);
 810                 if (rc) {
 811                         netif_err(efx, drv, efx->net_dev,
 812                                   "failed to link VI %u to PIO buffer %u (%d)\n",
 813                                   nic_data->pio_write_vi_base + index, index,
 814                                   rc);
 815                         goto fail;
 816                 }
 817                 netif_dbg(efx, probe, efx->net_dev,
 818                           "linked VI %u to PIO buffer %u\n",
 819                           nic_data->pio_write_vi_base + index, index);
 820         }
 821
 822         /* Link a buffer to each TX queue */
 823         efx_for_each_channel(channel, efx) {
 824                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 825                         /* We assign the PIO buffers to queues in
 826                          * reverse order to allow for the following
 827                          * special case.
 828                          */
 829                         offset = ((efx->tx_channel_offset + efx->n_tx_channels -
 830                                    tx_queue->channel->channel - 1) *
 831                                   efx_piobuf_size);
 832                         index = offset / nic_data->piobuf_size;
 833                         offset = offset % nic_data->piobuf_size;
 834
 835                         /* When the host page size is 4K, the first
 836                          * host page in the WC mapping may be within
 837                          * the same VI page as the last TX queue.  We
 838                          * can only link one buffer to each VI.
 839                          */
 840                         if (tx_queue->queue == nic_data->pio_write_vi_base) {
 841                                 BUG_ON(index != 0);
 842                                 rc = 0;
 843                         } else {
 844                                 MCDI_SET_DWORD(inbuf,
 845                                                LINK_PIOBUF_IN_PIOBUF_HANDLE,
 846                                                nic_data->piobuf_handle[index]);
 847                                 MCDI_SET_DWORD(inbuf,
 848                                                LINK_PIOBUF_IN_TXQ_INSTANCE,
 849                                                tx_queue->queue);
 850                                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 851                                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 852                                                   NULL, 0, NULL);
 853                         }
 854
 855                         if (rc) {
 856                                 /* This is non-fatal; the TX path just
 857                                  * won't use PIO for this queue
 858                                  */
 859                                 netif_err(efx, drv, efx->net_dev,
 860                                           "failed to link VI %u to PIO buffer %u (%d)\n",
 861                                           tx_queue->queue, index, rc);
 862                                 tx_queue->piobuf = NULL;
 863                         } else {
 864                                 tx_queue->piobuf =
 865                                         nic_data->pio_write_base +
 866                                         index * EFX_VI_PAGE_SIZE + offset;
 867                                 tx_queue->piobuf_offset = offset;
 868                                 netif_dbg(efx, probe, efx->net_dev,
 869                                           "linked VI %u to PIO buffer %u offset %x addr %p\n",
 870                                           tx_queue->queue, index,
 871                                           tx_queue->piobuf_offset,
 872                                           tx_queue->piobuf);
 873                         }
 874                 }
 875         }
 876
 877         return 0;
 878
 879 fail:
 880         while (index--) {
 881                 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
 882                                nic_data->pio_write_vi_base + index);
 883                 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
 884                              inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
 885                              NULL, 0, NULL);
 886         }
 887         return rc;
 888 }
 889
 890 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
 891 {
 892         struct efx_channel *channel;
 893         struct efx_tx_queue *tx_queue;
 894
 895         /* All our existing PIO buffers went away */
 896         efx_for_each_channel(channel, efx)
 897                 efx_for_each_channel_tx_queue(tx_queue, channel)
 898                         tx_queue->piobuf = NULL;
 899 }
 900
 901 #else /* !EFX_USE_PIO */
 902
 903 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 904 {
 905         return n == 0 ? 0 : -ENOBUFS;
 906 }
 907
 908 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 909 {
 910         return 0;
 911 }
 912
 913 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 914 {
 915 }
 916
 917 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
 918 {
 919 }
 920
 921 #endif /* EFX_USE_PIO */
 922
 923 static void efx_ef10_remove(struct efx_nic *efx)
 924 {
 925         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 926         int rc;
 927
 928 #ifdef CONFIG_SFC_SRIOV
 929         struct efx_ef10_nic_data *nic_data_pf;
 930         struct pci_dev *pci_dev_pf;
 931         struct efx_nic *efx_pf;
 932         struct ef10_vf *vf;
 933
 934         if (efx->pci_dev->is_virtfn) {
 935                 pci_dev_pf = efx->pci_dev->physfn;
 936                 if (pci_dev_pf) {
 937                         efx_pf = pci_get_drvdata(pci_dev_pf);
 938                         nic_data_pf = efx_pf->nic_data;
 939                         vf = nic_data_pf->vf + nic_data->vf_index;
 940                         vf->efx = NULL;
 941                 } else
 942                         netif_info(efx, drv, efx->net_dev,
 943                                    "Could not get the PF id from VF\n");
 944         }
 945 #endif
 946
 947         efx_ef10_cleanup_vlans(efx);
 948         mutex_destroy(&nic_data->vlan_lock);
 949
 950         efx_ptp_remove(efx);
 951
 952         efx_mcdi_mon_remove(efx);
 953
 954         efx_ef10_rx_free_indir_table(efx);
 955
 956         if (nic_data->wc_membase)
 957                 iounmap(nic_data->wc_membase);
 958
 959         rc = efx_ef10_free_vis(efx);
 960         WARN_ON(rc != 0);
 961
 962         if (!nic_data->must_restore_piobufs)
 963                 efx_ef10_free_piobufs(efx);
 964
 965         device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 966         device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
 967
 968         efx_mcdi_fini(efx);
 969         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 970         kfree(nic_data);
 971 }
 972
 973 static int efx_ef10_probe_pf(struct efx_nic *efx)
 974 {
 975         return efx_ef10_probe(efx);
 976 }
 977
 978 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
 979                             u32 *port_flags, u32 *vadaptor_flags,
 980                             unsigned int *vlan_tags)
 981 {
 982         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 983         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
 984         MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
 985         size_t outlen;
 986         int rc;
 987
 988         if (nic_data->datapath_caps &
 989             (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
 990                 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
 991                                port_id);
 992
 993                 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
 994                                   outbuf, sizeof(outbuf), &outlen);
 995                 if (rc)
 996                         return rc;
 997
 998                 if (outlen < sizeof(outbuf)) {
 999                         rc = -EIO;
1000                         return rc;
1001                 }
1002         }
1003
1004         if (port_flags)
1005                 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1006         if (vadaptor_flags)
1007                 *vadaptor_flags =
1008                         MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1009         if (vlan_tags)
1010                 *vlan_tags =
1011                         MCDI_DWORD(outbuf,
1012                                    VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1013
1014         return 0;
1015 }
1016
1017 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1018 {
1019         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1020
1021         MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1022         return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1023                             NULL, 0, NULL);
1024 }
1025
1026 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1027 {
1028         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1029
1030         MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1031         return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1032                             NULL, 0, NULL);
1033 }
1034
1035 int efx_ef10_vport_add_mac(struct efx_nic *efx,
1036                            unsigned int port_id, u8 *mac)
1037 {
1038         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1039
1040         MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1041         ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1042
1043         return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1044                             sizeof(inbuf), NULL, 0, NULL);
1045 }
1046
1047 int efx_ef10_vport_del_mac(struct efx_nic *efx,
1048                            unsigned int port_id, u8 *mac)
1049 {
1050         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1051
1052         MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1053         ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1054
1055         return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1056                             sizeof(inbuf), NULL, 0, NULL);
1057 }
1058
1059 #ifdef CONFIG_SFC_SRIOV
1060 static int efx_ef10_probe_vf(struct efx_nic *efx)
1061 {
1062         int rc;
1063         struct pci_dev *pci_dev_pf;
1064
1065         /* If the parent PF has no VF data structure, it doesn't know about this
1066          * VF so fail probe.  The VF needs to be re-created.  This can happen
1067          * if the PF driver is unloaded while the VF is assigned to a guest.
1068          */
1069         pci_dev_pf = efx->pci_dev->physfn;
1070         if (pci_dev_pf) {
1071                 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1072                 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1073
1074                 if (!nic_data_pf->vf) {
1075                         netif_info(efx, drv, efx->net_dev,
1076                                    "The VF cannot link to its parent PF; "
1077                                    "please destroy and re-create the VF\n");
1078                         return -EBUSY;
1079                 }
1080         }
1081
1082         rc = efx_ef10_probe(efx);
1083         if (rc)
1084                 return rc;
1085
1086         rc = efx_ef10_get_vf_index(efx);
1087         if (rc)
1088                 goto fail;
1089
1090         if (efx->pci_dev->is_virtfn) {
1091                 if (efx->pci_dev->physfn) {
1092                         struct efx_nic *efx_pf =
1093                                 pci_get_drvdata(efx->pci_dev->physfn);
1094                         struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1095                         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1096
1097                         nic_data_p->vf[nic_data->vf_index].efx = efx;
1098                         nic_data_p->vf[nic_data->vf_index].pci_dev =
1099                                 efx->pci_dev;
1100                 } else
1101                         netif_info(efx, drv, efx->net_dev,
1102                                    "Could not get the PF id from VF\n");
1103         }
1104
1105         return 0;
1106
1107 fail:
1108         efx_ef10_remove(efx);
1109         return rc;
1110 }
1111 #else
1112 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1113 {
1114         return 0;
1115 }
1116 #endif
1117
1118 static int efx_ef10_alloc_vis(struct efx_nic *efx,
1119                               unsigned int min_vis, unsigned int max_vis)
1120 {
1121         MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1122         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1123         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1124         size_t outlen;
1125         int rc;
1126
1127         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1128         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1129         rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1130                           outbuf, sizeof(outbuf), &outlen);
1131         if (rc != 0)
1132                 return rc;
1133
1134         if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1135                 return -EIO;
1136
1137         netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1138                   MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1139
1140         nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1141         nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1142         return 0;
1143 }
1144
1145 /* Note that the failure path of this function does not free
1146  * resources, as this will be done by efx_ef10_remove().
1147  */
1148 static int efx_ef10_dimension_resources(struct efx_nic *efx)
1149 {
1150         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1151         unsigned int uc_mem_map_size, wc_mem_map_size;
1152         unsigned int min_vis = max(EFX_TXQ_TYPES,
1153                                    efx_separate_tx_channels ? 2 : 1);
1154         unsigned int channel_vis, pio_write_vi_base, max_vis;
1155         void __iomem *membase;
1156         int rc;
1157
1158         channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
1159
1160 #ifdef EFX_USE_PIO
1161         /* Try to allocate PIO buffers if wanted and if the full
1162          * number of PIO buffers would be sufficient to allocate one
1163          * copy-buffer per TX channel.  Failure is non-fatal, as there
1164          * are only a small number of PIO buffers shared between all
1165          * functions of the controller.
1166          */
1167         if (efx_piobuf_size != 0 &&
1168             nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
1169             efx->n_tx_channels) {
1170                 unsigned int n_piobufs =
1171                         DIV_ROUND_UP(efx->n_tx_channels,
1172                                      nic_data->piobuf_size / efx_piobuf_size);
1173
1174                 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
1175                 if (rc)
1176                         netif_err(efx, probe, efx->net_dev,
1177                                   "failed to allocate PIO buffers (%d)\n", rc);
1178                 else
1179                         netif_dbg(efx, probe, efx->net_dev,
1180                                   "allocated %u PIO buffers\n", n_piobufs);
1181         }
1182 #else
1183         nic_data->n_piobufs = 0;
1184 #endif
1185
1186         /* PIO buffers should be mapped with write-combining enabled,
1187          * and we want to make single UC and WC mappings rather than
1188          * several of each (in fact that's the only option if host
1189          * page size is >4K).  So we may allocate some extra VIs just
1190          * for writing PIO buffers through.
1191          *
1192          * The UC mapping contains (channel_vis - 1) complete VIs and the
1193          * first half of the next VI.  Then the WC mapping begins with
1194          * the second half of this last VI.
1195          */
1196         uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
1197                                      ER_DZ_TX_PIOBUF);
1198         if (nic_data->n_piobufs) {
1199                 /* pio_write_vi_base rounds down to give the number of complete
1200                  * VIs inside the UC mapping.
1201                  */
1202                 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
1203                 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1204                                                nic_data->n_piobufs) *
1205                                               EFX_VI_PAGE_SIZE) -
1206                                    uc_mem_map_size);
1207                 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1208         } else {
1209                 pio_write_vi_base = 0;
1210                 wc_mem_map_size = 0;
1211                 max_vis = channel_vis;
1212         }
1213
1214         /* In case the last attached driver failed to free VIs, do it now */
1215         rc = efx_ef10_free_vis(efx);
1216         if (rc != 0)
1217                 return rc;
1218
1219         rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1220         if (rc != 0)
1221                 return rc;
1222
1223         if (nic_data->n_allocated_vis < channel_vis) {
1224                 netif_info(efx, drv, efx->net_dev,
1225                            "Could not allocate enough VIs to satisfy RSS"
1226                            " requirements. Performance may not be optimal.\n");
1227                 /* We didn't get the VIs to populate our channels.
1228                  * We could keep what we got but then we'd have more
1229                  * interrupts than we need.
1230                  * Instead calculate new max_channels and restart
1231                  */
1232                 efx->max_channels = nic_data->n_allocated_vis;
1233                 efx->max_tx_channels =
1234                         nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1235
1236                 efx_ef10_free_vis(efx);
1237                 return -EAGAIN;
1238         }
1239
1240         /* If we didn't get enough VIs to map all the PIO buffers, free the
1241          * PIO buffers
1242          */
1243         if (nic_data->n_piobufs &&
1244             nic_data->n_allocated_vis <
1245             pio_write_vi_base + nic_data->n_piobufs) {
1246                 netif_dbg(efx, probe, efx->net_dev,
1247                           "%u VIs are not sufficient to map %u PIO buffers\n",
1248                           nic_data->n_allocated_vis, nic_data->n_piobufs);
1249                 efx_ef10_free_piobufs(efx);
1250         }
1251
1252         /* Shrink the original UC mapping of the memory BAR */
1253         membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1254         if (!membase) {
1255                 netif_err(efx, probe, efx->net_dev,
1256                           "could not shrink memory BAR to %x\n",
1257                           uc_mem_map_size);
1258                 return -ENOMEM;
1259         }
1260         iounmap(efx->membase);
1261         efx->membase = membase;
1262
1263         /* Set up the WC mapping if needed */
1264         if (wc_mem_map_size) {
1265                 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1266                                                   uc_mem_map_size,
1267                                                   wc_mem_map_size);
1268                 if (!nic_data->wc_membase) {
1269                         netif_err(efx, probe, efx->net_dev,
1270                                   "could not allocate WC mapping of size %x\n",
1271                                   wc_mem_map_size);
1272                         return -ENOMEM;
1273                 }
1274                 nic_data->pio_write_vi_base = pio_write_vi_base;
1275                 nic_data->pio_write_base =
1276                         nic_data->wc_membase +
1277                         (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
1278                          uc_mem_map_size);
1279
1280                 rc = efx_ef10_link_piobufs(efx);
1281                 if (rc)
1282                         efx_ef10_free_piobufs(efx);
1283         }
1284
1285         netif_dbg(efx, probe, efx->net_dev,
1286                   "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1287                   &efx->membase_phys, efx->membase, uc_mem_map_size,
1288                   nic_data->wc_membase, wc_mem_map_size);
1289
1290         return 0;
1291 }
1292
1293 static int efx_ef10_init_nic(struct efx_nic *efx)
1294 {
1295         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1296         int rc;
1297
1298         if (nic_data->must_check_datapath_caps) {
1299                 rc = efx_ef10_init_datapath_caps(efx);
1300                 if (rc)
1301                         return rc;
1302                 nic_data->must_check_datapath_caps = false;
1303         }
1304
1305         if (nic_data->must_realloc_vis) {
1306                 /* We cannot let the number of VIs change now */
1307                 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1308                                         nic_data->n_allocated_vis);
1309                 if (rc)
1310                         return rc;
1311                 nic_data->must_realloc_vis = false;
1312         }
1313
1314         if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1315                 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1316                 if (rc == 0) {
1317                         rc = efx_ef10_link_piobufs(efx);
1318                         if (rc)
1319                                 efx_ef10_free_piobufs(efx);
1320                 }
1321
1322                 /* Log an error on failure, but this is non-fatal */
1323                 if (rc)
1324                         netif_err(efx, drv, efx->net_dev,
1325                                   "failed to restore PIO buffers (%d)\n", rc);
1326                 nic_data->must_restore_piobufs = false;
1327         }
1328
1329         /* don't fail init if RSS setup doesn't work */
1330         efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
1331
1332         return 0;
1333 }
1334
1335 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1336 {
1337         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1338 #ifdef CONFIG_SFC_SRIOV
1339         unsigned int i;
1340 #endif
1341
1342         /* All our allocations have been reset */
1343         nic_data->must_realloc_vis = true;
1344         nic_data->must_restore_filters = true;
1345         nic_data->must_restore_piobufs = true;
1346         efx_ef10_forget_old_piobufs(efx);
1347         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1348
1349         /* Driver-created vswitches and vports must be re-created */
1350         nic_data->must_probe_vswitching = true;
1351         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1352 #ifdef CONFIG_SFC_SRIOV
1353         if (nic_data->vf)
1354                 for (i = 0; i < efx->vf_count; i++)
1355                         nic_data->vf[i].vport_id = 0;
1356 #endif
1357 }
1358
1359 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1360 {
1361         if (reason == RESET_TYPE_MC_FAILURE)
1362                 return RESET_TYPE_DATAPATH;
1363
1364         return efx_mcdi_map_reset_reason(reason);
1365 }
1366
1367 static int efx_ef10_map_reset_flags(u32 *flags)
1368 {
1369         enum {
1370                 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1371                                    ETH_RESET_SHARED_SHIFT),
1372                 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1373                                   ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1374                                   ETH_RESET_PHY | ETH_RESET_MGMT) <<
1375                                  ETH_RESET_SHARED_SHIFT)
1376         };
1377
1378         /* We assume for now that our PCI function is permitted to
1379          * reset everything.
1380          */
1381
1382         if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1383                 *flags &= ~EF10_RESET_MC;
1384                 return RESET_TYPE_WORLD;
1385         }
1386
1387         if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1388                 *flags &= ~EF10_RESET_PORT;
1389                 return RESET_TYPE_ALL;
1390         }
1391
1392         /* no invisible reset implemented */
1393
1394         return -EINVAL;
1395 }
1396
1397 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1398 {
1399         int rc = efx_mcdi_reset(efx, reset_type);
1400
1401         /* Unprivileged functions return -EPERM, but need to return success
1402          * here so that the datapath is brought back up.
1403          */
1404         if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1405                 rc = 0;
1406
1407         /* If it was a port reset, trigger reallocation of MC resources.
1408          * Note that on an MC reset nothing needs to be done now because we'll
1409          * detect the MC reset later and handle it then.
1410          * For an FLR, we never get an MC reset event, but the MC has reset all
1411          * resources assigned to us, so we have to trigger reallocation now.
1412          */
1413         if ((reset_type == RESET_TYPE_ALL ||
1414              reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1415                 efx_ef10_reset_mc_allocations(efx);
1416         return rc;
1417 }
1418
1419 #define EF10_DMA_STAT(ext_name, mcdi_name)                      \
1420         [EF10_STAT_ ## ext_name] =                              \
1421         { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1422 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name)                \
1423         [EF10_STAT_ ## int_name] =                              \
1424         { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1425 #define EF10_OTHER_STAT(ext_name)                               \
1426         [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1427 #define GENERIC_SW_STAT(ext_name)                               \
1428         [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1429
1430 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1431         EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1432         EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1433         EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1434         EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1435         EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1436         EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1437         EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1438         EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1439         EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1440         EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1441         EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1442         EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1443         EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1444         EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1445         EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1446         EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1447         EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1448         EF10_OTHER_STAT(port_rx_good_bytes),
1449         EF10_OTHER_STAT(port_rx_bad_bytes),
1450         EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1451         EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1452         EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1453         EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1454         EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1455         EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1456         EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1457         EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1458         EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1459         EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1460         EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1461         EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1462         EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1463         EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1464         EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1465         EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1466         EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1467         EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1468         EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1469         EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1470         EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1471         EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1472         GENERIC_SW_STAT(rx_nodesc_trunc),
1473         GENERIC_SW_STAT(rx_noskb_drops),
1474         EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1475         EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1476         EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1477         EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1478         EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1479         EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1480         EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1481         EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1482         EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1483         EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1484         EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1485         EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1486         EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1487         EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1488         EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1489         EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1490         EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1491         EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1492         EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1493         EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1494         EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1495         EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1496         EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1497         EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1498         EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1499         EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1500         EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1501         EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1502         EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1503         EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1504 };
1505
1506 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) |      \
1507                                (1ULL << EF10_STAT_port_tx_packets) |    \
1508                                (1ULL << EF10_STAT_port_tx_pause) |      \
1509                                (1ULL << EF10_STAT_port_tx_unicast) |    \
1510                                (1ULL << EF10_STAT_port_tx_multicast) |  \
1511                                (1ULL << EF10_STAT_port_tx_broadcast) |  \
1512                                (1ULL << EF10_STAT_port_rx_bytes) |      \
1513                                (1ULL <<                                 \
1514                                 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1515                                (1ULL << EF10_STAT_port_rx_good_bytes) | \
1516                                (1ULL << EF10_STAT_port_rx_bad_bytes) |  \
1517                                (1ULL << EF10_STAT_port_rx_packets) |    \
1518                                (1ULL << EF10_STAT_port_rx_good) |       \
1519                                (1ULL << EF10_STAT_port_rx_bad) |        \
1520                                (1ULL << EF10_STAT_port_rx_pause) |      \
1521                                (1ULL << EF10_STAT_port_rx_control) |    \
1522                                (1ULL << EF10_STAT_port_rx_unicast) |    \
1523                                (1ULL << EF10_STAT_port_rx_multicast) |  \
1524                                (1ULL << EF10_STAT_port_rx_broadcast) |  \
1525                                (1ULL << EF10_STAT_port_rx_lt64) |       \
1526                                (1ULL << EF10_STAT_port_rx_64) |         \
1527                                (1ULL << EF10_STAT_port_rx_65_to_127) |  \
1528                                (1ULL << EF10_STAT_port_rx_128_to_255) | \
1529                                (1ULL << EF10_STAT_port_rx_256_to_511) | \
1530                                (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1531                                (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1532                                (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1533                                (1ULL << EF10_STAT_port_rx_gtjumbo) |    \
1534                                (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1535                                (1ULL << EF10_STAT_port_rx_overflow) |   \
1536                                (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1537                                (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1538                                (1ULL << GENERIC_STAT_rx_noskb_drops))
1539
1540 /* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1541  * For a 10G/40G switchable port we do not expose these because they might
1542  * not include all the packets they should.
1543  * On 8000 series NICs these statistics are always provided.
1544  */
1545 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) |  \
1546                                  (1ULL << EF10_STAT_port_tx_lt64) |     \
1547                                  (1ULL << EF10_STAT_port_tx_64) |       \
1548                                  (1ULL << EF10_STAT_port_tx_65_to_127) |\
1549                                  (1ULL << EF10_STAT_port_tx_128_to_255) |\
1550                                  (1ULL << EF10_STAT_port_tx_256_to_511) |\
1551                                  (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1552                                  (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1553                                  (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1554
1555 /* These statistics are only provided by the 40G MAC.  For a 10G/40G
1556  * switchable port we do expose these because the errors will otherwise
1557  * be silent.
1558  */
1559 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1560                                   (1ULL << EF10_STAT_port_rx_length_error))
1561
1562 /* These statistics are only provided if the firmware supports the
1563  * capability PM_AND_RXDP_COUNTERS.
1564  */
1565 #define HUNT_PM_AND_RXDP_STAT_MASK (                                    \
1566         (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) |              \
1567         (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) |            \
1568         (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) |               \
1569         (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) |             \
1570         (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) |                      \
1571         (1ULL << EF10_STAT_port_rx_pm_discard_qbb) |                    \
1572         (1ULL << EF10_STAT_port_rx_pm_discard_mapping) |                \
1573         (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) |             \
1574         (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) |             \
1575         (1ULL << EF10_STAT_port_rx_dp_streaming_packets) |              \
1576         (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) |                      \
1577         (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1578
1579 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1580 {
1581         u64 raw_mask = HUNT_COMMON_STAT_MASK;
1582         u32 port_caps = efx_mcdi_phy_get_caps(efx);
1583         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1584
1585         if (!(efx->mcdi->fn_flags &
1586               1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1587                 return 0;
1588
1589         if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
1590                 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1591                 /* 8000 series have everything even at 40G */
1592                 if (nic_data->datapath_caps2 &
1593                     (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1594                         raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1595         } else {
1596                 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1597         }
1598
1599         if (nic_data->datapath_caps &
1600             (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1601                 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1602
1603         return raw_mask;
1604 }
1605
1606 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1607 {
1608         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1609         u64 raw_mask[2];
1610
1611         raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1612
1613         /* Only show vadaptor stats when EVB capability is present */
1614         if (nic_data->datapath_caps &
1615             (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1616                 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1617                 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1618         } else {
1619                 raw_mask[1] = 0;
1620         }
1621
1622 #if BITS_PER_LONG == 64
1623         BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
1624         mask[0] = raw_mask[0];
1625         mask[1] = raw_mask[1];
1626 #else
1627         BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
1628         mask[0] = raw_mask[0] & 0xffffffff;
1629         mask[1] = raw_mask[0] >> 32;
1630         mask[2] = raw_mask[1] & 0xffffffff;
1631 #endif
1632 }
1633
1634 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1635 {
1636         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1637
1638         efx_ef10_get_stat_mask(efx, mask);
1639         return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1640                                       mask, names);
1641 }
1642
1643 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1644                                            struct rtnl_link_stats64 *core_stats)
1645 {
1646         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1647         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1648         u64 *stats = nic_data->stats;
1649         size_t stats_count = 0, index;
1650
1651         efx_ef10_get_stat_mask(efx, mask);
1652
1653         if (full_stats) {
1654                 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1655                         if (efx_ef10_stat_desc[index].name) {
1656                                 *full_stats++ = stats[index];
1657                                 ++stats_count;
1658                         }
1659                 }
1660         }
1661
1662         if (!core_stats)
1663                 return stats_count;
1664
1665         if (nic_data->datapath_caps &
1666                         1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1667                 /* Use vadaptor stats. */
1668                 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1669                                          stats[EF10_STAT_rx_multicast] +
1670                                          stats[EF10_STAT_rx_broadcast];
1671                 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1672                                          stats[EF10_STAT_tx_multicast] +
1673                                          stats[EF10_STAT_tx_broadcast];
1674                 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1675                                        stats[EF10_STAT_rx_multicast_bytes] +
1676                                        stats[EF10_STAT_rx_broadcast_bytes];
1677                 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1678                                        stats[EF10_STAT_tx_multicast_bytes] +
1679                                        stats[EF10_STAT_tx_broadcast_bytes];
1680                 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1681                                          stats[GENERIC_STAT_rx_noskb_drops];
1682                 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1683                 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1684                 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1685                 core_stats->rx_errors = core_stats->rx_crc_errors;
1686                 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1687         } else {
1688                 /* Use port stats. */
1689                 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1690                 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1691                 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1692                 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1693                 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1694                                          stats[GENERIC_STAT_rx_nodesc_trunc] +
1695                                          stats[GENERIC_STAT_rx_noskb_drops];
1696                 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1697                 core_stats->rx_length_errors =
1698                                 stats[EF10_STAT_port_rx_gtjumbo] +
1699                                 stats[EF10_STAT_port_rx_length_error];
1700                 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1701                 core_stats->rx_frame_errors =
1702                                 stats[EF10_STAT_port_rx_align_error];
1703                 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1704                 core_stats->rx_errors = (core_stats->rx_length_errors +
1705                                          core_stats->rx_crc_errors +
1706                                          core_stats->rx_frame_errors);
1707         }
1708
1709         return stats_count;
1710 }
1711
1712 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
1713 {
1714         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1715         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1716         __le64 generation_start, generation_end;
1717         u64 *stats = nic_data->stats;
1718         __le64 *dma_stats;
1719
1720         efx_ef10_get_stat_mask(efx, mask);
1721
1722         dma_stats = efx->stats_buffer.addr;
1723
1724         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1725         if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1726                 return 0;
1727         rmb();
1728         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1729                              stats, efx->stats_buffer.addr, false);
1730         rmb();
1731         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1732         if (generation_end != generation_start)
1733                 return -EAGAIN;
1734
1735         /* Update derived statistics */
1736         efx_nic_fix_nodesc_drop_stat(efx,
1737                                      &stats[EF10_STAT_port_rx_nodesc_drops]);
1738         stats[EF10_STAT_port_rx_good_bytes] =
1739                 stats[EF10_STAT_port_rx_bytes] -
1740                 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1741         efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1742                              stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1743         efx_update_sw_stats(efx, stats);
1744         return 0;
1745 }
1746
1747
1748 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1749                                        struct rtnl_link_stats64 *core_stats)
1750 {
1751         int retry;
1752
1753         /* If we're unlucky enough to read statistics during the DMA, wait
1754          * up to 10ms for it to finish (typically takes <500us)
1755          */
1756         for (retry = 0; retry < 100; ++retry) {
1757                 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
1758                         break;
1759                 udelay(100);
1760         }
1761
1762         return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1763 }
1764
1765 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1766 {
1767         MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1768         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1769         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1770         __le64 generation_start, generation_end;
1771         u64 *stats = nic_data->stats;
1772         u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1773         struct efx_buffer stats_buf;
1774         __le64 *dma_stats;
1775         int rc;
1776
1777         spin_unlock_bh(&efx->stats_lock);
1778
1779         if (in_interrupt()) {
1780                 /* If in atomic context, cannot update stats.  Just update the
1781                  * software stats and return so the caller can continue.
1782                  */
1783                 spin_lock_bh(&efx->stats_lock);
1784                 efx_update_sw_stats(efx, stats);
1785                 return 0;
1786         }
1787
1788         efx_ef10_get_stat_mask(efx, mask);
1789
1790         rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
1791         if (rc) {
1792                 spin_lock_bh(&efx->stats_lock);
1793                 return rc;
1794         }
1795
1796         dma_stats = stats_buf.addr;
1797         dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1798
1799         MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1800         MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
1801                               MAC_STATS_IN_DMA, 1);
1802         MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1803         MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1804
1805         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1806                                 NULL, 0, NULL);
1807         spin_lock_bh(&efx->stats_lock);
1808         if (rc) {
1809                 /* Expect ENOENT if DMA queues have not been set up */
1810                 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1811                         efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1812                                                sizeof(inbuf), NULL, 0, rc);
1813                 goto out;
1814         }
1815
1816         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1817         if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1818                 WARN_ON_ONCE(1);
1819                 goto out;
1820         }
1821         rmb();
1822         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1823                              stats, stats_buf.addr, false);
1824         rmb();
1825         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1826         if (generation_end != generation_start) {
1827                 rc = -EAGAIN;
1828                 goto out;
1829         }
1830
1831         efx_update_sw_stats(efx, stats);
1832 out:
1833         /* releasing a DMA coherent buffer with BH disabled can panic */
1834         spin_unlock_bh(&efx->stats_lock);
1835         efx_nic_free_buffer(efx, &stats_buf);
1836         spin_lock_bh(&efx->stats_lock);
1837         return rc;
1838 }
1839
1840 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1841                                        struct rtnl_link_stats64 *core_stats)
1842 {
1843         if (efx_ef10_try_update_nic_stats_vf(efx))
1844                 return 0;
1845
1846         return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1847 }
1848
1849 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1850 {
1851         struct efx_nic *efx = channel->efx;
1852         unsigned int mode, usecs;
1853         efx_dword_t timer_cmd;
1854
1855         if (channel->irq_moderation_us) {
1856                 mode = 3;
1857                 usecs = channel->irq_moderation_us;
1858         } else {
1859                 mode = 0;
1860                 usecs = 0;
1861         }
1862
1863         if (EFX_EF10_WORKAROUND_61265(efx)) {
1864                 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
1865                 unsigned int ns = usecs * 1000;
1866
1867                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
1868                                channel->channel);
1869                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
1870                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
1871                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
1872
1873                 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
1874                                    inbuf, sizeof(inbuf), 0, NULL, 0);
1875         } else if (EFX_EF10_WORKAROUND_35388(efx)) {
1876                 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1877
1878                 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1879                                      EFE_DD_EVQ_IND_TIMER_FLAGS,
1880                                      ERF_DD_EVQ_IND_TIMER_MODE, mode,
1881                                      ERF_DD_EVQ_IND_TIMER_VAL, ticks);
1882                 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1883                                 channel->channel);
1884         } else {
1885                 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1886
1887                 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1888                                      ERF_DZ_TC_TIMER_VAL, ticks);
1889                 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1890                                 channel->channel);
1891         }
1892 }
1893
1894 static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1895                                 struct ethtool_wolinfo *wol) {}
1896
1897 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1898 {
1899         return -EOPNOTSUPP;
1900 }
1901
1902 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1903 {
1904         wol->supported = 0;
1905         wol->wolopts = 0;
1906         memset(&wol->sopass, 0, sizeof(wol->sopass));
1907 }
1908
1909 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1910 {
1911         if (type != 0)
1912                 return -EINVAL;
1913         return 0;
1914 }
1915
1916 static void efx_ef10_mcdi_request(struct efx_nic *efx,
1917                                   const efx_dword_t *hdr, size_t hdr_len,
1918                                   const efx_dword_t *sdu, size_t sdu_len)
1919 {
1920         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1921         u8 *pdu = nic_data->mcdi_buf.addr;
1922
1923         memcpy(pdu, hdr, hdr_len);
1924         memcpy(pdu + hdr_len, sdu, sdu_len);
1925         wmb();
1926
1927         /* The hardware provides 'low' and 'high' (doorbell) registers
1928          * for passing the 64-bit address of an MCDI request to
1929          * firmware.  However the dwords are swapped by firmware.  The
1930          * least significant bits of the doorbell are then 0 for all
1931          * MCDI requests due to alignment.
1932          */
1933         _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1934                     ER_DZ_MC_DB_LWRD);
1935         _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1936                     ER_DZ_MC_DB_HWRD);
1937 }
1938
1939 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1940 {
1941         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1942         const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1943
1944         rmb();
1945         return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1946 }
1947
1948 static void
1949 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1950                             size_t offset, size_t outlen)
1951 {
1952         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1953         const u8 *pdu = nic_data->mcdi_buf.addr;
1954
1955         memcpy(outbuf, pdu + offset, outlen);
1956 }
1957
1958 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
1959 {
1960         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1961
1962         /* All our allocations have been reset */
1963         efx_ef10_reset_mc_allocations(efx);
1964
1965         /* The datapath firmware might have been changed */
1966         nic_data->must_check_datapath_caps = true;
1967
1968         /* MAC statistics have been cleared on the NIC; clear the local
1969          * statistic that we update with efx_update_diff_stat().
1970          */
1971         nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
1972 }
1973
1974 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1975 {
1976         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1977         int rc;
1978
1979         rc = efx_ef10_get_warm_boot_count(efx);
1980         if (rc < 0) {
1981                 /* The firmware is presumably in the process of
1982                  * rebooting.  However, we are supposed to report each
1983                  * reboot just once, so we must only do that once we
1984                  * can read and store the updated warm boot count.
1985                  */
1986                 return 0;
1987         }
1988
1989         if (rc == nic_data->warm_boot_count)
1990                 return 0;
1991
1992         nic_data->warm_boot_count = rc;
1993         efx_ef10_mcdi_reboot_detected(efx);
1994
1995         return -EIO;
1996 }
1997
1998 /* Handle an MSI interrupt
1999  *
2000  * Handle an MSI hardware interrupt.  This routine schedules event
2001  * queue processing.  No interrupt acknowledgement cycle is necessary.
2002  * Also, we never need to check that the interrupt is for us, since
2003  * MSI interrupts cannot be shared.
2004  */
2005 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
2006 {
2007         struct efx_msi_context *context = dev_id;
2008         struct efx_nic *efx = context->efx;
2009
2010         netif_vdbg(efx, intr, efx->net_dev,
2011                    "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2012
2013         if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
2014                 /* Note test interrupts */
2015                 if (context->index == efx->irq_level)
2016                         efx->last_irq_cpu = raw_smp_processor_id();
2017
2018                 /* Schedule processing of the channel */
2019                 efx_schedule_channel_irq(efx->channel[context->index]);
2020         }
2021
2022         return IRQ_HANDLED;
2023 }
2024
2025 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2026 {
2027         struct efx_nic *efx = dev_id;
2028         bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
2029         struct efx_channel *channel;
2030         efx_dword_t reg;
2031         u32 queues;
2032
2033         /* Read the ISR which also ACKs the interrupts */
2034         efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
2035         queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2036
2037         if (queues == 0)
2038                 return IRQ_NONE;
2039
2040         if (likely(soft_enabled)) {
2041                 /* Note test interrupts */
2042                 if (queues & (1U << efx->irq_level))
2043                         efx->last_irq_cpu = raw_smp_processor_id();
2044
2045                 efx_for_each_channel(channel, efx) {
2046                         if (queues & 1)
2047                                 efx_schedule_channel_irq(channel);
2048                         queues >>= 1;
2049                 }
2050         }
2051
2052         netif_vdbg(efx, intr, efx->net_dev,
2053                    "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2054                    irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2055
2056         return IRQ_HANDLED;
2057 }
2058
2059 static int efx_ef10_irq_test_generate(struct efx_nic *efx)
2060 {
2061         MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2062
2063         if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2064                                     NULL) == 0)
2065                 return -ENOTSUPP;
2066
2067         BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2068
2069         MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
2070         return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
2071                             inbuf, sizeof(inbuf), NULL, 0, NULL);
2072 }
2073
2074 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2075 {
2076         return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2077                                     (tx_queue->ptr_mask + 1) *
2078                                     sizeof(efx_qword_t),
2079                                     GFP_KERNEL);
2080 }
2081
2082 /* This writes to the TX_DESC_WPTR and also pushes data */
2083 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2084                                          const efx_qword_t *txd)
2085 {
2086         unsigned int write_ptr;
2087         efx_oword_t reg;
2088
2089         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2090         EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2091         reg.qword[0] = *txd;
2092         efx_writeo_page(tx_queue->efx, &reg,
2093                         ER_DZ_TX_DESC_UPD, tx_queue->queue);
2094 }
2095
2096 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2097 {
2098         MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2099                                                        EFX_BUF_SIZE));
2100         bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
2101         size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
2102         struct efx_channel *channel = tx_queue->channel;
2103         struct efx_nic *efx = tx_queue->efx;
2104         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2105         size_t inlen;
2106         dma_addr_t dma_addr;
2107         efx_qword_t *txd;
2108         int rc;
2109         int i;
2110         BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
2111
2112         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
2113         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
2114         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
2115         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
2116         MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
2117                               INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
2118                               INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
2119         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
2120         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
2121
2122         dma_addr = tx_queue->txd.buf.dma_addr;
2123
2124         netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2125                   tx_queue->queue, entries, (u64)dma_addr);
2126
2127         for (i = 0; i < entries; ++i) {
2128                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2129                 dma_addr += EFX_BUF_SIZE;
2130         }
2131
2132         inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2133
2134         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
2135                           NULL, 0, NULL);
2136         if (rc)
2137                 goto fail;
2138
2139         /* A previous user of this TX queue might have set us up the
2140          * bomb by writing a descriptor to the TX push collector but
2141          * not the doorbell.  (Each collector belongs to a port, not a
2142          * queue or function, so cannot easily be reset.)  We must
2143          * attempt to push a no-op descriptor in its place.
2144          */
2145         tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2146         tx_queue->insert_count = 1;
2147         txd = efx_tx_desc(tx_queue, 0);
2148         EFX_POPULATE_QWORD_4(*txd,
2149                              ESF_DZ_TX_DESC_IS_OPT, true,
2150                              ESF_DZ_TX_OPTION_TYPE,
2151                              ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2152                              ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2153                              ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
2154         tx_queue->write_count = 1;
2155
2156         if (nic_data->datapath_caps &
2157             (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
2158                 tx_queue->tso_version = 1;
2159         }
2160
2161         wmb();
2162         efx_ef10_push_tx_desc(tx_queue, txd);
2163
2164         return;
2165
2166 fail:
2167         netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2168                     tx_queue->queue);
2169 }
2170
2171 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2172 {
2173         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
2174         MCDI_DECLARE_BUF_ERR(outbuf);
2175         struct efx_nic *efx = tx_queue->efx;
2176         size_t outlen;
2177         int rc;
2178
2179         MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2180                        tx_queue->queue);
2181
2182         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
2183                           outbuf, sizeof(outbuf), &outlen);
2184
2185         if (rc && rc != -EALREADY)
2186                 goto fail;
2187
2188         return;
2189
2190 fail:
2191         efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2192                                outbuf, outlen, rc);
2193 }
2194
2195 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2196 {
2197         efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2198 }
2199
2200 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2201 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2202 {
2203         unsigned int write_ptr;
2204         efx_dword_t reg;
2205
2206         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2207         EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2208         efx_writed_page(tx_queue->efx, &reg,
2209                         ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2210 }
2211
2212 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2213 {
2214         unsigned int old_write_count = tx_queue->write_count;
2215         struct efx_tx_buffer *buffer;
2216         unsigned int write_ptr;
2217         efx_qword_t *txd;
2218
2219         tx_queue->xmit_more_available = false;
2220         if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2221                 return;
2222
2223         do {
2224                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2225                 buffer = &tx_queue->buffer[write_ptr];
2226                 txd = efx_tx_desc(tx_queue, write_ptr);
2227                 ++tx_queue->write_count;
2228
2229                 /* Create TX descriptor ring entry */
2230                 if (buffer->flags & EFX_TX_BUF_OPTION) {
2231                         *txd = buffer->option;
2232                 } else {
2233                         BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2234                         EFX_POPULATE_QWORD_3(
2235                                 *txd,
2236                                 ESF_DZ_TX_KER_CONT,
2237                                 buffer->flags & EFX_TX_BUF_CONT,
2238                                 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2239                                 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2240                 }
2241         } while (tx_queue->write_count != tx_queue->insert_count);
2242
2243         wmb(); /* Ensure descriptors are written before they are fetched */
2244
2245         if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2246                 txd = efx_tx_desc(tx_queue,
2247                                   old_write_count & tx_queue->ptr_mask);
2248                 efx_ef10_push_tx_desc(tx_queue, txd);
2249                 ++tx_queue->pushes;
2250         } else {
2251                 efx_ef10_notify_tx_desc(tx_queue);
2252         }
2253 }
2254
2255 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
2256                                       bool exclusive, unsigned *context_size)
2257 {
2258         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2259         MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
2260         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2261         size_t outlen;
2262         int rc;
2263         u32 alloc_type = exclusive ?
2264                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2265                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2266         unsigned rss_spread = exclusive ?
2267                                 efx->rss_spread :
2268                                 min(rounddown_pow_of_two(efx->rss_spread),
2269                                     EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2270
2271         if (!exclusive && rss_spread == 1) {
2272                 *context = EFX_EF10_RSS_CONTEXT_INVALID;
2273                 if (context_size)
2274                         *context_size = 1;
2275                 return 0;
2276         }
2277
2278         if (nic_data->datapath_caps &
2279             1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2280                 return -EOPNOTSUPP;
2281
2282         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
2283                        nic_data->vport_id);
2284         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2285         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
2286
2287         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2288                 outbuf, sizeof(outbuf), &outlen);
2289         if (rc != 0)
2290                 return rc;
2291
2292         if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2293                 return -EIO;
2294
2295         *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2296
2297         if (context_size)
2298                 *context_size = rss_spread;
2299
2300         return 0;
2301 }
2302
2303 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2304 {
2305         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2306         int rc;
2307
2308         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2309                        context);
2310
2311         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2312                             NULL, 0, NULL);
2313         WARN_ON(rc != 0);
2314 }
2315
2316 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
2317                                        const u32 *rx_indir_table)
2318 {
2319         MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2320         MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2321         int i, rc;
2322
2323         MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2324                        context);
2325         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2326                      MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2327
2328         for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
2329                 MCDI_PTR(tablebuf,
2330                          RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
2331                                 (u8) rx_indir_table[i];
2332
2333         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2334                           sizeof(tablebuf), NULL, 0, NULL);
2335         if (rc != 0)
2336                 return rc;
2337
2338         MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2339                        context);
2340         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2341                      MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2342         for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2343                 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
2344                         efx->rx_hash_key[i];
2345
2346         return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2347                             sizeof(keybuf), NULL, 0, NULL);
2348 }
2349
2350 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2351 {
2352         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2353
2354         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2355                 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
2356         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
2357 }
2358
2359 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2360                                               unsigned *context_size)
2361 {
2362         u32 new_rx_rss_context;
2363         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2364         int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2365                                             false, context_size);
2366
2367         if (rc != 0)
2368                 return rc;
2369
2370         nic_data->rx_rss_context = new_rx_rss_context;
2371         nic_data->rx_rss_context_exclusive = false;
2372         efx_set_default_rx_indir_table(efx);
2373         return 0;
2374 }
2375
2376 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2377                                                  const u32 *rx_indir_table)
2378 {
2379         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2380         int rc;
2381         u32 new_rx_rss_context;
2382
2383         if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2384             !nic_data->rx_rss_context_exclusive) {
2385                 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2386                                                 true, NULL);
2387                 if (rc == -EOPNOTSUPP)
2388                         return rc;
2389                 else if (rc != 0)
2390                         goto fail1;
2391         } else {
2392                 new_rx_rss_context = nic_data->rx_rss_context;
2393         }
2394
2395         rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2396                                          rx_indir_table);
2397         if (rc != 0)
2398                 goto fail2;
2399
2400         if (nic_data->rx_rss_context != new_rx_rss_context)
2401                 efx_ef10_rx_free_indir_table(efx);
2402         nic_data->rx_rss_context = new_rx_rss_context;
2403         nic_data->rx_rss_context_exclusive = true;
2404         if (rx_indir_table != efx->rx_indir_table)
2405                 memcpy(efx->rx_indir_table, rx_indir_table,
2406                        sizeof(efx->rx_indir_table));
2407         return 0;
2408
2409 fail2:
2410         if (new_rx_rss_context != nic_data->rx_rss_context)
2411                 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2412 fail1:
2413         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2414         return rc;
2415 }
2416
2417 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2418                                           const u32 *rx_indir_table)
2419 {
2420         int rc;
2421
2422         if (efx->rss_spread == 1)
2423                 return 0;
2424
2425         rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
2426
2427         if (rc == -ENOBUFS && !user) {
2428                 unsigned context_size;
2429                 bool mismatch = false;
2430                 size_t i;
2431
2432                 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2433                      i++)
2434                         mismatch = rx_indir_table[i] !=
2435                                 ethtool_rxfh_indir_default(i, efx->rss_spread);
2436
2437                 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2438                 if (rc == 0) {
2439                         if (context_size != efx->rss_spread)
2440                                 netif_warn(efx, probe, efx->net_dev,
2441                                            "Could not allocate an exclusive RSS"
2442                                            " context; allocated a shared one of"
2443                                            " different size."
2444                                            " Wanted %u, got %u.\n",
2445                                            efx->rss_spread, context_size);
2446                         else if (mismatch)
2447                                 netif_warn(efx, probe, efx->net_dev,
2448                                            "Could not allocate an exclusive RSS"
2449                                            " context; allocated a shared one but"
2450                                            " could not apply custom"
2451                                            " indirection.\n");
2452                         else
2453                                 netif_info(efx, probe, efx->net_dev,
2454                                            "Could not allocate an exclusive RSS"
2455                                            " context; allocated a shared one.\n");
2456                 }
2457         }
2458         return rc;
2459 }
2460
2461 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2462                                           const u32 *rx_indir_table
2463                                           __attribute__ ((unused)))
2464 {
2465         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2466
2467         if (user)
2468                 return -EOPNOTSUPP;
2469         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2470                 return 0;
2471         return efx_ef10_rx_push_shared_rss_config(efx, NULL);
2472 }
2473
2474 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2475 {
2476         return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2477                                     (rx_queue->ptr_mask + 1) *
2478                                     sizeof(efx_qword_t),
2479                                     GFP_KERNEL);
2480 }
2481
2482 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2483 {
2484         MCDI_DECLARE_BUF(inbuf,
2485                          MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2486                                                 EFX_BUF_SIZE));
2487         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2488         size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2489         struct efx_nic *efx = rx_queue->efx;
2490         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2491         size_t inlen;
2492         dma_addr_t dma_addr;
2493         int rc;
2494         int i;
2495         BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
2496
2497         rx_queue->scatter_n = 0;
2498         rx_queue->scatter_len = 0;
2499
2500         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2501         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2502         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2503         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2504                        efx_rx_queue_index(rx_queue));
2505         MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2506                               INIT_RXQ_IN_FLAG_PREFIX, 1,
2507                               INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
2508         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
2509         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
2510
2511         dma_addr = rx_queue->rxd.buf.dma_addr;
2512
2513         netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2514                   efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2515
2516         for (i = 0; i < entries; ++i) {
2517                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2518                 dma_addr += EFX_BUF_SIZE;
2519         }
2520
2521         inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2522
2523         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
2524                           NULL, 0, NULL);
2525         if (rc)
2526                 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2527                             efx_rx_queue_index(rx_queue));
2528 }
2529
2530 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2531 {
2532         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
2533         MCDI_DECLARE_BUF_ERR(outbuf);
2534         struct efx_nic *efx = rx_queue->efx;
2535         size_t outlen;
2536         int rc;
2537
2538         MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2539                        efx_rx_queue_index(rx_queue));
2540
2541         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
2542                           outbuf, sizeof(outbuf), &outlen);
2543
2544         if (rc && rc != -EALREADY)
2545                 goto fail;
2546
2547         return;
2548
2549 fail:
2550         efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2551                                outbuf, outlen, rc);
2552 }
2553
2554 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2555 {
2556         efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2557 }
2558
2559 /* This creates an entry in the RX descriptor queue */
2560 static inline void
2561 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2562 {
2563         struct efx_rx_buffer *rx_buf;
2564         efx_qword_t *rxd;
2565
2566         rxd = efx_rx_desc(rx_queue, index);
2567         rx_buf = efx_rx_buffer(rx_queue, index);
2568         EFX_POPULATE_QWORD_2(*rxd,
2569                              ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2570                              ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2571 }
2572
2573 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2574 {
2575         struct efx_nic *efx = rx_queue->efx;
2576         unsigned int write_count;
2577         efx_dword_t reg;
2578
2579         /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2580         write_count = rx_queue->added_count & ~7;
2581         if (rx_queue->notified_count == write_count)
2582                 return;
2583
2584         do
2585                 efx_ef10_build_rx_desc(
2586                         rx_queue,
2587                         rx_queue->notified_count & rx_queue->ptr_mask);
2588         while (++rx_queue->notified_count != write_count);
2589
2590         wmb();
2591         EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2592                              write_count & rx_queue->ptr_mask);
2593         efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2594                         efx_rx_queue_index(rx_queue));
2595 }
2596
2597 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2598
2599 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2600 {
2601         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2602         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2603         efx_qword_t event;
2604
2605         EFX_POPULATE_QWORD_2(event,
2606                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2607                              ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2608
2609         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2610
2611         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2612          * already swapped the data to little-endian order.
2613          */
2614         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2615                sizeof(efx_qword_t));
2616
2617         efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2618                            inbuf, sizeof(inbuf), 0,
2619                            efx_ef10_rx_defer_refill_complete, 0);
2620 }
2621
2622 static void
2623 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2624                                   int rc, efx_dword_t *outbuf,
2625                                   size_t outlen_actual)
2626 {
2627         /* nothing to do */
2628 }
2629
2630 static int efx_ef10_ev_probe(struct efx_channel *channel)
2631 {
2632         return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2633                                     (channel->eventq_mask + 1) *
2634                                     sizeof(efx_qword_t),
2635                                     GFP_KERNEL);
2636 }
2637
2638 static void efx_ef10_ev_fini(struct efx_channel *channel)
2639 {
2640         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2641         MCDI_DECLARE_BUF_ERR(outbuf);
2642         struct efx_nic *efx = channel->efx;
2643         size_t outlen;
2644         int rc;
2645
2646         MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2647
2648         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2649                           outbuf, sizeof(outbuf), &outlen);
2650
2651         if (rc && rc != -EALREADY)
2652                 goto fail;
2653
2654         return;
2655
2656 fail:
2657         efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2658                                outbuf, outlen, rc);
2659 }
2660
2661 static int efx_ef10_ev_init(struct efx_channel *channel)
2662 {
2663         MCDI_DECLARE_BUF(inbuf,
2664                          MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2665                                                    EFX_BUF_SIZE));
2666         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
2667         size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2668         struct efx_nic *efx = channel->efx;
2669         struct efx_ef10_nic_data *nic_data;
2670         size_t inlen, outlen;
2671         unsigned int enabled, implemented;
2672         dma_addr_t dma_addr;
2673         int rc;
2674         int i;
2675
2676         nic_data = efx->nic_data;
2677
2678         /* Fill event queue with all ones (i.e. empty events) */
2679         memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2680
2681         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2682         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2683         /* INIT_EVQ expects index in vector table, not absolute */
2684         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
2685         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2686                        MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2687         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2688         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2689         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2690                        MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2691         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2692
2693         if (nic_data->datapath_caps2 &
2694             1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN) {
2695                 /* Use the new generic approach to specifying event queue
2696                  * configuration, requesting lower latency or higher throughput.
2697                  * The options that actually get used appear in the output.
2698                  */
2699                 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
2700                                       INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
2701                                       INIT_EVQ_V2_IN_FLAG_TYPE,
2702                                       MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
2703         } else {
2704                 bool cut_thru = !(nic_data->datapath_caps &
2705                         1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2706
2707                 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
2708                                       INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
2709                                       INIT_EVQ_IN_FLAG_RX_MERGE, 1,
2710                                       INIT_EVQ_IN_FLAG_TX_MERGE, 1,
2711                                       INIT_EVQ_IN_FLAG_CUT_THRU, cut_thru);
2712         }
2713
2714         dma_addr = channel->eventq.buf.dma_addr;
2715         for (i = 0; i < entries; ++i) {
2716                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
2717                 dma_addr += EFX_BUF_SIZE;
2718         }
2719
2720         inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
2721
2722         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
2723                           outbuf, sizeof(outbuf), &outlen);
2724
2725         if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
2726                 netif_dbg(efx, drv, efx->net_dev,
2727                           "Channel %d using event queue flags %08x\n",
2728                           channel->channel,
2729                           MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
2730
2731         /* IRQ return is ignored */
2732         if (channel->channel || rc)
2733                 return rc;
2734
2735         /* Successfully created event queue on channel 0 */
2736         rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
2737         if (rc == -ENOSYS) {
2738                 /* GET_WORKAROUNDS was implemented before this workaround,
2739                  * thus it must be unavailable in this firmware.
2740                  */
2741                 nic_data->workaround_26807 = false;
2742                 rc = 0;
2743         } else if (rc) {
2744                 goto fail;
2745         } else {
2746                 nic_data->workaround_26807 =
2747                         !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2748
2749                 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
2750                     !nic_data->workaround_26807) {
2751                         unsigned int flags;
2752
2753                         rc = efx_mcdi_set_workaround(efx,
2754                                                      MC_CMD_WORKAROUND_BUG26807,
2755                                                      true, &flags);
2756
2757                         if (!rc) {
2758                                 if (flags &
2759                                     1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2760                                         netif_info(efx, drv, efx->net_dev,
2761                                                    "other functions on NIC have been reset\n");
2762
2763                                         /* With MCFW v4.6.x and earlier, the
2764                                          * boot count will have incremented,
2765                                          * so re-read the warm_boot_count
2766                                          * value now to ensure this function
2767                                          * doesn't think it has changed next
2768                                          * time it checks.
2769                                          */
2770                                         rc = efx_ef10_get_warm_boot_count(efx);
2771                                         if (rc >= 0) {
2772                                                 nic_data->warm_boot_count = rc;
2773                                                 rc = 0;
2774                                         }
2775                                 }
2776                                 nic_data->workaround_26807 = true;
2777                         } else if (rc == -EPERM) {
2778                                 rc = 0;
2779                         }
2780                 }
2781         }
2782
2783         if (!rc)
2784                 return 0;
2785
2786 fail:
2787         efx_ef10_ev_fini(channel);
2788         return rc;
2789 }
2790
2791 static void efx_ef10_ev_remove(struct efx_channel *channel)
2792 {
2793         efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
2794 }
2795
2796 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2797                                            unsigned int rx_queue_label)
2798 {
2799         struct efx_nic *efx = rx_queue->efx;
2800
2801         netif_info(efx, hw, efx->net_dev,
2802                    "rx event arrived on queue %d labeled as queue %u\n",
2803                    efx_rx_queue_index(rx_queue), rx_queue_label);
2804
2805         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2806 }
2807
2808 static void
2809 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2810                              unsigned int actual, unsigned int expected)
2811 {
2812         unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2813         struct efx_nic *efx = rx_queue->efx;
2814
2815         netif_info(efx, hw, efx->net_dev,
2816                    "dropped %d events (index=%d expected=%d)\n",
2817                    dropped, actual, expected);
2818
2819         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2820 }
2821
2822 /* partially received RX was aborted. clean up. */
2823 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2824 {
2825         unsigned int rx_desc_ptr;
2826
2827         netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2828                   "scattered RX aborted (dropping %u buffers)\n",
2829                   rx_queue->scatter_n);
2830
2831         rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2832
2833         efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2834                       0, EFX_RX_PKT_DISCARD);
2835
2836         rx_queue->removed_count += rx_queue->scatter_n;
2837         rx_queue->scatter_n = 0;
2838         rx_queue->scatter_len = 0;
2839         ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2840 }
2841
2842 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2843                                     const efx_qword_t *event)
2844 {
2845         unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
2846         unsigned int n_descs, n_packets, i;
2847         struct efx_nic *efx = channel->efx;
2848         struct efx_rx_queue *rx_queue;
2849         bool rx_cont;
2850         u16 flags = 0;
2851
2852         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2853                 return 0;
2854
2855         /* Basic packet information */
2856         rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2857         next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2858         rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2859         rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
2860         rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2861
2862         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2863                 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2864                             EFX_QWORD_FMT "\n",
2865                             EFX_QWORD_VAL(*event));
2866
2867         rx_queue = efx_channel_get_rx_queue(channel);
2868
2869         if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2870                 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2871
2872         n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2873                    ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2874
2875         if (n_descs != rx_queue->scatter_n + 1) {
2876                 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2877
2878                 /* detect rx abort */
2879                 if (unlikely(n_descs == rx_queue->scatter_n)) {
2880                         if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2881                                 netdev_WARN(efx->net_dev,
2882                                             "invalid RX abort: scatter_n=%u event="
2883                                             EFX_QWORD_FMT "\n",
2884                                             rx_queue->scatter_n,
2885                                             EFX_QWORD_VAL(*event));
2886                         efx_ef10_handle_rx_abort(rx_queue);
2887                         return 0;
2888                 }
2889
2890                 /* Check that RX completion merging is valid, i.e.
2891                  * the current firmware supports it and this is a
2892                  * non-scattered packet.
2893                  */
2894                 if (!(nic_data->datapath_caps &
2895                       (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2896                     rx_queue->scatter_n != 0 || rx_cont) {
2897                         efx_ef10_handle_rx_bad_lbits(
2898                                 rx_queue, next_ptr_lbits,
2899                                 (rx_queue->removed_count +
2900                                  rx_queue->scatter_n + 1) &
2901                                 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2902                         return 0;
2903                 }
2904
2905                 /* Merged completion for multiple non-scattered packets */
2906                 rx_queue->scatter_n = 1;
2907                 rx_queue->scatter_len = 0;
2908                 n_packets = n_descs;
2909                 ++channel->n_rx_merge_events;
2910                 channel->n_rx_merge_packets += n_packets;
2911                 flags |= EFX_RX_PKT_PREFIX_LEN;
2912         } else {
2913                 ++rx_queue->scatter_n;
2914                 rx_queue->scatter_len += rx_bytes;
2915                 if (rx_cont)
2916                         return 0;
2917                 n_packets = 1;
2918         }
2919
2920         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
2921                 flags |= EFX_RX_PKT_DISCARD;
2922
2923         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
2924                 channel->n_rx_ip_hdr_chksum_err += n_packets;
2925         } else if (unlikely(EFX_QWORD_FIELD(*event,
2926                                             ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
2927                 channel->n_rx_tcp_udp_chksum_err += n_packets;
2928         } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
2929                    rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
2930                 flags |= EFX_RX_PKT_CSUMMED;
2931         }
2932
2933         if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
2934                 flags |= EFX_RX_PKT_TCP;
2935
2936         channel->irq_mod_score += 2 * n_packets;
2937
2938         /* Handle received packet(s) */
2939         for (i = 0; i < n_packets; i++) {
2940                 efx_rx_packet(rx_queue,
2941                               rx_queue->removed_count & rx_queue->ptr_mask,
2942                               rx_queue->scatter_n, rx_queue->scatter_len,
2943                               flags);
2944                 rx_queue->removed_count += rx_queue->scatter_n;
2945         }
2946
2947         rx_queue->scatter_n = 0;
2948         rx_queue->scatter_len = 0;
2949
2950         return n_packets;
2951 }
2952
2953 static int
2954 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
2955 {
2956         struct efx_nic *efx = channel->efx;
2957         struct efx_tx_queue *tx_queue;
2958         unsigned int tx_ev_desc_ptr;
2959         unsigned int tx_ev_q_label;
2960         int tx_descs = 0;
2961
2962         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2963                 return 0;
2964
2965         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
2966                 return 0;
2967
2968         /* Transmit completion */
2969         tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2970         tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
2971         tx_queue = efx_channel_get_tx_queue(channel,
2972                                             tx_ev_q_label % EFX_TXQ_TYPES);
2973         tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
2974                     tx_queue->ptr_mask);
2975         efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2976
2977         return tx_descs;
2978 }
2979
2980 static void
2981 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
2982 {
2983         struct efx_nic *efx = channel->efx;
2984         int subcode;
2985
2986         subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
2987
2988         switch (subcode) {
2989         case ESE_DZ_DRV_TIMER_EV:
2990         case ESE_DZ_DRV_WAKE_UP_EV:
2991                 break;
2992         case ESE_DZ_DRV_START_UP_EV:
2993                 /* event queue init complete. ok. */
2994                 break;
2995         default:
2996                 netif_err(efx, hw, efx->net_dev,
2997                           "channel %d unknown driver event type %d"
2998                           " (data " EFX_QWORD_FMT ")\n",
2999                           channel->channel, subcode,
3000                           EFX_QWORD_VAL(*event));
3001
3002         }
3003 }
3004
3005 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
3006                                                    efx_qword_t *event)
3007 {
3008         struct efx_nic *efx = channel->efx;
3009         u32 subcode;
3010
3011         subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
3012
3013         switch (subcode) {
3014         case EFX_EF10_TEST:
3015                 channel->event_test_cpu = raw_smp_processor_id();
3016                 break;
3017         case EFX_EF10_REFILL:
3018                 /* The queue must be empty, so we won't receive any rx
3019                  * events, so efx_process_channel() won't refill the
3020                  * queue. Refill it here
3021                  */
3022                 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
3023                 break;
3024         default:
3025                 netif_err(efx, hw, efx->net_dev,
3026                           "channel %d unknown driver event type %u"
3027                           " (data " EFX_QWORD_FMT ")\n",
3028                           channel->channel, (unsigned) subcode,
3029                           EFX_QWORD_VAL(*event));
3030         }
3031 }
3032
3033 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3034 {
3035         struct efx_nic *efx = channel->efx;
3036         efx_qword_t event, *p_event;
3037         unsigned int read_ptr;
3038         int ev_code;
3039         int tx_descs = 0;
3040         int spent = 0;
3041
3042         if (quota <= 0)
3043                 return spent;
3044
3045         read_ptr = channel->eventq_read_ptr;
3046
3047         for (;;) {
3048                 p_event = efx_event(channel, read_ptr);
3049                 event = *p_event;
3050
3051                 if (!efx_event_present(&event))
3052                         break;
3053
3054                 EFX_SET_QWORD(*p_event);
3055
3056                 ++read_ptr;
3057
3058                 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3059
3060                 netif_vdbg(efx, drv, efx->net_dev,
3061                            "processing event on %d " EFX_QWORD_FMT "\n",
3062                            channel->channel, EFX_QWORD_VAL(event));
3063
3064                 switch (ev_code) {
3065                 case ESE_DZ_EV_CODE_MCDI_EV:
3066                         efx_mcdi_process_event(channel, &event);
3067                         break;
3068                 case ESE_DZ_EV_CODE_RX_EV:
3069                         spent += efx_ef10_handle_rx_event(channel, &event);
3070                         if (spent >= quota) {
3071                                 /* XXX can we split a merged event to
3072                                  * avoid going over-quota?
3073                                  */
3074                                 spent = quota;
3075                                 goto out;
3076                         }
3077                         break;
3078                 case ESE_DZ_EV_CODE_TX_EV:
3079                         tx_descs += efx_ef10_handle_tx_event(channel, &event);
3080                         if (tx_descs > efx->txq_entries) {
3081                                 spent = quota;
3082                                 goto out;
3083                         } else if (++spent == quota) {
3084                                 goto out;
3085                         }
3086                         break;
3087                 case ESE_DZ_EV_CODE_DRIVER_EV:
3088                         efx_ef10_handle_driver_event(channel, &event);
3089                         if (++spent == quota)
3090                                 goto out;
3091                         break;
3092                 case EFX_EF10_DRVGEN_EV:
3093                         efx_ef10_handle_driver_generated_event(channel, &event);
3094                         break;
3095                 default:
3096                         netif_err(efx, hw, efx->net_dev,
3097                                   "channel %d unknown event type %d"
3098                                   " (data " EFX_QWORD_FMT ")\n",
3099                                   channel->channel, ev_code,
3100                                   EFX_QWORD_VAL(event));
3101                 }
3102         }
3103
3104 out:
3105         channel->eventq_read_ptr = read_ptr;
3106         return spent;
3107 }
3108
3109 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3110 {
3111         struct efx_nic *efx = channel->efx;
3112         efx_dword_t rptr;
3113
3114         if (EFX_EF10_WORKAROUND_35388(efx)) {
3115                 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3116                              (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3117                 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3118                              (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3119
3120                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3121                                      EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3122                                      ERF_DD_EVQ_IND_RPTR,
3123                                      (channel->eventq_read_ptr &
3124                                       channel->eventq_mask) >>
3125                                      ERF_DD_EVQ_IND_RPTR_WIDTH);
3126                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3127                                 channel->channel);
3128                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3129                                      EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3130                                      ERF_DD_EVQ_IND_RPTR,
3131                                      channel->eventq_read_ptr &
3132                                      ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3133                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3134                                 channel->channel);
3135         } else {
3136                 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3137                                      channel->eventq_read_ptr &
3138                                      channel->eventq_mask);
3139                 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3140         }
3141 }
3142
3143 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3144 {
3145         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3146         struct efx_nic *efx = channel->efx;
3147         efx_qword_t event;
3148         int rc;
3149
3150         EFX_POPULATE_QWORD_2(event,
3151                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3152                              ESF_DZ_EV_DATA, EFX_EF10_TEST);
3153
3154         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3155
3156         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3157          * already swapped the data to little-endian order.
3158          */
3159         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3160                sizeof(efx_qword_t));
3161
3162         rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3163                           NULL, 0, NULL);
3164         if (rc != 0)
3165                 goto fail;
3166
3167         return;
3168
3169 fail:
3170         WARN_ON(true);
3171         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3172 }
3173
3174 void efx_ef10_handle_drain_event(struct efx_nic *efx)
3175 {
3176         if (atomic_dec_and_test(&efx->active_queues))
3177                 wake_up(&efx->flush_wq);
3178
3179         WARN_ON(atomic_read(&efx->active_queues) < 0);
3180 }
3181
3182 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3183 {
3184         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3185         struct efx_channel *channel;
3186         struct efx_tx_queue *tx_queue;
3187         struct efx_rx_queue *rx_queue;
3188         int pending;
3189
3190         /* If the MC has just rebooted, the TX/RX queues will have already been
3191          * torn down, but efx->active_queues needs to be set to zero.
3192          */
3193         if (nic_data->must_realloc_vis) {
3194                 atomic_set(&efx->active_queues, 0);
3195                 return 0;
3196         }
3197
3198         /* Do not attempt to write to the NIC during EEH recovery */
3199         if (efx->state != STATE_RECOVERY) {
3200                 efx_for_each_channel(channel, efx) {
3201                         efx_for_each_channel_rx_queue(rx_queue, channel)
3202                                 efx_ef10_rx_fini(rx_queue);
3203                         efx_for_each_channel_tx_queue(tx_queue, channel)
3204                                 efx_ef10_tx_fini(tx_queue);
3205                 }
3206
3207                 wait_event_timeout(efx->flush_wq,
3208                                    atomic_read(&efx->active_queues) == 0,
3209                                    msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3210                 pending = atomic_read(&efx->active_queues);
3211                 if (pending) {
3212                         netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3213                                   pending);
3214                         return -ETIMEDOUT;
3215                 }
3216         }
3217
3218         return 0;
3219 }
3220
3221 static void efx_ef10_prepare_flr(struct efx_nic *efx)
3222 {
3223         atomic_set(&efx->active_queues, 0);
3224 }
3225
3226 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
3227                                   const struct efx_filter_spec *right)
3228 {
3229         if ((left->match_flags ^ right->match_flags) |
3230             ((left->flags ^ right->flags) &
3231              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
3232                 return false;
3233
3234         return memcmp(&left->outer_vid, &right->outer_vid,
3235                       sizeof(struct efx_filter_spec) -
3236                       offsetof(struct efx_filter_spec, outer_vid)) == 0;
3237 }
3238
3239 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
3240 {
3241         BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
3242         return jhash2((const u32 *)&spec->outer_vid,
3243                       (sizeof(struct efx_filter_spec) -
3244                        offsetof(struct efx_filter_spec, outer_vid)) / 4,
3245                       0);
3246         /* XXX should we randomise the initval? */
3247 }
3248
3249 /* Decide whether a filter should be exclusive or else should allow
3250  * delivery to additional recipients.  Currently we decide that
3251  * filters for specific local unicast MAC and IP addresses are
3252  * exclusive.
3253  */
3254 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
3255 {
3256         if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
3257             !is_multicast_ether_addr(spec->loc_mac))
3258                 return true;
3259
3260         if ((spec->match_flags &
3261              (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
3262             (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
3263                 if (spec->ether_type == htons(ETH_P_IP) &&
3264                     !ipv4_is_multicast(spec->loc_host[0]))
3265                         return true;
3266                 if (spec->ether_type == htons(ETH_P_IPV6) &&
3267                     ((const u8 *)spec->loc_host)[0] != 0xff)
3268                         return true;
3269         }
3270
3271         return false;
3272 }
3273
3274 static struct efx_filter_spec *
3275 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
3276                            unsigned int filter_idx)
3277 {
3278         return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
3279                                           ~EFX_EF10_FILTER_FLAGS);
3280 }
3281
3282 static unsigned int
3283 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
3284                            unsigned int filter_idx)
3285 {
3286         return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
3287 }
3288
3289 static void
3290 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
3291                           unsigned int filter_idx,
3292                           const struct efx_filter_spec *spec,
3293                           unsigned int flags)
3294 {
3295         table->entry[filter_idx].spec = (unsigned long)spec | flags;
3296 }
3297
3298 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
3299                                       const struct efx_filter_spec *spec,
3300                                       efx_dword_t *inbuf, u64 handle,
3301                                       bool replacing)
3302 {
3303         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3304         u32 flags = spec->flags;
3305
3306         memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
3307
3308         /* Remove RSS flag if we don't have an RSS context. */
3309         if (flags & EFX_FILTER_FLAG_RX_RSS &&
3310             spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
3311             nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
3312                 flags &= ~EFX_FILTER_FLAG_RX_RSS;
3313
3314         if (replacing) {
3315                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3316                                MC_CMD_FILTER_OP_IN_OP_REPLACE);
3317                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
3318         } else {
3319                 u32 match_fields = 0;
3320
3321                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3322                                efx_ef10_filter_is_exclusive(spec) ?
3323                                MC_CMD_FILTER_OP_IN_OP_INSERT :
3324                                MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
3325
3326                 /* Convert match flags and values.  Unlike almost
3327                  * everything else in MCDI, these fields are in
3328                  * network byte order.
3329                  */
3330                 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
3331                         match_fields |=
3332                                 is_multicast_ether_addr(spec->loc_mac) ?
3333                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
3334                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3335 #define COPY_FIELD(gen_flag, gen_field, mcdi_field)                          \
3336                 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) {     \
3337                         match_fields |=                                      \
3338                                 1 << MC_CMD_FILTER_OP_IN_MATCH_ ##           \
3339                                 mcdi_field ## _LBN;                          \
3340                         BUILD_BUG_ON(                                        \
3341                                 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3342                                 sizeof(spec->gen_field));                    \
3343                         memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3344                                &spec->gen_field, sizeof(spec->gen_field));   \
3345                 }
3346                 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
3347                 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
3348                 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
3349                 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
3350                 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
3351                 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
3352                 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
3353                 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
3354                 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
3355                 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
3356 #undef COPY_FIELD
3357                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
3358                                match_fields);
3359         }
3360
3361         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
3362         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
3363                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3364                        MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
3365                        MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
3366         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
3367         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
3368                        MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
3369         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
3370                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3371                        0 : spec->dmaq_id);
3372         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
3373                        (flags & EFX_FILTER_FLAG_RX_RSS) ?
3374                        MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
3375                        MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
3376         if (flags & EFX_FILTER_FLAG_RX_RSS)
3377                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
3378                                spec->rss_context !=
3379                                EFX_FILTER_RSS_CONTEXT_DEFAULT ?
3380                                spec->rss_context : nic_data->rx_rss_context);
3381 }
3382
3383 static int efx_ef10_filter_push(struct efx_nic *efx,
3384                                 const struct efx_filter_spec *spec,
3385                                 u64 *handle, bool replacing)
3386 {
3387         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3388         MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
3389         int rc;
3390
3391         efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
3392         rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3393                           outbuf, sizeof(outbuf), NULL);
3394         if (rc == 0)
3395                 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3396         if (rc == -ENOSPC)
3397                 rc = -EBUSY; /* to match efx_farch_filter_insert() */
3398         return rc;
3399 }
3400
3401 static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
3402 {
3403         unsigned int match_flags = spec->match_flags;
3404         u32 mcdi_flags = 0;
3405
3406         if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
3407                 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
3408                 mcdi_flags |=
3409                         is_multicast_ether_addr(spec->loc_mac) ?
3410                         (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN) :
3411                         (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN);
3412         }
3413
3414 #define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field) {                 \
3415                 unsigned int old_match_flags = match_flags;             \
3416                 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag;          \
3417                 if (match_flags != old_match_flags)                     \
3418                         mcdi_flags |=                                   \
3419                                 (1 << MC_CMD_FILTER_OP_IN_MATCH_ ##     \
3420                                  mcdi_field ## _LBN);                   \
3421         }
3422         MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP);
3423         MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP);
3424         MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC);
3425         MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT);
3426         MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC);
3427         MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT);
3428         MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE);
3429         MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN);
3430         MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN);
3431         MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO);
3432 #undef MAP_FILTER_TO_MCDI_FLAG
3433
3434         /* Did we map them all? */
3435         WARN_ON_ONCE(match_flags);
3436
3437         return mcdi_flags;
3438 }
3439
3440 static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
3441                                const struct efx_filter_spec *spec)
3442 {
3443         u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
3444         unsigned int match_pri;
3445
3446         for (match_pri = 0;
3447              match_pri < table->rx_match_count;
3448              match_pri++)
3449                 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
3450                         return match_pri;
3451
3452         return -EPROTONOSUPPORT;
3453 }
3454
3455 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
3456                                   struct efx_filter_spec *spec,
3457                                   bool replace_equal)
3458 {
3459         struct efx_ef10_filter_table *table = efx->filter_state;
3460         DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3461         struct efx_filter_spec *saved_spec;
3462         unsigned int match_pri, hash;
3463         unsigned int priv_flags;
3464         bool replacing = false;
3465         int ins_index = -1;
3466         DEFINE_WAIT(wait);
3467         bool is_mc_recip;
3468         s32 rc;
3469
3470         /* For now, only support RX filters */
3471         if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
3472             EFX_FILTER_FLAG_RX)
3473                 return -EINVAL;
3474
3475         rc = efx_ef10_filter_pri(table, spec);
3476         if (rc < 0)
3477                 return rc;
3478         match_pri = rc;
3479
3480         hash = efx_ef10_filter_hash(spec);
3481         is_mc_recip = efx_filter_is_mc_recipient(spec);
3482         if (is_mc_recip)
3483                 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3484
3485         /* Find any existing filters with the same match tuple or
3486          * else a free slot to insert at.  If any of them are busy,
3487          * we have to wait and retry.
3488          */
3489         for (;;) {
3490                 unsigned int depth = 1;
3491                 unsigned int i;
3492
3493                 spin_lock_bh(&efx->filter_lock);
3494
3495                 for (;;) {
3496                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3497                         saved_spec = efx_ef10_filter_entry_spec(table, i);
3498
3499                         if (!saved_spec) {
3500                                 if (ins_index < 0)
3501                                         ins_index = i;
3502                         } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3503                                 if (table->entry[i].spec &
3504                                     EFX_EF10_FILTER_FLAG_BUSY)
3505                                         break;
3506                                 if (spec->priority < saved_spec->priority &&
3507                                     spec->priority != EFX_FILTER_PRI_AUTO) {
3508                                         rc = -EPERM;
3509                                         goto out_unlock;
3510                                 }
3511                                 if (!is_mc_recip) {
3512                                         /* This is the only one */
3513                                         if (spec->priority ==
3514                                             saved_spec->priority &&
3515                                             !replace_equal) {
3516                                                 rc = -EEXIST;
3517                                                 goto out_unlock;
3518                                         }
3519                                         ins_index = i;
3520                                         goto found;
3521                                 } else if (spec->priority >
3522                                            saved_spec->priority ||
3523                                            (spec->priority ==
3524                                             saved_spec->priority &&
3525                                             replace_equal)) {
3526                                         if (ins_index < 0)
3527                                                 ins_index = i;
3528                                         else
3529                                                 __set_bit(depth, mc_rem_map);
3530                                 }
3531                         }
3532
3533                         /* Once we reach the maximum search depth, use
3534                          * the first suitable slot or return -EBUSY if
3535                          * there was none
3536                          */
3537                         if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3538                                 if (ins_index < 0) {
3539                                         rc = -EBUSY;
3540                                         goto out_unlock;
3541                                 }
3542                                 goto found;
3543                         }
3544
3545                         ++depth;
3546                 }
3547
3548                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3549                 spin_unlock_bh(&efx->filter_lock);
3550                 schedule();
3551         }
3552
3553 found:
3554         /* Create a software table entry if necessary, and mark it
3555          * busy.  We might yet fail to insert, but any attempt to
3556          * insert a conflicting filter while we're waiting for the
3557          * firmware must find the busy entry.
3558          */
3559         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3560         if (saved_spec) {
3561                 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3562                     saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
3563                         /* Just make sure it won't be removed */
3564                         if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3565                                 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
3566                         table->entry[ins_index].spec &=
3567                                 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3568                         rc = ins_index;
3569                         goto out_unlock;
3570                 }
3571                 replacing = true;
3572                 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3573         } else {
3574                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3575                 if (!saved_spec) {
3576                         rc = -ENOMEM;
3577                         goto out_unlock;
3578                 }
3579                 *saved_spec = *spec;
3580                 priv_flags = 0;
3581         }
3582         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3583                                   priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3584
3585         /* Mark lower-priority multicast recipients busy prior to removal */
3586         if (is_mc_recip) {
3587                 unsigned int depth, i;
3588
3589                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3590                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3591                         if (test_bit(depth, mc_rem_map))
3592                                 table->entry[i].spec |=
3593                                         EFX_EF10_FILTER_FLAG_BUSY;
3594                 }
3595         }
3596
3597         spin_unlock_bh(&efx->filter_lock);
3598
3599         rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3600                                   replacing);
3601
3602         /* Finalise the software table entry */
3603         spin_lock_bh(&efx->filter_lock);
3604         if (rc == 0) {
3605                 if (replacing) {
3606                         /* Update the fields that may differ */
3607                         if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
3608                                 saved_spec->flags |=
3609                                         EFX_FILTER_FLAG_RX_OVER_AUTO;
3610                         saved_spec->priority = spec->priority;
3611                         saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
3612                         saved_spec->flags |= spec->flags;
3613                         saved_spec->rss_context = spec->rss_context;
3614                         saved_spec->dmaq_id = spec->dmaq_id;
3615                 }
3616         } else if (!replacing) {
3617                 kfree(saved_spec);
3618                 saved_spec = NULL;
3619         }
3620         efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
3621
3622         /* Remove and finalise entries for lower-priority multicast
3623          * recipients
3624          */
3625         if (is_mc_recip) {
3626                 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3627                 unsigned int depth, i;
3628
3629                 memset(inbuf, 0, sizeof(inbuf));
3630
3631                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3632                         if (!test_bit(depth, mc_rem_map))
3633                                 continue;
3634
3635                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3636                         saved_spec = efx_ef10_filter_entry_spec(table, i);
3637                         priv_flags = efx_ef10_filter_entry_flags(table, i);
3638
3639                         if (rc == 0) {
3640                                 spin_unlock_bh(&efx->filter_lock);
3641                                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3642                                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3643                                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3644                                                table->entry[i].handle);
3645                                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3646                                                   inbuf, sizeof(inbuf),
3647                                                   NULL, 0, NULL);
3648                                 spin_lock_bh(&efx->filter_lock);
3649                         }
3650
3651                         if (rc == 0) {
3652                                 kfree(saved_spec);
3653                                 saved_spec = NULL;
3654                                 priv_flags = 0;
3655                         } else {
3656                                 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
3657                         }
3658                         efx_ef10_filter_set_entry(table, i, saved_spec,
3659                                                   priv_flags);
3660                 }
3661         }
3662
3663         /* If successful, return the inserted filter ID */
3664         if (rc == 0)
3665                 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
3666
3667         wake_up_all(&table->waitq);
3668 out_unlock:
3669         spin_unlock_bh(&efx->filter_lock);
3670         finish_wait(&table->waitq, &wait);
3671         return rc;
3672 }
3673
3674 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
3675 {
3676         /* no need to do anything here on EF10 */
3677 }
3678
3679 /* Remove a filter.
3680  * If !by_index, remove by ID
3681  * If by_index, remove by index
3682  * Filter ID may come from userland and must be range-checked.
3683  */
3684 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
3685                                            unsigned int priority_mask,
3686                                            u32 filter_id, bool by_index)
3687 {
3688         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3689         struct efx_ef10_filter_table *table = efx->filter_state;
3690         MCDI_DECLARE_BUF(inbuf,
3691                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3692                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3693         struct efx_filter_spec *spec;
3694         DEFINE_WAIT(wait);
3695         int rc;
3696
3697         /* Find the software table entry and mark it busy.  Don't
3698          * remove it yet; any attempt to update while we're waiting
3699          * for the firmware must find the busy entry.
3700          */
3701         for (;;) {
3702                 spin_lock_bh(&efx->filter_lock);
3703                 if (!(table->entry[filter_idx].spec &
3704                       EFX_EF10_FILTER_FLAG_BUSY))
3705                         break;
3706                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3707                 spin_unlock_bh(&efx->filter_lock);
3708                 schedule();
3709         }
3710
3711         spec = efx_ef10_filter_entry_spec(table, filter_idx);
3712         if (!spec ||
3713             (!by_index &&
3714              efx_ef10_filter_pri(table, spec) !=
3715              filter_id / HUNT_FILTER_TBL_ROWS)) {
3716                 rc = -ENOENT;
3717                 goto out_unlock;
3718         }
3719
3720         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
3721             priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
3722                 /* Just remove flags */
3723                 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
3724                 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3725                 rc = 0;
3726                 goto out_unlock;
3727         }
3728
3729         if (!(priority_mask & (1U << spec->priority))) {
3730                 rc = -ENOENT;
3731                 goto out_unlock;
3732         }
3733
3734         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3735         spin_unlock_bh(&efx->filter_lock);
3736
3737         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
3738                 /* Reset to an automatic filter */
3739
3740                 struct efx_filter_spec new_spec = *spec;
3741
3742                 new_spec.priority = EFX_FILTER_PRI_AUTO;
3743                 new_spec.flags = (EFX_FILTER_FLAG_RX |
3744                                   (efx_rss_enabled(efx) ?
3745                                    EFX_FILTER_FLAG_RX_RSS : 0));
3746                 new_spec.dmaq_id = 0;
3747                 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
3748                 rc = efx_ef10_filter_push(efx, &new_spec,
3749                                           &table->entry[filter_idx].handle,
3750                                           true);
3751
3752                 spin_lock_bh(&efx->filter_lock);
3753                 if (rc == 0)
3754                         *spec = new_spec;
3755         } else {
3756                 /* Really remove the filter */
3757
3758                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3759                                efx_ef10_filter_is_exclusive(spec) ?
3760                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
3761                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3762                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3763                                table->entry[filter_idx].handle);
3764                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3765                                   inbuf, sizeof(inbuf), NULL, 0, NULL);
3766
3767                 spin_lock_bh(&efx->filter_lock);
3768                 if (rc == 0) {
3769                         kfree(spec);
3770                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3771                 }
3772         }
3773
3774         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3775         wake_up_all(&table->waitq);
3776 out_unlock:
3777         spin_unlock_bh(&efx->filter_lock);
3778         finish_wait(&table->waitq, &wait);
3779         return rc;
3780 }
3781
3782 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
3783                                        enum efx_filter_priority priority,
3784                                        u32 filter_id)
3785 {
3786         return efx_ef10_filter_remove_internal(efx, 1U << priority,
3787                                                filter_id, false);
3788 }
3789
3790 static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
3791 {
3792         return filter_id % HUNT_FILTER_TBL_ROWS;
3793 }
3794
3795 static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
3796                                           enum efx_filter_priority priority,
3797                                           u32 filter_id)
3798 {
3799         if (filter_id == EFX_EF10_FILTER_ID_INVALID)
3800                 return;
3801         efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true);
3802 }
3803
3804 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
3805                                     enum efx_filter_priority priority,
3806                                     u32 filter_id, struct efx_filter_spec *spec)
3807 {
3808         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3809         struct efx_ef10_filter_table *table = efx->filter_state;
3810         const struct efx_filter_spec *saved_spec;
3811         int rc;
3812
3813         spin_lock_bh(&efx->filter_lock);
3814         saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
3815         if (saved_spec && saved_spec->priority == priority &&
3816             efx_ef10_filter_pri(table, saved_spec) ==
3817             filter_id / HUNT_FILTER_TBL_ROWS) {
3818                 *spec = *saved_spec;
3819                 rc = 0;
3820         } else {
3821                 rc = -ENOENT;
3822         }
3823         spin_unlock_bh(&efx->filter_lock);
3824         return rc;
3825 }
3826
3827 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
3828                                      enum efx_filter_priority priority)
3829 {
3830         unsigned int priority_mask;
3831         unsigned int i;
3832         int rc;
3833
3834         priority_mask = (((1U << (priority + 1)) - 1) &
3835                          ~(1U << EFX_FILTER_PRI_AUTO));
3836
3837         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3838                 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
3839                                                      i, true);
3840                 if (rc && rc != -ENOENT)
3841                         return rc;
3842         }
3843
3844         return 0;
3845 }
3846
3847 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
3848                                          enum efx_filter_priority priority)
3849 {
3850         struct efx_ef10_filter_table *table = efx->filter_state;
3851         unsigned int filter_idx;
3852         s32 count = 0;
3853
3854         spin_lock_bh(&efx->filter_lock);
3855         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3856                 if (table->entry[filter_idx].spec &&
3857                     efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
3858                     priority)
3859                         ++count;
3860         }
3861         spin_unlock_bh(&efx->filter_lock);
3862         return count;
3863 }
3864
3865 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
3866 {
3867         struct efx_ef10_filter_table *table = efx->filter_state;
3868
3869         return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
3870 }
3871
3872 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
3873                                       enum efx_filter_priority priority,
3874                                       u32 *buf, u32 size)
3875 {
3876         struct efx_ef10_filter_table *table = efx->filter_state;
3877         struct efx_filter_spec *spec;
3878         unsigned int filter_idx;
3879         s32 count = 0;
3880
3881         spin_lock_bh(&efx->filter_lock);
3882         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3883                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3884                 if (spec && spec->priority == priority) {
3885                         if (count == size) {
3886                                 count = -EMSGSIZE;
3887                                 break;
3888                         }
3889                         buf[count++] = (efx_ef10_filter_pri(table, spec) *
3890                                         HUNT_FILTER_TBL_ROWS +
3891                                         filter_idx);
3892                 }
3893         }
3894         spin_unlock_bh(&efx->filter_lock);
3895         return count;
3896 }
3897
3898 #ifdef CONFIG_RFS_ACCEL
3899
3900 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
3901
3902 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
3903                                       struct efx_filter_spec *spec)
3904 {
3905         struct efx_ef10_filter_table *table = efx->filter_state;
3906         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3907         struct efx_filter_spec *saved_spec;
3908         unsigned int hash, i, depth = 1;
3909         bool replacing = false;
3910         int ins_index = -1;
3911         u64 cookie;
3912         s32 rc;
3913
3914         /* Must be an RX filter without RSS and not for a multicast
3915          * destination address (RFS only works for connected sockets).
3916          * These restrictions allow us to pass only a tiny amount of
3917          * data through to the completion function.
3918          */
3919         EFX_WARN_ON_PARANOID(spec->flags !=
3920                              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
3921         EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
3922         EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
3923
3924         hash = efx_ef10_filter_hash(spec);
3925
3926         spin_lock_bh(&efx->filter_lock);
3927
3928         /* Find any existing filter with the same match tuple or else
3929          * a free slot to insert at.  If an existing filter is busy,
3930          * we have to give up.
3931          */
3932         for (;;) {
3933                 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3934                 saved_spec = efx_ef10_filter_entry_spec(table, i);
3935
3936                 if (!saved_spec) {
3937                         if (ins_index < 0)
3938                                 ins_index = i;
3939                 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3940                         if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
3941                                 rc = -EBUSY;
3942                                 goto fail_unlock;
3943                         }
3944                         if (spec->priority < saved_spec->priority) {
3945                                 rc = -EPERM;
3946                                 goto fail_unlock;
3947                         }
3948                         ins_index = i;
3949                         break;
3950                 }
3951
3952                 /* Once we reach the maximum search depth, use the
3953                  * first suitable slot or return -EBUSY if there was
3954                  * none
3955                  */
3956                 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3957                         if (ins_index < 0) {
3958                                 rc = -EBUSY;
3959                                 goto fail_unlock;
3960                         }
3961                         break;
3962                 }
3963
3964                 ++depth;
3965         }
3966
3967         /* Create a software table entry if necessary, and mark it
3968          * busy.  We might yet fail to insert, but any attempt to
3969          * insert a conflicting filter while we're waiting for the
3970          * firmware must find the busy entry.
3971          */
3972         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3973         if (saved_spec) {
3974                 replacing = true;
3975         } else {
3976                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3977                 if (!saved_spec) {
3978                         rc = -ENOMEM;
3979                         goto fail_unlock;
3980                 }
3981                 *saved_spec = *spec;
3982         }
3983         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3984                                   EFX_EF10_FILTER_FLAG_BUSY);
3985
3986         spin_unlock_bh(&efx->filter_lock);
3987
3988         /* Pack up the variables needed on completion */
3989         cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
3990
3991         efx_ef10_filter_push_prep(efx, spec, inbuf,
3992                                   table->entry[ins_index].handle, replacing);
3993         efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3994                            MC_CMD_FILTER_OP_OUT_LEN,
3995                            efx_ef10_filter_rfs_insert_complete, cookie);
3996
3997         return ins_index;
3998
3999 fail_unlock:
4000         spin_unlock_bh(&efx->filter_lock);
4001         return rc;
4002 }
4003
4004 static void
4005 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
4006                                     int rc, efx_dword_t *outbuf,
4007                                     size_t outlen_actual)
4008 {
4009         struct efx_ef10_filter_table *table = efx->filter_state;
4010         unsigned int ins_index, dmaq_id;
4011         struct efx_filter_spec *spec;
4012         bool replacing;
4013
4014         /* Unpack the cookie */
4015         replacing = cookie >> 31;
4016         ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
4017         dmaq_id = cookie & 0xffff;
4018
4019         spin_lock_bh(&efx->filter_lock);
4020         spec = efx_ef10_filter_entry_spec(table, ins_index);
4021         if (rc == 0) {
4022                 table->entry[ins_index].handle =
4023                         MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
4024                 if (replacing)
4025                         spec->dmaq_id = dmaq_id;
4026         } else if (!replacing) {
4027                 kfree(spec);
4028                 spec = NULL;
4029         }
4030         efx_ef10_filter_set_entry(table, ins_index, spec, 0);
4031         spin_unlock_bh(&efx->filter_lock);
4032
4033         wake_up_all(&table->waitq);
4034 }
4035
4036 static void
4037 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4038                                     unsigned long filter_idx,
4039                                     int rc, efx_dword_t *outbuf,
4040                                     size_t outlen_actual);
4041
4042 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
4043                                            unsigned int filter_idx)
4044 {
4045         struct efx_ef10_filter_table *table = efx->filter_state;
4046         struct efx_filter_spec *spec =
4047                 efx_ef10_filter_entry_spec(table, filter_idx);
4048         MCDI_DECLARE_BUF(inbuf,
4049                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4050                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4051
4052         if (!spec ||
4053             (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
4054             spec->priority != EFX_FILTER_PRI_HINT ||
4055             !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
4056                                  flow_id, filter_idx))
4057                 return false;
4058
4059         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4060                        MC_CMD_FILTER_OP_IN_OP_REMOVE);
4061         MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4062                        table->entry[filter_idx].handle);
4063         if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
4064                                efx_ef10_filter_rfs_expire_complete, filter_idx))
4065                 return false;
4066
4067         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4068         return true;
4069 }
4070
4071 static void
4072 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4073                                     unsigned long filter_idx,
4074                                     int rc, efx_dword_t *outbuf,
4075                                     size_t outlen_actual)
4076 {
4077         struct efx_ef10_filter_table *table = efx->filter_state;
4078         struct efx_filter_spec *spec =
4079                 efx_ef10_filter_entry_spec(table, filter_idx);
4080
4081         spin_lock_bh(&efx->filter_lock);
4082         if (rc == 0) {
4083                 kfree(spec);
4084                 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4085         }
4086         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4087         wake_up_all(&table->waitq);
4088         spin_unlock_bh(&efx->filter_lock);
4089 }
4090
4091 #endif /* CONFIG_RFS_ACCEL */
4092
4093 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
4094 {
4095         int match_flags = 0;
4096
4097 #define MAP_FLAG(gen_flag, mcdi_field) {                                \
4098                 u32 old_mcdi_flags = mcdi_flags;                        \
4099                 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ##      \
4100                                 mcdi_field ## _LBN);                    \
4101                 if (mcdi_flags != old_mcdi_flags)                       \
4102                         match_flags |= EFX_FILTER_MATCH_ ## gen_flag;   \
4103         }
4104         MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
4105         MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
4106         MAP_FLAG(REM_HOST, SRC_IP);
4107         MAP_FLAG(LOC_HOST, DST_IP);
4108         MAP_FLAG(REM_MAC, SRC_MAC);
4109         MAP_FLAG(REM_PORT, SRC_PORT);
4110         MAP_FLAG(LOC_MAC, DST_MAC);
4111         MAP_FLAG(LOC_PORT, DST_PORT);
4112         MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
4113         MAP_FLAG(INNER_VID, INNER_VLAN);
4114         MAP_FLAG(OUTER_VID, OUTER_VLAN);
4115         MAP_FLAG(IP_PROTO, IP_PROTO);
4116 #undef MAP_FLAG
4117
4118         /* Did we map them all? */
4119         if (mcdi_flags)
4120                 return -EINVAL;
4121
4122         return match_flags;
4123 }
4124
4125 static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
4126 {
4127         struct efx_ef10_filter_table *table = efx->filter_state;
4128         struct efx_ef10_filter_vlan *vlan, *next_vlan;
4129
4130         /* See comment in efx_ef10_filter_table_remove() */
4131         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4132                 return;
4133
4134         if (!table)
4135                 return;
4136
4137         list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
4138                 efx_ef10_filter_del_vlan_internal(efx, vlan);
4139 }
4140
4141 static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
4142                                             enum efx_filter_match_flags match_flags)
4143 {
4144         unsigned int match_pri;
4145         int mf;
4146
4147         for (match_pri = 0;
4148              match_pri < table->rx_match_count;
4149              match_pri++) {
4150                 mf = efx_ef10_filter_match_flags_from_mcdi(
4151                                 table->rx_match_mcdi_flags[match_pri]);
4152                 if (mf == match_flags)
4153                         return true;
4154         }
4155
4156         return false;
4157 }
4158
4159 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
4160 {
4161         MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4162         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
4163         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4164         struct net_device *net_dev = efx->net_dev;
4165         unsigned int pd_match_pri, pd_match_count;
4166         struct efx_ef10_filter_table *table;
4167         struct efx_ef10_vlan *vlan;
4168         size_t outlen;
4169         int rc;
4170
4171         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4172                 return -EINVAL;
4173
4174         if (efx->filter_state) /* already probed */
4175                 return 0;
4176
4177         table = kzalloc(sizeof(*table), GFP_KERNEL);
4178         if (!table)
4179                 return -ENOMEM;
4180
4181         /* Find out which RX filter types are supported, and their priorities */
4182         MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
4183                        MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4184         rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4185                           inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4186                           &outlen);
4187         if (rc)
4188                 goto fail;
4189         pd_match_count = MCDI_VAR_ARRAY_LEN(
4190                 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
4191         table->rx_match_count = 0;
4192
4193         for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4194                 u32 mcdi_flags =
4195                         MCDI_ARRAY_DWORD(
4196                                 outbuf,
4197                                 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4198                                 pd_match_pri);
4199                 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
4200                 if (rc < 0) {
4201                         netif_dbg(efx, probe, efx->net_dev,
4202                                   "%s: fw flags %#x pri %u not supported in driver\n",
4203                                   __func__, mcdi_flags, pd_match_pri);
4204                 } else {
4205                         netif_dbg(efx, probe, efx->net_dev,
4206                                   "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4207                                   __func__, mcdi_flags, pd_match_pri,
4208                                   rc, table->rx_match_count);
4209                         table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
4210                         table->rx_match_count++;
4211                 }
4212         }
4213
4214         if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
4215             !(efx_ef10_filter_match_supported(table,
4216                 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
4217               efx_ef10_filter_match_supported(table,
4218                 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
4219                 netif_info(efx, probe, net_dev,
4220                            "VLAN filters are not supported in this firmware variant\n");
4221                 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4222                 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4223                 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4224         }
4225
4226         table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
4227         if (!table->entry) {
4228                 rc = -ENOMEM;
4229                 goto fail;
4230         }
4231
4232         table->mc_promisc_last = false;
4233         table->vlan_filter =
4234                 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
4235         INIT_LIST_HEAD(&table->vlan_list);
4236
4237         efx->filter_state = table;
4238         init_waitqueue_head(&table->waitq);
4239
4240         list_for_each_entry(vlan, &nic_data->vlan_list, list) {
4241                 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
4242                 if (rc)
4243                         goto fail_add_vlan;
4244         }
4245
4246         return 0;
4247
4248 fail_add_vlan:
4249         efx_ef10_filter_cleanup_vlans(efx);
4250         efx->filter_state = NULL;
4251 fail:
4252         kfree(table);
4253         return rc;
4254 }
4255
4256 /* Caller must hold efx->filter_sem for read if race against
4257  * efx_ef10_filter_table_remove() is possible
4258  */
4259 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
4260 {
4261         struct efx_ef10_filter_table *table = efx->filter_state;
4262         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4263         struct efx_filter_spec *spec;
4264         unsigned int filter_idx;
4265         bool failed = false;
4266         int rc;
4267
4268         WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4269
4270         if (!nic_data->must_restore_filters)
4271                 return;
4272
4273         if (!table)
4274                 return;
4275
4276         spin_lock_bh(&efx->filter_lock);
4277
4278         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4279                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4280                 if (!spec)
4281                         continue;
4282
4283                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4284                 spin_unlock_bh(&efx->filter_lock);
4285
4286                 rc = efx_ef10_filter_push(efx, spec,
4287                                           &table->entry[filter_idx].handle,
4288                                           false);
4289                 if (rc)
4290                         failed = true;
4291
4292                 spin_lock_bh(&efx->filter_lock);
4293                 if (rc) {
4294                         kfree(spec);
4295                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4296                 } else {
4297                         table->entry[filter_idx].spec &=
4298                                 ~EFX_EF10_FILTER_FLAG_BUSY;
4299                 }
4300         }
4301
4302         spin_unlock_bh(&efx->filter_lock);
4303
4304         if (failed)
4305                 netif_err(efx, hw, efx->net_dev,
4306                           "unable to restore all filters\n");
4307         else
4308                 nic_data->must_restore_filters = false;
4309 }
4310
4311 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
4312 {
4313         struct efx_ef10_filter_table *table = efx->filter_state;
4314         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
4315         struct efx_filter_spec *spec;
4316         unsigned int filter_idx;
4317         int rc;
4318
4319         efx_ef10_filter_cleanup_vlans(efx);
4320         efx->filter_state = NULL;
4321         /* If we were called without locking, then it's not safe to free
4322          * the table as others might be using it.  So we just WARN, leak
4323          * the memory, and potentially get an inconsistent filter table
4324          * state.
4325          * This should never actually happen.
4326          */
4327         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4328                 return;
4329
4330         if (!table)
4331                 return;
4332
4333         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4334                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4335                 if (!spec)
4336                         continue;
4337
4338                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4339                                efx_ef10_filter_is_exclusive(spec) ?
4340                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
4341                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4342                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4343                                table->entry[filter_idx].handle);
4344                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
4345                                         sizeof(inbuf), NULL, 0, NULL);
4346                 if (rc)
4347                         netif_info(efx, drv, efx->net_dev,
4348                                    "%s: filter %04x remove failed\n",
4349                                    __func__, filter_idx);
4350                 kfree(spec);
4351         }
4352
4353         vfree(table->entry);
4354         kfree(table);
4355 }
4356
4357 static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
4358 {
4359         struct efx_ef10_filter_table *table = efx->filter_state;
4360         unsigned int filter_idx;
4361
4362         if (*id != EFX_EF10_FILTER_ID_INVALID) {
4363                 filter_idx = efx_ef10_filter_get_unsafe_id(efx, *id);
4364                 if (!table->entry[filter_idx].spec)
4365                         netif_dbg(efx, drv, efx->net_dev,
4366                                   "marked null spec old %04x:%04x\n", *id,
4367                                   filter_idx);
4368                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
4369                 *id = EFX_EF10_FILTER_ID_INVALID;
4370         }
4371 }
4372
4373 /* Mark old per-VLAN filters that may need to be removed */
4374 static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
4375                                            struct efx_ef10_filter_vlan *vlan)
4376 {
4377         struct efx_ef10_filter_table *table = efx->filter_state;
4378         unsigned int i;
4379
4380         for (i = 0; i < table->dev_uc_count; i++)
4381                 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
4382         for (i = 0; i < table->dev_mc_count; i++)
4383                 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
4384         efx_ef10_filter_mark_one_old(efx, &vlan->ucdef);
4385         efx_ef10_filter_mark_one_old(efx, &vlan->bcast);
4386         efx_ef10_filter_mark_one_old(efx, &vlan->mcdef);
4387 }
4388
4389 /* Mark old filters that may need to be removed.
4390  * Caller must hold efx->filter_sem for read if race against
4391  * efx_ef10_filter_table_remove() is possible
4392  */
4393 static void efx_ef10_filter_mark_old(struct efx_nic *efx)
4394 {
4395         struct efx_ef10_filter_table *table = efx->filter_state;
4396         struct efx_ef10_filter_vlan *vlan;
4397
4398         spin_lock_bh(&efx->filter_lock);
4399         list_for_each_entry(vlan, &table->vlan_list, list)
4400                 _efx_ef10_filter_vlan_mark_old(efx, vlan);
4401         spin_unlock_bh(&efx->filter_lock);
4402 }
4403
4404 static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
4405 {
4406         struct efx_ef10_filter_table *table = efx->filter_state;
4407         struct net_device *net_dev = efx->net_dev;
4408         struct netdev_hw_addr *uc;
4409         unsigned int i;
4410
4411         table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
4412         ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
4413         i = 1;
4414         netdev_for_each_uc_addr(uc, net_dev) {
4415                 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
4416                         table->uc_promisc = true;
4417                         break;
4418                 }
4419                 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
4420                 i++;
4421         }
4422
4423         table->dev_uc_count = i;
4424 }
4425
4426 static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
4427 {
4428         struct efx_ef10_filter_table *table = efx->filter_state;
4429         struct net_device *net_dev = efx->net_dev;
4430         struct netdev_hw_addr *mc;
4431         unsigned int i;
4432
4433         table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
4434
4435         i = 0;
4436         netdev_for_each_mc_addr(mc, net_dev) {
4437                 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
4438                         table->mc_promisc = true;
4439                         break;
4440                 }
4441                 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
4442                 i++;
4443         }
4444
4445         table->dev_mc_count = i;
4446 }
4447
4448 static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
4449                                             struct efx_ef10_filter_vlan *vlan,
4450                                             bool multicast, bool rollback)
4451 {
4452         struct efx_ef10_filter_table *table = efx->filter_state;
4453         struct efx_ef10_dev_addr *addr_list;
4454         enum efx_filter_flags filter_flags;
4455         struct efx_filter_spec spec;
4456         u8 baddr[ETH_ALEN];
4457         unsigned int i, j;
4458         int addr_count;
4459         u16 *ids;
4460         int rc;
4461
4462         if (multicast) {
4463                 addr_list = table->dev_mc_list;
4464                 addr_count = table->dev_mc_count;
4465                 ids = vlan->mc;
4466         } else {
4467                 addr_list = table->dev_uc_list;
4468                 addr_count = table->dev_uc_count;
4469                 ids = vlan->uc;
4470         }
4471
4472         filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4473
4474         /* Insert/renew filters */
4475         for (i = 0; i < addr_count; i++) {
4476                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4477                 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
4478                 rc = efx_ef10_filter_insert(efx, &spec, true);
4479                 if (rc < 0) {
4480                         if (rollback) {
4481                                 netif_info(efx, drv, efx->net_dev,
4482                                            "efx_ef10_filter_insert failed rc=%d\n",
4483                                            rc);
4484                                 /* Fall back to promiscuous */
4485                                 for (j = 0; j < i; j++) {
4486                                         efx_ef10_filter_remove_unsafe(
4487                                                 efx, EFX_FILTER_PRI_AUTO,
4488                                                 ids[j]);
4489                                         ids[j] = EFX_EF10_FILTER_ID_INVALID;
4490                                 }
4491                                 return rc;
4492                         } else {
4493                                 /* mark as not inserted, and carry on */
4494                                 rc = EFX_EF10_FILTER_ID_INVALID;
4495                         }
4496                 }
4497                 ids[i] = efx_ef10_filter_get_unsafe_id(efx, rc);
4498         }
4499
4500         if (multicast && rollback) {
4501                 /* Also need an Ethernet broadcast filter */
4502                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4503                 eth_broadcast_addr(baddr);
4504                 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
4505                 rc = efx_ef10_filter_insert(efx, &spec, true);
4506                 if (rc < 0) {
4507                         netif_warn(efx, drv, efx->net_dev,
4508                                    "Broadcast filter insert failed rc=%d\n", rc);
4509                         /* Fall back to promiscuous */
4510                         for (j = 0; j < i; j++) {
4511                                 efx_ef10_filter_remove_unsafe(
4512                                         efx, EFX_FILTER_PRI_AUTO,
4513                                         ids[j]);
4514                                 ids[j] = EFX_EF10_FILTER_ID_INVALID;
4515                         }
4516                         return rc;
4517                 } else {
4518                         EFX_WARN_ON_PARANOID(vlan->bcast !=
4519                                              EFX_EF10_FILTER_ID_INVALID);
4520                         vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
4521                 }
4522         }
4523
4524         return 0;
4525 }
4526
4527 static int efx_ef10_filter_insert_def(struct efx_nic *efx,
4528                                       struct efx_ef10_filter_vlan *vlan,
4529                                       bool multicast, bool rollback)
4530 {
4531         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4532         enum efx_filter_flags filter_flags;
4533         struct efx_filter_spec spec;
4534         u8 baddr[ETH_ALEN];
4535         int rc;
4536
4537         filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4538
4539         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4540
4541         if (multicast)
4542                 efx_filter_set_mc_def(&spec);
4543         else
4544                 efx_filter_set_uc_def(&spec);
4545
4546         if (vlan->vid != EFX_FILTER_VID_UNSPEC)
4547                 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
4548
4549         rc = efx_ef10_filter_insert(efx, &spec, true);
4550         if (rc < 0) {
4551                 netif_printk(efx, drv, rc == -EPERM ? KERN_DEBUG : KERN_WARNING,
4552                              efx->net_dev,
4553                              "%scast mismatch filter insert failed rc=%d\n",
4554                              multicast ? "Multi" : "Uni", rc);
4555         } else if (multicast) {
4556                 EFX_WARN_ON_PARANOID(vlan->mcdef != EFX_EF10_FILTER_ID_INVALID);
4557                 vlan->mcdef = efx_ef10_filter_get_unsafe_id(efx, rc);
4558                 if (!nic_data->workaround_26807) {
4559                         /* Also need an Ethernet broadcast filter */
4560                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
4561                                            filter_flags, 0);
4562                         eth_broadcast_addr(baddr);
4563                         efx_filter_set_eth_local(&spec, vlan->vid, baddr);
4564                         rc = efx_ef10_filter_insert(efx, &spec, true);
4565                         if (rc < 0) {
4566                                 netif_warn(efx, drv, efx->net_dev,
4567                                            "Broadcast filter insert failed rc=%d\n",
4568                                            rc);
4569                                 if (rollback) {
4570                                         /* Roll back the mc_def filter */
4571                                         efx_ef10_filter_remove_unsafe(
4572                                                         efx, EFX_FILTER_PRI_AUTO,
4573                                                         vlan->mcdef);
4574                                         vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
4575                                         return rc;
4576                                 }
4577                         } else {
4578                                 EFX_WARN_ON_PARANOID(vlan->bcast !=
4579                                                      EFX_EF10_FILTER_ID_INVALID);
4580                                 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
4581                         }
4582                 }
4583                 rc = 0;
4584         } else {
4585                 EFX_WARN_ON_PARANOID(vlan->ucdef != EFX_EF10_FILTER_ID_INVALID);
4586                 vlan->ucdef = rc;
4587                 rc = 0;
4588         }
4589         return rc;
4590 }
4591
4592 /* Remove filters that weren't renewed.  Since nothing else changes the AUTO_OLD
4593  * flag or removes these filters, we don't need to hold the filter_lock while
4594  * scanning for these filters.
4595  */
4596 static void efx_ef10_filter_remove_old(struct efx_nic *efx)
4597 {
4598         struct efx_ef10_filter_table *table = efx->filter_state;
4599         int remove_failed = 0;
4600         int remove_noent = 0;
4601         int rc;
4602         int i;
4603
4604         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4605                 if (ACCESS_ONCE(table->entry[i].spec) &
4606                     EFX_EF10_FILTER_FLAG_AUTO_OLD) {
4607                         rc = efx_ef10_filter_remove_internal(efx,
4608                                         1U << EFX_FILTER_PRI_AUTO, i, true);
4609                         if (rc == -ENOENT)
4610                                 remove_noent++;
4611                         else if (rc)
4612                                 remove_failed++;
4613                 }
4614         }
4615
4616         if (remove_failed)
4617                 netif_info(efx, drv, efx->net_dev,
4618                            "%s: failed to remove %d filters\n",
4619                            __func__, remove_failed);
4620         if (remove_noent)
4621                 netif_info(efx, drv, efx->net_dev,
4622                            "%s: failed to remove %d non-existent filters\n",
4623                            __func__, remove_noent);
4624 }
4625
4626 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
4627 {
4628         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4629         u8 mac_old[ETH_ALEN];
4630         int rc, rc2;
4631
4632         /* Only reconfigure a PF-created vport */
4633         if (is_zero_ether_addr(nic_data->vport_mac))
4634                 return 0;
4635
4636         efx_device_detach_sync(efx);
4637         efx_net_stop(efx->net_dev);
4638         down_write(&efx->filter_sem);
4639         efx_ef10_filter_table_remove(efx);
4640         up_write(&efx->filter_sem);
4641
4642         rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
4643         if (rc)
4644                 goto restore_filters;
4645
4646         ether_addr_copy(mac_old, nic_data->vport_mac);
4647         rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
4648                                     nic_data->vport_mac);
4649         if (rc)
4650                 goto restore_vadaptor;
4651
4652         rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
4653                                     efx->net_dev->dev_addr);
4654         if (!rc) {
4655                 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
4656         } else {
4657                 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
4658                 if (rc2) {
4659                         /* Failed to add original MAC, so clear vport_mac */
4660                         eth_zero_addr(nic_data->vport_mac);
4661                         goto reset_nic;
4662                 }
4663         }
4664
4665 restore_vadaptor:
4666         rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
4667         if (rc2)
4668                 goto reset_nic;
4669 restore_filters:
4670         down_write(&efx->filter_sem);
4671         rc2 = efx_ef10_filter_table_probe(efx);
4672         up_write(&efx->filter_sem);
4673         if (rc2)
4674                 goto reset_nic;
4675
4676         rc2 = efx_net_open(efx->net_dev);
4677         if (rc2)
4678                 goto reset_nic;
4679
4680         netif_device_attach(efx->net_dev);
4681
4682         return rc;
4683
4684 reset_nic:
4685         netif_err(efx, drv, efx->net_dev,
4686                   "Failed to restore when changing MAC address - scheduling reset\n");
4687         efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
4688
4689         return rc ? rc : rc2;
4690 }
4691
4692 /* Caller must hold efx->filter_sem for read if race against
4693  * efx_ef10_filter_table_remove() is possible
4694  */
4695 static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
4696                                               struct efx_ef10_filter_vlan *vlan)
4697 {
4698         struct efx_ef10_filter_table *table = efx->filter_state;
4699         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4700
4701         /* Do not install unspecified VID if VLAN filtering is enabled.
4702          * Do not install all specified VIDs if VLAN filtering is disabled.
4703          */
4704         if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
4705                 return;
4706
4707         /* Insert/renew unicast filters */
4708         if (table->uc_promisc) {
4709                 efx_ef10_filter_insert_def(efx, vlan, false, false);
4710                 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
4711         } else {
4712                 /* If any of the filters failed to insert, fall back to
4713                  * promiscuous mode - add in the uc_def filter.  But keep
4714                  * our individual unicast filters.
4715                  */
4716                 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
4717                         efx_ef10_filter_insert_def(efx, vlan, false, false);
4718         }
4719
4720         /* Insert/renew multicast filters */
4721         /* If changing promiscuous state with cascaded multicast filters, remove
4722          * old filters first, so that packets are dropped rather than duplicated
4723          */
4724         if (nic_data->workaround_26807 &&
4725             table->mc_promisc_last != table->mc_promisc)
4726                 efx_ef10_filter_remove_old(efx);
4727         if (table->mc_promisc) {
4728                 if (nic_data->workaround_26807) {
4729                         /* If we failed to insert promiscuous filters, rollback
4730                          * and fall back to individual multicast filters
4731                          */
4732                         if (efx_ef10_filter_insert_def(efx, vlan, true, true)) {
4733                                 /* Changing promisc state, so remove old filters */
4734                                 efx_ef10_filter_remove_old(efx);
4735                                 efx_ef10_filter_insert_addr_list(efx, vlan,
4736                                                                  true, false);
4737                         }
4738                 } else {
4739                         /* If we failed to insert promiscuous filters, don't
4740                          * rollback.  Regardless, also insert the mc_list
4741                          */
4742                         efx_ef10_filter_insert_def(efx, vlan, true, false);
4743                         efx_ef10_filter_insert_addr_list(efx, vlan, true, false);
4744                 }
4745         } else {
4746                 /* If any filters failed to insert, rollback and fall back to
4747                  * promiscuous mode - mc_def filter and maybe broadcast.  If
4748                  * that fails, roll back again and insert as many of our
4749                  * individual multicast filters as we can.
4750                  */
4751                 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
4752                         /* Changing promisc state, so remove old filters */
4753                         if (nic_data->workaround_26807)
4754                                 efx_ef10_filter_remove_old(efx);
4755                         if (efx_ef10_filter_insert_def(efx, vlan, true, true))
4756                                 efx_ef10_filter_insert_addr_list(efx, vlan,
4757                                                                  true, false);
4758                 }
4759         }
4760 }
4761
4762 /* Caller must hold efx->filter_sem for read if race against
4763  * efx_ef10_filter_table_remove() is possible
4764  */
4765 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
4766 {
4767         struct efx_ef10_filter_table *table = efx->filter_state;
4768         struct net_device *net_dev = efx->net_dev;
4769         struct efx_ef10_filter_vlan *vlan;
4770         bool vlan_filter;
4771
4772         if (!efx_dev_registered(efx))
4773                 return;
4774
4775         if (!table)
4776                 return;
4777
4778         efx_ef10_filter_mark_old(efx);
4779
4780         /* Copy/convert the address lists; add the primary station
4781          * address and broadcast address
4782          */
4783         netif_addr_lock_bh(net_dev);
4784         efx_ef10_filter_uc_addr_list(efx);
4785         efx_ef10_filter_mc_addr_list(efx);
4786         netif_addr_unlock_bh(net_dev);
4787
4788         /* If VLAN filtering changes, all old filters are finally removed.
4789          * Do it in advance to avoid conflicts for unicast untagged and
4790          * VLAN 0 tagged filters.
4791          */
4792         vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
4793         if (table->vlan_filter != vlan_filter) {
4794                 table->vlan_filter = vlan_filter;
4795                 efx_ef10_filter_remove_old(efx);
4796         }
4797
4798         list_for_each_entry(vlan, &table->vlan_list, list)
4799                 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
4800
4801         efx_ef10_filter_remove_old(efx);
4802         table->mc_promisc_last = table->mc_promisc;
4803 }
4804
4805 static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
4806 {
4807         struct efx_ef10_filter_table *table = efx->filter_state;
4808         struct efx_ef10_filter_vlan *vlan;
4809
4810         WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4811
4812         list_for_each_entry(vlan, &table->vlan_list, list) {
4813                 if (vlan->vid == vid)
4814                         return vlan;
4815         }
4816
4817         return NULL;
4818 }
4819
4820 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
4821 {
4822         struct efx_ef10_filter_table *table = efx->filter_state;
4823         struct efx_ef10_filter_vlan *vlan;
4824         unsigned int i;
4825
4826         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4827                 return -EINVAL;
4828
4829         vlan = efx_ef10_filter_find_vlan(efx, vid);
4830         if (WARN_ON(vlan)) {
4831                 netif_err(efx, drv, efx->net_dev,
4832                           "VLAN %u already added\n", vid);
4833                 return -EALREADY;
4834         }
4835
4836         vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
4837         if (!vlan)
4838                 return -ENOMEM;
4839
4840         vlan->vid = vid;
4841
4842         for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
4843                 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
4844         for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
4845                 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
4846         vlan->ucdef = EFX_EF10_FILTER_ID_INVALID;
4847         vlan->bcast = EFX_EF10_FILTER_ID_INVALID;
4848         vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
4849
4850         list_add_tail(&vlan->list, &table->vlan_list);
4851
4852         if (efx_dev_registered(efx))
4853                 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
4854
4855         return 0;
4856 }
4857
4858 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
4859                                               struct efx_ef10_filter_vlan *vlan)
4860 {
4861         unsigned int i;
4862
4863         /* See comment in efx_ef10_filter_table_remove() */
4864         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4865                 return;
4866
4867         list_del(&vlan->list);
4868
4869         for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
4870                 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
4871                                               vlan->uc[i]);
4872         for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
4873                 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
4874                                               vlan->mc[i]);
4875         efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->ucdef);
4876         efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->bcast);
4877         efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->mcdef);
4878
4879         kfree(vlan);
4880 }
4881
4882 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
4883 {
4884         struct efx_ef10_filter_vlan *vlan;
4885
4886         /* See comment in efx_ef10_filter_table_remove() */
4887         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4888                 return;
4889
4890         vlan = efx_ef10_filter_find_vlan(efx, vid);
4891         if (!vlan) {
4892                 netif_err(efx, drv, efx->net_dev,
4893                           "VLAN %u not found in filter state\n", vid);
4894                 return;
4895         }
4896
4897         efx_ef10_filter_del_vlan_internal(efx, vlan);
4898 }
4899
4900 static int efx_ef10_set_mac_address(struct efx_nic *efx)
4901 {
4902         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
4903         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4904         bool was_enabled = efx->port_enabled;
4905         int rc;
4906
4907         efx_device_detach_sync(efx);
4908         efx_net_stop(efx->net_dev);
4909
4910         mutex_lock(&efx->mac_lock);
4911         down_write(&efx->filter_sem);
4912         efx_ef10_filter_table_remove(efx);
4913
4914         ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
4915                         efx->net_dev->dev_addr);
4916         MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
4917                        nic_data->vport_id);
4918         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
4919                                 sizeof(inbuf), NULL, 0, NULL);
4920
4921         efx_ef10_filter_table_probe(efx);
4922         up_write(&efx->filter_sem);
4923         mutex_unlock(&efx->mac_lock);
4924
4925         if (was_enabled)
4926                 efx_net_open(efx->net_dev);
4927         netif_device_attach(efx->net_dev);
4928
4929 #ifdef CONFIG_SFC_SRIOV
4930         if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
4931                 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
4932
4933                 if (rc == -EPERM) {
4934                         struct efx_nic *efx_pf;
4935
4936                         /* Switch to PF and change MAC address on vport */
4937                         efx_pf = pci_get_drvdata(pci_dev_pf);
4938
4939                         rc = efx_ef10_sriov_set_vf_mac(efx_pf,
4940                                                        nic_data->vf_index,
4941                                                        efx->net_dev->dev_addr);
4942                 } else if (!rc) {
4943                         struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
4944                         struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
4945                         unsigned int i;
4946
4947                         /* MAC address successfully changed by VF (with MAC
4948                          * spoofing) so update the parent PF if possible.
4949                          */
4950                         for (i = 0; i < efx_pf->vf_count; ++i) {
4951                                 struct ef10_vf *vf = nic_data->vf + i;
4952
4953                                 if (vf->efx == efx) {
4954                                         ether_addr_copy(vf->mac,
4955                                                         efx->net_dev->dev_addr);
4956                                         return 0;
4957                                 }
4958                         }
4959                 }
4960         } else
4961 #endif
4962         if (rc == -EPERM) {
4963                 netif_err(efx, drv, efx->net_dev,
4964                           "Cannot change MAC address; use sfboot to enable"
4965                           " mac-spoofing on this interface\n");
4966         } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
4967                 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
4968                  * fall-back to the method of changing the MAC address on the
4969                  * vport.  This only applies to PFs because such versions of
4970                  * MCFW do not support VFs.
4971                  */
4972                 rc = efx_ef10_vport_set_mac_address(efx);
4973         } else if (rc) {
4974                 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
4975                                        sizeof(inbuf), NULL, 0, rc);
4976         }
4977
4978         return rc;
4979 }
4980
4981 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
4982 {
4983         efx_ef10_filter_sync_rx_mode(efx);
4984
4985         return efx_mcdi_set_mac(efx);
4986 }
4987
4988 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
4989 {
4990         efx_ef10_filter_sync_rx_mode(efx);
4991
4992         return 0;
4993 }
4994
4995 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
4996 {
4997         MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
4998
4999         MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
5000         return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
5001                             NULL, 0, NULL);
5002 }
5003
5004 /* MC BISTs follow a different poll mechanism to phy BISTs.
5005  * The BIST is done in the poll handler on the MC, and the MCDI command
5006  * will block until the BIST is done.
5007  */
5008 static int efx_ef10_poll_bist(struct efx_nic *efx)
5009 {
5010         int rc;
5011         MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
5012         size_t outlen;
5013         u32 result;
5014
5015         rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
5016                            outbuf, sizeof(outbuf), &outlen);
5017         if (rc != 0)
5018                 return rc;
5019
5020         if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
5021                 return -EIO;
5022
5023         result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
5024         switch (result) {
5025         case MC_CMD_POLL_BIST_PASSED:
5026                 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
5027                 return 0;
5028         case MC_CMD_POLL_BIST_TIMEOUT:
5029                 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
5030                 return -EIO;
5031         case MC_CMD_POLL_BIST_FAILED:
5032                 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
5033                 return -EIO;
5034         default:
5035                 netif_err(efx, hw, efx->net_dev,
5036                           "BIST returned unknown result %u", result);
5037                 return -EIO;
5038         }
5039 }
5040
5041 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
5042 {
5043         int rc;
5044
5045         netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
5046
5047         rc = efx_ef10_start_bist(efx, bist_type);
5048         if (rc != 0)
5049                 return rc;
5050
5051         return efx_ef10_poll_bist(efx);
5052 }
5053
5054 static int
5055 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
5056 {
5057         int rc, rc2;
5058
5059         efx_reset_down(efx, RESET_TYPE_WORLD);
5060
5061         rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
5062                           NULL, 0, NULL, 0, NULL);
5063         if (rc != 0)
5064                 goto out;
5065
5066         tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
5067         tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
5068
5069         rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
5070
5071 out:
5072         if (rc == -EPERM)
5073                 rc = 0;
5074         rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
5075         return rc ? rc : rc2;
5076 }
5077
5078 #ifdef CONFIG_SFC_MTD
5079
5080 struct efx_ef10_nvram_type_info {
5081         u16 type, type_mask;
5082         u8 port;
5083         const char *name;
5084 };
5085
5086 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
5087         { NVRAM_PARTITION_TYPE_MC_FIRMWARE,        0,    0, "sfc_mcfw" },
5088         { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0,    0, "sfc_mcfw_backup" },
5089         { NVRAM_PARTITION_TYPE_EXPANSION_ROM,      0,    0, "sfc_exp_rom" },
5090         { NVRAM_PARTITION_TYPE_STATIC_CONFIG,      0,    0, "sfc_static_cfg" },
5091         { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG,     0,    0, "sfc_dynamic_cfg" },
5092         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0,   0, "sfc_exp_rom_cfg" },
5093         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0,   1, "sfc_exp_rom_cfg" },
5094         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0,   2, "sfc_exp_rom_cfg" },
5095         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0,   3, "sfc_exp_rom_cfg" },
5096         { NVRAM_PARTITION_TYPE_LICENSE,            0,    0, "sfc_license" },
5097         { NVRAM_PARTITION_TYPE_PHY_MIN,            0xff, 0, "sfc_phy_fw" },
5098 };
5099 #define EF10_NVRAM_PARTITION_COUNT      ARRAY_SIZE(efx_ef10_nvram_types)
5100
5101 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
5102                                         struct efx_mcdi_mtd_partition *part,
5103                                         unsigned int type,
5104                                         unsigned long *found)
5105 {
5106         MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
5107         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
5108         const struct efx_ef10_nvram_type_info *info;
5109         size_t size, erase_size, outlen;
5110         int type_idx = 0;
5111         bool protected;
5112         int rc;
5113
5114         for (type_idx = 0; ; type_idx++) {
5115                 if (type_idx == EF10_NVRAM_PARTITION_COUNT)
5116                         return -ENODEV;
5117                 info = efx_ef10_nvram_types + type_idx;
5118                 if ((type & ~info->type_mask) == info->type)
5119                         break;
5120         }
5121         if (info->port != efx_port_num(efx))
5122                 return -ENODEV;
5123
5124         rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
5125         if (rc)
5126                 return rc;
5127         if (protected)
5128                 return -ENODEV; /* hide it */
5129
5130         /* If we've already exposed a partition of this type, hide this
5131          * duplicate.  All operations on MTDs are keyed by the type anyway,
5132          * so we can't act on the duplicate.
5133          */
5134         if (__test_and_set_bit(type_idx, found))
5135                 return -EEXIST;
5136
5137         part->nvram_type = type;
5138
5139         MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
5140         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
5141                           outbuf, sizeof(outbuf), &outlen);
5142         if (rc)
5143                 return rc;
5144         if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
5145                 return -EIO;
5146         if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
5147             (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
5148                 part->fw_subtype = MCDI_DWORD(outbuf,
5149                                               NVRAM_METADATA_OUT_SUBTYPE);
5150
5151         part->common.dev_type_name = "EF10 NVRAM manager";
5152         part->common.type_name = info->name;
5153
5154         part->common.mtd.type = MTD_NORFLASH;
5155         part->common.mtd.flags = MTD_CAP_NORFLASH;
5156         part->common.mtd.size = size;
5157         part->common.mtd.erasesize = erase_size;
5158
5159         return 0;
5160 }
5161
5162 static int efx_ef10_mtd_probe(struct efx_nic *efx)
5163 {
5164         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
5165         DECLARE_BITMAP(found, EF10_NVRAM_PARTITION_COUNT) = { 0 };
5166         struct efx_mcdi_mtd_partition *parts;
5167         size_t outlen, n_parts_total, i, n_parts;
5168         unsigned int type;
5169         int rc;
5170
5171         ASSERT_RTNL();
5172
5173         BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
5174         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
5175                           outbuf, sizeof(outbuf), &outlen);
5176         if (rc)
5177                 return rc;
5178         if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
5179                 return -EIO;
5180
5181         n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
5182         if (n_parts_total >
5183             MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
5184                 return -EIO;
5185
5186         parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
5187         if (!parts)
5188                 return -ENOMEM;
5189
5190         n_parts = 0;
5191         for (i = 0; i < n_parts_total; i++) {
5192                 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
5193                                         i);
5194                 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type,
5195                                                   found);
5196                 if (rc == -EEXIST || rc == -ENODEV)
5197                         continue;
5198                 if (rc)
5199                         goto fail;
5200                 n_parts++;
5201         }
5202
5203         if (!n_parts) {
5204                 kfree(parts);
5205                 return 0;
5206         }
5207
5208         rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
5209 fail:
5210         if (rc)
5211                 kfree(parts);
5212         return rc;
5213 }
5214
5215 #endif /* CONFIG_SFC_MTD */
5216
5217 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
5218 {
5219         _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
5220 }
5221
5222 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
5223                                             u32 host_time) {}
5224
5225 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
5226                                            bool temp)
5227 {
5228         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
5229         int rc;
5230
5231         if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
5232             channel->sync_events_state == SYNC_EVENTS_VALID ||
5233             (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
5234                 return 0;
5235         channel->sync_events_state = SYNC_EVENTS_REQUESTED;
5236
5237         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
5238         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5239         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
5240                        channel->channel);
5241
5242         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5243                           inbuf, sizeof(inbuf), NULL, 0, NULL);
5244
5245         if (rc != 0)
5246                 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5247                                                     SYNC_EVENTS_DISABLED;
5248
5249         return rc;
5250 }
5251
5252 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
5253                                             bool temp)
5254 {
5255         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
5256         int rc;
5257
5258         if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
5259             (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
5260                 return 0;
5261         if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
5262                 channel->sync_events_state = SYNC_EVENTS_DISABLED;
5263                 return 0;
5264         }
5265         channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5266                                             SYNC_EVENTS_DISABLED;
5267
5268         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
5269         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5270         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
5271                        MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
5272         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
5273                        channel->channel);
5274
5275         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5276                           inbuf, sizeof(inbuf), NULL, 0, NULL);
5277
5278         return rc;
5279 }
5280
5281 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
5282                                            bool temp)
5283 {
5284         int (*set)(struct efx_channel *channel, bool temp);
5285         struct efx_channel *channel;
5286
5287         set = en ?
5288               efx_ef10_rx_enable_timestamping :
5289               efx_ef10_rx_disable_timestamping;
5290
5291         efx_for_each_channel(channel, efx) {
5292                 int rc = set(channel, temp);
5293                 if (en && rc != 0) {
5294                         efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
5295                         return rc;
5296                 }
5297         }
5298
5299         return 0;
5300 }
5301
5302 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
5303                                          struct hwtstamp_config *init)
5304 {
5305         return -EOPNOTSUPP;
5306 }
5307
5308 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
5309                                       struct hwtstamp_config *init)
5310 {
5311         int rc;
5312
5313         switch (init->rx_filter) {
5314         case HWTSTAMP_FILTER_NONE:
5315                 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
5316                 /* if TX timestamping is still requested then leave PTP on */
5317                 return efx_ptp_change_mode(efx,
5318                                            init->tx_type != HWTSTAMP_TX_OFF, 0);
5319         case HWTSTAMP_FILTER_ALL:
5320         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5321         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
5322         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5323         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5324         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5325         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5326         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5327         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5328         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5329         case HWTSTAMP_FILTER_PTP_V2_EVENT:
5330         case HWTSTAMP_FILTER_PTP_V2_SYNC:
5331         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5332                 init->rx_filter = HWTSTAMP_FILTER_ALL;
5333                 rc = efx_ptp_change_mode(efx, true, 0);
5334                 if (!rc)
5335                         rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
5336                 if (rc)
5337                         efx_ptp_change_mode(efx, false, 0);
5338                 return rc;
5339         default:
5340                 return -ERANGE;
5341         }
5342 }
5343
5344 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5345 {
5346         if (proto != htons(ETH_P_8021Q))
5347                 return -EINVAL;
5348
5349         return efx_ef10_add_vlan(efx, vid);
5350 }
5351
5352 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5353 {
5354         if (proto != htons(ETH_P_8021Q))
5355                 return -EINVAL;
5356
5357         return efx_ef10_del_vlan(efx, vid);
5358 }
5359
5360 #define EF10_OFFLOAD_FEATURES           \
5361         (NETIF_F_IP_CSUM |              \
5362          NETIF_F_HW_VLAN_CTAG_FILTER |  \
5363          NETIF_F_IPV6_CSUM |            \
5364          NETIF_F_RXHASH |               \
5365          NETIF_F_NTUPLE)
5366
5367 const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
5368         .is_vf = true,
5369         .mem_bar = EFX_MEM_VF_BAR,
5370         .mem_map_size = efx_ef10_mem_map_size,
5371         .probe = efx_ef10_probe_vf,
5372         .remove = efx_ef10_remove,
5373         .dimension_resources = efx_ef10_dimension_resources,
5374         .init = efx_ef10_init_nic,
5375         .fini = efx_port_dummy_op_void,
5376         .map_reset_reason = efx_ef10_map_reset_reason,
5377         .map_reset_flags = efx_ef10_map_reset_flags,
5378         .reset = efx_ef10_reset,
5379         .probe_port = efx_mcdi_port_probe,
5380         .remove_port = efx_mcdi_port_remove,
5381         .fini_dmaq = efx_ef10_fini_dmaq,
5382         .prepare_flr = efx_ef10_prepare_flr,
5383         .finish_flr = efx_port_dummy_op_void,
5384         .describe_stats = efx_ef10_describe_stats,
5385         .update_stats = efx_ef10_update_stats_vf,
5386         .start_stats = efx_port_dummy_op_void,
5387         .pull_stats = efx_port_dummy_op_void,
5388         .stop_stats = efx_port_dummy_op_void,
5389         .set_id_led = efx_mcdi_set_id_led,
5390         .push_irq_moderation = efx_ef10_push_irq_moderation,
5391         .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
5392         .check_mac_fault = efx_mcdi_mac_check_fault,
5393         .reconfigure_port = efx_mcdi_port_reconfigure,
5394         .get_wol = efx_ef10_get_wol_vf,
5395         .set_wol = efx_ef10_set_wol_vf,
5396         .resume_wol = efx_port_dummy_op_void,
5397         .mcdi_request = efx_ef10_mcdi_request,
5398         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5399         .mcdi_read_response = efx_ef10_mcdi_read_response,
5400         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
5401         .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
5402         .irq_enable_master = efx_port_dummy_op_void,
5403         .irq_test_generate = efx_ef10_irq_test_generate,
5404         .irq_disable_non_ev = efx_port_dummy_op_void,
5405         .irq_handle_msi = efx_ef10_msi_interrupt,
5406         .irq_handle_legacy = efx_ef10_legacy_interrupt,
5407         .tx_probe = efx_ef10_tx_probe,
5408         .tx_init = efx_ef10_tx_init,
5409         .tx_remove = efx_ef10_tx_remove,
5410         .tx_write = efx_ef10_tx_write,
5411         .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
5412         .rx_probe = efx_ef10_rx_probe,
5413         .rx_init = efx_ef10_rx_init,
5414         .rx_remove = efx_ef10_rx_remove,
5415         .rx_write = efx_ef10_rx_write,
5416         .rx_defer_refill = efx_ef10_rx_defer_refill,
5417         .ev_probe = efx_ef10_ev_probe,
5418         .ev_init = efx_ef10_ev_init,
5419         .ev_fini = efx_ef10_ev_fini,
5420         .ev_remove = efx_ef10_ev_remove,
5421         .ev_process = efx_ef10_ev_process,
5422         .ev_read_ack = efx_ef10_ev_read_ack,
5423         .ev_test_generate = efx_ef10_ev_test_generate,
5424         .filter_table_probe = efx_ef10_filter_table_probe,
5425         .filter_table_restore = efx_ef10_filter_table_restore,
5426         .filter_table_remove = efx_ef10_filter_table_remove,
5427         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
5428         .filter_insert = efx_ef10_filter_insert,
5429         .filter_remove_safe = efx_ef10_filter_remove_safe,
5430         .filter_get_safe = efx_ef10_filter_get_safe,
5431         .filter_clear_rx = efx_ef10_filter_clear_rx,
5432         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
5433         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
5434         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
5435 #ifdef CONFIG_RFS_ACCEL
5436         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
5437         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
5438 #endif
5439 #ifdef CONFIG_SFC_MTD
5440         .mtd_probe = efx_port_dummy_op_int,
5441 #endif
5442         .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
5443         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
5444         .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
5445         .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
5446 #ifdef CONFIG_SFC_SRIOV
5447         .vswitching_probe = efx_ef10_vswitching_probe_vf,
5448         .vswitching_restore = efx_ef10_vswitching_restore_vf,
5449         .vswitching_remove = efx_ef10_vswitching_remove_vf,
5450         .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id,
5451 #endif
5452         .get_mac_address = efx_ef10_get_mac_address_vf,
5453         .set_mac_address = efx_ef10_set_mac_address,
5454
5455         .revision = EFX_REV_HUNT_A0,
5456         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
5457         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
5458         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
5459         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
5460         .can_rx_scatter = true,
5461         .always_rx_scatter = true,
5462         .max_interrupt_mode = EFX_INT_MODE_MSIX,
5463         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
5464         .offload_features = EF10_OFFLOAD_FEATURES,
5465         .mcdi_max_ver = 2,
5466         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
5467         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
5468                             1 << HWTSTAMP_FILTER_ALL,
5469 };
5470
5471 const struct efx_nic_type efx_hunt_a0_nic_type = {
5472         .is_vf = false,
5473         .mem_bar = EFX_MEM_BAR,
5474         .mem_map_size = efx_ef10_mem_map_size,
5475         .probe = efx_ef10_probe_pf,
5476         .remove = efx_ef10_remove,
5477         .dimension_resources = efx_ef10_dimension_resources,
5478         .init = efx_ef10_init_nic,
5479         .fini = efx_port_dummy_op_void,
5480         .map_reset_reason = efx_ef10_map_reset_reason,
5481         .map_reset_flags = efx_ef10_map_reset_flags,
5482         .reset = efx_ef10_reset,
5483         .probe_port = efx_mcdi_port_probe,
5484         .remove_port = efx_mcdi_port_remove,
5485         .fini_dmaq = efx_ef10_fini_dmaq,
5486         .prepare_flr = efx_ef10_prepare_flr,
5487         .finish_flr = efx_port_dummy_op_void,
5488         .describe_stats = efx_ef10_describe_stats,
5489         .update_stats = efx_ef10_update_stats_pf,
5490         .start_stats = efx_mcdi_mac_start_stats,
5491         .pull_stats = efx_mcdi_mac_pull_stats,
5492         .stop_stats = efx_mcdi_mac_stop_stats,
5493         .set_id_led = efx_mcdi_set_id_led,
5494         .push_irq_moderation = efx_ef10_push_irq_moderation,
5495         .reconfigure_mac = efx_ef10_mac_reconfigure,
5496         .check_mac_fault = efx_mcdi_mac_check_fault,
5497         .reconfigure_port = efx_mcdi_port_reconfigure,
5498         .get_wol = efx_ef10_get_wol,
5499         .set_wol = efx_ef10_set_wol,
5500         .resume_wol = efx_port_dummy_op_void,
5501         .test_chip = efx_ef10_test_chip,
5502         .test_nvram = efx_mcdi_nvram_test_all,
5503         .mcdi_request = efx_ef10_mcdi_request,
5504         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5505         .mcdi_read_response = efx_ef10_mcdi_read_response,
5506         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
5507         .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
5508         .irq_enable_master = efx_port_dummy_op_void,
5509         .irq_test_generate = efx_ef10_irq_test_generate,
5510         .irq_disable_non_ev = efx_port_dummy_op_void,
5511         .irq_handle_msi = efx_ef10_msi_interrupt,
5512         .irq_handle_legacy = efx_ef10_legacy_interrupt,
5513         .tx_probe = efx_ef10_tx_probe,
5514         .tx_init = efx_ef10_tx_init,
5515         .tx_remove = efx_ef10_tx_remove,
5516         .tx_write = efx_ef10_tx_write,
5517         .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
5518         .rx_probe = efx_ef10_rx_probe,
5519         .rx_init = efx_ef10_rx_init,
5520         .rx_remove = efx_ef10_rx_remove,
5521         .rx_write = efx_ef10_rx_write,
5522         .rx_defer_refill = efx_ef10_rx_defer_refill,
5523         .ev_probe = efx_ef10_ev_probe,
5524         .ev_init = efx_ef10_ev_init,
5525         .ev_fini = efx_ef10_ev_fini,
5526         .ev_remove = efx_ef10_ev_remove,
5527         .ev_process = efx_ef10_ev_process,
5528         .ev_read_ack = efx_ef10_ev_read_ack,
5529         .ev_test_generate = efx_ef10_ev_test_generate,
5530         .filter_table_probe = efx_ef10_filter_table_probe,
5531         .filter_table_restore = efx_ef10_filter_table_restore,
5532         .filter_table_remove = efx_ef10_filter_table_remove,
5533         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
5534         .filter_insert = efx_ef10_filter_insert,
5535         .filter_remove_safe = efx_ef10_filter_remove_safe,
5536         .filter_get_safe = efx_ef10_filter_get_safe,
5537         .filter_clear_rx = efx_ef10_filter_clear_rx,
5538         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
5539         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
5540         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
5541 #ifdef CONFIG_RFS_ACCEL
5542         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
5543         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
5544 #endif
5545 #ifdef CONFIG_SFC_MTD
5546         .mtd_probe = efx_ef10_mtd_probe,
5547         .mtd_rename = efx_mcdi_mtd_rename,
5548         .mtd_read = efx_mcdi_mtd_read,
5549         .mtd_erase = efx_mcdi_mtd_erase,
5550         .mtd_write = efx_mcdi_mtd_write,
5551         .mtd_sync = efx_mcdi_mtd_sync,
5552 #endif
5553         .ptp_write_host_time = efx_ef10_ptp_write_host_time,
5554         .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
5555         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
5556         .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
5557         .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
5558 #ifdef CONFIG_SFC_SRIOV
5559         .sriov_configure = efx_ef10_sriov_configure,
5560         .sriov_init = efx_ef10_sriov_init,
5561         .sriov_fini = efx_ef10_sriov_fini,
5562         .sriov_wanted = efx_ef10_sriov_wanted,
5563         .sriov_reset = efx_ef10_sriov_reset,
5564         .sriov_flr = efx_ef10_sriov_flr,
5565         .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
5566         .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
5567         .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
5568         .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
5569         .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
5570         .vswitching_probe = efx_ef10_vswitching_probe_pf,
5571         .vswitching_restore = efx_ef10_vswitching_restore_pf,
5572         .vswitching_remove = efx_ef10_vswitching_remove_pf,
5573 #endif
5574         .get_mac_address = efx_ef10_get_mac_address_pf,
5575         .set_mac_address = efx_ef10_set_mac_address,
5576
5577         .revision = EFX_REV_HUNT_A0,
5578         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
5579         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
5580         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
5581         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
5582         .can_rx_scatter = true,
5583         .always_rx_scatter = true,
5584         .max_interrupt_mode = EFX_INT_MODE_MSIX,
5585         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
5586         .offload_features = EF10_OFFLOAD_FEATURES,
5587         .mcdi_max_ver = 2,
5588         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
5589         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
5590                             1 << HWTSTAMP_FILTER_ALL,
5591 };