drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c

   1 /* 10G controller driver for Samsung SoCs
   2  *
   3  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * Author: Siva Reddy Kallam <siva.kallam@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14
  15 #include <linux/clk.h>
  16 #include <linux/crc32.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/if.h>
  21 #include <linux/if_ether.h>
  22 #include <linux/if_vlan.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/ip.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mii.h>
  28 #include <linux/module.h>
  29 #include <linux/net_tstamp.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/phy.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/prefetch.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/slab.h>
  36 #include <linux/tcp.h>
  37 #include <linux/sxgbe_platform.h>
  38
  39 #include "sxgbe_common.h"
  40 #include "sxgbe_desc.h"
  41 #include "sxgbe_dma.h"
  42 #include "sxgbe_mtl.h"
  43 #include "sxgbe_reg.h"
  44
  45 #define SXGBE_ALIGN(x)  L1_CACHE_ALIGN(x)
  46 #define JUMBO_LEN       9000
  47
  48 /* Module parameters */
  49 #define TX_TIMEO        5000
  50 #define DMA_TX_SIZE     512
  51 #define DMA_RX_SIZE     1024
  52 #define TC_DEFAULT      64
  53 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
  54 /* The default timer value as per the sxgbe specification 1 sec(1000 ms) */
  55 #define SXGBE_DEFAULT_LPI_TIMER 1000
  56
  57 static int debug = -1;
  58 static int eee_timer = SXGBE_DEFAULT_LPI_TIMER;
  59
  60 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
  61
  62 module_param(debug, int, S_IRUGO | S_IWUSR);
  63 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  64                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
  65                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
  66
  67 static irqreturn_t sxgbe_common_interrupt(int irq, void *dev_id);
  68 static irqreturn_t sxgbe_tx_interrupt(int irq, void *dev_id);
  69 static irqreturn_t sxgbe_rx_interrupt(int irq, void *dev_id);
  70
  71 #define SXGBE_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
  72
  73 #define SXGBE_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x))
  74
  75 /**
  76  * sxgbe_verify_args - verify the driver parameters.
  77  * Description: it verifies if some wrong parameter is passed to the driver.
  78  * Note that wrong parameters are replaced with the default values.
  79  */
  80 static void sxgbe_verify_args(void)
  81 {
  82         if (unlikely(eee_timer < 0))
  83                 eee_timer = SXGBE_DEFAULT_LPI_TIMER;
  84 }
  85
  86 static void sxgbe_enable_eee_mode(const struct sxgbe_priv_data *priv)
  87 {
  88         /* Check and enter in LPI mode */
  89         if (!priv->tx_path_in_lpi_mode)
  90                 priv->hw->mac->set_eee_mode(priv->ioaddr);
  91 }
  92
  93 void sxgbe_disable_eee_mode(struct sxgbe_priv_data * const priv)
  94 {
  95         /* Exit and disable EEE in case of we are are in LPI state. */
  96         priv->hw->mac->reset_eee_mode(priv->ioaddr);
  97         del_timer_sync(&priv->eee_ctrl_timer);
  98         priv->tx_path_in_lpi_mode = false;
  99 }
 100
 101 /**
 102  * sxgbe_eee_ctrl_timer
 103  * @arg : data hook
 104  * Description:
 105  *  If there is no data transfer and if we are not in LPI state,
 106  *  then MAC Transmitter can be moved to LPI state.
 107  */
 108 static void sxgbe_eee_ctrl_timer(unsigned long arg)
 109 {
 110         struct sxgbe_priv_data *priv = (struct sxgbe_priv_data *)arg;
 111
 112         sxgbe_enable_eee_mode(priv);
 113         mod_timer(&priv->eee_ctrl_timer, SXGBE_LPI_TIMER(eee_timer));
 114 }
 115
 116 /**
 117  * sxgbe_eee_init
 118  * @priv: private device pointer
 119  * Description:
 120  *  If the EEE support has been enabled while configuring the driver,
 121  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
 122  *  phy can also manage EEE, so enable the LPI state and start the timer
 123  *  to verify if the tx path can enter in LPI state.
 124  */
 125 bool sxgbe_eee_init(struct sxgbe_priv_data * const priv)
 126 {
 127         struct net_device *ndev = priv->dev;
 128         bool ret = false;
 129
 130         /* MAC core supports the EEE feature. */
 131         if (priv->hw_cap.eee) {
 132                 /* Check if the PHY supports EEE */
 133                 if (phy_init_eee(ndev->phydev, 1))
 134                         return false;
 135
 136                 priv->eee_active = 1;
 137                 setup_timer(&priv->eee_ctrl_timer, sxgbe_eee_ctrl_timer,
 138                             (unsigned long)priv);
 139                 priv->eee_ctrl_timer.expires = SXGBE_LPI_TIMER(eee_timer);
 140                 add_timer(&priv->eee_ctrl_timer);
 141
 142                 priv->hw->mac->set_eee_timer(priv->ioaddr,
 143                                              SXGBE_DEFAULT_LPI_TIMER,
 144                                              priv->tx_lpi_timer);
 145
 146                 pr_info("Energy-Efficient Ethernet initialized\n");
 147
 148                 ret = true;
 149         }
 150
 151         return ret;
 152 }
 153
 154 static void sxgbe_eee_adjust(const struct sxgbe_priv_data *priv)
 155 {
 156         struct net_device *ndev = priv->dev;
 157
 158         /* When the EEE has been already initialised we have to
 159          * modify the PLS bit in the LPI ctrl & status reg according
 160          * to the PHY link status. For this reason.
 161          */
 162         if (priv->eee_enabled)
 163                 priv->hw->mac->set_eee_pls(priv->ioaddr, ndev->phydev->link);
 164 }
 165
 166 /**
 167  * sxgbe_clk_csr_set - dynamically set the MDC clock
 168  * @priv: driver private structure
 169  * Description: this is to dynamically set the MDC clock according to the csr
 170  * clock input.
 171  */
 172 static void sxgbe_clk_csr_set(struct sxgbe_priv_data *priv)
 173 {
 174         u32 clk_rate = clk_get_rate(priv->sxgbe_clk);
 175
 176         /* assign the proper divider, this will be used during
 177          * mdio communication
 178          */
 179         if (clk_rate < SXGBE_CSR_F_150M)
 180                 priv->clk_csr = SXGBE_CSR_100_150M;
 181         else if (clk_rate <= SXGBE_CSR_F_250M)
 182                 priv->clk_csr = SXGBE_CSR_150_250M;
 183         else if (clk_rate <= SXGBE_CSR_F_300M)
 184                 priv->clk_csr = SXGBE_CSR_250_300M;
 185         else if (clk_rate <= SXGBE_CSR_F_350M)
 186                 priv->clk_csr = SXGBE_CSR_300_350M;
 187         else if (clk_rate <= SXGBE_CSR_F_400M)
 188                 priv->clk_csr = SXGBE_CSR_350_400M;
 189         else if (clk_rate <= SXGBE_CSR_F_500M)
 190                 priv->clk_csr = SXGBE_CSR_400_500M;
 191 }
 192
 193 /* minimum number of free TX descriptors required to wake up TX process */
 194 #define SXGBE_TX_THRESH(x)      (x->dma_tx_size/4)
 195
 196 static inline u32 sxgbe_tx_avail(struct sxgbe_tx_queue *queue, int tx_qsize)
 197 {
 198         return queue->dirty_tx + tx_qsize - queue->cur_tx - 1;
 199 }
 200
 201 /**
 202  * sxgbe_adjust_link
 203  * @dev: net device structure
 204  * Description: it adjusts the link parameters.
 205  */
 206 static void sxgbe_adjust_link(struct net_device *dev)
 207 {
 208         struct sxgbe_priv_data *priv = netdev_priv(dev);
 209         struct phy_device *phydev = dev->phydev;
 210         u8 new_state = 0;
 211         u8 speed = 0xff;
 212
 213         if (!phydev)
 214                 return;
 215
 216         /* SXGBE is not supporting auto-negotiation and
 217          * half duplex mode. so, not handling duplex change
 218          * in this function. only handling speed and link status
 219          */
 220         if (phydev->link) {
 221                 if (phydev->speed != priv->speed) {
 222                         new_state = 1;
 223                         switch (phydev->speed) {
 224                         case SPEED_10000:
 225                                 speed = SXGBE_SPEED_10G;
 226                                 break;
 227                         case SPEED_2500:
 228                                 speed = SXGBE_SPEED_2_5G;
 229                                 break;
 230                         case SPEED_1000:
 231                                 speed = SXGBE_SPEED_1G;
 232                                 break;
 233                         default:
 234                                 netif_err(priv, link, dev,
 235                                           "Speed (%d) not supported\n",
 236                                           phydev->speed);
 237                         }
 238
 239                         priv->speed = phydev->speed;
 240                         priv->hw->mac->set_speed(priv->ioaddr, speed);
 241                 }
 242
 243                 if (!priv->oldlink) {
 244                         new_state = 1;
 245                         priv->oldlink = 1;
 246                 }
 247         } else if (priv->oldlink) {
 248                 new_state = 1;
 249                 priv->oldlink = 0;
 250                 priv->speed = SPEED_UNKNOWN;
 251         }
 252
 253         if (new_state & netif_msg_link(priv))
 254                 phy_print_status(phydev);
 255
 256         /* Alter the MAC settings for EEE */
 257         sxgbe_eee_adjust(priv);
 258 }
 259
 260 /**
 261  * sxgbe_init_phy - PHY initialization
 262  * @dev: net device structure
 263  * Description: it initializes the driver's PHY state, and attaches the PHY
 264  * to the mac driver.
 265  *  Return value:
 266  *  0 on success
 267  */
 268 static int sxgbe_init_phy(struct net_device *ndev)
 269 {
 270         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 271         char bus_id[MII_BUS_ID_SIZE];
 272         struct phy_device *phydev;
 273         struct sxgbe_priv_data *priv = netdev_priv(ndev);
 274         int phy_iface = priv->plat->interface;
 275
 276         /* assign default link status */
 277         priv->oldlink = 0;
 278         priv->speed = SPEED_UNKNOWN;
 279         priv->oldduplex = DUPLEX_UNKNOWN;
 280
 281         if (priv->plat->phy_bus_name)
 282                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 283                          priv->plat->phy_bus_name, priv->plat->bus_id);
 284         else
 285                 snprintf(bus_id, MII_BUS_ID_SIZE, "sxgbe-%x",
 286                          priv->plat->bus_id);
 287
 288         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 289                  priv->plat->phy_addr);
 290         netdev_dbg(ndev, "%s: trying to attach to %s\n", __func__, phy_id_fmt);
 291
 292         phydev = phy_connect(ndev, phy_id_fmt, &sxgbe_adjust_link, phy_iface);
 293
 294         if (IS_ERR(phydev)) {
 295                 netdev_err(ndev, "Could not attach to PHY\n");
 296                 return PTR_ERR(phydev);
 297         }
 298
 299         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 300         if ((phy_iface == PHY_INTERFACE_MODE_MII) ||
 301             (phy_iface == PHY_INTERFACE_MODE_RMII))
 302                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 303                                          SUPPORTED_1000baseT_Full);
 304         if (phydev->phy_id == 0) {
 305                 phy_disconnect(phydev);
 306                 return -ENODEV;
 307         }
 308
 309         netdev_dbg(ndev, "%s: attached to PHY (UID 0x%x) Link = %d\n",
 310                    __func__, phydev->phy_id, phydev->link);
 311
 312         return 0;
 313 }
 314
 315 /**
 316  * sxgbe_clear_descriptors: clear descriptors
 317  * @priv: driver private structure
 318  * Description: this function is called to clear the tx and rx descriptors
 319  * in case of both basic and extended descriptors are used.
 320  */
 321 static void sxgbe_clear_descriptors(struct sxgbe_priv_data *priv)
 322 {
 323         int i, j;
 324         unsigned int txsize = priv->dma_tx_size;
 325         unsigned int rxsize = priv->dma_rx_size;
 326
 327         /* Clear the Rx/Tx descriptors */
 328         for (j = 0; j < SXGBE_RX_QUEUES; j++) {
 329                 for (i = 0; i < rxsize; i++)
 330                         priv->hw->desc->init_rx_desc(&priv->rxq[j]->dma_rx[i],
 331                                                      priv->use_riwt, priv->mode,
 332                                                      (i == rxsize - 1));
 333         }
 334
 335         for (j = 0; j < SXGBE_TX_QUEUES; j++) {
 336                 for (i = 0; i < txsize; i++)
 337                         priv->hw->desc->init_tx_desc(&priv->txq[j]->dma_tx[i]);
 338         }
 339 }
 340
 341 static int sxgbe_init_rx_buffers(struct net_device *dev,
 342                                  struct sxgbe_rx_norm_desc *p, int i,
 343                                  unsigned int dma_buf_sz,
 344                                  struct sxgbe_rx_queue *rx_ring)
 345 {
 346         struct sxgbe_priv_data *priv = netdev_priv(dev);
 347         struct sk_buff *skb;
 348
 349         skb = __netdev_alloc_skb_ip_align(dev, dma_buf_sz, GFP_KERNEL);
 350         if (!skb)
 351                 return -ENOMEM;
 352
 353         rx_ring->rx_skbuff[i] = skb;
 354         rx_ring->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 355                                                    dma_buf_sz, DMA_FROM_DEVICE);
 356
 357         if (dma_mapping_error(priv->device, rx_ring->rx_skbuff_dma[i])) {
 358                 netdev_err(dev, "%s: DMA mapping error\n", __func__);
 359                 dev_kfree_skb_any(skb);
 360                 return -EINVAL;
 361         }
 362
 363         p->rdes23.rx_rd_des23.buf2_addr = rx_ring->rx_skbuff_dma[i];
 364
 365         return 0;
 366 }
 367
 368 /**
 369  * sxgbe_free_rx_buffers - free what sxgbe_init_rx_buffers() allocated
 370  * @dev: net device structure
 371  * @rx_ring: ring to be freed
 372  * @rx_rsize: ring size
 373  * Description:  this function initializes the DMA RX descriptor
 374  */
 375 static void sxgbe_free_rx_buffers(struct net_device *dev,
 376                                   struct sxgbe_rx_norm_desc *p, int i,
 377                                   unsigned int dma_buf_sz,
 378                                   struct sxgbe_rx_queue *rx_ring)
 379 {
 380         struct sxgbe_priv_data *priv = netdev_priv(dev);
 381
 382         kfree_skb(rx_ring->rx_skbuff[i]);
 383         dma_unmap_single(priv->device, rx_ring->rx_skbuff_dma[i],
 384                          dma_buf_sz, DMA_FROM_DEVICE);
 385 }
 386
 387 /**
 388  * init_tx_ring - init the TX descriptor ring
 389  * @dev: net device structure
 390  * @tx_ring: ring to be intialised
 391  * @tx_rsize: ring size
 392  * Description:  this function initializes the DMA TX descriptor
 393  */
 394 static int init_tx_ring(struct device *dev, u8 queue_no,
 395                         struct sxgbe_tx_queue *tx_ring, int tx_rsize)
 396 {
 397         /* TX ring is not allcoated */
 398         if (!tx_ring) {
 399                 dev_err(dev, "No memory for TX queue of SXGBE\n");
 400                 return -ENOMEM;
 401         }
 402
 403         /* allocate memory for TX descriptors */
 404         tx_ring->dma_tx = dma_zalloc_coherent(dev,
 405                                               tx_rsize * sizeof(struct sxgbe_tx_norm_desc),
 406                                               &tx_ring->dma_tx_phy, GFP_KERNEL);
 407         if (!tx_ring->dma_tx)
 408                 return -ENOMEM;
 409
 410         /* allocate memory for TX skbuff array */
 411         tx_ring->tx_skbuff_dma = devm_kcalloc(dev, tx_rsize,
 412                                               sizeof(dma_addr_t), GFP_KERNEL);
 413         if (!tx_ring->tx_skbuff_dma)
 414                 goto dmamem_err;
 415
 416         tx_ring->tx_skbuff = devm_kcalloc(dev, tx_rsize,
 417                                           sizeof(struct sk_buff *), GFP_KERNEL);
 418
 419         if (!tx_ring->tx_skbuff)
 420                 goto dmamem_err;
 421
 422         /* assign queue number */
 423         tx_ring->queue_no = queue_no;
 424
 425         /* initialise counters */
 426         tx_ring->dirty_tx = 0;
 427         tx_ring->cur_tx = 0;
 428
 429         /* initialise TX queue lock */
 430         spin_lock_init(&tx_ring->tx_lock);
 431
 432         return 0;
 433
 434 dmamem_err:
 435         dma_free_coherent(dev, tx_rsize * sizeof(struct sxgbe_tx_norm_desc),
 436                           tx_ring->dma_tx, tx_ring->dma_tx_phy);
 437         return -ENOMEM;
 438 }
 439
 440 /**
 441  * free_rx_ring - free the RX descriptor ring
 442  * @dev: net device structure
 443  * @rx_ring: ring to be intialised
 444  * @rx_rsize: ring size
 445  * Description:  this function initializes the DMA RX descriptor
 446  */
 447 static void free_rx_ring(struct device *dev, struct sxgbe_rx_queue *rx_ring,
 448                          int rx_rsize)
 449 {
 450         dma_free_coherent(dev, rx_rsize * sizeof(struct sxgbe_rx_norm_desc),
 451                           rx_ring->dma_rx, rx_ring->dma_rx_phy);
 452         kfree(rx_ring->rx_skbuff_dma);
 453         kfree(rx_ring->rx_skbuff);
 454 }
 455
 456 /**
 457  * init_rx_ring - init the RX descriptor ring
 458  * @dev: net device structure
 459  * @rx_ring: ring to be intialised
 460  * @rx_rsize: ring size
 461  * Description:  this function initializes the DMA RX descriptor
 462  */
 463 static int init_rx_ring(struct net_device *dev, u8 queue_no,
 464                         struct sxgbe_rx_queue *rx_ring, int rx_rsize)
 465 {
 466         struct sxgbe_priv_data *priv = netdev_priv(dev);
 467         int desc_index;
 468         unsigned int bfsize = 0;
 469         unsigned int ret = 0;
 470
 471         /* Set the max buffer size according to the MTU. */
 472         bfsize = ALIGN(dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN, 8);
 473
 474         netif_dbg(priv, probe, dev, "%s: bfsize %d\n", __func__, bfsize);
 475
 476         /* RX ring is not allcoated */
 477         if (rx_ring == NULL) {
 478                 netdev_err(dev, "No memory for RX queue\n");
 479                 return -ENOMEM;
 480         }
 481
 482         /* assign queue number */
 483         rx_ring->queue_no = queue_no;
 484
 485         /* allocate memory for RX descriptors */
 486         rx_ring->dma_rx = dma_zalloc_coherent(priv->device,
 487                                               rx_rsize * sizeof(struct sxgbe_rx_norm_desc),
 488                                               &rx_ring->dma_rx_phy, GFP_KERNEL);
 489
 490         if (rx_ring->dma_rx == NULL)
 491                 return -ENOMEM;
 492
 493         /* allocate memory for RX skbuff array */
 494         rx_ring->rx_skbuff_dma = kmalloc_array(rx_rsize,
 495                                                sizeof(dma_addr_t), GFP_KERNEL);
 496         if (!rx_ring->rx_skbuff_dma) {
 497                 ret = -ENOMEM;
 498                 goto err_free_dma_rx;
 499         }
 500
 501         rx_ring->rx_skbuff = kmalloc_array(rx_rsize,
 502                                            sizeof(struct sk_buff *), GFP_KERNEL);
 503         if (!rx_ring->rx_skbuff) {
 504                 ret = -ENOMEM;
 505                 goto err_free_skbuff_dma;
 506         }
 507
 508         /* initialise the buffers */
 509         for (desc_index = 0; desc_index < rx_rsize; desc_index++) {
 510                 struct sxgbe_rx_norm_desc *p;
 511                 p = rx_ring->dma_rx + desc_index;
 512                 ret = sxgbe_init_rx_buffers(dev, p, desc_index,
 513                                             bfsize, rx_ring);
 514                 if (ret)
 515                         goto err_free_rx_buffers;
 516         }
 517
 518         /* initialise counters */
 519         rx_ring->cur_rx = 0;
 520         rx_ring->dirty_rx = (unsigned int)(desc_index - rx_rsize);
 521         priv->dma_buf_sz = bfsize;
 522
 523         return 0;
 524
 525 err_free_rx_buffers:
 526         while (--desc_index >= 0) {
 527                 struct sxgbe_rx_norm_desc *p;
 528
 529                 p = rx_ring->dma_rx + desc_index;
 530                 sxgbe_free_rx_buffers(dev, p, desc_index, bfsize, rx_ring);
 531         }
 532         kfree(rx_ring->rx_skbuff);
 533 err_free_skbuff_dma:
 534         kfree(rx_ring->rx_skbuff_dma);
 535 err_free_dma_rx:
 536         dma_free_coherent(priv->device,
 537                           rx_rsize * sizeof(struct sxgbe_rx_norm_desc),
 538                           rx_ring->dma_rx, rx_ring->dma_rx_phy);
 539
 540         return ret;
 541 }
 542 /**
 543  * free_tx_ring - free the TX descriptor ring
 544  * @dev: net device structure
 545  * @tx_ring: ring to be intialised
 546  * @tx_rsize: ring size
 547  * Description:  this function initializes the DMA TX descriptor
 548  */
 549 static void free_tx_ring(struct device *dev, struct sxgbe_tx_queue *tx_ring,
 550                          int tx_rsize)
 551 {
 552         dma_free_coherent(dev, tx_rsize * sizeof(struct sxgbe_tx_norm_desc),
 553                           tx_ring->dma_tx, tx_ring->dma_tx_phy);
 554 }
 555
 556 /**
 557  * init_dma_desc_rings - init the RX/TX descriptor rings
 558  * @dev: net device structure
 559  * Description:  this function initializes the DMA RX/TX descriptors
 560  * and allocates the socket buffers. It suppors the chained and ring
 561  * modes.
 562  */
 563 static int init_dma_desc_rings(struct net_device *netd)
 564 {
 565         int queue_num, ret;
 566         struct sxgbe_priv_data *priv = netdev_priv(netd);
 567         int tx_rsize = priv->dma_tx_size;
 568         int rx_rsize = priv->dma_rx_size;
 569
 570         /* Allocate memory for queue structures and TX descs */
 571         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
 572                 ret = init_tx_ring(priv->device, queue_num,
 573                                    priv->txq[queue_num], tx_rsize);
 574                 if (ret) {
 575                         dev_err(&netd->dev, "TX DMA ring allocation failed!\n");
 576                         goto txalloc_err;
 577                 }
 578
 579                 /* save private pointer in each ring this
 580                  * pointer is needed during cleaing TX queue
 581                  */
 582                 priv->txq[queue_num]->priv_ptr = priv;
 583         }
 584
 585         /* Allocate memory for queue structures and RX descs */
 586         SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
 587                 ret = init_rx_ring(netd, queue_num,
 588                                    priv->rxq[queue_num], rx_rsize);
 589                 if (ret) {
 590                         netdev_err(netd, "RX DMA ring allocation failed!!\n");
 591                         goto rxalloc_err;
 592                 }
 593
 594                 /* save private pointer in each ring this
 595                  * pointer is needed during cleaing TX queue
 596                  */
 597                 priv->rxq[queue_num]->priv_ptr = priv;
 598         }
 599
 600         sxgbe_clear_descriptors(priv);
 601
 602         return 0;
 603
 604 txalloc_err:
 605         while (queue_num--)
 606                 free_tx_ring(priv->device, priv->txq[queue_num], tx_rsize);
 607         return ret;
 608
 609 rxalloc_err:
 610         while (queue_num--)
 611                 free_rx_ring(priv->device, priv->rxq[queue_num], rx_rsize);
 612         return ret;
 613 }
 614
 615 static void tx_free_ring_skbufs(struct sxgbe_tx_queue *txqueue)
 616 {
 617         int dma_desc;
 618         struct sxgbe_priv_data *priv = txqueue->priv_ptr;
 619         int tx_rsize = priv->dma_tx_size;
 620
 621         for (dma_desc = 0; dma_desc < tx_rsize; dma_desc++) {
 622                 struct sxgbe_tx_norm_desc *tdesc = txqueue->dma_tx + dma_desc;
 623
 624                 if (txqueue->tx_skbuff_dma[dma_desc])
 625                         dma_unmap_single(priv->device,
 626                                          txqueue->tx_skbuff_dma[dma_desc],
 627                                          priv->hw->desc->get_tx_len(tdesc),
 628                                          DMA_TO_DEVICE);
 629
 630                 dev_kfree_skb_any(txqueue->tx_skbuff[dma_desc]);
 631                 txqueue->tx_skbuff[dma_desc] = NULL;
 632                 txqueue->tx_skbuff_dma[dma_desc] = 0;
 633         }
 634 }
 635
 636
 637 static void dma_free_tx_skbufs(struct sxgbe_priv_data *priv)
 638 {
 639         int queue_num;
 640
 641         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
 642                 struct sxgbe_tx_queue *tqueue = priv->txq[queue_num];
 643                 tx_free_ring_skbufs(tqueue);
 644         }
 645 }
 646
 647 static void free_dma_desc_resources(struct sxgbe_priv_data *priv)
 648 {
 649         int queue_num;
 650         int tx_rsize = priv->dma_tx_size;
 651         int rx_rsize = priv->dma_rx_size;
 652
 653         /* Release the DMA TX buffers */
 654         dma_free_tx_skbufs(priv);
 655
 656         /* Release the TX ring memory also */
 657         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
 658                 free_tx_ring(priv->device, priv->txq[queue_num], tx_rsize);
 659         }
 660
 661         /* Release the RX ring memory also */
 662         SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
 663                 free_rx_ring(priv->device, priv->rxq[queue_num], rx_rsize);
 664         }
 665 }
 666
 667 static int txring_mem_alloc(struct sxgbe_priv_data *priv)
 668 {
 669         int queue_num;
 670
 671         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
 672                 priv->txq[queue_num] = devm_kmalloc(priv->device,
 673                                                     sizeof(struct sxgbe_tx_queue), GFP_KERNEL);
 674                 if (!priv->txq[queue_num])
 675                         return -ENOMEM;
 676         }
 677
 678         return 0;
 679 }
 680
 681 static int rxring_mem_alloc(struct sxgbe_priv_data *priv)
 682 {
 683         int queue_num;
 684
 685         SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
 686                 priv->rxq[queue_num] = devm_kmalloc(priv->device,
 687                                                     sizeof(struct sxgbe_rx_queue), GFP_KERNEL);
 688                 if (!priv->rxq[queue_num])
 689                         return -ENOMEM;
 690         }
 691
 692         return 0;
 693 }
 694
 695 /**
 696  *  sxgbe_mtl_operation_mode - HW MTL operation mode
 697  *  @priv: driver private structure
 698  *  Description: it sets the MTL operation mode: tx/rx MTL thresholds
 699  *  or Store-And-Forward capability.
 700  */
 701 static void sxgbe_mtl_operation_mode(struct sxgbe_priv_data *priv)
 702 {
 703         int queue_num;
 704
 705         /* TX/RX threshold control */
 706         if (likely(priv->plat->force_sf_dma_mode)) {
 707                 /* set TC mode for TX QUEUES */
 708                 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.tx_mtl_queues, queue_num)
 709                         priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr, queue_num,
 710                                                        SXGBE_MTL_SFMODE);
 711                 priv->tx_tc = SXGBE_MTL_SFMODE;
 712
 713                 /* set TC mode for RX QUEUES */
 714                 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.rx_mtl_queues, queue_num)
 715                         priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr, queue_num,
 716                                                        SXGBE_MTL_SFMODE);
 717                 priv->rx_tc = SXGBE_MTL_SFMODE;
 718         } else if (unlikely(priv->plat->force_thresh_dma_mode)) {
 719                 /* set TC mode for TX QUEUES */
 720                 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.tx_mtl_queues, queue_num)
 721                         priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr, queue_num,
 722                                                        priv->tx_tc);
 723                 /* set TC mode for RX QUEUES */
 724                 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.rx_mtl_queues, queue_num)
 725                         priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr, queue_num,
 726                                                        priv->rx_tc);
 727         } else {
 728                 pr_err("ERROR: %s: Invalid TX threshold mode\n", __func__);
 729         }
 730 }
 731
 732 /**
 733  * sxgbe_tx_queue_clean:
 734  * @priv: driver private structure
 735  * Description: it reclaims resources after transmission completes.
 736  */
 737 static void sxgbe_tx_queue_clean(struct sxgbe_tx_queue *tqueue)
 738 {
 739         struct sxgbe_priv_data *priv = tqueue->priv_ptr;
 740         unsigned int tx_rsize = priv->dma_tx_size;
 741         struct netdev_queue *dev_txq;
 742         u8 queue_no = tqueue->queue_no;
 743
 744         dev_txq = netdev_get_tx_queue(priv->dev, queue_no);
 745
 746         spin_lock(&tqueue->tx_lock);
 747
 748         priv->xstats.tx_clean++;
 749         while (tqueue->dirty_tx != tqueue->cur_tx) {
 750                 unsigned int entry = tqueue->dirty_tx % tx_rsize;
 751                 struct sk_buff *skb = tqueue->tx_skbuff[entry];
 752                 struct sxgbe_tx_norm_desc *p;
 753
 754                 p = tqueue->dma_tx + entry;
 755
 756                 /* Check if the descriptor is owned by the DMA. */
 757                 if (priv->hw->desc->get_tx_owner(p))
 758                         break;
 759
 760                 if (netif_msg_tx_done(priv))
 761                         pr_debug("%s: curr %d, dirty %d\n",
 762                                  __func__, tqueue->cur_tx, tqueue->dirty_tx);
 763
 764                 if (likely(tqueue->tx_skbuff_dma[entry])) {
 765                         dma_unmap_single(priv->device,
 766                                          tqueue->tx_skbuff_dma[entry],
 767                                          priv->hw->desc->get_tx_len(p),
 768                                          DMA_TO_DEVICE);
 769                         tqueue->tx_skbuff_dma[entry] = 0;
 770                 }
 771
 772                 if (likely(skb)) {
 773                         dev_kfree_skb(skb);
 774                         tqueue->tx_skbuff[entry] = NULL;
 775                 }
 776
 777                 priv->hw->desc->release_tx_desc(p);
 778
 779                 tqueue->dirty_tx++;
 780         }
 781
 782         /* wake up queue */
 783         if (unlikely(netif_tx_queue_stopped(dev_txq) &&
 784                      sxgbe_tx_avail(tqueue, tx_rsize) > SXGBE_TX_THRESH(priv))) {
 785                 netif_tx_lock(priv->dev);
 786                 if (netif_tx_queue_stopped(dev_txq) &&
 787                     sxgbe_tx_avail(tqueue, tx_rsize) > SXGBE_TX_THRESH(priv)) {
 788                         if (netif_msg_tx_done(priv))
 789                                 pr_debug("%s: restart transmit\n", __func__);
 790                         netif_tx_wake_queue(dev_txq);
 791                 }
 792                 netif_tx_unlock(priv->dev);
 793         }
 794
 795         spin_unlock(&tqueue->tx_lock);
 796 }
 797
 798 /**
 799  * sxgbe_tx_clean:
 800  * @priv: driver private structure
 801  * Description: it reclaims resources after transmission completes.
 802  */
 803 static void sxgbe_tx_all_clean(struct sxgbe_priv_data * const priv)
 804 {
 805         u8 queue_num;
 806
 807         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
 808                 struct sxgbe_tx_queue *tqueue = priv->txq[queue_num];
 809
 810                 sxgbe_tx_queue_clean(tqueue);
 811         }
 812
 813         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
 814                 sxgbe_enable_eee_mode(priv);
 815                 mod_timer(&priv->eee_ctrl_timer, SXGBE_LPI_TIMER(eee_timer));
 816         }
 817 }
 818
 819 /**
 820  * sxgbe_restart_tx_queue: irq tx error mng function
 821  * @priv: driver private structure
 822  * Description: it cleans the descriptors and restarts the transmission
 823  * in case of errors.
 824  */
 825 static void sxgbe_restart_tx_queue(struct sxgbe_priv_data *priv, int queue_num)
 826 {
 827         struct sxgbe_tx_queue *tx_ring = priv->txq[queue_num];
 828         struct netdev_queue *dev_txq = netdev_get_tx_queue(priv->dev,
 829                                                            queue_num);
 830
 831         /* stop the queue */
 832         netif_tx_stop_queue(dev_txq);
 833
 834         /* stop the tx dma */
 835         priv->hw->dma->stop_tx_queue(priv->ioaddr, queue_num);
 836
 837         /* free the skbuffs of the ring */
 838         tx_free_ring_skbufs(tx_ring);
 839
 840         /* initialise counters */
 841         tx_ring->cur_tx = 0;
 842         tx_ring->dirty_tx = 0;
 843
 844         /* start the tx dma */
 845         priv->hw->dma->start_tx_queue(priv->ioaddr, queue_num);
 846
 847         priv->dev->stats.tx_errors++;
 848
 849         /* wakeup the queue */
 850         netif_tx_wake_queue(dev_txq);
 851 }
 852
 853 /**
 854  * sxgbe_reset_all_tx_queues: irq tx error mng function
 855  * @priv: driver private structure
 856  * Description: it cleans all the descriptors and
 857  * restarts the transmission on all queues in case of errors.
 858  */
 859 static void sxgbe_reset_all_tx_queues(struct sxgbe_priv_data *priv)
 860 {
 861         int queue_num;
 862
 863         /* On TX timeout of net device, resetting of all queues
 864          * may not be proper way, revisit this later if needed
 865          */
 866         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num)
 867                 sxgbe_restart_tx_queue(priv, queue_num);
 868 }
 869
 870 /**
 871  * sxgbe_get_hw_features: get XMAC capabilities from the HW cap. register.
 872  * @priv: driver private structure
 873  * Description:
 874  *  new GMAC chip generations have a new register to indicate the
 875  *  presence of the optional feature/functions.
 876  *  This can be also used to override the value passed through the
 877  *  platform and necessary for old MAC10/100 and GMAC chips.
 878  */
 879 static int sxgbe_get_hw_features(struct sxgbe_priv_data * const priv)
 880 {
 881         int rval = 0;
 882         struct sxgbe_hw_features *features = &priv->hw_cap;
 883
 884         /* Read First Capability Register CAP[0] */
 885         rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 0);
 886         if (rval) {
 887                 features->pmt_remote_wake_up =
 888                         SXGBE_HW_FEAT_PMT_TEMOTE_WOP(rval);
 889                 features->pmt_magic_frame = SXGBE_HW_FEAT_PMT_MAGIC_PKT(rval);
 890                 features->atime_stamp = SXGBE_HW_FEAT_IEEE1500_2008(rval);
 891                 features->tx_csum_offload =
 892                         SXGBE_HW_FEAT_TX_CSUM_OFFLOAD(rval);
 893                 features->rx_csum_offload =
 894                         SXGBE_HW_FEAT_RX_CSUM_OFFLOAD(rval);
 895                 features->multi_macaddr = SXGBE_HW_FEAT_MACADDR_COUNT(rval);
 896                 features->tstamp_srcselect = SXGBE_HW_FEAT_TSTMAP_SRC(rval);
 897                 features->sa_vlan_insert = SXGBE_HW_FEAT_SRCADDR_VLAN(rval);
 898                 features->eee = SXGBE_HW_FEAT_EEE(rval);
 899         }
 900
 901         /* Read First Capability Register CAP[1] */
 902         rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 1);
 903         if (rval) {
 904                 features->rxfifo_size = SXGBE_HW_FEAT_RX_FIFO_SIZE(rval);
 905                 features->txfifo_size = SXGBE_HW_FEAT_TX_FIFO_SIZE(rval);
 906                 features->atstmap_hword = SXGBE_HW_FEAT_TX_FIFO_SIZE(rval);
 907                 features->dcb_enable = SXGBE_HW_FEAT_DCB(rval);
 908                 features->splithead_enable = SXGBE_HW_FEAT_SPLIT_HDR(rval);
 909                 features->tcpseg_offload = SXGBE_HW_FEAT_TSO(rval);
 910                 features->debug_mem = SXGBE_HW_FEAT_DEBUG_MEM_IFACE(rval);
 911                 features->rss_enable = SXGBE_HW_FEAT_RSS(rval);
 912                 features->hash_tsize = SXGBE_HW_FEAT_HASH_TABLE_SIZE(rval);
 913                 features->l3l4_filer_size = SXGBE_HW_FEAT_L3L4_FILTER_NUM(rval);
 914         }
 915
 916         /* Read First Capability Register CAP[2] */
 917         rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 2);
 918         if (rval) {
 919                 features->rx_mtl_queues = SXGBE_HW_FEAT_RX_MTL_QUEUES(rval);
 920                 features->tx_mtl_queues = SXGBE_HW_FEAT_TX_MTL_QUEUES(rval);
 921                 features->rx_dma_channels = SXGBE_HW_FEAT_RX_DMA_CHANNELS(rval);
 922                 features->tx_dma_channels = SXGBE_HW_FEAT_TX_DMA_CHANNELS(rval);
 923                 features->pps_output_count = SXGBE_HW_FEAT_PPS_OUTPUTS(rval);
 924                 features->aux_input_count = SXGBE_HW_FEAT_AUX_SNAPSHOTS(rval);
 925         }
 926
 927         return rval;
 928 }
 929
 930 /**
 931  * sxgbe_check_ether_addr: check if the MAC addr is valid
 932  * @priv: driver private structure
 933  * Description:
 934  * it is to verify if the MAC address is valid, in case of failures it
 935  * generates a random MAC address
 936  */
 937 static void sxgbe_check_ether_addr(struct sxgbe_priv_data *priv)
 938 {
 939         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
 940                 priv->hw->mac->get_umac_addr((void __iomem *)
 941                                              priv->ioaddr,
 942                                              priv->dev->dev_addr, 0);
 943                 if (!is_valid_ether_addr(priv->dev->dev_addr))
 944                         eth_hw_addr_random(priv->dev);
 945         }
 946         dev_info(priv->device, "device MAC address %pM\n",
 947                  priv->dev->dev_addr);
 948 }
 949
 950 /**
 951  * sxgbe_init_dma_engine: DMA init.
 952  * @priv: driver private structure
 953  * Description:
 954  * It inits the DMA invoking the specific SXGBE callback.
 955  * Some DMA parameters can be passed from the platform;
 956  * in case of these are not passed a default is kept for the MAC or GMAC.
 957  */
 958 static int sxgbe_init_dma_engine(struct sxgbe_priv_data *priv)
 959 {
 960         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_map = 0;
 961         int queue_num;
 962
 963         if (priv->plat->dma_cfg) {
 964                 pbl = priv->plat->dma_cfg->pbl;
 965                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
 966                 burst_map = priv->plat->dma_cfg->burst_map;
 967         }
 968
 969         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num)
 970                 priv->hw->dma->cha_init(priv->ioaddr, queue_num,
 971                                         fixed_burst, pbl,
 972                                         (priv->txq[queue_num])->dma_tx_phy,
 973                                         (priv->rxq[queue_num])->dma_rx_phy,
 974                                         priv->dma_tx_size, priv->dma_rx_size);
 975
 976         return priv->hw->dma->init(priv->ioaddr, fixed_burst, burst_map);
 977 }
 978
 979 /**
 980  * sxgbe_init_mtl_engine: MTL init.
 981  * @priv: driver private structure
 982  * Description:
 983  * It inits the MTL invoking the specific SXGBE callback.
 984  */
 985 static void sxgbe_init_mtl_engine(struct sxgbe_priv_data *priv)
 986 {
 987         int queue_num;
 988
 989         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
 990                 priv->hw->mtl->mtl_set_txfifosize(priv->ioaddr, queue_num,
 991                                                   priv->hw_cap.tx_mtl_qsize);
 992                 priv->hw->mtl->mtl_enable_txqueue(priv->ioaddr, queue_num);
 993         }
 994 }
 995
 996 /**
 997  * sxgbe_disable_mtl_engine: MTL disable.
 998  * @priv: driver private structure
 999  * Description:
1000  * It disables the MTL queues by invoking the specific SXGBE callback.
1001  */
1002 static void sxgbe_disable_mtl_engine(struct sxgbe_priv_data *priv)
1003 {
1004         int queue_num;
1005
1006         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num)
1007                 priv->hw->mtl->mtl_disable_txqueue(priv->ioaddr, queue_num);
1008 }
1009
1010
1011 /**
1012  * sxgbe_tx_timer: mitigation sw timer for tx.
1013  * @data: data pointer
1014  * Description:
1015  * This is the timer handler to directly invoke the sxgbe_tx_clean.
1016  */
1017 static void sxgbe_tx_timer(unsigned long data)
1018 {
1019         struct sxgbe_tx_queue *p = (struct sxgbe_tx_queue *)data;
1020         sxgbe_tx_queue_clean(p);
1021 }
1022
1023 /**
1024  * sxgbe_init_tx_coalesce: init tx mitigation options.
1025  * @priv: driver private structure
1026  * Description:
1027  * This inits the transmit coalesce parameters: i.e. timer rate,
1028  * timer handler and default threshold used for enabling the
1029  * interrupt on completion bit.
1030  */
1031 static void sxgbe_tx_init_coalesce(struct sxgbe_priv_data *priv)
1032 {
1033         u8 queue_num;
1034
1035         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
1036                 struct sxgbe_tx_queue *p = priv->txq[queue_num];
1037                 p->tx_coal_frames =  SXGBE_TX_FRAMES;
1038                 p->tx_coal_timer = SXGBE_COAL_TX_TIMER;
1039                 setup_timer(&p->txtimer, sxgbe_tx_timer,
1040                             (unsigned long)&priv->txq[queue_num]);
1041                 p->txtimer.expires = SXGBE_COAL_TIMER(p->tx_coal_timer);
1042                 add_timer(&p->txtimer);
1043         }
1044 }
1045
1046 static void sxgbe_tx_del_timer(struct sxgbe_priv_data *priv)
1047 {
1048         u8 queue_num;
1049
1050         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
1051                 struct sxgbe_tx_queue *p = priv->txq[queue_num];
1052                 del_timer_sync(&p->txtimer);
1053         }
1054 }
1055
1056 /**
1057  *  sxgbe_open - open entry point of the driver
1058  *  @dev : pointer to the device structure.
1059  *  Description:
1060  *  This function is the open entry point of the driver.
1061  *  Return value:
1062  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1063  *  file on failure.
1064  */
1065 static int sxgbe_open(struct net_device *dev)
1066 {
1067         struct sxgbe_priv_data *priv = netdev_priv(dev);
1068         int ret, queue_num;
1069
1070         clk_prepare_enable(priv->sxgbe_clk);
1071
1072         sxgbe_check_ether_addr(priv);
1073
1074         /* Init the phy */
1075         ret = sxgbe_init_phy(dev);
1076         if (ret) {
1077                 netdev_err(dev, "%s: Cannot attach to PHY (error: %d)\n",
1078                            __func__, ret);
1079                 goto phy_error;
1080         }
1081
1082         /* Create and initialize the TX/RX descriptors chains. */
1083         priv->dma_tx_size = SXGBE_ALIGN(DMA_TX_SIZE);
1084         priv->dma_rx_size = SXGBE_ALIGN(DMA_RX_SIZE);
1085         priv->dma_buf_sz = SXGBE_ALIGN(DMA_BUFFER_SIZE);
1086         priv->tx_tc = TC_DEFAULT;
1087         priv->rx_tc = TC_DEFAULT;
1088         init_dma_desc_rings(dev);
1089
1090         /* DMA initialization and SW reset */
1091         ret = sxgbe_init_dma_engine(priv);
1092         if (ret < 0) {
1093                 netdev_err(dev, "%s: DMA initialization failed\n", __func__);
1094                 goto init_error;
1095         }
1096
1097         /*  MTL initialization */
1098         sxgbe_init_mtl_engine(priv);
1099
1100         /* Copy the MAC addr into the HW  */
1101         priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1102
1103         /* Initialize the MAC Core */
1104         priv->hw->mac->core_init(priv->ioaddr);
1105         SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
1106                 priv->hw->mac->enable_rxqueue(priv->ioaddr, queue_num);
1107         }
1108
1109         /* Request the IRQ lines */
1110         ret = devm_request_irq(priv->device, priv->irq, sxgbe_common_interrupt,
1111                                IRQF_SHARED, dev->name, dev);
1112         if (unlikely(ret < 0)) {
1113                 netdev_err(dev, "%s: ERROR: allocating the IRQ %d (error: %d)\n",
1114                            __func__, priv->irq, ret);
1115                 goto init_error;
1116         }
1117
1118         /* If the LPI irq is different from the mac irq
1119          * register a dedicated handler
1120          */
1121         if (priv->lpi_irq != dev->irq) {
1122                 ret = devm_request_irq(priv->device, priv->lpi_irq,
1123                                        sxgbe_common_interrupt,
1124                                        IRQF_SHARED, dev->name, dev);
1125                 if (unlikely(ret < 0)) {
1126                         netdev_err(dev, "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1127                                    __func__, priv->lpi_irq, ret);
1128                         goto init_error;
1129                 }
1130         }
1131
1132         /* Request TX DMA irq lines */
1133         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
1134                 ret = devm_request_irq(priv->device,
1135                                        (priv->txq[queue_num])->irq_no,
1136                                        sxgbe_tx_interrupt, 0,
1137                                        dev->name, priv->txq[queue_num]);
1138                 if (unlikely(ret < 0)) {
1139                         netdev_err(dev, "%s: ERROR: allocating TX IRQ %d (error: %d)\n",
1140                                    __func__, priv->irq, ret);
1141                         goto init_error;
1142                 }
1143         }
1144
1145         /* Request RX DMA irq lines */
1146         SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
1147                 ret = devm_request_irq(priv->device,
1148                                        (priv->rxq[queue_num])->irq_no,
1149                                        sxgbe_rx_interrupt, 0,
1150                                        dev->name, priv->rxq[queue_num]);
1151                 if (unlikely(ret < 0)) {
1152                         netdev_err(dev, "%s: ERROR: allocating TX IRQ %d (error: %d)\n",
1153                                    __func__, priv->irq, ret);
1154                         goto init_error;
1155                 }
1156         }
1157
1158         /* Enable the MAC Rx/Tx */
1159         priv->hw->mac->enable_tx(priv->ioaddr, true);
1160         priv->hw->mac->enable_rx(priv->ioaddr, true);
1161
1162         /* Set the HW DMA mode and the COE */
1163         sxgbe_mtl_operation_mode(priv);
1164
1165         /* Extra statistics */
1166         memset(&priv->xstats, 0, sizeof(struct sxgbe_extra_stats));
1167
1168         priv->xstats.tx_threshold = priv->tx_tc;
1169         priv->xstats.rx_threshold = priv->rx_tc;
1170
1171         /* Start the ball rolling... */
1172         netdev_dbg(dev, "DMA RX/TX processes started...\n");
1173         priv->hw->dma->start_tx(priv->ioaddr, SXGBE_TX_QUEUES);
1174         priv->hw->dma->start_rx(priv->ioaddr, SXGBE_RX_QUEUES);
1175
1176         if (dev->phydev)
1177                 phy_start(dev->phydev);
1178
1179         /* initialise TX coalesce parameters */
1180         sxgbe_tx_init_coalesce(priv);
1181
1182         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1183                 priv->rx_riwt = SXGBE_MAX_DMA_RIWT;
1184                 priv->hw->dma->rx_watchdog(priv->ioaddr, SXGBE_MAX_DMA_RIWT);
1185         }
1186
1187         priv->tx_lpi_timer = SXGBE_DEFAULT_LPI_TIMER;
1188         priv->eee_enabled = sxgbe_eee_init(priv);
1189
1190         napi_enable(&priv->napi);
1191         netif_start_queue(dev);
1192
1193         return 0;
1194
1195 init_error:
1196         free_dma_desc_resources(priv);
1197         if (dev->phydev)
1198                 phy_disconnect(dev->phydev);
1199 phy_error:
1200         clk_disable_unprepare(priv->sxgbe_clk);
1201
1202         return ret;
1203 }
1204
1205 /**
1206  *  sxgbe_release - close entry point of the driver
1207  *  @dev : device pointer.
1208  *  Description:
1209  *  This is the stop entry point of the driver.
1210  */
1211 static int sxgbe_release(struct net_device *dev)
1212 {
1213         struct sxgbe_priv_data *priv = netdev_priv(dev);
1214
1215         if (priv->eee_enabled)
1216                 del_timer_sync(&priv->eee_ctrl_timer);
1217
1218         /* Stop and disconnect the PHY */
1219         if (dev->phydev) {
1220                 phy_stop(dev->phydev);
1221                 phy_disconnect(dev->phydev);
1222         }
1223
1224         netif_tx_stop_all_queues(dev);
1225
1226         napi_disable(&priv->napi);
1227
1228         /* delete TX timers */
1229         sxgbe_tx_del_timer(priv);
1230
1231         /* Stop TX/RX DMA and clear the descriptors */
1232         priv->hw->dma->stop_tx(priv->ioaddr, SXGBE_TX_QUEUES);
1233         priv->hw->dma->stop_rx(priv->ioaddr, SXGBE_RX_QUEUES);
1234
1235         /* disable MTL queue */
1236         sxgbe_disable_mtl_engine(priv);
1237
1238         /* Release and free the Rx/Tx resources */
1239         free_dma_desc_resources(priv);
1240
1241         /* Disable the MAC Rx/Tx */
1242         priv->hw->mac->enable_tx(priv->ioaddr, false);
1243         priv->hw->mac->enable_rx(priv->ioaddr, false);
1244
1245         clk_disable_unprepare(priv->sxgbe_clk);
1246
1247         return 0;
1248 }
1249 /* Prepare first Tx descriptor for doing TSO operation */
1250 static void sxgbe_tso_prepare(struct sxgbe_priv_data *priv,
1251                               struct sxgbe_tx_norm_desc *first_desc,
1252                               struct sk_buff *skb)
1253 {
1254         unsigned int total_hdr_len, tcp_hdr_len;
1255
1256         /* Write first Tx descriptor with appropriate value */
1257         tcp_hdr_len = tcp_hdrlen(skb);
1258         total_hdr_len = skb_transport_offset(skb) + tcp_hdr_len;
1259
1260         first_desc->tdes01 = dma_map_single(priv->device, skb->data,
1261                                             total_hdr_len, DMA_TO_DEVICE);
1262         if (dma_mapping_error(priv->device, first_desc->tdes01))
1263                 pr_err("%s: TX dma mapping failed!!\n", __func__);
1264
1265         first_desc->tdes23.tx_rd_des23.first_desc = 1;
1266         priv->hw->desc->tx_desc_enable_tse(first_desc, 1, total_hdr_len,
1267                                            tcp_hdr_len,
1268                                            skb->len - total_hdr_len);
1269 }
1270
1271 /**
1272  *  sxgbe_xmit: Tx entry point of the driver
1273  *  @skb : the socket buffer
1274  *  @dev : device pointer
1275  *  Description : this is the tx entry point of the driver.
1276  *  It programs the chain or the ring and supports oversized frames
1277  *  and SG feature.
1278  */
1279 static netdev_tx_t sxgbe_xmit(struct sk_buff *skb, struct net_device *dev)
1280 {
1281         unsigned int entry, frag_num;
1282         int cksum_flag = 0;
1283         struct netdev_queue *dev_txq;
1284         unsigned txq_index = skb_get_queue_mapping(skb);
1285         struct sxgbe_priv_data *priv = netdev_priv(dev);
1286         unsigned int tx_rsize = priv->dma_tx_size;
1287         struct sxgbe_tx_queue *tqueue = priv->txq[txq_index];
1288         struct sxgbe_tx_norm_desc *tx_desc, *first_desc;
1289         struct sxgbe_tx_ctxt_desc *ctxt_desc = NULL;
1290         int nr_frags = skb_shinfo(skb)->nr_frags;
1291         int no_pagedlen = skb_headlen(skb);
1292         int is_jumbo = 0;
1293         u16 cur_mss = skb_shinfo(skb)->gso_size;
1294         u32 ctxt_desc_req = 0;
1295
1296         /* get the TX queue handle */
1297         dev_txq = netdev_get_tx_queue(dev, txq_index);
1298
1299         if (unlikely(skb_is_gso(skb) && tqueue->prev_mss != cur_mss))
1300                 ctxt_desc_req = 1;
1301
1302         if (unlikely(skb_vlan_tag_present(skb) ||
1303                      ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1304                       tqueue->hwts_tx_en)))
1305                 ctxt_desc_req = 1;
1306
1307         /* get the spinlock */
1308         spin_lock(&tqueue->tx_lock);
1309
1310         if (priv->tx_path_in_lpi_mode)
1311                 sxgbe_disable_eee_mode(priv);
1312
1313         if (unlikely(sxgbe_tx_avail(tqueue, tx_rsize) < nr_frags + 1)) {
1314                 if (!netif_tx_queue_stopped(dev_txq)) {
1315                         netif_tx_stop_queue(dev_txq);
1316                         netdev_err(dev, "%s: Tx Ring is full when %d queue is awake\n",
1317                                    __func__, txq_index);
1318                 }
1319                 /* release the spin lock in case of BUSY */
1320                 spin_unlock(&tqueue->tx_lock);
1321                 return NETDEV_TX_BUSY;
1322         }
1323
1324         entry = tqueue->cur_tx % tx_rsize;
1325         tx_desc = tqueue->dma_tx + entry;
1326
1327         first_desc = tx_desc;
1328         if (ctxt_desc_req)
1329                 ctxt_desc = (struct sxgbe_tx_ctxt_desc *)first_desc;
1330
1331         /* save the skb address */
1332         tqueue->tx_skbuff[entry] = skb;
1333
1334         if (!is_jumbo) {
1335                 if (likely(skb_is_gso(skb))) {
1336                         /* TSO support */
1337                         if (unlikely(tqueue->prev_mss != cur_mss)) {
1338                                 priv->hw->desc->tx_ctxt_desc_set_mss(
1339                                                 ctxt_desc, cur_mss);
1340                                 priv->hw->desc->tx_ctxt_desc_set_tcmssv(
1341                                                 ctxt_desc);
1342                                 priv->hw->desc->tx_ctxt_desc_reset_ostc(
1343                                                 ctxt_desc);
1344                                 priv->hw->desc->tx_ctxt_desc_set_ctxt(
1345                                                 ctxt_desc);
1346                                 priv->hw->desc->tx_ctxt_desc_set_owner(
1347                                                 ctxt_desc);
1348
1349                                 entry = (++tqueue->cur_tx) % tx_rsize;
1350                                 first_desc = tqueue->dma_tx + entry;
1351
1352                                 tqueue->prev_mss = cur_mss;
1353                         }
1354                         sxgbe_tso_prepare(priv, first_desc, skb);
1355                 } else {
1356                         tx_desc->tdes01 = dma_map_single(priv->device,
1357                                                          skb->data, no_pagedlen, DMA_TO_DEVICE);
1358                         if (dma_mapping_error(priv->device, tx_desc->tdes01))
1359                                 netdev_err(dev, "%s: TX dma mapping failed!!\n",
1360                                            __func__);
1361
1362                         priv->hw->desc->prepare_tx_desc(tx_desc, 1, no_pagedlen,
1363                                                         no_pagedlen, cksum_flag);
1364                 }
1365         }
1366
1367         for (frag_num = 0; frag_num < nr_frags; frag_num++) {
1368                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_num];
1369                 int len = skb_frag_size(frag);
1370
1371                 entry = (++tqueue->cur_tx) % tx_rsize;
1372                 tx_desc = tqueue->dma_tx + entry;
1373                 tx_desc->tdes01 = skb_frag_dma_map(priv->device, frag, 0, len,
1374                                                    DMA_TO_DEVICE);
1375
1376                 tqueue->tx_skbuff_dma[entry] = tx_desc->tdes01;
1377                 tqueue->tx_skbuff[entry] = NULL;
1378
1379                 /* prepare the descriptor */
1380                 priv->hw->desc->prepare_tx_desc(tx_desc, 0, len,
1381                                                 len, cksum_flag);
1382                 /* memory barrier to flush descriptor */
1383                 wmb();
1384
1385                 /* set the owner */
1386                 priv->hw->desc->set_tx_owner(tx_desc);
1387         }
1388
1389         /* close the descriptors */
1390         priv->hw->desc->close_tx_desc(tx_desc);
1391
1392         /* memory barrier to flush descriptor */
1393         wmb();
1394
1395         tqueue->tx_count_frames += nr_frags + 1;
1396         if (tqueue->tx_count_frames > tqueue->tx_coal_frames) {
1397                 priv->hw->desc->clear_tx_ic(tx_desc);
1398                 priv->xstats.tx_reset_ic_bit++;
1399                 mod_timer(&tqueue->txtimer,
1400                           SXGBE_COAL_TIMER(tqueue->tx_coal_timer));
1401         } else {
1402                 tqueue->tx_count_frames = 0;
1403         }
1404
1405         /* set owner for first desc */
1406         priv->hw->desc->set_tx_owner(first_desc);
1407
1408         /* memory barrier to flush descriptor */
1409         wmb();
1410
1411         tqueue->cur_tx++;
1412
1413         /* display current ring */
1414         netif_dbg(priv, pktdata, dev, "%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d\n",
1415                   __func__, tqueue->cur_tx % tx_rsize,
1416                   tqueue->dirty_tx % tx_rsize, entry,
1417                   first_desc, nr_frags);
1418
1419         if (unlikely(sxgbe_tx_avail(tqueue, tx_rsize) <= (MAX_SKB_FRAGS + 1))) {
1420                 netif_dbg(priv, hw, dev, "%s: stop transmitted packets\n",
1421                           __func__);
1422                 netif_tx_stop_queue(dev_txq);
1423         }
1424
1425         dev->stats.tx_bytes += skb->len;
1426
1427         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1428                      tqueue->hwts_tx_en)) {
1429                 /* declare that device is doing timestamping */
1430                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1431                 priv->hw->desc->tx_enable_tstamp(first_desc);
1432         }
1433
1434         if (!tqueue->hwts_tx_en)
1435                 skb_tx_timestamp(skb);
1436
1437         priv->hw->dma->enable_dma_transmission(priv->ioaddr, txq_index);
1438
1439         spin_unlock(&tqueue->tx_lock);
1440
1441         return NETDEV_TX_OK;
1442 }
1443
1444 /**
1445  * sxgbe_rx_refill: refill used skb preallocated buffers
1446  * @priv: driver private structure
1447  * Description : this is to reallocate the skb for the reception process
1448  * that is based on zero-copy.
1449  */
1450 static void sxgbe_rx_refill(struct sxgbe_priv_data *priv)
1451 {
1452         unsigned int rxsize = priv->dma_rx_size;
1453         int bfsize = priv->dma_buf_sz;
1454         u8 qnum = priv->cur_rx_qnum;
1455
1456         for (; priv->rxq[qnum]->cur_rx - priv->rxq[qnum]->dirty_rx > 0;
1457              priv->rxq[qnum]->dirty_rx++) {
1458                 unsigned int entry = priv->rxq[qnum]->dirty_rx % rxsize;
1459                 struct sxgbe_rx_norm_desc *p;
1460
1461                 p = priv->rxq[qnum]->dma_rx + entry;
1462
1463                 if (likely(priv->rxq[qnum]->rx_skbuff[entry] == NULL)) {
1464                         struct sk_buff *skb;
1465
1466                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
1467
1468                         if (unlikely(skb == NULL))
1469                                 break;
1470
1471                         priv->rxq[qnum]->rx_skbuff[entry] = skb;
1472                         priv->rxq[qnum]->rx_skbuff_dma[entry] =
1473                                 dma_map_single(priv->device, skb->data, bfsize,
1474                                                DMA_FROM_DEVICE);
1475
1476                         p->rdes23.rx_rd_des23.buf2_addr =
1477                                 priv->rxq[qnum]->rx_skbuff_dma[entry];
1478                 }
1479
1480                 /* Added memory barrier for RX descriptor modification */
1481                 wmb();
1482                 priv->hw->desc->set_rx_owner(p);
1483                 priv->hw->desc->set_rx_int_on_com(p);
1484                 /* Added memory barrier for RX descriptor modification */
1485                 wmb();
1486         }
1487 }
1488
1489 /**
1490  * sxgbe_rx: receive the frames from the remote host
1491  * @priv: driver private structure
1492  * @limit: napi bugget.
1493  * Description :  this the function called by the napi poll method.
1494  * It gets all the frames inside the ring.
1495  */
1496 static int sxgbe_rx(struct sxgbe_priv_data *priv, int limit)
1497 {
1498         u8 qnum = priv->cur_rx_qnum;
1499         unsigned int rxsize = priv->dma_rx_size;
1500         unsigned int entry = priv->rxq[qnum]->cur_rx;
1501         unsigned int next_entry = 0;
1502         unsigned int count = 0;
1503         int checksum;
1504         int status;
1505
1506         while (count < limit) {
1507                 struct sxgbe_rx_norm_desc *p;
1508                 struct sk_buff *skb;
1509                 int frame_len;
1510
1511                 p = priv->rxq[qnum]->dma_rx + entry;
1512
1513                 if (priv->hw->desc->get_rx_owner(p))
1514                         break;
1515
1516                 count++;
1517
1518                 next_entry = (++priv->rxq[qnum]->cur_rx) % rxsize;
1519                 prefetch(priv->rxq[qnum]->dma_rx + next_entry);
1520
1521                 /* Read the status of the incoming frame and also get checksum
1522                  * value based on whether it is enabled in SXGBE hardware or
1523                  * not.
1524                  */
1525                 status = priv->hw->desc->rx_wbstatus(p, &priv->xstats,
1526                                                      &checksum);
1527                 if (unlikely(status < 0)) {
1528                         entry = next_entry;
1529                         continue;
1530                 }
1531                 if (unlikely(!priv->rxcsum_insertion))
1532                         checksum = CHECKSUM_NONE;
1533
1534                 skb = priv->rxq[qnum]->rx_skbuff[entry];
1535
1536                 if (unlikely(!skb))
1537                         netdev_err(priv->dev, "rx descriptor is not consistent\n");
1538
1539                 prefetch(skb->data - NET_IP_ALIGN);
1540                 priv->rxq[qnum]->rx_skbuff[entry] = NULL;
1541
1542                 frame_len = priv->hw->desc->get_rx_frame_len(p);
1543
1544                 skb_put(skb, frame_len);
1545
1546                 skb->ip_summed = checksum;
1547                 if (checksum == CHECKSUM_NONE)
1548                         netif_receive_skb(skb);
1549                 else
1550                         napi_gro_receive(&priv->napi, skb);
1551
1552                 entry = next_entry;
1553         }
1554
1555         sxgbe_rx_refill(priv);
1556
1557         return count;
1558 }
1559
1560 /**
1561  *  sxgbe_poll - sxgbe poll method (NAPI)
1562  *  @napi : pointer to the napi structure.
1563  *  @budget : maximum number of packets that the current CPU can receive from
1564  *            all interfaces.
1565  *  Description :
1566  *  To look at the incoming frames and clear the tx resources.
1567  */
1568 static int sxgbe_poll(struct napi_struct *napi, int budget)
1569 {
1570         struct sxgbe_priv_data *priv = container_of(napi,
1571                                                     struct sxgbe_priv_data, napi);
1572         int work_done = 0;
1573         u8 qnum = priv->cur_rx_qnum;
1574
1575         priv->xstats.napi_poll++;
1576         /* first, clean the tx queues */
1577         sxgbe_tx_all_clean(priv);
1578
1579         work_done = sxgbe_rx(priv, budget);
1580         if (work_done < budget) {
1581                 napi_complete(napi);
1582                 priv->hw->dma->enable_dma_irq(priv->ioaddr, qnum);
1583         }
1584
1585         return work_done;
1586 }
1587
1588 /**
1589  *  sxgbe_tx_timeout
1590  *  @dev : Pointer to net device structure
1591  *  Description: this function is called when a packet transmission fails to
1592  *   complete within a reasonable time. The driver will mark the error in the
1593  *   netdev structure and arrange for the device to be reset to a sane state
1594  *   in order to transmit a new packet.
1595  */
1596 static void sxgbe_tx_timeout(struct net_device *dev)
1597 {
1598         struct sxgbe_priv_data *priv = netdev_priv(dev);
1599
1600         sxgbe_reset_all_tx_queues(priv);
1601 }
1602
1603 /**
1604  *  sxgbe_common_interrupt - main ISR
1605  *  @irq: interrupt number.
1606  *  @dev_id: to pass the net device pointer.
1607  *  Description: this is the main driver interrupt service routine.
1608  *  It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
1609  *  interrupts.
1610  */
1611 static irqreturn_t sxgbe_common_interrupt(int irq, void *dev_id)
1612 {
1613         struct net_device *netdev = (struct net_device *)dev_id;
1614         struct sxgbe_priv_data *priv = netdev_priv(netdev);
1615         int status;
1616
1617         status = priv->hw->mac->host_irq_status(priv->ioaddr, &priv->xstats);
1618         /* For LPI we need to save the tx status */
1619         if (status & TX_ENTRY_LPI_MODE) {
1620                 priv->xstats.tx_lpi_entry_n++;
1621                 priv->tx_path_in_lpi_mode = true;
1622         }
1623         if (status & TX_EXIT_LPI_MODE) {
1624                 priv->xstats.tx_lpi_exit_n++;
1625                 priv->tx_path_in_lpi_mode = false;
1626         }
1627         if (status & RX_ENTRY_LPI_MODE)
1628                 priv->xstats.rx_lpi_entry_n++;
1629         if (status & RX_EXIT_LPI_MODE)
1630                 priv->xstats.rx_lpi_exit_n++;
1631
1632         return IRQ_HANDLED;
1633 }
1634
1635 /**
1636  *  sxgbe_tx_interrupt - TX DMA ISR
1637  *  @irq: interrupt number.
1638  *  @dev_id: to pass the net device pointer.
1639  *  Description: this is the tx dma interrupt service routine.
1640  */
1641 static irqreturn_t sxgbe_tx_interrupt(int irq, void *dev_id)
1642 {
1643         int status;
1644         struct sxgbe_tx_queue *txq = (struct sxgbe_tx_queue *)dev_id;
1645         struct sxgbe_priv_data *priv = txq->priv_ptr;
1646
1647         /* get the channel status */
1648         status = priv->hw->dma->tx_dma_int_status(priv->ioaddr, txq->queue_no,
1649                                                   &priv->xstats);
1650         /* check for normal path */
1651         if (likely((status & handle_tx)))
1652                 napi_schedule(&priv->napi);
1653
1654         /* check for unrecoverable error */
1655         if (unlikely((status & tx_hard_error)))
1656                 sxgbe_restart_tx_queue(priv, txq->queue_no);
1657
1658         /* check for TC configuration change */
1659         if (unlikely((status & tx_bump_tc) &&
1660                      (priv->tx_tc != SXGBE_MTL_SFMODE) &&
1661                      (priv->tx_tc < 512))) {
1662                 /* step of TX TC is 32 till 128, otherwise 64 */
1663                 priv->tx_tc += (priv->tx_tc < 128) ? 32 : 64;
1664                 priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr,
1665                                                txq->queue_no, priv->tx_tc);
1666                 priv->xstats.tx_threshold = priv->tx_tc;
1667         }
1668
1669         return IRQ_HANDLED;
1670 }
1671
1672 /**
1673  *  sxgbe_rx_interrupt - RX DMA ISR
1674  *  @irq: interrupt number.
1675  *  @dev_id: to pass the net device pointer.
1676  *  Description: this is the rx dma interrupt service routine.
1677  */
1678 static irqreturn_t sxgbe_rx_interrupt(int irq, void *dev_id)
1679 {
1680         int status;
1681         struct sxgbe_rx_queue *rxq = (struct sxgbe_rx_queue *)dev_id;
1682         struct sxgbe_priv_data *priv = rxq->priv_ptr;
1683
1684         /* get the channel status */
1685         status = priv->hw->dma->rx_dma_int_status(priv->ioaddr, rxq->queue_no,
1686                                                   &priv->xstats);
1687
1688         if (likely((status & handle_rx) && (napi_schedule_prep(&priv->napi)))) {
1689                 priv->hw->dma->disable_dma_irq(priv->ioaddr, rxq->queue_no);
1690                 __napi_schedule(&priv->napi);
1691         }
1692
1693         /* check for TC configuration change */
1694         if (unlikely((status & rx_bump_tc) &&
1695                      (priv->rx_tc != SXGBE_MTL_SFMODE) &&
1696                      (priv->rx_tc < 128))) {
1697                 /* step of TC is 32 */
1698                 priv->rx_tc += 32;
1699                 priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr,
1700                                                rxq->queue_no, priv->rx_tc);
1701                 priv->xstats.rx_threshold = priv->rx_tc;
1702         }
1703
1704         return IRQ_HANDLED;
1705 }
1706
1707 static inline u64 sxgbe_get_stat64(void __iomem *ioaddr, int reg_lo, int reg_hi)
1708 {
1709         u64 val = readl(ioaddr + reg_lo);
1710
1711         val |= ((u64)readl(ioaddr + reg_hi)) << 32;
1712
1713         return val;
1714 }
1715
1716
1717 /*  sxgbe_get_stats64 - entry point to see statistical information of device
1718  *  @dev : device pointer.
1719  *  @stats : pointer to hold all the statistical information of device.
1720  *  Description:
1721  *  This function is a driver entry point whenever ifconfig command gets
1722  *  executed to see device statistics. Statistics are number of
1723  *  bytes sent or received, errors occurred etc.
1724  *  Return value:
1725  *  This function returns various statistical information of device.
1726  */
1727 static struct rtnl_link_stats64 *sxgbe_get_stats64(struct net_device *dev,
1728                                                    struct rtnl_link_stats64 *stats)
1729 {
1730         struct sxgbe_priv_data *priv = netdev_priv(dev);
1731         void __iomem *ioaddr = priv->ioaddr;
1732         u64 count;
1733
1734         spin_lock(&priv->stats_lock);
1735         /* Freeze the counter registers before reading value otherwise it may
1736          * get updated by hardware while we are reading them
1737          */
1738         writel(SXGBE_MMC_CTRL_CNT_FRZ, ioaddr + SXGBE_MMC_CTL_REG);
1739
1740         stats->rx_bytes = sxgbe_get_stat64(ioaddr,
1741                                            SXGBE_MMC_RXOCTETLO_GCNT_REG,
1742                                            SXGBE_MMC_RXOCTETHI_GCNT_REG);
1743
1744         stats->rx_packets = sxgbe_get_stat64(ioaddr,
1745                                              SXGBE_MMC_RXFRAMELO_GBCNT_REG,
1746                                              SXGBE_MMC_RXFRAMEHI_GBCNT_REG);
1747
1748         stats->multicast = sxgbe_get_stat64(ioaddr,
1749                                             SXGBE_MMC_RXMULTILO_GCNT_REG,
1750                                             SXGBE_MMC_RXMULTIHI_GCNT_REG);
1751
1752         stats->rx_crc_errors = sxgbe_get_stat64(ioaddr,
1753                                                 SXGBE_MMC_RXCRCERRLO_REG,
1754                                                 SXGBE_MMC_RXCRCERRHI_REG);
1755
1756         stats->rx_length_errors = sxgbe_get_stat64(ioaddr,
1757                                                   SXGBE_MMC_RXLENERRLO_REG,
1758                                                   SXGBE_MMC_RXLENERRHI_REG);
1759
1760         stats->rx_missed_errors = sxgbe_get_stat64(ioaddr,
1761                                                    SXGBE_MMC_RXFIFOOVERFLOWLO_GBCNT_REG,
1762                                                    SXGBE_MMC_RXFIFOOVERFLOWHI_GBCNT_REG);
1763
1764         stats->tx_bytes = sxgbe_get_stat64(ioaddr,
1765                                            SXGBE_MMC_TXOCTETLO_GCNT_REG,
1766                                            SXGBE_MMC_TXOCTETHI_GCNT_REG);
1767
1768         count = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXFRAMELO_GBCNT_REG,
1769                                  SXGBE_MMC_TXFRAMEHI_GBCNT_REG);
1770
1771         stats->tx_errors = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXFRAMELO_GCNT_REG,
1772                                             SXGBE_MMC_TXFRAMEHI_GCNT_REG);
1773         stats->tx_errors = count - stats->tx_errors;
1774         stats->tx_packets = count;
1775         stats->tx_fifo_errors = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXUFLWLO_GBCNT_REG,
1776                                                  SXGBE_MMC_TXUFLWHI_GBCNT_REG);
1777         writel(0, ioaddr + SXGBE_MMC_CTL_REG);
1778         spin_unlock(&priv->stats_lock);
1779
1780         return stats;
1781 }
1782
1783 /*  sxgbe_set_features - entry point to set offload features of the device.
1784  *  @dev : device pointer.
1785  *  @features : features which are required to be set.
1786  *  Description:
1787  *  This function is a driver entry point and called by Linux kernel whenever
1788  *  any device features are set or reset by user.
1789  *  Return value:
1790  *  This function returns 0 after setting or resetting device features.
1791  */
1792 static int sxgbe_set_features(struct net_device *dev,
1793                               netdev_features_t features)
1794 {
1795         struct sxgbe_priv_data *priv = netdev_priv(dev);
1796         netdev_features_t changed = dev->features ^ features;
1797
1798         if (changed & NETIF_F_RXCSUM) {
1799                 if (features & NETIF_F_RXCSUM) {
1800                         priv->hw->mac->enable_rx_csum(priv->ioaddr);
1801                         priv->rxcsum_insertion = true;
1802                 } else {
1803                         priv->hw->mac->disable_rx_csum(priv->ioaddr);
1804                         priv->rxcsum_insertion = false;
1805                 }
1806         }
1807
1808         return 0;
1809 }
1810
1811 /*  sxgbe_change_mtu - entry point to change MTU size for the device.
1812  *  @dev : device pointer.
1813  *  @new_mtu : the new MTU size for the device.
1814  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
1815  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
1816  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
1817  *  Return value:
1818  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1819  *  file on failure.
1820  */
1821 static int sxgbe_change_mtu(struct net_device *dev, int new_mtu)
1822 {
1823         /* RFC 791, page 25, "Every internet module must be able to forward
1824          * a datagram of 68 octets without further fragmentation."
1825          */
1826         if (new_mtu < MIN_MTU || (new_mtu > MAX_MTU)) {
1827                 netdev_err(dev, "invalid MTU, MTU should be in between %d and %d\n",
1828                            MIN_MTU, MAX_MTU);
1829                 return -EINVAL;
1830         }
1831
1832         /* Return if the buffer sizes will not change */
1833         if (dev->mtu == new_mtu)
1834                 return 0;
1835
1836         dev->mtu = new_mtu;
1837
1838         if (!netif_running(dev))
1839                 return 0;
1840
1841         /* Recevice ring buffer size is needed to be set based on MTU. If MTU is
1842          * changed then reinitilisation of the receive ring buffers need to be
1843          * done. Hence bring interface down and bring interface back up
1844          */
1845         sxgbe_release(dev);
1846         return sxgbe_open(dev);
1847 }
1848
1849 static void sxgbe_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
1850                                 unsigned int reg_n)
1851 {
1852         unsigned long data;
1853
1854         data = (addr[5] << 8) | addr[4];
1855         /* For MAC Addr registers se have to set the Address Enable (AE)
1856          * bit that has no effect on the High Reg 0 where the bit 31 (MO)
1857          * is RO.
1858          */
1859         writel(data | SXGBE_HI_REG_AE, ioaddr + SXGBE_ADDR_HIGH(reg_n));
1860         data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
1861         writel(data, ioaddr + SXGBE_ADDR_LOW(reg_n));
1862 }
1863
1864 /**
1865  * sxgbe_set_rx_mode - entry point for setting different receive mode of
1866  * a device. unicast, multicast addressing
1867  * @dev : pointer to the device structure
1868  * Description:
1869  * This function is a driver entry point which gets called by the kernel
1870  * whenever different receive mode like unicast, multicast and promiscuous
1871  * must be enabled/disabled.
1872  * Return value:
1873  * void.
1874  */
1875 static void sxgbe_set_rx_mode(struct net_device *dev)
1876 {
1877         struct sxgbe_priv_data *priv = netdev_priv(dev);
1878         void __iomem *ioaddr = (void __iomem *)priv->ioaddr;
1879         unsigned int value = 0;
1880         u32 mc_filter[2];
1881         struct netdev_hw_addr *ha;
1882         int reg = 1;
1883
1884         netdev_dbg(dev, "%s: # mcasts %d, # unicast %d\n",
1885                    __func__, netdev_mc_count(dev), netdev_uc_count(dev));
1886
1887         if (dev->flags & IFF_PROMISC) {
1888                 value = SXGBE_FRAME_FILTER_PR;
1889
1890         } else if ((netdev_mc_count(dev) > SXGBE_HASH_TABLE_SIZE) ||
1891                    (dev->flags & IFF_ALLMULTI)) {
1892                 value = SXGBE_FRAME_FILTER_PM;  /* pass all multi */
1893                 writel(0xffffffff, ioaddr + SXGBE_HASH_HIGH);
1894                 writel(0xffffffff, ioaddr + SXGBE_HASH_LOW);
1895
1896         } else if (!netdev_mc_empty(dev)) {
1897                 /* Hash filter for multicast */
1898                 value = SXGBE_FRAME_FILTER_HMC;
1899
1900                 memset(mc_filter, 0, sizeof(mc_filter));
1901                 netdev_for_each_mc_addr(ha, dev) {
1902                         /* The upper 6 bits of the calculated CRC are used to
1903                          * index the contens of the hash table
1904                          */
1905                         int bit_nr = bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
1906
1907                         /* The most significant bit determines the register to
1908                          * use (H/L) while the other 5 bits determine the bit
1909                          * within the register.
1910                          */
1911                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1912                 }
1913                 writel(mc_filter[0], ioaddr + SXGBE_HASH_LOW);
1914                 writel(mc_filter[1], ioaddr + SXGBE_HASH_HIGH);
1915         }
1916
1917         /* Handle multiple unicast addresses (perfect filtering) */
1918         if (netdev_uc_count(dev) > SXGBE_MAX_PERFECT_ADDRESSES)
1919                 /* Switch to promiscuous mode if more than 16 addrs
1920                  * are required
1921                  */
1922                 value |= SXGBE_FRAME_FILTER_PR;
1923         else {
1924                 netdev_for_each_uc_addr(ha, dev) {
1925                         sxgbe_set_umac_addr(ioaddr, ha->addr, reg);
1926                         reg++;
1927                 }
1928         }
1929 #ifdef FRAME_FILTER_DEBUG
1930         /* Enable Receive all mode (to debug filtering_fail errors) */
1931         value |= SXGBE_FRAME_FILTER_RA;
1932 #endif
1933         writel(value, ioaddr + SXGBE_FRAME_FILTER);
1934
1935         netdev_dbg(dev, "Filter: 0x%08x\n\tHash: HI 0x%08x, LO 0x%08x\n",
1936                    readl(ioaddr + SXGBE_FRAME_FILTER),
1937                    readl(ioaddr + SXGBE_HASH_HIGH),
1938                    readl(ioaddr + SXGBE_HASH_LOW));
1939 }
1940
1941 #ifdef CONFIG_NET_POLL_CONTROLLER
1942 /**
1943  * sxgbe_poll_controller - entry point for polling receive by device
1944  * @dev : pointer to the device structure
1945  * Description:
1946  * This function is used by NETCONSOLE and other diagnostic tools
1947  * to allow network I/O with interrupts disabled.
1948  * Return value:
1949  * Void.
1950  */
1951 static void sxgbe_poll_controller(struct net_device *dev)
1952 {
1953         struct sxgbe_priv_data *priv = netdev_priv(dev);
1954
1955         disable_irq(priv->irq);
1956         sxgbe_rx_interrupt(priv->irq, dev);
1957         enable_irq(priv->irq);
1958 }
1959 #endif
1960
1961 /*  sxgbe_ioctl - Entry point for the Ioctl
1962  *  @dev: Device pointer.
1963  *  @rq: An IOCTL specefic structure, that can contain a pointer to
1964  *  a proprietary structure used to pass information to the driver.
1965  *  @cmd: IOCTL command
1966  *  Description:
1967  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
1968  */
1969 static int sxgbe_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1970 {
1971         int ret = -EOPNOTSUPP;
1972
1973         if (!netif_running(dev))
1974                 return -EINVAL;
1975
1976         switch (cmd) {
1977         case SIOCGMIIPHY:
1978         case SIOCGMIIREG:
1979         case SIOCSMIIREG:
1980                 if (!dev->phydev)
1981                         return -EINVAL;
1982                 ret = phy_mii_ioctl(dev->phydev, rq, cmd);
1983                 break;
1984         default:
1985                 break;
1986         }
1987
1988         return ret;
1989 }
1990
1991 static const struct net_device_ops sxgbe_netdev_ops = {
1992         .ndo_open               = sxgbe_open,
1993         .ndo_start_xmit         = sxgbe_xmit,
1994         .ndo_stop               = sxgbe_release,
1995         .ndo_get_stats64        = sxgbe_get_stats64,
1996         .ndo_change_mtu         = sxgbe_change_mtu,
1997         .ndo_set_features       = sxgbe_set_features,
1998         .ndo_set_rx_mode        = sxgbe_set_rx_mode,
1999         .ndo_tx_timeout         = sxgbe_tx_timeout,
2000         .ndo_do_ioctl           = sxgbe_ioctl,
2001 #ifdef CONFIG_NET_POLL_CONTROLLER
2002         .ndo_poll_controller    = sxgbe_poll_controller,
2003 #endif
2004         .ndo_set_mac_address    = eth_mac_addr,
2005 };
2006
2007 /* Get the hardware ops */
2008 static void sxgbe_get_ops(struct sxgbe_ops * const ops_ptr)
2009 {
2010         ops_ptr->mac            = sxgbe_get_core_ops();
2011         ops_ptr->desc           = sxgbe_get_desc_ops();
2012         ops_ptr->dma            = sxgbe_get_dma_ops();
2013         ops_ptr->mtl            = sxgbe_get_mtl_ops();
2014
2015         /* set the MDIO communication Address/Data regisers */
2016         ops_ptr->mii.addr       = SXGBE_MDIO_SCMD_ADD_REG;
2017         ops_ptr->mii.data       = SXGBE_MDIO_SCMD_DATA_REG;
2018
2019         /* Assigning the default link settings
2020          * no SXGBE defined default values to be set in registers,
2021          * so assigning as 0 for port and duplex
2022          */
2023         ops_ptr->link.port      = 0;
2024         ops_ptr->link.duplex    = 0;
2025         ops_ptr->link.speed     = SXGBE_SPEED_10G;
2026 }
2027
2028 /**
2029  *  sxgbe_hw_init - Init the GMAC device
2030  *  @priv: driver private structure
2031  *  Description: this function checks the HW capability
2032  *  (if supported) and sets the driver's features.
2033  */
2034 static int sxgbe_hw_init(struct sxgbe_priv_data * const priv)
2035 {
2036         u32 ctrl_ids;
2037
2038         priv->hw = kmalloc(sizeof(*priv->hw), GFP_KERNEL);
2039         if(!priv->hw)
2040                 return -ENOMEM;
2041
2042         /* get the hardware ops */
2043         sxgbe_get_ops(priv->hw);
2044
2045         /* get the controller id */
2046         ctrl_ids = priv->hw->mac->get_controller_version(priv->ioaddr);
2047         priv->hw->ctrl_uid = (ctrl_ids & 0x00ff0000) >> 16;
2048         priv->hw->ctrl_id = (ctrl_ids & 0x000000ff);
2049         pr_info("user ID: 0x%x, Controller ID: 0x%x\n",
2050                 priv->hw->ctrl_uid, priv->hw->ctrl_id);
2051
2052         /* get the H/W features */
2053         if (!sxgbe_get_hw_features(priv))
2054                 pr_info("Hardware features not found\n");
2055
2056         if (priv->hw_cap.tx_csum_offload)
2057                 pr_info("TX Checksum offload supported\n");
2058
2059         if (priv->hw_cap.rx_csum_offload)
2060                 pr_info("RX Checksum offload supported\n");
2061
2062         return 0;
2063 }
2064
2065 static int sxgbe_sw_reset(void __iomem *addr)
2066 {
2067         int retry_count = 10;
2068
2069         writel(SXGBE_DMA_SOFT_RESET, addr + SXGBE_DMA_MODE_REG);
2070         while (retry_count--) {
2071                 if (!(readl(addr + SXGBE_DMA_MODE_REG) &
2072                       SXGBE_DMA_SOFT_RESET))
2073                         break;
2074                 mdelay(10);
2075         }
2076
2077         if (retry_count < 0)
2078                 return -EBUSY;
2079
2080         return 0;
2081 }
2082
2083 /**
2084  * sxgbe_drv_probe
2085  * @device: device pointer
2086  * @plat_dat: platform data pointer
2087  * @addr: iobase memory address
2088  * Description: this is the main probe function used to
2089  * call the alloc_etherdev, allocate the priv structure.
2090  */
2091 struct sxgbe_priv_data *sxgbe_drv_probe(struct device *device,
2092                                         struct sxgbe_plat_data *plat_dat,
2093                                         void __iomem *addr)
2094 {
2095         struct sxgbe_priv_data *priv;
2096         struct net_device *ndev;
2097         int ret;
2098         u8 queue_num;
2099
2100         ndev = alloc_etherdev_mqs(sizeof(struct sxgbe_priv_data),
2101                                   SXGBE_TX_QUEUES, SXGBE_RX_QUEUES);
2102         if (!ndev)
2103                 return NULL;
2104
2105         SET_NETDEV_DEV(ndev, device);
2106
2107         priv = netdev_priv(ndev);
2108         priv->device = device;
2109         priv->dev = ndev;
2110
2111         sxgbe_set_ethtool_ops(ndev);
2112         priv->plat = plat_dat;
2113         priv->ioaddr = addr;
2114
2115         ret = sxgbe_sw_reset(priv->ioaddr);
2116         if (ret)
2117                 goto error_free_netdev;
2118
2119         /* Verify driver arguments */
2120         sxgbe_verify_args();
2121
2122         /* Init MAC and get the capabilities */
2123         ret = sxgbe_hw_init(priv);
2124         if (ret)
2125                 goto error_free_netdev;
2126
2127         /* allocate memory resources for Descriptor rings */
2128         ret = txring_mem_alloc(priv);
2129         if (ret)
2130                 goto error_free_hw;
2131
2132         ret = rxring_mem_alloc(priv);
2133         if (ret)
2134                 goto error_free_hw;
2135
2136         ndev->netdev_ops = &sxgbe_netdev_ops;
2137
2138         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2139                 NETIF_F_RXCSUM | NETIF_F_TSO | NETIF_F_TSO6 |
2140                 NETIF_F_GRO;
2141         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2142         ndev->watchdog_timeo = msecs_to_jiffies(TX_TIMEO);
2143
2144         /* assign filtering support */
2145         ndev->priv_flags |= IFF_UNICAST_FLT;
2146
2147         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2148
2149         /* Enable TCP segmentation offload for all DMA channels */
2150         if (priv->hw_cap.tcpseg_offload) {
2151                 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
2152                         priv->hw->dma->enable_tso(priv->ioaddr, queue_num);
2153                 }
2154         }
2155
2156         /* Enable Rx checksum offload */
2157         if (priv->hw_cap.rx_csum_offload) {
2158                 priv->hw->mac->enable_rx_csum(priv->ioaddr);
2159                 priv->rxcsum_insertion = true;
2160         }
2161
2162         /* Initialise pause frame settings */
2163         priv->rx_pause = 1;
2164         priv->tx_pause = 1;
2165
2166         /* Rx Watchdog is available, enable depend on platform data */
2167         if (!priv->plat->riwt_off) {
2168                 priv->use_riwt = 1;
2169                 pr_info("Enable RX Mitigation via HW Watchdog Timer\n");
2170         }
2171
2172         netif_napi_add(ndev, &priv->napi, sxgbe_poll, 64);
2173
2174         spin_lock_init(&priv->stats_lock);
2175
2176         priv->sxgbe_clk = clk_get(priv->device, SXGBE_RESOURCE_NAME);
2177         if (IS_ERR(priv->sxgbe_clk)) {
2178                 netdev_warn(ndev, "%s: warning: cannot get CSR clock\n",
2179                             __func__);
2180                 goto error_napi_del;
2181         }
2182
2183         /* If a specific clk_csr value is passed from the platform
2184          * this means that the CSR Clock Range selection cannot be
2185          * changed at run-time and it is fixed. Viceversa the driver'll try to
2186          * set the MDC clock dynamically according to the csr actual
2187          * clock input.
2188          */
2189         if (!priv->plat->clk_csr)
2190                 sxgbe_clk_csr_set(priv);
2191         else
2192                 priv->clk_csr = priv->plat->clk_csr;
2193
2194         /* MDIO bus Registration */
2195         ret = sxgbe_mdio_register(ndev);
2196         if (ret < 0) {
2197                 netdev_dbg(ndev, "%s: MDIO bus (id: %d) registration failed\n",
2198                            __func__, priv->plat->bus_id);
2199                 goto error_clk_put;
2200         }
2201
2202         ret = register_netdev(ndev);
2203         if (ret) {
2204                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2205                 goto error_mdio_unregister;
2206         }
2207
2208         sxgbe_check_ether_addr(priv);
2209
2210         return priv;
2211
2212 error_mdio_unregister:
2213         sxgbe_mdio_unregister(ndev);
2214 error_clk_put:
2215         clk_put(priv->sxgbe_clk);
2216 error_napi_del:
2217         netif_napi_del(&priv->napi);
2218 error_free_hw:
2219         kfree(priv->hw);
2220 error_free_netdev:
2221         free_netdev(ndev);
2222
2223         return NULL;
2224 }
2225
2226 /**
2227  * sxgbe_drv_remove
2228  * @ndev: net device pointer
2229  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2230  * changes the link status, releases the DMA descriptor rings.
2231  */
2232 int sxgbe_drv_remove(struct net_device *ndev)
2233 {
2234         struct sxgbe_priv_data *priv = netdev_priv(ndev);
2235         u8 queue_num;
2236
2237         netdev_info(ndev, "%s: removing driver\n", __func__);
2238
2239         SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
2240                 priv->hw->mac->disable_rxqueue(priv->ioaddr, queue_num);
2241         }
2242
2243         priv->hw->dma->stop_rx(priv->ioaddr, SXGBE_RX_QUEUES);
2244         priv->hw->dma->stop_tx(priv->ioaddr, SXGBE_TX_QUEUES);
2245
2246         priv->hw->mac->enable_tx(priv->ioaddr, false);
2247         priv->hw->mac->enable_rx(priv->ioaddr, false);
2248
2249         unregister_netdev(ndev);
2250
2251         sxgbe_mdio_unregister(ndev);
2252
2253         clk_put(priv->sxgbe_clk);
2254
2255         netif_napi_del(&priv->napi);
2256
2257         kfree(priv->hw);
2258
2259         free_netdev(ndev);
2260
2261         return 0;
2262 }
2263
2264 #ifdef CONFIG_PM
2265 int sxgbe_suspend(struct net_device *ndev)
2266 {
2267         return 0;
2268 }
2269
2270 int sxgbe_resume(struct net_device *ndev)
2271 {
2272         return 0;
2273 }
2274
2275 int sxgbe_freeze(struct net_device *ndev)
2276 {
2277         return -ENOSYS;
2278 }
2279
2280 int sxgbe_restore(struct net_device *ndev)
2281 {
2282         return -ENOSYS;
2283 }
2284 #endif /* CONFIG_PM */
2285
2286 /* Driver is configured as Platform driver */
2287 static int __init sxgbe_init(void)
2288 {
2289         int ret;
2290
2291         ret = sxgbe_register_platform();
2292         if (ret)
2293                 goto err;
2294         return 0;
2295 err:
2296         pr_err("driver registration failed\n");
2297         return ret;
2298 }
2299
2300 static void __exit sxgbe_exit(void)
2301 {
2302         sxgbe_unregister_platform();
2303 }
2304
2305 module_init(sxgbe_init);
2306 module_exit(sxgbe_exit);
2307
2308 #ifndef MODULE
2309 static int __init sxgbe_cmdline_opt(char *str)
2310 {
2311         char *opt;
2312
2313         if (!str || !*str)
2314                 return 1;
2315         while ((opt = strsep(&str, ",")) != NULL) {
2316                 if (!strncmp(opt, "eee_timer:", 10)) {
2317                         if (kstrtoint(opt + 10, 0, &eee_timer))
2318                                 goto err;
2319                 }
2320         }
2321         return 1;
2322
2323 err:
2324         pr_err("%s: ERROR broken module parameter conversion\n", __func__);
2325         return 1;
2326 }
2327
2328 __setup("sxgbeeth=", sxgbe_cmdline_opt);
2329 #endif /* MODULE */
2330
2331
2332
2333 MODULE_DESCRIPTION("SAMSUNG 10G/2.5G/1G Ethernet PLATFORM driver");
2334
2335 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
2336 MODULE_PARM_DESC(eee_timer, "EEE-LPI Default LS timer value");
2337
2338 MODULE_AUTHOR("Siva Reddy Kallam <siva.kallam@samsung.com>");
2339 MODULE_AUTHOR("ByungHo An <bh74.an@samsung.com>");
2340 MODULE_AUTHOR("Girish K S <ks.giri@samsung.com>");
2341 MODULE_AUTHOR("Vipul Pandya <vipul.pandya@samsung.com>");
2342
2343 MODULE_LICENSE("GPL");