1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* 10G controller driver for Samsung SoCs
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Author: Siva Reddy Kallam <siva.kallam@samsung.com>
9 #ifndef __SXGBE_DESC_H__
10 #define __SXGBE_DESC_H__
12 #define SXGBE_DESC_SIZE_BYTES 16
14 /* forward declaration */
15 struct sxgbe_extra_stats;
17 /* Transmit checksum insertion control */
18 enum tdes_csum_insertion {
19 cic_disabled = 0, /* Checksum Insertion Control */
20 cic_only_ip = 1, /* Only IP header */
21 /* IP header but pseudoheader is not calculated */
22 cic_no_pseudoheader = 2,
23 cic_full = 3, /* IP header and pseudoheader */
26 struct sxgbe_tx_norm_desc {
27 u64 tdes01; /* buf1 address */
29 /* TX Read-Format Desc 2,3 */
35 u32 timestmp_enable:1;
57 /* tx write back Desc 2,3 */
68 struct sxgbe_rx_norm_desc {
70 u64 rdes01; /* buf1 address */
79 /* RX Read format Desc 2,3 */
96 u32 vlan_filter_match:1;
99 u32 hash_filter_pass:1;
100 u32 macaddr_filter_match:8;
101 u32 l3_filter_match:1;
102 u32 l4_filter_match:1;
103 u32 l34_filter_num:3;
107 u32 rdes3_reserved:1;
110 u32 layer34_pkt_type:4;
111 u32 no_coagulation_pkt:1;
114 u32 context_des_avail:1;
117 u32 recv_context_desc:1;
123 /* Context descriptor structure */
124 struct sxgbe_tx_ctxt_desc {
132 u32 ivlan_tag_valid:1;
144 struct sxgbe_rx_ctxt_desc {
149 u32 tstamp_available:1;
151 u32 tstamp_dropped:1;
157 struct sxgbe_desc_ops {
158 /* DMA TX descriptor ring initialization */
159 void (*init_tx_desc)(struct sxgbe_tx_norm_desc *p);
161 /* Invoked by the xmit function to prepare the tx descriptor */
162 void (*tx_desc_enable_tse)(struct sxgbe_tx_norm_desc *p, u8 is_tse,
163 u32 total_hdr_len, u32 tcp_hdr_len,
164 u32 tcp_payload_len);
166 /* Assign buffer lengths for descriptor */
167 void (*prepare_tx_desc)(struct sxgbe_tx_norm_desc *p, u8 is_fd,
168 int buf1_len, int pkt_len, int cksum);
170 /* Set VLAN control information */
171 void (*tx_vlanctl_desc)(struct sxgbe_tx_norm_desc *p, int vlan_ctl);
173 /* Set the owner of the descriptor */
174 void (*set_tx_owner)(struct sxgbe_tx_norm_desc *p);
176 /* Get the owner of the descriptor */
177 int (*get_tx_owner)(struct sxgbe_tx_norm_desc *p);
179 /* Invoked by the xmit function to close the tx descriptor */
180 void (*close_tx_desc)(struct sxgbe_tx_norm_desc *p);
182 /* Clean the tx descriptor as soon as the tx irq is received */
183 void (*release_tx_desc)(struct sxgbe_tx_norm_desc *p);
185 /* Clear interrupt on tx frame completion. When this bit is
186 * set an interrupt happens as soon as the frame is transmitted
188 void (*clear_tx_ic)(struct sxgbe_tx_norm_desc *p);
190 /* Last tx segment reports the transmit status */
191 int (*get_tx_ls)(struct sxgbe_tx_norm_desc *p);
193 /* Get the buffer size from the descriptor */
194 int (*get_tx_len)(struct sxgbe_tx_norm_desc *p);
196 /* Set tx timestamp enable bit */
197 void (*tx_enable_tstamp)(struct sxgbe_tx_norm_desc *p);
199 /* get tx timestamp status */
200 int (*get_tx_timestamp_status)(struct sxgbe_tx_norm_desc *p);
202 /* TX Context Descripto Specific */
203 void (*tx_ctxt_desc_set_ctxt)(struct sxgbe_tx_ctxt_desc *p);
205 /* Set the owner of the TX context descriptor */
206 void (*tx_ctxt_desc_set_owner)(struct sxgbe_tx_ctxt_desc *p);
208 /* Get the owner of the TX context descriptor */
209 int (*get_tx_ctxt_owner)(struct sxgbe_tx_ctxt_desc *p);
212 void (*tx_ctxt_desc_set_mss)(struct sxgbe_tx_ctxt_desc *p, u16 mss);
215 int (*tx_ctxt_desc_get_mss)(struct sxgbe_tx_ctxt_desc *p);
218 void (*tx_ctxt_desc_set_tcmssv)(struct sxgbe_tx_ctxt_desc *p);
221 void (*tx_ctxt_desc_reset_ostc)(struct sxgbe_tx_ctxt_desc *p);
223 /* Set IVLAN information */
224 void (*tx_ctxt_desc_set_ivlantag)(struct sxgbe_tx_ctxt_desc *p,
225 int is_ivlanvalid, int ivlan_tag,
228 /* Return IVLAN Tag */
229 int (*tx_ctxt_desc_get_ivlantag)(struct sxgbe_tx_ctxt_desc *p);
232 void (*tx_ctxt_desc_set_vlantag)(struct sxgbe_tx_ctxt_desc *p,
233 int is_vlanvalid, int vlan_tag);
235 /* Return VLAN Tag */
236 int (*tx_ctxt_desc_get_vlantag)(struct sxgbe_tx_ctxt_desc *p);
239 void (*tx_ctxt_set_tstamp)(struct sxgbe_tx_ctxt_desc *p,
240 u8 ostc_enable, u64 tstamp);
242 /* Close TX context descriptor */
243 void (*close_tx_ctxt_desc)(struct sxgbe_tx_ctxt_desc *p);
245 /* WB status of context descriptor */
246 int (*get_tx_ctxt_cde)(struct sxgbe_tx_ctxt_desc *p);
248 /* DMA RX descriptor ring initialization */
249 void (*init_rx_desc)(struct sxgbe_rx_norm_desc *p, int disable_rx_ic,
253 int (*get_rx_owner)(struct sxgbe_rx_norm_desc *p);
256 void (*set_rx_owner)(struct sxgbe_rx_norm_desc *p);
258 /* Set Interrupt on completion bit */
259 void (*set_rx_int_on_com)(struct sxgbe_rx_norm_desc *p);
261 /* Get the receive frame size */
262 int (*get_rx_frame_len)(struct sxgbe_rx_norm_desc *p);
264 /* Return first Descriptor status */
265 int (*get_rx_fd_status)(struct sxgbe_rx_norm_desc *p);
267 /* Return first Descriptor status */
268 int (*get_rx_ld_status)(struct sxgbe_rx_norm_desc *p);
270 /* Return the reception status looking at the RDES1 */
271 int (*rx_wbstatus)(struct sxgbe_rx_norm_desc *p,
272 struct sxgbe_extra_stats *x, int *checksum);
275 int (*get_rx_ctxt_owner)(struct sxgbe_rx_ctxt_desc *p);
278 void (*set_rx_ctxt_owner)(struct sxgbe_rx_ctxt_desc *p);
280 /* Return the reception status looking at Context control information */
281 void (*rx_ctxt_wbstatus)(struct sxgbe_rx_ctxt_desc *p,
282 struct sxgbe_extra_stats *x);
284 /* Get rx timestamp status */
285 int (*get_rx_ctxt_tstamp_status)(struct sxgbe_rx_ctxt_desc *p);
287 /* Get timestamp value for rx, need to check this */
288 u64 (*get_timestamp)(struct sxgbe_rx_ctxt_desc *p);
291 const struct sxgbe_desc_ops *sxgbe_get_desc_ops(void);
293 #endif /* __SXGBE_DESC_H__ */