1 // SPDX-License-Identifier: GPL-2.0
2 /* SuperH Ethernet device driver
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
6 * Copyright (C) 2008-2014 Renesas Solutions Corp.
7 * Copyright (C) 2013-2017 Cogent Embedded, Inc.
8 * Copyright (C) 2014 Codethink Limited
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/spinlock.h>
14 #include <linux/interrupt.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/etherdevice.h>
17 #include <linux/delay.h>
18 #include <linux/platform_device.h>
19 #include <linux/mdio-bitbang.h>
20 #include <linux/netdevice.h>
22 #include <linux/of_device.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_net.h>
25 #include <linux/phy.h>
26 #include <linux/cache.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/slab.h>
30 #include <linux/ethtool.h>
31 #include <linux/if_vlan.h>
32 #include <linux/sh_eth.h>
33 #include <linux/of_mdio.h>
37 #define SH_ETH_DEF_MSG_ENABLE \
43 #define SH_ETH_OFFSET_INVALID ((u16)~0)
45 #define SH_ETH_OFFSET_DEFAULTS \
46 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
48 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
49 SH_ETH_OFFSET_DEFAULTS,
104 [TSU_CTRST] = 0x0004,
105 [TSU_FWEN0] = 0x0010,
106 [TSU_FWEN1] = 0x0014,
108 [TSU_BSYSL0] = 0x0020,
109 [TSU_BSYSL1] = 0x0024,
110 [TSU_PRISL0] = 0x0028,
111 [TSU_PRISL1] = 0x002c,
112 [TSU_FWSL0] = 0x0030,
113 [TSU_FWSL1] = 0x0034,
114 [TSU_FWSLC] = 0x0038,
115 [TSU_QTAGM0] = 0x0040,
116 [TSU_QTAGM1] = 0x0044,
118 [TSU_FWINMK] = 0x0054,
119 [TSU_ADQT0] = 0x0048,
120 [TSU_ADQT1] = 0x004c,
121 [TSU_VTAG0] = 0x0058,
122 [TSU_VTAG1] = 0x005c,
123 [TSU_ADSBSY] = 0x0060,
125 [TSU_POST1] = 0x0070,
126 [TSU_POST2] = 0x0074,
127 [TSU_POST3] = 0x0078,
128 [TSU_POST4] = 0x007c,
129 [TSU_ADRH0] = 0x0100,
145 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
146 SH_ETH_OFFSET_DEFAULTS,
191 [TSU_CTRST] = 0x0004,
192 [TSU_FWSLC] = 0x0038,
193 [TSU_VTAG0] = 0x0058,
194 [TSU_ADSBSY] = 0x0060,
196 [TSU_POST1] = 0x0070,
197 [TSU_POST2] = 0x0074,
198 [TSU_POST3] = 0x0078,
199 [TSU_POST4] = 0x007c,
200 [TSU_ADRH0] = 0x0100,
208 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
209 SH_ETH_OFFSET_DEFAULTS,
256 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
257 SH_ETH_OFFSET_DEFAULTS,
310 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
311 SH_ETH_OFFSET_DEFAULTS,
359 [TSU_CTRST] = 0x0004,
360 [TSU_FWEN0] = 0x0010,
361 [TSU_FWEN1] = 0x0014,
363 [TSU_BSYSL0] = 0x0020,
364 [TSU_BSYSL1] = 0x0024,
365 [TSU_PRISL0] = 0x0028,
366 [TSU_PRISL1] = 0x002c,
367 [TSU_FWSL0] = 0x0030,
368 [TSU_FWSL1] = 0x0034,
369 [TSU_FWSLC] = 0x0038,
370 [TSU_QTAGM0] = 0x0040,
371 [TSU_QTAGM1] = 0x0044,
372 [TSU_ADQT0] = 0x0048,
373 [TSU_ADQT1] = 0x004c,
375 [TSU_FWINMK] = 0x0054,
376 [TSU_ADSBSY] = 0x0060,
378 [TSU_POST1] = 0x0070,
379 [TSU_POST2] = 0x0074,
380 [TSU_POST3] = 0x0078,
381 [TSU_POST4] = 0x007c,
396 [TSU_ADRH0] = 0x0100,
399 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
400 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
402 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
404 struct sh_eth_private *mdp = netdev_priv(ndev);
405 u16 offset = mdp->reg_offset[enum_index];
407 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
410 iowrite32(data, mdp->addr + offset);
413 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
415 struct sh_eth_private *mdp = netdev_priv(ndev);
416 u16 offset = mdp->reg_offset[enum_index];
418 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
421 return ioread32(mdp->addr + offset);
424 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
427 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
431 static u16 sh_eth_tsu_get_offset(struct sh_eth_private *mdp, int enum_index)
433 return mdp->reg_offset[enum_index];
436 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
439 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
441 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
444 iowrite32(data, mdp->tsu_addr + offset);
447 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
449 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
451 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
454 return ioread32(mdp->tsu_addr + offset);
457 static void sh_eth_soft_swap(char *src, int len)
459 #ifdef __LITTLE_ENDIAN
461 u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32));
463 for (; p < maxp; p++)
468 static void sh_eth_select_mii(struct net_device *ndev)
470 struct sh_eth_private *mdp = netdev_priv(ndev);
473 switch (mdp->phy_interface) {
474 case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID:
477 case PHY_INTERFACE_MODE_GMII:
480 case PHY_INTERFACE_MODE_MII:
483 case PHY_INTERFACE_MODE_RMII:
488 "PHY interface mode was not setup. Set to MII.\n");
493 sh_eth_write(ndev, value, RMII_MII);
496 static void sh_eth_set_duplex(struct net_device *ndev)
498 struct sh_eth_private *mdp = netdev_priv(ndev);
500 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
503 static void sh_eth_chip_reset(struct net_device *ndev)
505 struct sh_eth_private *mdp = netdev_priv(ndev);
508 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
512 static int sh_eth_soft_reset(struct net_device *ndev)
514 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
516 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
521 static int sh_eth_check_soft_reset(struct net_device *ndev)
525 for (cnt = 100; cnt > 0; cnt--) {
526 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
531 netdev_err(ndev, "Device reset failed\n");
535 static int sh_eth_soft_reset_gether(struct net_device *ndev)
537 struct sh_eth_private *mdp = netdev_priv(ndev);
540 sh_eth_write(ndev, EDSR_ENALL, EDSR);
541 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
543 ret = sh_eth_check_soft_reset(ndev);
548 sh_eth_write(ndev, 0, TDLAR);
549 sh_eth_write(ndev, 0, TDFAR);
550 sh_eth_write(ndev, 0, TDFXR);
551 sh_eth_write(ndev, 0, TDFFR);
552 sh_eth_write(ndev, 0, RDLAR);
553 sh_eth_write(ndev, 0, RDFAR);
554 sh_eth_write(ndev, 0, RDFXR);
555 sh_eth_write(ndev, 0, RDFFR);
557 /* Reset HW CRC register */
558 if (mdp->cd->hw_checksum)
559 sh_eth_write(ndev, 0, CSMR);
561 /* Select MII mode */
562 if (mdp->cd->select_mii)
563 sh_eth_select_mii(ndev);
568 static void sh_eth_set_rate_gether(struct net_device *ndev)
570 struct sh_eth_private *mdp = netdev_priv(ndev);
572 switch (mdp->speed) {
573 case 10: /* 10BASE */
574 sh_eth_write(ndev, GECMR_10, GECMR);
576 case 100:/* 100BASE */
577 sh_eth_write(ndev, GECMR_100, GECMR);
579 case 1000: /* 1000BASE */
580 sh_eth_write(ndev, GECMR_1000, GECMR);
587 static struct sh_eth_cpu_data r7s72100_data = {
588 .soft_reset = sh_eth_soft_reset_gether,
590 .chip_reset = sh_eth_chip_reset,
591 .set_duplex = sh_eth_set_duplex,
593 .register_type = SH_ETH_REG_FAST_RZ,
595 .edtrr_trns = EDTRR_TRNS_GETHER,
596 .ecsr_value = ECSR_ICD,
597 .ecsipr_value = ECSIPR_ICDIP,
598 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
599 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
601 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
602 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
603 EESIPR_RMAFIP | EESIPR_RRFIP |
604 EESIPR_RTLFIP | EESIPR_RTSFIP |
605 EESIPR_PREIP | EESIPR_CERFIP,
607 .tx_check = EESR_TC1 | EESR_FTC,
608 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
609 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
611 .fdr_value = 0x0000070f,
613 .trscer_err_mask = DESC_I_RINT8 | DESC_I_RINT5,
629 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
631 sh_eth_chip_reset(ndev);
633 sh_eth_select_mii(ndev);
637 static struct sh_eth_cpu_data r8a7740_data = {
638 .soft_reset = sh_eth_soft_reset_gether,
640 .chip_reset = sh_eth_chip_reset_r8a7740,
641 .set_duplex = sh_eth_set_duplex,
642 .set_rate = sh_eth_set_rate_gether,
644 .register_type = SH_ETH_REG_GIGABIT,
646 .edtrr_trns = EDTRR_TRNS_GETHER,
647 .ecsr_value = ECSR_ICD | ECSR_MPD,
648 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
649 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
650 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
651 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
652 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
653 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
654 EESIPR_CEEFIP | EESIPR_CELFIP |
655 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
656 EESIPR_PREIP | EESIPR_CERFIP,
658 .tx_check = EESR_TC1 | EESR_FTC,
659 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
660 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
662 .fdr_value = 0x0000070f,
680 /* There is CPU dependent code */
681 static void sh_eth_set_rate_rcar(struct net_device *ndev)
683 struct sh_eth_private *mdp = netdev_priv(ndev);
685 switch (mdp->speed) {
686 case 10: /* 10BASE */
687 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
689 case 100:/* 100BASE */
690 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
696 static struct sh_eth_cpu_data rcar_gen1_data = {
697 .soft_reset = sh_eth_soft_reset,
699 .set_duplex = sh_eth_set_duplex,
700 .set_rate = sh_eth_set_rate_rcar,
702 .register_type = SH_ETH_REG_FAST_RCAR,
704 .edtrr_trns = EDTRR_TRNS_ETHER,
705 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
706 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
707 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
708 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
709 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
710 EESIPR_RMAFIP | EESIPR_RRFIP |
711 EESIPR_RTLFIP | EESIPR_RTSFIP |
712 EESIPR_PREIP | EESIPR_CERFIP,
714 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
715 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
716 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
717 .fdr_value = 0x00000f0f,
726 /* R-Car Gen2 and RZ/G1 */
727 static struct sh_eth_cpu_data rcar_gen2_data = {
728 .soft_reset = sh_eth_soft_reset,
730 .set_duplex = sh_eth_set_duplex,
731 .set_rate = sh_eth_set_rate_rcar,
733 .register_type = SH_ETH_REG_FAST_RCAR,
735 .edtrr_trns = EDTRR_TRNS_ETHER,
736 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
737 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
739 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
740 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
741 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
742 EESIPR_RMAFIP | EESIPR_RRFIP |
743 EESIPR_RTLFIP | EESIPR_RTSFIP |
744 EESIPR_PREIP | EESIPR_CERFIP,
746 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
747 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
748 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
749 .fdr_value = 0x00000f0f,
751 .trscer_err_mask = DESC_I_RINT8,
763 static struct sh_eth_cpu_data r8a77980_data = {
764 .soft_reset = sh_eth_soft_reset_gether,
766 .set_duplex = sh_eth_set_duplex,
767 .set_rate = sh_eth_set_rate_gether,
769 .register_type = SH_ETH_REG_GIGABIT,
771 .edtrr_trns = EDTRR_TRNS_GETHER,
772 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
773 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
775 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
776 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
777 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
778 EESIPR_RMAFIP | EESIPR_RRFIP |
779 EESIPR_RTLFIP | EESIPR_RTSFIP |
780 EESIPR_PREIP | EESIPR_CERFIP,
782 .tx_check = EESR_FTC | EESR_CD | EESR_TRO,
783 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
784 EESR_RFE | EESR_RDE | EESR_RFRMER |
785 EESR_TFE | EESR_TDE | EESR_ECI,
786 .fdr_value = 0x0000070f,
805 static struct sh_eth_cpu_data r7s9210_data = {
806 .soft_reset = sh_eth_soft_reset,
808 .set_duplex = sh_eth_set_duplex,
809 .set_rate = sh_eth_set_rate_rcar,
811 .register_type = SH_ETH_REG_FAST_SH4,
813 .edtrr_trns = EDTRR_TRNS_ETHER,
814 .ecsr_value = ECSR_ICD,
815 .ecsipr_value = ECSIPR_ICDIP,
816 .eesipr_value = EESIPR_TWBIP | EESIPR_TABTIP | EESIPR_RABTIP |
817 EESIPR_RFCOFIP | EESIPR_ECIIP | EESIPR_FTCIP |
818 EESIPR_TDEIP | EESIPR_TFUFIP | EESIPR_FRIP |
819 EESIPR_RDEIP | EESIPR_RFOFIP | EESIPR_CNDIP |
820 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
821 EESIPR_RMAFIP | EESIPR_RRFIP | EESIPR_RTLFIP |
822 EESIPR_RTSFIP | EESIPR_PREIP | EESIPR_CERFIP,
824 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
825 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
826 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
828 .fdr_value = 0x0000070f,
830 .trscer_err_mask = DESC_I_RINT8 | DESC_I_RINT5,
840 #endif /* CONFIG_OF */
842 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
844 struct sh_eth_private *mdp = netdev_priv(ndev);
846 switch (mdp->speed) {
847 case 10: /* 10BASE */
848 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
850 case 100:/* 100BASE */
851 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
857 static struct sh_eth_cpu_data sh7724_data = {
858 .soft_reset = sh_eth_soft_reset,
860 .set_duplex = sh_eth_set_duplex,
861 .set_rate = sh_eth_set_rate_sh7724,
863 .register_type = SH_ETH_REG_FAST_SH4,
865 .edtrr_trns = EDTRR_TRNS_ETHER,
866 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
867 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
868 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
869 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
870 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
871 EESIPR_RMAFIP | EESIPR_RRFIP |
872 EESIPR_RTLFIP | EESIPR_RTSFIP |
873 EESIPR_PREIP | EESIPR_CERFIP,
875 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
876 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
877 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
886 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
888 struct sh_eth_private *mdp = netdev_priv(ndev);
890 switch (mdp->speed) {
891 case 10: /* 10BASE */
892 sh_eth_write(ndev, 0, RTRATE);
894 case 100:/* 100BASE */
895 sh_eth_write(ndev, 1, RTRATE);
901 static struct sh_eth_cpu_data sh7757_data = {
902 .soft_reset = sh_eth_soft_reset,
904 .set_duplex = sh_eth_set_duplex,
905 .set_rate = sh_eth_set_rate_sh7757,
907 .register_type = SH_ETH_REG_FAST_SH4,
909 .edtrr_trns = EDTRR_TRNS_ETHER,
910 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
911 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
912 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
913 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
914 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
915 EESIPR_CEEFIP | EESIPR_CELFIP |
916 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
917 EESIPR_PREIP | EESIPR_CERFIP,
919 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
920 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
921 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
923 .irq_flags = IRQF_SHARED,
934 #define SH_GIGA_ETH_BASE 0xfee00000UL
935 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
936 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
937 static void sh_eth_chip_reset_giga(struct net_device *ndev)
939 u32 mahr[2], malr[2];
942 /* save MAHR and MALR */
943 for (i = 0; i < 2; i++) {
944 malr[i] = ioread32((void *)GIGA_MALR(i));
945 mahr[i] = ioread32((void *)GIGA_MAHR(i));
948 sh_eth_chip_reset(ndev);
950 /* restore MAHR and MALR */
951 for (i = 0; i < 2; i++) {
952 iowrite32(malr[i], (void *)GIGA_MALR(i));
953 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
957 static void sh_eth_set_rate_giga(struct net_device *ndev)
959 struct sh_eth_private *mdp = netdev_priv(ndev);
961 switch (mdp->speed) {
962 case 10: /* 10BASE */
963 sh_eth_write(ndev, 0x00000000, GECMR);
965 case 100:/* 100BASE */
966 sh_eth_write(ndev, 0x00000010, GECMR);
968 case 1000: /* 1000BASE */
969 sh_eth_write(ndev, 0x00000020, GECMR);
974 /* SH7757(GETHERC) */
975 static struct sh_eth_cpu_data sh7757_data_giga = {
976 .soft_reset = sh_eth_soft_reset_gether,
978 .chip_reset = sh_eth_chip_reset_giga,
979 .set_duplex = sh_eth_set_duplex,
980 .set_rate = sh_eth_set_rate_giga,
982 .register_type = SH_ETH_REG_GIGABIT,
984 .edtrr_trns = EDTRR_TRNS_GETHER,
985 .ecsr_value = ECSR_ICD | ECSR_MPD,
986 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
987 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
988 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
989 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
990 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
991 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
992 EESIPR_CEEFIP | EESIPR_CELFIP |
993 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
994 EESIPR_PREIP | EESIPR_CERFIP,
996 .tx_check = EESR_TC1 | EESR_FTC,
997 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
998 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
1000 .fdr_value = 0x0000072f,
1002 .irq_flags = IRQF_SHARED,
1018 static struct sh_eth_cpu_data sh7734_data = {
1019 .soft_reset = sh_eth_soft_reset_gether,
1021 .chip_reset = sh_eth_chip_reset,
1022 .set_duplex = sh_eth_set_duplex,
1023 .set_rate = sh_eth_set_rate_gether,
1025 .register_type = SH_ETH_REG_GIGABIT,
1027 .edtrr_trns = EDTRR_TRNS_GETHER,
1028 .ecsr_value = ECSR_ICD | ECSR_MPD,
1029 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
1030 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1031 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1032 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1033 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1034 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1035 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1036 EESIPR_PREIP | EESIPR_CERFIP,
1038 .tx_check = EESR_TC1 | EESR_FTC,
1039 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1040 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
1059 static struct sh_eth_cpu_data sh7763_data = {
1060 .soft_reset = sh_eth_soft_reset_gether,
1062 .chip_reset = sh_eth_chip_reset,
1063 .set_duplex = sh_eth_set_duplex,
1064 .set_rate = sh_eth_set_rate_gether,
1066 .register_type = SH_ETH_REG_GIGABIT,
1068 .edtrr_trns = EDTRR_TRNS_GETHER,
1069 .ecsr_value = ECSR_ICD | ECSR_MPD,
1070 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
1071 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1072 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1073 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1074 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1075 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1076 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1077 EESIPR_PREIP | EESIPR_CERFIP,
1079 .tx_check = EESR_TC1 | EESR_FTC,
1080 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1081 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
1092 .irq_flags = IRQF_SHARED,
1098 static struct sh_eth_cpu_data sh7619_data = {
1099 .soft_reset = sh_eth_soft_reset,
1101 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1103 .edtrr_trns = EDTRR_TRNS_ETHER,
1104 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1105 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1106 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1107 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1108 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1109 EESIPR_CEEFIP | EESIPR_CELFIP |
1110 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1111 EESIPR_PREIP | EESIPR_CERFIP,
1119 static struct sh_eth_cpu_data sh771x_data = {
1120 .soft_reset = sh_eth_soft_reset,
1122 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1124 .edtrr_trns = EDTRR_TRNS_ETHER,
1125 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1126 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1127 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1128 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1129 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1130 EESIPR_CEEFIP | EESIPR_CELFIP |
1131 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1132 EESIPR_PREIP | EESIPR_CERFIP,
1134 .trscer_err_mask = DESC_I_RINT8,
1140 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
1142 if (!cd->ecsr_value)
1143 cd->ecsr_value = DEFAULT_ECSR_INIT;
1145 if (!cd->ecsipr_value)
1146 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
1148 if (!cd->fcftr_value)
1149 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
1150 DEFAULT_FIFO_F_D_RFD;
1153 cd->fdr_value = DEFAULT_FDR_INIT;
1156 cd->tx_check = DEFAULT_TX_CHECK;
1158 if (!cd->eesr_err_check)
1159 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
1161 if (!cd->trscer_err_mask)
1162 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
1165 static void sh_eth_set_receive_align(struct sk_buff *skb)
1167 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
1170 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
1173 /* Program the hardware MAC address from dev->dev_addr. */
1174 static void update_mac_address(struct net_device *ndev)
1177 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1178 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
1180 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1183 /* Get MAC address from SuperH MAC address register
1185 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1186 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1187 * When you want use this device, you must set MAC address in bootloader.
1190 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1192 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1193 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1195 u32 mahr = sh_eth_read(ndev, MAHR);
1196 u32 malr = sh_eth_read(ndev, MALR);
1198 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1199 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1200 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
1201 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
1202 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
1203 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
1208 void (*set_gate)(void *addr);
1209 struct mdiobb_ctrl ctrl;
1213 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1215 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1218 if (bitbang->set_gate)
1219 bitbang->set_gate(bitbang->addr);
1221 pir = ioread32(bitbang->addr);
1226 iowrite32(pir, bitbang->addr);
1229 /* Data I/O pin control */
1230 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1232 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1236 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1238 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1242 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1244 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1246 if (bitbang->set_gate)
1247 bitbang->set_gate(bitbang->addr);
1249 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1252 /* MDC pin control */
1253 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1255 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1258 /* mdio bus control struct */
1259 static struct mdiobb_ops bb_ops = {
1260 .owner = THIS_MODULE,
1261 .set_mdc = sh_mdc_ctrl,
1262 .set_mdio_dir = sh_mmd_ctrl,
1263 .set_mdio_data = sh_set_mdio,
1264 .get_mdio_data = sh_get_mdio,
1267 /* free Tx skb function */
1268 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1270 struct sh_eth_private *mdp = netdev_priv(ndev);
1271 struct sh_eth_txdesc *txdesc;
1276 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1277 entry = mdp->dirty_tx % mdp->num_tx_ring;
1278 txdesc = &mdp->tx_ring[entry];
1279 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1280 if (sent_only && !sent)
1282 /* TACT bit must be checked before all the following reads */
1284 netif_info(mdp, tx_done, ndev,
1285 "tx entry %d status 0x%08x\n",
1286 entry, le32_to_cpu(txdesc->status));
1287 /* Free the original skb. */
1288 if (mdp->tx_skbuff[entry]) {
1289 dma_unmap_single(&mdp->pdev->dev,
1290 le32_to_cpu(txdesc->addr),
1291 le32_to_cpu(txdesc->len) >> 16,
1293 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1294 mdp->tx_skbuff[entry] = NULL;
1297 txdesc->status = cpu_to_le32(TD_TFP);
1298 if (entry >= mdp->num_tx_ring - 1)
1299 txdesc->status |= cpu_to_le32(TD_TDLE);
1302 ndev->stats.tx_packets++;
1303 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1309 /* free skb and descriptor buffer */
1310 static void sh_eth_ring_free(struct net_device *ndev)
1312 struct sh_eth_private *mdp = netdev_priv(ndev);
1316 for (i = 0; i < mdp->num_rx_ring; i++) {
1317 if (mdp->rx_skbuff[i]) {
1318 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1320 dma_unmap_single(&mdp->pdev->dev,
1321 le32_to_cpu(rxdesc->addr),
1322 ALIGN(mdp->rx_buf_sz, 32),
1326 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1327 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring,
1329 mdp->rx_ring = NULL;
1332 /* Free Rx skb ringbuffer */
1333 if (mdp->rx_skbuff) {
1334 for (i = 0; i < mdp->num_rx_ring; i++)
1335 dev_kfree_skb(mdp->rx_skbuff[i]);
1337 kfree(mdp->rx_skbuff);
1338 mdp->rx_skbuff = NULL;
1341 sh_eth_tx_free(ndev, false);
1343 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1344 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring,
1346 mdp->tx_ring = NULL;
1349 /* Free Tx skb ringbuffer */
1350 kfree(mdp->tx_skbuff);
1351 mdp->tx_skbuff = NULL;
1354 /* format skb and descriptor buffer */
1355 static void sh_eth_ring_format(struct net_device *ndev)
1357 struct sh_eth_private *mdp = netdev_priv(ndev);
1359 struct sk_buff *skb;
1360 struct sh_eth_rxdesc *rxdesc = NULL;
1361 struct sh_eth_txdesc *txdesc = NULL;
1362 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1363 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1364 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1365 dma_addr_t dma_addr;
1373 memset(mdp->rx_ring, 0, rx_ringsize);
1375 /* build Rx ring buffer */
1376 for (i = 0; i < mdp->num_rx_ring; i++) {
1378 mdp->rx_skbuff[i] = NULL;
1379 skb = netdev_alloc_skb(ndev, skbuff_size);
1382 sh_eth_set_receive_align(skb);
1384 /* The size of the buffer is a multiple of 32 bytes. */
1385 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1386 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len,
1388 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1392 mdp->rx_skbuff[i] = skb;
1395 rxdesc = &mdp->rx_ring[i];
1396 rxdesc->len = cpu_to_le32(buf_len << 16);
1397 rxdesc->addr = cpu_to_le32(dma_addr);
1398 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1400 /* Rx descriptor address set */
1402 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1403 if (mdp->cd->xdfar_rw)
1404 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1408 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1410 /* Mark the last entry as wrapping the ring. */
1412 rxdesc->status |= cpu_to_le32(RD_RDLE);
1414 memset(mdp->tx_ring, 0, tx_ringsize);
1416 /* build Tx ring buffer */
1417 for (i = 0; i < mdp->num_tx_ring; i++) {
1418 mdp->tx_skbuff[i] = NULL;
1419 txdesc = &mdp->tx_ring[i];
1420 txdesc->status = cpu_to_le32(TD_TFP);
1421 txdesc->len = cpu_to_le32(0);
1423 /* Tx descriptor address set */
1424 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1425 if (mdp->cd->xdfar_rw)
1426 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1430 txdesc->status |= cpu_to_le32(TD_TDLE);
1433 /* Get skb and descriptor buffer */
1434 static int sh_eth_ring_init(struct net_device *ndev)
1436 struct sh_eth_private *mdp = netdev_priv(ndev);
1437 int rx_ringsize, tx_ringsize;
1439 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1440 * card needs room to do 8 byte alignment, +2 so we can reserve
1441 * the first 2 bytes, and +16 gets room for the status word from the
1444 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1445 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1446 if (mdp->cd->rpadir)
1447 mdp->rx_buf_sz += NET_IP_ALIGN;
1449 /* Allocate RX and TX skb rings */
1450 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1452 if (!mdp->rx_skbuff)
1455 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1457 if (!mdp->tx_skbuff)
1460 /* Allocate all Rx descriptors. */
1461 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1462 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize,
1463 &mdp->rx_desc_dma, GFP_KERNEL);
1469 /* Allocate all Tx descriptors. */
1470 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1471 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize,
1472 &mdp->tx_desc_dma, GFP_KERNEL);
1478 /* Free Rx and Tx skb ring buffer and DMA buffer */
1479 sh_eth_ring_free(ndev);
1484 static int sh_eth_dev_init(struct net_device *ndev)
1486 struct sh_eth_private *mdp = netdev_priv(ndev);
1490 ret = mdp->cd->soft_reset(ndev);
1494 if (mdp->cd->rmiimode)
1495 sh_eth_write(ndev, 0x1, RMIIMODE);
1497 /* Descriptor format */
1498 sh_eth_ring_format(ndev);
1499 if (mdp->cd->rpadir)
1500 sh_eth_write(ndev, NET_IP_ALIGN << 16, RPADIR);
1502 /* all sh_eth int mask */
1503 sh_eth_write(ndev, 0, EESIPR);
1505 #if defined(__LITTLE_ENDIAN)
1506 if (mdp->cd->hw_swap)
1507 sh_eth_write(ndev, EDMR_EL, EDMR);
1510 sh_eth_write(ndev, 0, EDMR);
1513 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1514 sh_eth_write(ndev, 0, TFTR);
1516 /* Frame recv control (enable multiple-packets per rx irq) */
1517 sh_eth_write(ndev, RMCR_RNC, RMCR);
1519 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1521 /* DMA transfer burst mode */
1523 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST);
1525 /* Burst cycle count upper-limit */
1527 sh_eth_write(ndev, 0x800, BCULR);
1529 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1531 if (!mdp->cd->no_trimd)
1532 sh_eth_write(ndev, 0, TRIMD);
1534 /* Recv frame limit set register */
1535 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1538 sh_eth_modify(ndev, EESR, 0, 0);
1539 mdp->irq_enabled = true;
1540 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1542 /* PAUSE Prohibition */
1543 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1544 ECMR_TE | ECMR_RE, ECMR);
1546 if (mdp->cd->set_rate)
1547 mdp->cd->set_rate(ndev);
1549 /* E-MAC Status Register clear */
1550 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1552 /* E-MAC Interrupt Enable register */
1553 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1555 /* Set MAC address */
1556 update_mac_address(ndev);
1560 sh_eth_write(ndev, 1, APR);
1562 sh_eth_write(ndev, 1, MPR);
1563 if (mdp->cd->tpauser)
1564 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1566 /* Setting the Rx mode will start the Rx process. */
1567 sh_eth_write(ndev, EDRRR_R, EDRRR);
1572 static void sh_eth_dev_exit(struct net_device *ndev)
1574 struct sh_eth_private *mdp = netdev_priv(ndev);
1577 /* Deactivate all TX descriptors, so DMA should stop at next
1578 * packet boundary if it's currently running
1580 for (i = 0; i < mdp->num_tx_ring; i++)
1581 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1583 /* Disable TX FIFO egress to MAC */
1584 sh_eth_rcv_snd_disable(ndev);
1586 /* Stop RX DMA at next packet boundary */
1587 sh_eth_write(ndev, 0, EDRRR);
1589 /* Aside from TX DMA, we can't tell when the hardware is
1590 * really stopped, so we need to reset to make sure.
1591 * Before doing that, wait for long enough to *probably*
1592 * finish transmitting the last packet and poll stats.
1594 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1595 sh_eth_get_stats(ndev);
1596 mdp->cd->soft_reset(ndev);
1598 /* Set the RMII mode again if required */
1599 if (mdp->cd->rmiimode)
1600 sh_eth_write(ndev, 0x1, RMIIMODE);
1602 /* Set MAC address again */
1603 update_mac_address(ndev);
1606 /* Packet receive function */
1607 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1609 struct sh_eth_private *mdp = netdev_priv(ndev);
1610 struct sh_eth_rxdesc *rxdesc;
1612 int entry = mdp->cur_rx % mdp->num_rx_ring;
1613 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1615 struct sk_buff *skb;
1617 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1618 dma_addr_t dma_addr;
1622 boguscnt = min(boguscnt, *quota);
1624 rxdesc = &mdp->rx_ring[entry];
1625 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1626 /* RACT bit must be checked before all the following reads */
1628 desc_status = le32_to_cpu(rxdesc->status);
1629 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1634 netif_info(mdp, rx_status, ndev,
1635 "rx entry %d status 0x%08x len %d\n",
1636 entry, desc_status, pkt_len);
1638 if (!(desc_status & RDFEND))
1639 ndev->stats.rx_length_errors++;
1641 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1642 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1643 * bit 0. However, in case of the R8A7740 and R7S72100
1644 * the RFS bits are from bit 25 to bit 16. So, the
1645 * driver needs right shifting by 16.
1647 if (mdp->cd->hw_checksum)
1650 skb = mdp->rx_skbuff[entry];
1651 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1652 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1653 ndev->stats.rx_errors++;
1654 if (desc_status & RD_RFS1)
1655 ndev->stats.rx_crc_errors++;
1656 if (desc_status & RD_RFS2)
1657 ndev->stats.rx_frame_errors++;
1658 if (desc_status & RD_RFS3)
1659 ndev->stats.rx_length_errors++;
1660 if (desc_status & RD_RFS4)
1661 ndev->stats.rx_length_errors++;
1662 if (desc_status & RD_RFS6)
1663 ndev->stats.rx_missed_errors++;
1664 if (desc_status & RD_RFS10)
1665 ndev->stats.rx_over_errors++;
1667 dma_addr = le32_to_cpu(rxdesc->addr);
1668 if (!mdp->cd->hw_swap)
1670 phys_to_virt(ALIGN(dma_addr, 4)),
1672 mdp->rx_skbuff[entry] = NULL;
1673 if (mdp->cd->rpadir)
1674 skb_reserve(skb, NET_IP_ALIGN);
1675 dma_unmap_single(&mdp->pdev->dev, dma_addr,
1676 ALIGN(mdp->rx_buf_sz, 32),
1678 skb_put(skb, pkt_len);
1679 skb->protocol = eth_type_trans(skb, ndev);
1680 netif_receive_skb(skb);
1681 ndev->stats.rx_packets++;
1682 ndev->stats.rx_bytes += pkt_len;
1683 if (desc_status & RD_RFS8)
1684 ndev->stats.multicast++;
1686 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1687 rxdesc = &mdp->rx_ring[entry];
1690 /* Refill the Rx ring buffers. */
1691 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1692 entry = mdp->dirty_rx % mdp->num_rx_ring;
1693 rxdesc = &mdp->rx_ring[entry];
1694 /* The size of the buffer is 32 byte boundary. */
1695 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1696 rxdesc->len = cpu_to_le32(buf_len << 16);
1698 if (mdp->rx_skbuff[entry] == NULL) {
1699 skb = netdev_alloc_skb(ndev, skbuff_size);
1701 break; /* Better luck next round. */
1702 sh_eth_set_receive_align(skb);
1703 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data,
1704 buf_len, DMA_FROM_DEVICE);
1705 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1709 mdp->rx_skbuff[entry] = skb;
1711 skb_checksum_none_assert(skb);
1712 rxdesc->addr = cpu_to_le32(dma_addr);
1714 dma_wmb(); /* RACT bit must be set after all the above writes */
1715 if (entry >= mdp->num_rx_ring - 1)
1717 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1719 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1722 /* Restart Rx engine if stopped. */
1723 /* If we don't need to check status, don't. -KDU */
1724 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1725 /* fix the values for the next receiving if RDE is set */
1726 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) {
1727 u32 count = (sh_eth_read(ndev, RDFAR) -
1728 sh_eth_read(ndev, RDLAR)) >> 4;
1730 mdp->cur_rx = count;
1731 mdp->dirty_rx = count;
1733 sh_eth_write(ndev, EDRRR_R, EDRRR);
1736 *quota -= limit - boguscnt - 1;
1741 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1743 /* disable tx and rx */
1744 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1747 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1749 /* enable tx and rx */
1750 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1753 /* E-MAC interrupt handler */
1754 static void sh_eth_emac_interrupt(struct net_device *ndev)
1756 struct sh_eth_private *mdp = netdev_priv(ndev);
1760 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1761 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1762 if (felic_stat & ECSR_ICD)
1763 ndev->stats.tx_carrier_errors++;
1764 if (felic_stat & ECSR_MPD)
1765 pm_wakeup_event(&mdp->pdev->dev, 0);
1766 if (felic_stat & ECSR_LCHNG) {
1768 if (mdp->cd->no_psr || mdp->no_ether_link)
1770 link_stat = sh_eth_read(ndev, PSR);
1771 if (mdp->ether_link_active_low)
1772 link_stat = ~link_stat;
1773 if (!(link_stat & PHY_ST_LINK)) {
1774 sh_eth_rcv_snd_disable(ndev);
1777 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
1779 sh_eth_modify(ndev, ECSR, 0, 0);
1780 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
1781 /* enable tx and rx */
1782 sh_eth_rcv_snd_enable(ndev);
1787 /* error control function */
1788 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1790 struct sh_eth_private *mdp = netdev_priv(ndev);
1793 if (intr_status & EESR_TWB) {
1794 /* Unused write back interrupt */
1795 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1796 ndev->stats.tx_aborted_errors++;
1797 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1801 if (intr_status & EESR_RABT) {
1802 /* Receive Abort int */
1803 if (intr_status & EESR_RFRMER) {
1804 /* Receive Frame Overflow int */
1805 ndev->stats.rx_frame_errors++;
1809 if (intr_status & EESR_TDE) {
1810 /* Transmit Descriptor Empty int */
1811 ndev->stats.tx_fifo_errors++;
1812 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1815 if (intr_status & EESR_TFE) {
1816 /* FIFO under flow */
1817 ndev->stats.tx_fifo_errors++;
1818 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1821 if (intr_status & EESR_RDE) {
1822 /* Receive Descriptor Empty int */
1823 ndev->stats.rx_over_errors++;
1826 if (intr_status & EESR_RFE) {
1827 /* Receive FIFO Overflow int */
1828 ndev->stats.rx_fifo_errors++;
1831 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1833 ndev->stats.tx_fifo_errors++;
1834 netif_err(mdp, tx_err, ndev, "Address Error\n");
1837 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1838 if (mdp->cd->no_ade)
1840 if (intr_status & mask) {
1842 u32 edtrr = sh_eth_read(ndev, EDTRR);
1845 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1846 intr_status, mdp->cur_tx, mdp->dirty_tx,
1847 (u32)ndev->state, edtrr);
1848 /* dirty buffer free */
1849 sh_eth_tx_free(ndev, true);
1852 if (edtrr ^ mdp->cd->edtrr_trns) {
1854 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
1857 netif_wake_queue(ndev);
1861 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1863 struct net_device *ndev = netdev;
1864 struct sh_eth_private *mdp = netdev_priv(ndev);
1865 struct sh_eth_cpu_data *cd = mdp->cd;
1866 irqreturn_t ret = IRQ_NONE;
1867 u32 intr_status, intr_enable;
1869 spin_lock(&mdp->lock);
1871 /* Get interrupt status */
1872 intr_status = sh_eth_read(ndev, EESR);
1873 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1874 * enabled since it's the one that comes thru regardless of the mask,
1875 * and we need to fully handle it in sh_eth_emac_interrupt() in order
1876 * to quench it as it doesn't get cleared by just writing 1 to the ECI
1879 intr_enable = sh_eth_read(ndev, EESIPR);
1880 intr_status &= intr_enable | EESIPR_ECIIP;
1881 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1882 cd->eesr_err_check))
1887 if (unlikely(!mdp->irq_enabled)) {
1888 sh_eth_write(ndev, 0, EESIPR);
1892 if (intr_status & EESR_RX_CHECK) {
1893 if (napi_schedule_prep(&mdp->napi)) {
1894 /* Mask Rx interrupts */
1895 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1897 __napi_schedule(&mdp->napi);
1900 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1901 intr_status, intr_enable);
1906 if (intr_status & cd->tx_check) {
1907 /* Clear Tx interrupts */
1908 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1910 sh_eth_tx_free(ndev, true);
1911 netif_wake_queue(ndev);
1914 /* E-MAC interrupt */
1915 if (intr_status & EESR_ECI)
1916 sh_eth_emac_interrupt(ndev);
1918 if (intr_status & cd->eesr_err_check) {
1919 /* Clear error interrupts */
1920 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1922 sh_eth_error(ndev, intr_status);
1926 spin_unlock(&mdp->lock);
1931 static int sh_eth_poll(struct napi_struct *napi, int budget)
1933 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1935 struct net_device *ndev = napi->dev;
1940 intr_status = sh_eth_read(ndev, EESR);
1941 if (!(intr_status & EESR_RX_CHECK))
1943 /* Clear Rx interrupts */
1944 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1946 if (sh_eth_rx(ndev, intr_status, "a))
1950 napi_complete(napi);
1952 /* Reenable Rx interrupts */
1953 if (mdp->irq_enabled)
1954 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1956 return budget - quota;
1959 /* PHY state control function */
1960 static void sh_eth_adjust_link(struct net_device *ndev)
1962 struct sh_eth_private *mdp = netdev_priv(ndev);
1963 struct phy_device *phydev = ndev->phydev;
1964 unsigned long flags;
1967 spin_lock_irqsave(&mdp->lock, flags);
1969 /* Disable TX and RX right over here, if E-MAC change is ignored */
1970 if (mdp->cd->no_psr || mdp->no_ether_link)
1971 sh_eth_rcv_snd_disable(ndev);
1974 if (phydev->duplex != mdp->duplex) {
1976 mdp->duplex = phydev->duplex;
1977 if (mdp->cd->set_duplex)
1978 mdp->cd->set_duplex(ndev);
1981 if (phydev->speed != mdp->speed) {
1983 mdp->speed = phydev->speed;
1984 if (mdp->cd->set_rate)
1985 mdp->cd->set_rate(ndev);
1988 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1990 mdp->link = phydev->link;
1992 } else if (mdp->link) {
1999 /* Enable TX and RX right over here, if E-MAC change is ignored */
2000 if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link)
2001 sh_eth_rcv_snd_enable(ndev);
2004 spin_unlock_irqrestore(&mdp->lock, flags);
2006 if (new_state && netif_msg_link(mdp))
2007 phy_print_status(phydev);
2010 /* PHY init function */
2011 static int sh_eth_phy_init(struct net_device *ndev)
2013 struct device_node *np = ndev->dev.parent->of_node;
2014 struct sh_eth_private *mdp = netdev_priv(ndev);
2015 struct phy_device *phydev;
2021 /* Try connect to PHY */
2023 struct device_node *pn;
2025 pn = of_parse_phandle(np, "phy-handle", 0);
2026 phydev = of_phy_connect(ndev, pn,
2027 sh_eth_adjust_link, 0,
2028 mdp->phy_interface);
2032 phydev = ERR_PTR(-ENOENT);
2034 char phy_id[MII_BUS_ID_SIZE + 3];
2036 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2037 mdp->mii_bus->id, mdp->phy_id);
2039 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
2040 mdp->phy_interface);
2043 if (IS_ERR(phydev)) {
2044 netdev_err(ndev, "failed to connect PHY\n");
2045 return PTR_ERR(phydev);
2048 /* mask with MAC supported features */
2049 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) {
2050 int err = phy_set_max_speed(phydev, SPEED_100);
2052 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n");
2053 phy_disconnect(phydev);
2058 phy_attached_info(phydev);
2063 /* PHY control start function */
2064 static int sh_eth_phy_start(struct net_device *ndev)
2068 ret = sh_eth_phy_init(ndev);
2072 phy_start(ndev->phydev);
2077 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
2078 * version must be bumped as well. Just adding registers up to that
2079 * limit is fine, as long as the existing register indices don't
2082 #define SH_ETH_REG_DUMP_VERSION 1
2083 #define SH_ETH_REG_DUMP_MAX_REGS 256
2085 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
2087 struct sh_eth_private *mdp = netdev_priv(ndev);
2088 struct sh_eth_cpu_data *cd = mdp->cd;
2092 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
2094 /* Dump starts with a bitmap that tells ethtool which
2095 * registers are defined for this chip.
2097 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
2105 /* Add a register to the dump, if it has a defined offset.
2106 * This automatically skips most undefined registers, but for
2107 * some it is also necessary to check a capability flag in
2108 * struct sh_eth_cpu_data.
2110 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2111 #define add_reg_from(reg, read_expr) do { \
2112 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
2114 mark_reg_valid(reg); \
2115 *buf++ = read_expr; \
2120 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2121 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2187 if (cd->hw_checksum)
2193 add_tsu_reg(TSU_CTRST);
2194 if (cd->dual_port) {
2195 add_tsu_reg(TSU_FWEN0);
2196 add_tsu_reg(TSU_FWEN1);
2197 add_tsu_reg(TSU_FCM);
2198 add_tsu_reg(TSU_BSYSL0);
2199 add_tsu_reg(TSU_BSYSL1);
2200 add_tsu_reg(TSU_PRISL0);
2201 add_tsu_reg(TSU_PRISL1);
2202 add_tsu_reg(TSU_FWSL0);
2203 add_tsu_reg(TSU_FWSL1);
2205 add_tsu_reg(TSU_FWSLC);
2206 if (cd->dual_port) {
2207 add_tsu_reg(TSU_QTAGM0);
2208 add_tsu_reg(TSU_QTAGM1);
2209 add_tsu_reg(TSU_FWSR);
2210 add_tsu_reg(TSU_FWINMK);
2211 add_tsu_reg(TSU_ADQT0);
2212 add_tsu_reg(TSU_ADQT1);
2213 add_tsu_reg(TSU_VTAG0);
2214 add_tsu_reg(TSU_VTAG1);
2216 add_tsu_reg(TSU_ADSBSY);
2217 add_tsu_reg(TSU_TEN);
2218 add_tsu_reg(TSU_POST1);
2219 add_tsu_reg(TSU_POST2);
2220 add_tsu_reg(TSU_POST3);
2221 add_tsu_reg(TSU_POST4);
2222 /* This is the start of a table, not just a single register. */
2226 mark_reg_valid(TSU_ADRH0);
2227 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2228 *buf++ = ioread32(mdp->tsu_addr +
2229 mdp->reg_offset[TSU_ADRH0] +
2232 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2235 #undef mark_reg_valid
2243 static int sh_eth_get_regs_len(struct net_device *ndev)
2245 return __sh_eth_get_regs(ndev, NULL);
2248 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2251 struct sh_eth_private *mdp = netdev_priv(ndev);
2253 regs->version = SH_ETH_REG_DUMP_VERSION;
2255 pm_runtime_get_sync(&mdp->pdev->dev);
2256 __sh_eth_get_regs(ndev, buf);
2257 pm_runtime_put_sync(&mdp->pdev->dev);
2260 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2262 struct sh_eth_private *mdp = netdev_priv(ndev);
2263 return mdp->msg_enable;
2266 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2268 struct sh_eth_private *mdp = netdev_priv(ndev);
2269 mdp->msg_enable = value;
2272 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2273 "rx_current", "tx_current",
2274 "rx_dirty", "tx_dirty",
2276 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2278 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2282 return SH_ETH_STATS_LEN;
2288 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2289 struct ethtool_stats *stats, u64 *data)
2291 struct sh_eth_private *mdp = netdev_priv(ndev);
2294 /* device-specific stats */
2295 data[i++] = mdp->cur_rx;
2296 data[i++] = mdp->cur_tx;
2297 data[i++] = mdp->dirty_rx;
2298 data[i++] = mdp->dirty_tx;
2301 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2303 switch (stringset) {
2305 memcpy(data, sh_eth_gstrings_stats,
2306 sizeof(sh_eth_gstrings_stats));
2311 static void sh_eth_get_ringparam(struct net_device *ndev,
2312 struct ethtool_ringparam *ring)
2314 struct sh_eth_private *mdp = netdev_priv(ndev);
2316 ring->rx_max_pending = RX_RING_MAX;
2317 ring->tx_max_pending = TX_RING_MAX;
2318 ring->rx_pending = mdp->num_rx_ring;
2319 ring->tx_pending = mdp->num_tx_ring;
2322 static int sh_eth_set_ringparam(struct net_device *ndev,
2323 struct ethtool_ringparam *ring)
2325 struct sh_eth_private *mdp = netdev_priv(ndev);
2328 if (ring->tx_pending > TX_RING_MAX ||
2329 ring->rx_pending > RX_RING_MAX ||
2330 ring->tx_pending < TX_RING_MIN ||
2331 ring->rx_pending < RX_RING_MIN)
2333 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2336 if (netif_running(ndev)) {
2337 netif_device_detach(ndev);
2338 netif_tx_disable(ndev);
2340 /* Serialise with the interrupt handler and NAPI, then
2341 * disable interrupts. We have to clear the
2342 * irq_enabled flag first to ensure that interrupts
2343 * won't be re-enabled.
2345 mdp->irq_enabled = false;
2346 synchronize_irq(ndev->irq);
2347 napi_synchronize(&mdp->napi);
2348 sh_eth_write(ndev, 0x0000, EESIPR);
2350 sh_eth_dev_exit(ndev);
2352 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2353 sh_eth_ring_free(ndev);
2356 /* Set new parameters */
2357 mdp->num_rx_ring = ring->rx_pending;
2358 mdp->num_tx_ring = ring->tx_pending;
2360 if (netif_running(ndev)) {
2361 ret = sh_eth_ring_init(ndev);
2363 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2367 ret = sh_eth_dev_init(ndev);
2369 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2374 netif_device_attach(ndev);
2380 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2382 struct sh_eth_private *mdp = netdev_priv(ndev);
2387 if (mdp->cd->magic) {
2388 wol->supported = WAKE_MAGIC;
2389 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2393 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2395 struct sh_eth_private *mdp = netdev_priv(ndev);
2397 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC)
2400 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2402 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2407 static const struct ethtool_ops sh_eth_ethtool_ops = {
2408 .get_regs_len = sh_eth_get_regs_len,
2409 .get_regs = sh_eth_get_regs,
2410 .nway_reset = phy_ethtool_nway_reset,
2411 .get_msglevel = sh_eth_get_msglevel,
2412 .set_msglevel = sh_eth_set_msglevel,
2413 .get_link = ethtool_op_get_link,
2414 .get_strings = sh_eth_get_strings,
2415 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2416 .get_sset_count = sh_eth_get_sset_count,
2417 .get_ringparam = sh_eth_get_ringparam,
2418 .set_ringparam = sh_eth_set_ringparam,
2419 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2420 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2421 .get_wol = sh_eth_get_wol,
2422 .set_wol = sh_eth_set_wol,
2425 /* network device open function */
2426 static int sh_eth_open(struct net_device *ndev)
2428 struct sh_eth_private *mdp = netdev_priv(ndev);
2431 pm_runtime_get_sync(&mdp->pdev->dev);
2433 napi_enable(&mdp->napi);
2435 ret = request_irq(ndev->irq, sh_eth_interrupt,
2436 mdp->cd->irq_flags, ndev->name, ndev);
2438 netdev_err(ndev, "Can not assign IRQ number\n");
2442 /* Descriptor set */
2443 ret = sh_eth_ring_init(ndev);
2448 ret = sh_eth_dev_init(ndev);
2452 /* PHY control start*/
2453 ret = sh_eth_phy_start(ndev);
2457 netif_start_queue(ndev);
2464 free_irq(ndev->irq, ndev);
2466 napi_disable(&mdp->napi);
2467 pm_runtime_put_sync(&mdp->pdev->dev);
2471 /* Timeout function */
2472 static void sh_eth_tx_timeout(struct net_device *ndev)
2474 struct sh_eth_private *mdp = netdev_priv(ndev);
2475 struct sh_eth_rxdesc *rxdesc;
2478 netif_stop_queue(ndev);
2480 netif_err(mdp, timer, ndev,
2481 "transmit timed out, status %8.8x, resetting...\n",
2482 sh_eth_read(ndev, EESR));
2484 /* tx_errors count up */
2485 ndev->stats.tx_errors++;
2487 /* Free all the skbuffs in the Rx queue. */
2488 for (i = 0; i < mdp->num_rx_ring; i++) {
2489 rxdesc = &mdp->rx_ring[i];
2490 rxdesc->status = cpu_to_le32(0);
2491 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2492 dev_kfree_skb(mdp->rx_skbuff[i]);
2493 mdp->rx_skbuff[i] = NULL;
2495 for (i = 0; i < mdp->num_tx_ring; i++) {
2496 dev_kfree_skb(mdp->tx_skbuff[i]);
2497 mdp->tx_skbuff[i] = NULL;
2501 sh_eth_dev_init(ndev);
2503 netif_start_queue(ndev);
2506 /* Packet transmit function */
2507 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2509 struct sh_eth_private *mdp = netdev_priv(ndev);
2510 struct sh_eth_txdesc *txdesc;
2511 dma_addr_t dma_addr;
2513 unsigned long flags;
2515 spin_lock_irqsave(&mdp->lock, flags);
2516 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2517 if (!sh_eth_tx_free(ndev, true)) {
2518 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2519 netif_stop_queue(ndev);
2520 spin_unlock_irqrestore(&mdp->lock, flags);
2521 return NETDEV_TX_BUSY;
2524 spin_unlock_irqrestore(&mdp->lock, flags);
2526 if (skb_put_padto(skb, ETH_ZLEN))
2527 return NETDEV_TX_OK;
2529 entry = mdp->cur_tx % mdp->num_tx_ring;
2530 mdp->tx_skbuff[entry] = skb;
2531 txdesc = &mdp->tx_ring[entry];
2533 if (!mdp->cd->hw_swap)
2534 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2535 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len,
2537 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
2539 return NETDEV_TX_OK;
2541 txdesc->addr = cpu_to_le32(dma_addr);
2542 txdesc->len = cpu_to_le32(skb->len << 16);
2544 dma_wmb(); /* TACT bit must be set after all the above writes */
2545 if (entry >= mdp->num_tx_ring - 1)
2546 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2548 txdesc->status |= cpu_to_le32(TD_TACT);
2550 wmb(); /* cur_tx must be incremented after TACT bit was set */
2553 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns))
2554 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
2556 return NETDEV_TX_OK;
2559 /* The statistics registers have write-clear behaviour, which means we
2560 * will lose any increment between the read and write. We mitigate
2561 * this by only clearing when we read a non-zero value, so we will
2562 * never falsely report a total of zero.
2565 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2567 u32 delta = sh_eth_read(ndev, reg);
2571 sh_eth_write(ndev, 0, reg);
2575 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2577 struct sh_eth_private *mdp = netdev_priv(ndev);
2579 if (mdp->cd->no_tx_cntrs)
2580 return &ndev->stats;
2582 if (!mdp->is_opened)
2583 return &ndev->stats;
2585 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2586 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2587 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2589 if (mdp->cd->cexcr) {
2590 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2592 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2595 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2599 return &ndev->stats;
2602 /* device close function */
2603 static int sh_eth_close(struct net_device *ndev)
2605 struct sh_eth_private *mdp = netdev_priv(ndev);
2607 netif_stop_queue(ndev);
2609 /* Serialise with the interrupt handler and NAPI, then disable
2610 * interrupts. We have to clear the irq_enabled flag first to
2611 * ensure that interrupts won't be re-enabled.
2613 mdp->irq_enabled = false;
2614 synchronize_irq(ndev->irq);
2615 napi_disable(&mdp->napi);
2616 sh_eth_write(ndev, 0x0000, EESIPR);
2618 sh_eth_dev_exit(ndev);
2620 /* PHY Disconnect */
2622 phy_stop(ndev->phydev);
2623 phy_disconnect(ndev->phydev);
2626 free_irq(ndev->irq, ndev);
2628 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2629 sh_eth_ring_free(ndev);
2633 pm_runtime_put(&mdp->pdev->dev);
2638 /* ioctl to device function */
2639 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2641 struct phy_device *phydev = ndev->phydev;
2643 if (!netif_running(ndev))
2649 return phy_mii_ioctl(phydev, rq, cmd);
2652 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2654 if (netif_running(ndev))
2657 ndev->mtu = new_mtu;
2658 netdev_update_features(ndev);
2663 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2664 static u32 sh_eth_tsu_get_post_mask(int entry)
2666 return 0x0f << (28 - ((entry % 8) * 4));
2669 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2671 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2674 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2677 struct sh_eth_private *mdp = netdev_priv(ndev);
2678 int reg = TSU_POST1 + entry / 8;
2681 tmp = sh_eth_tsu_read(mdp, reg);
2682 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg);
2685 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2688 struct sh_eth_private *mdp = netdev_priv(ndev);
2689 int reg = TSU_POST1 + entry / 8;
2690 u32 post_mask, ref_mask, tmp;
2692 post_mask = sh_eth_tsu_get_post_mask(entry);
2693 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2695 tmp = sh_eth_tsu_read(mdp, reg);
2696 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg);
2698 /* If other port enables, the function returns "true" */
2699 return tmp & ref_mask;
2702 static int sh_eth_tsu_busy(struct net_device *ndev)
2704 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2705 struct sh_eth_private *mdp = netdev_priv(ndev);
2707 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2711 netdev_err(ndev, "%s: timeout\n", __func__);
2719 static int sh_eth_tsu_write_entry(struct net_device *ndev, u16 offset,
2722 struct sh_eth_private *mdp = netdev_priv(ndev);
2725 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2726 iowrite32(val, mdp->tsu_addr + offset);
2727 if (sh_eth_tsu_busy(ndev) < 0)
2730 val = addr[4] << 8 | addr[5];
2731 iowrite32(val, mdp->tsu_addr + offset + 4);
2732 if (sh_eth_tsu_busy(ndev) < 0)
2738 static void sh_eth_tsu_read_entry(struct net_device *ndev, u16 offset, u8 *addr)
2740 struct sh_eth_private *mdp = netdev_priv(ndev);
2743 val = ioread32(mdp->tsu_addr + offset);
2744 addr[0] = (val >> 24) & 0xff;
2745 addr[1] = (val >> 16) & 0xff;
2746 addr[2] = (val >> 8) & 0xff;
2747 addr[3] = val & 0xff;
2748 val = ioread32(mdp->tsu_addr + offset + 4);
2749 addr[4] = (val >> 8) & 0xff;
2750 addr[5] = val & 0xff;
2754 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2756 struct sh_eth_private *mdp = netdev_priv(ndev);
2757 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2759 u8 c_addr[ETH_ALEN];
2761 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2762 sh_eth_tsu_read_entry(ndev, reg_offset, c_addr);
2763 if (ether_addr_equal(addr, c_addr))
2770 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2775 memset(blank, 0, sizeof(blank));
2776 entry = sh_eth_tsu_find_entry(ndev, blank);
2777 return (entry < 0) ? -ENOMEM : entry;
2780 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2783 struct sh_eth_private *mdp = netdev_priv(ndev);
2784 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2788 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2789 ~(1 << (31 - entry)), TSU_TEN);
2791 memset(blank, 0, sizeof(blank));
2792 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2798 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2800 struct sh_eth_private *mdp = netdev_priv(ndev);
2801 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2807 i = sh_eth_tsu_find_entry(ndev, addr);
2809 /* No entry found, create one */
2810 i = sh_eth_tsu_find_empty(ndev);
2813 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2817 /* Enable the entry */
2818 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2819 (1 << (31 - i)), TSU_TEN);
2822 /* Entry found or created, enable POST */
2823 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2828 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2830 struct sh_eth_private *mdp = netdev_priv(ndev);
2836 i = sh_eth_tsu_find_entry(ndev, addr);
2839 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2842 /* Disable the entry if both ports was disabled */
2843 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2851 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2853 struct sh_eth_private *mdp = netdev_priv(ndev);
2859 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2860 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2863 /* Disable the entry if both ports was disabled */
2864 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2872 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2874 struct sh_eth_private *mdp = netdev_priv(ndev);
2875 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2882 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2883 sh_eth_tsu_read_entry(ndev, reg_offset, addr);
2884 if (is_multicast_ether_addr(addr))
2885 sh_eth_tsu_del_entry(ndev, addr);
2889 /* Update promiscuous flag and multicast filter */
2890 static void sh_eth_set_rx_mode(struct net_device *ndev)
2892 struct sh_eth_private *mdp = netdev_priv(ndev);
2895 unsigned long flags;
2897 spin_lock_irqsave(&mdp->lock, flags);
2898 /* Initial condition is MCT = 1, PRM = 0.
2899 * Depending on ndev->flags, set PRM or clear MCT
2901 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2903 ecmr_bits |= ECMR_MCT;
2905 if (!(ndev->flags & IFF_MULTICAST)) {
2906 sh_eth_tsu_purge_mcast(ndev);
2909 if (ndev->flags & IFF_ALLMULTI) {
2910 sh_eth_tsu_purge_mcast(ndev);
2911 ecmr_bits &= ~ECMR_MCT;
2915 if (ndev->flags & IFF_PROMISC) {
2916 sh_eth_tsu_purge_all(ndev);
2917 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2918 } else if (mdp->cd->tsu) {
2919 struct netdev_hw_addr *ha;
2920 netdev_for_each_mc_addr(ha, ndev) {
2921 if (mcast_all && is_multicast_ether_addr(ha->addr))
2924 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2926 sh_eth_tsu_purge_mcast(ndev);
2927 ecmr_bits &= ~ECMR_MCT;
2934 /* update the ethernet mode */
2935 sh_eth_write(ndev, ecmr_bits, ECMR);
2937 spin_unlock_irqrestore(&mdp->lock, flags);
2940 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2948 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2949 __be16 proto, u16 vid)
2951 struct sh_eth_private *mdp = netdev_priv(ndev);
2952 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2954 if (unlikely(!mdp->cd->tsu))
2957 /* No filtering if vid = 0 */
2961 mdp->vlan_num_ids++;
2963 /* The controller has one VLAN tag HW filter. So, if the filter is
2964 * already enabled, the driver disables it and the filte
2966 if (mdp->vlan_num_ids > 1) {
2967 /* disable VLAN filter */
2968 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2972 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2978 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2979 __be16 proto, u16 vid)
2981 struct sh_eth_private *mdp = netdev_priv(ndev);
2982 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2984 if (unlikely(!mdp->cd->tsu))
2987 /* No filtering if vid = 0 */
2991 mdp->vlan_num_ids--;
2992 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2997 /* SuperH's TSU register init function */
2998 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
3000 if (!mdp->cd->dual_port) {
3001 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
3002 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
3003 TSU_FWSLC); /* Enable POST registers */
3007 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
3008 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
3009 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
3010 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
3011 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
3012 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
3013 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
3014 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
3015 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
3016 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
3017 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
3018 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
3019 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
3020 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
3021 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
3022 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
3023 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
3024 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
3025 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
3028 /* MDIO bus release function */
3029 static int sh_mdio_release(struct sh_eth_private *mdp)
3031 /* unregister mdio bus */
3032 mdiobus_unregister(mdp->mii_bus);
3034 /* free bitbang info */
3035 free_mdio_bitbang(mdp->mii_bus);
3040 /* MDIO bus init function */
3041 static int sh_mdio_init(struct sh_eth_private *mdp,
3042 struct sh_eth_plat_data *pd)
3045 struct bb_info *bitbang;
3046 struct platform_device *pdev = mdp->pdev;
3047 struct device *dev = &mdp->pdev->dev;
3049 /* create bit control struct for PHY */
3050 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
3055 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
3056 bitbang->set_gate = pd->set_mdio_gate;
3057 bitbang->ctrl.ops = &bb_ops;
3059 /* MII controller setting */
3060 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
3064 /* Hook up MII support for ethtool */
3065 mdp->mii_bus->name = "sh_mii";
3066 mdp->mii_bus->parent = dev;
3067 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
3068 pdev->name, pdev->id);
3070 /* register MDIO bus */
3071 if (pd->phy_irq > 0)
3072 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
3074 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
3081 free_mdio_bitbang(mdp->mii_bus);
3085 static const u16 *sh_eth_get_register_offset(int register_type)
3087 const u16 *reg_offset = NULL;
3089 switch (register_type) {
3090 case SH_ETH_REG_GIGABIT:
3091 reg_offset = sh_eth_offset_gigabit;
3093 case SH_ETH_REG_FAST_RZ:
3094 reg_offset = sh_eth_offset_fast_rz;
3096 case SH_ETH_REG_FAST_RCAR:
3097 reg_offset = sh_eth_offset_fast_rcar;
3099 case SH_ETH_REG_FAST_SH4:
3100 reg_offset = sh_eth_offset_fast_sh4;
3102 case SH_ETH_REG_FAST_SH3_SH2:
3103 reg_offset = sh_eth_offset_fast_sh3_sh2;
3110 static const struct net_device_ops sh_eth_netdev_ops = {
3111 .ndo_open = sh_eth_open,
3112 .ndo_stop = sh_eth_close,
3113 .ndo_start_xmit = sh_eth_start_xmit,
3114 .ndo_get_stats = sh_eth_get_stats,
3115 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3116 .ndo_tx_timeout = sh_eth_tx_timeout,
3117 .ndo_do_ioctl = sh_eth_do_ioctl,
3118 .ndo_change_mtu = sh_eth_change_mtu,
3119 .ndo_validate_addr = eth_validate_addr,
3120 .ndo_set_mac_address = eth_mac_addr,
3123 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3124 .ndo_open = sh_eth_open,
3125 .ndo_stop = sh_eth_close,
3126 .ndo_start_xmit = sh_eth_start_xmit,
3127 .ndo_get_stats = sh_eth_get_stats,
3128 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3129 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3130 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3131 .ndo_tx_timeout = sh_eth_tx_timeout,
3132 .ndo_do_ioctl = sh_eth_do_ioctl,
3133 .ndo_change_mtu = sh_eth_change_mtu,
3134 .ndo_validate_addr = eth_validate_addr,
3135 .ndo_set_mac_address = eth_mac_addr,
3139 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3141 struct device_node *np = dev->of_node;
3142 struct sh_eth_plat_data *pdata;
3143 const char *mac_addr;
3146 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3150 ret = of_get_phy_mode(np);
3153 pdata->phy_interface = ret;
3155 mac_addr = of_get_mac_address(np);
3157 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3159 pdata->no_ether_link =
3160 of_property_read_bool(np, "renesas,no-ether-link");
3161 pdata->ether_link_active_low =
3162 of_property_read_bool(np, "renesas,ether-link-active-low");
3167 static const struct of_device_id sh_eth_match_table[] = {
3168 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3169 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data },
3170 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data },
3171 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data },
3172 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data },
3173 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data },
3174 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
3175 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
3176 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
3177 { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data },
3178 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3179 { .compatible = "renesas,ether-r7s9210", .data = &r7s9210_data },
3180 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
3181 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
3184 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3186 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3192 static int sh_eth_drv_probe(struct platform_device *pdev)
3194 struct resource *res;
3195 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3196 const struct platform_device_id *id = platform_get_device_id(pdev);
3197 struct sh_eth_private *mdp;
3198 struct net_device *ndev;
3202 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3204 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3208 pm_runtime_enable(&pdev->dev);
3209 pm_runtime_get_sync(&pdev->dev);
3211 ret = platform_get_irq(pdev, 0);
3216 SET_NETDEV_DEV(ndev, &pdev->dev);
3218 mdp = netdev_priv(ndev);
3219 mdp->num_tx_ring = TX_RING_SIZE;
3220 mdp->num_rx_ring = RX_RING_SIZE;
3221 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3222 if (IS_ERR(mdp->addr)) {
3223 ret = PTR_ERR(mdp->addr);
3227 ndev->base_addr = res->start;
3229 spin_lock_init(&mdp->lock);
3232 if (pdev->dev.of_node)
3233 pd = sh_eth_parse_dt(&pdev->dev);
3235 dev_err(&pdev->dev, "no platform data\n");
3241 mdp->phy_id = pd->phy;
3242 mdp->phy_interface = pd->phy_interface;
3243 mdp->no_ether_link = pd->no_ether_link;
3244 mdp->ether_link_active_low = pd->ether_link_active_low;
3248 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3250 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3252 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3253 if (!mdp->reg_offset) {
3254 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3255 mdp->cd->register_type);
3259 sh_eth_set_default_cpu_data(mdp->cd);
3261 /* User's manual states max MTU should be 2048 but due to the
3262 * alignment calculations in sh_eth_ring_init() the practical
3263 * MTU is a bit less. Maybe this can be optimized some more.
3265 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3266 ndev->min_mtu = ETH_MIN_MTU;
3270 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3272 ndev->netdev_ops = &sh_eth_netdev_ops;
3273 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3274 ndev->watchdog_timeo = TX_TIMEOUT;
3276 /* debug message level */
3277 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3279 /* read and set MAC address */
3280 read_mac_address(ndev, pd->mac_addr);
3281 if (!is_valid_ether_addr(ndev->dev_addr)) {
3282 dev_warn(&pdev->dev,
3283 "no valid MAC address supplied, using a random one.\n");
3284 eth_hw_addr_random(ndev);
3288 int port = pdev->id < 0 ? 0 : pdev->id % 2;
3289 struct resource *rtsu;
3291 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3293 dev_err(&pdev->dev, "no TSU resource\n");
3297 /* We can only request the TSU region for the first port
3298 * of the two sharing this TSU for the probe to succeed...
3301 !devm_request_mem_region(&pdev->dev, rtsu->start,
3302 resource_size(rtsu),
3303 dev_name(&pdev->dev))) {
3304 dev_err(&pdev->dev, "can't request TSU resource.\n");
3308 /* ioremap the TSU registers */
3309 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
3310 resource_size(rtsu));
3311 if (!mdp->tsu_addr) {
3312 dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
3317 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3319 /* Need to init only the first port of the two sharing a TSU */
3321 if (mdp->cd->chip_reset)
3322 mdp->cd->chip_reset(ndev);
3324 /* TSU init (Init only)*/
3325 sh_eth_tsu_init(mdp);
3329 if (mdp->cd->rmiimode)
3330 sh_eth_write(ndev, 0x1, RMIIMODE);
3333 ret = sh_mdio_init(mdp, pd);
3335 if (ret != -EPROBE_DEFER)
3336 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
3340 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3342 /* network device register */
3343 ret = register_netdev(ndev);
3348 device_set_wakeup_capable(&pdev->dev, 1);
3350 /* print device information */
3351 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3352 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3354 pm_runtime_put(&pdev->dev);
3355 platform_set_drvdata(pdev, ndev);
3360 netif_napi_del(&mdp->napi);
3361 sh_mdio_release(mdp);
3367 pm_runtime_put(&pdev->dev);
3368 pm_runtime_disable(&pdev->dev);
3372 static int sh_eth_drv_remove(struct platform_device *pdev)
3374 struct net_device *ndev = platform_get_drvdata(pdev);
3375 struct sh_eth_private *mdp = netdev_priv(ndev);
3377 unregister_netdev(ndev);
3378 netif_napi_del(&mdp->napi);
3379 sh_mdio_release(mdp);
3380 pm_runtime_disable(&pdev->dev);
3387 #ifdef CONFIG_PM_SLEEP
3388 static int sh_eth_wol_setup(struct net_device *ndev)
3390 struct sh_eth_private *mdp = netdev_priv(ndev);
3392 /* Only allow ECI interrupts */
3393 synchronize_irq(ndev->irq);
3394 napi_disable(&mdp->napi);
3395 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
3397 /* Enable MagicPacket */
3398 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
3400 return enable_irq_wake(ndev->irq);
3403 static int sh_eth_wol_restore(struct net_device *ndev)
3405 struct sh_eth_private *mdp = netdev_priv(ndev);
3408 napi_enable(&mdp->napi);
3410 /* Disable MagicPacket */
3411 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3413 /* The device needs to be reset to restore MagicPacket logic
3414 * for next wakeup. If we close and open the device it will
3415 * both be reset and all registers restored. This is what
3416 * happens during suspend and resume without WoL enabled.
3418 ret = sh_eth_close(ndev);
3421 ret = sh_eth_open(ndev);
3425 return disable_irq_wake(ndev->irq);
3428 static int sh_eth_suspend(struct device *dev)
3430 struct net_device *ndev = dev_get_drvdata(dev);
3431 struct sh_eth_private *mdp = netdev_priv(ndev);
3434 if (!netif_running(ndev))
3437 netif_device_detach(ndev);
3439 if (mdp->wol_enabled)
3440 ret = sh_eth_wol_setup(ndev);
3442 ret = sh_eth_close(ndev);
3447 static int sh_eth_resume(struct device *dev)
3449 struct net_device *ndev = dev_get_drvdata(dev);
3450 struct sh_eth_private *mdp = netdev_priv(ndev);
3453 if (!netif_running(ndev))
3456 if (mdp->wol_enabled)
3457 ret = sh_eth_wol_restore(ndev);
3459 ret = sh_eth_open(ndev);
3464 netif_device_attach(ndev);
3470 static int sh_eth_runtime_nop(struct device *dev)
3472 /* Runtime PM callback shared between ->runtime_suspend()
3473 * and ->runtime_resume(). Simply returns success.
3475 * This driver re-initializes all registers after
3476 * pm_runtime_get_sync() anyway so there is no need
3477 * to save and restore registers here.
3482 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3483 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3484 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3486 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3488 #define SH_ETH_PM_OPS NULL
3491 static const struct platform_device_id sh_eth_id_table[] = {
3492 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3493 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3494 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3495 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3496 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3497 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3498 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3501 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3503 static struct platform_driver sh_eth_driver = {
3504 .probe = sh_eth_drv_probe,
3505 .remove = sh_eth_drv_remove,
3506 .id_table = sh_eth_id_table,
3509 .pm = SH_ETH_PM_OPS,
3510 .of_match_table = of_match_ptr(sh_eth_match_table),
3514 module_platform_driver(sh_eth_driver);
3516 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3517 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3518 MODULE_LICENSE("GPL v2");